Narrow body, RoHS-compliant, 8-lead SOIC
Low power operation
5 V operation
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps
3.7 mA per channel maximum @ 10 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps
2.2 mA per channel maximum @ 10 Mbps
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 10 Mbps (NRZ)
Precise timing characteristics
3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V
= 560 V peak
IORM
APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation
Gate drive interface
ADuM1210
GENERAL DESCRIPTION
The ADuM12101 is a dual-channel, digital isolator based on
Analog Devices, Inc., iCoupler® technology. Combining high
speed CMOS and monolithic transformer technology, this
isolation component provides outstanding performance
characteristics superior to alternatives such as optocoupler
devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with optocouplers. The concerns of the typical optocoupler regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with iCoupler products. Furthermore,
iCoupler devices consume one-tenth to one-sixth the power of
optocouplers at comparable signal data rates.
The ADuM1210 isolator provides two independent isolation
channels operable with the supply voltage on either side,
ranging from 2.7 V to 5.5 V. This provides compatibility with
lower voltage systems and enables voltage translation
functionality across the isolation barrier. In addition, the
ADuM1210 provides low pulse width distortion (<3 ns) and
tight channel-to-channel matching (<3 ns). Unlike other optocoupler alternatives, the ADuM1210 isolator has a patented
refresh feature that ensures dc correctness in the absence of
input logic transitions and during power-up/power-down
conditions. Furthermore, as an alternative to the ADuM1200
dual-channel digital isolator that defaults to an output high
condition, the ADuM1210 outputs default to a logic low state
when input power is off.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.
FUNCTIONAL BLOCK DIAGRAM
1
V
DD1
ENCODEDECODE
2
V
IA
ENCODEDECODE
3
V
IB
4
GND
1
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
4.5 V ≤ V
unless otherwise noted. All typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel,
Output Supply Current, per Channel,
Total Supply Current, Two Channels1
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ V
Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages V
V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current
associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total V
currents as a function of data rate.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
≤ 5.5 V, 4.5 V ≤ V
DD1
≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,
DD2
= 25°C, V
A
0.50 0.60 mA
I
DDI (Q)
DD1
= V
= 5 V. All voltages are relative to their respective ground.
DD2
Quiescent
I
0.19 0.25 mA
DDO (Q)
Quiescent
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.1 1.4 mA DC to 1 MHz logic signal frequency
DD1 (Q)
0.5 0.8 mA DC to 1 MHz logic signal frequency
DD2 (Q)
10 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
− t
PLH
|4 PWD 3 ns CL = 15 pF, CMOS signal levels
PHL
4.3 5.5 mA 5 MHz logic signal frequency
DD1 (10)
1.3 2.0 mA 5 MHz logic signal frequency
DD2 (10)
DD1
V
DD1
V
DD1
, V
V
OAH
OBH
, V
OAL
OBL
, t
20 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
− 0.1 5.0 V IOx = −20 μA, VIx = V
DD2
− 0.5 4.8 V IOx = −4 mA, VIx = V
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
IxH
IxH
IxL
IxL
IxL
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
15 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
6
Codirectional Channels
Opposing-Directional Channels
7
at Logic High Output
at Logic Low Output
per Channel
per Channel
8
8
7
PSKCD
15 ns CL = 15 pF, CMOS signal levels
t
PSKOD
6
| 25 35 kV/μs
|CM
H
= V
Ix
DD1
, VCM = 1000 V,
V
transient magnitude = 800 V
| 25 35 kV/μs
|CM
L
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.19 mA/Mbps
I
DDI (D)
0.05 mA/Mbps
I
DDO (D)
and V
DD2
supply
DD1
Rev. D | Page 3 of 20
Page 4
ADuM1210 Data Sheet
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
. CML is the maximum common-mode voltage slew rate
DD2
Figure 4Figure 6
Power Consumption
calculating per-channel supply current for a given data rate.
propagation delay is
PLH
Rev. D | Page 4 of 20
Page 5
Data Sheet ADuM1210
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ V
unless otherwise noted. All typical specifications are at T
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel,
Output Supply Current, per Channel,
Total Supply Current, Two Channels1
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB, ≤ V
Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages V
V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
Figure 4Figure 6 Figure 7Figure 8
total V
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
≤ 3.6 V, 2.7 V ≤ V
DD1
≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range,
DD2
= 25°C, V
A
0.26 0.35 mA
I
DDI (Q)
DD1
= V
= 3.0 V. All voltages are relative to their respective ground.
DD2
Quiescent
I
0.11 0.20 mA
DDO (Q)
Quiescent
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
0.6 1.0 mA DC to 1 MHz logic signal frequency
DD1 (Q)
0.2 0.6 mA DC to 1 MHz logic signal frequency
DD2 (Q)
10 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
− t
PLH
PHL
|4 PWD 3 ns CL = 15 pF, CMOS signal levels
2.2 3.4 mA 5 MHz logic signal frequency
DD1 (10)
0.7 1.1 mA 5 MHz logic signal frequency
DD2 (10)
DD1
V
DD1
V
DD1
, V
V
OAH
OBH
, V
OAL
OBL
, t
20 60 ns CL = 15 pF, CMOS signal levels
PHL
PLH
− 0.1 3.0 V IOx = −20 μA, VIx = V
DD2
− 0.5 2.8 V IOx = −4 mA, VIx = V
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
IxH
IxH
IxL
IxL
IxL
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
22 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
6
Codirectional Channels
Opposing-Directional Channels
7
at Logic High Output
at Logic Low Output
per Channel
per Channel
through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See and for
and V
DD1
8
8
supply currents as a function of data rate.
DD2
7
PSKCD
22 ns CL = 15 pF, CMOS signal levels
t
PSKOD
6
| 25 35 kV/μs
|CM
H
= V
Ix
DD1
, VCM = 1000 V,
V
transient magnitude = 800 V
| 25 35 kV/μs
|CM
L
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
I
0.10 mA/Mbps
DDI (D)
0.03 mA/Mbps
I
DDO (D)
Power Consumption
propagation delay is
PLH
Rev. D | Page 5 of 20
Page 6
ADuM1210 Data Sheet
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
O
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Figure 4Figure 6
Power Consumption
Rev. D | Page 6 of 20
Page 7
Data Sheet ADuM1210
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V ≤ V
maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at
= 25°C; V
T
A
= 3.0 V, V
DD1
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel,
Quiescent
5 V/3 V Operation 0.50 0.6 mA
3 V/5 V Operation 0.26 0.35 mA
Output Supply Current, per Channel,
Quiescent
5 V/3 V Operation 0.11 0.20 mA
3 V/5 V Operation 0.19 0.25 mA
Total Supply Current, Two Channels1
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal frequency
V
Supply Current I
DD2
5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal frequency
10 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal frequency
3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal frequency
V
Supply Current I
DD2
5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal frequency
3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal frequency
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ V
Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages V
V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Opposing-Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
≤ 5.5 V, 2.7 V ≤ V
DD1
= 5.0 V; or V
DD2
− t
PLH
|4 PWD 3 ns CL = 15 pF, CMOS signal levels
PHL
6
6
≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ V
DD2
= 5.0 V, V
DD1
mA
I
DDI (Q)
I
mA
DDO (Q)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
, V
OAH
OBH
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
, t
15 55 ns CL = 15 pF, CMOS signal levels
PHL
PLH
22 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
22 ns CL = 15 pF, CMOS signal levels
t
PSKOD
= 3.0 V. All voltages are relative to their respective ground.
DD2
V
DD1
V
− 0.1 V
DD2
− 0.5 V
DD2
V IOx = −20 μA, VIx = V
DD2
− 0.2 V IOx = −4 mA, VIx = V
DD2
≤ 3.6 V, 4.5 V ≤ V
DD1
V
DD1
≤ 5.5 V. All minimum/
DD2
DD1
IxH
IxH
IxL
IxL
IxL
Rev. D | Page 7 of 20
Page 8
ADuM1210 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
| 25 35 kV/μs
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
7
7
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current,
per Channel
8
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current,
per Channel
8
5 V/3 V Operation 0.03 mA/Mbps
3 V/5 V Operation 0.05 mA/Mbps
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See and for
Figure 4
total V
DD1
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
Figure 6
and V
supply currents as a function of data rate.
DD2
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
|CM
H
|CML| 25 35 kV/μs
I
DDI (D)
I
DDO (D)
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Power Consumption
= V
Ix
DD1
, VCM = 1000 V,
V
transient magnitude = 800 V
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
Power Consumption
Figure 7Figure 8
propagation delay is
PLH
Figure 4
Figure 6
Rev. D | Page 8 of 20
Page 9
Data Sheet ADuM1210
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)1 C
Input Capacitance2 CI 4.0 pF
IC Junction-to-Case Thermal Resistance
Side 1
Side 2 θ
1
The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
2
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1210 is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended
maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
ULCSAVDE
Recognized Under 1577
Component Recognition
Program1
Single/Basic 2500 V rms
Isolation Voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM1210 is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).
2
In accordance with DIN V VDE V 0884-10, each ADuM1210 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection
limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10approval.
Approved under CSA Component Acceptance Notice #5A
Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms
(566 peak) maximum working voltage
Functional insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
1012 Ω
I-O
1.0 pF f = 1 MHz
I-O
θ
46 °C/W Thermocouple located at center of package underside
JCI
41 °C/W
JCO
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-12
2
Reinforced insulation, 560 V peak
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm
Minimum External Tracking (Creepage) L(I02) 4.01 min mm
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Rev. D | Page 9 of 20
Page 10
ADuM1210 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective
circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 7.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage, Method B1
× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
After Input and/or Safety Test Subgroup 2
V
IORM
and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure;
see Figure 2
Case Temperature TS 150 °C
Side 1 Current IS1 160 mA
Side 2 Current IS2 170 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
560 V peak
IORM
1050 V peak
V
PR
200
180
160
140
120
100
SAFETY-LIMITING CURRENT (mA)
SIDE #1
80
60
40
20
0
0
SIDE #2
50100150200
CASE TEMPERAT URE ( °C)
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values
on Case Temperature, per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages1 V
Input Signal Rise and Fall Times 1.0 ms
1
All voltages are relative to their respective ground. See the
Magnetic Field Immunity
magnetic fields.
05459-002
section for information on immunity to external
, V
2.7 5.5 V
DD1
DD2
DC Correctness and
Rev. D | Page 10 of 20
Page 11
Data Sheet ADuM1210
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 9.
Parameter Rating
Storage Temperature (TST) Range −55°C to +150°C
Ambient Operating Temperature
) Range
(T
A
Supply Voltages (V
DD1
, V
DD2
1
)
Input Voltage (VIA, VIB)1 −0.5 V to V
Output Voltage (VOA, VOB)1 −0.5 V to V
−40°C to +105°C
−0.5 V to +7.0 V
+ 0.5 V
DDI
+ 0.5 V
DDO
Average Output Current, Per Pin (IO)2 −35 mA to +35 mA
Common-Mode Transients (CML, CMH)3 −100 kV/μs to +100 kV/μs
1
All voltages are relative to their respective ground.
2
See Figure 2 for maximum rated current values for various temperatures.
3
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating may cause
latch-up or permanent damage.
1
Table 10. Maximum Continuous Working Voltage
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Functional Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Basic Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Functional Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Basic Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. D | Page 11 of 20
Page 12
ADuM1210 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
18
DD1
ADuM1210
V
27
IA
TOP VIEW
V
36
IB
(Not to S cale)
GND
45
1
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
DD1
2 VIA Logic Input A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground reference for Isolator Side 1.
5 GND2 Ground 2. Ground reference for Isolator Side 2.
6 VOB Logic Output B.
7 VOA Logic Output A.
8 V
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
DD2
Table 12. ADuM1210 Truth Table (Positive Logic)
VIA Input VIB Input V
State V
DD1
State VOA Output VOB Output Description
DD2
H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered L L
X X Powered Unpowered Indeterminate Indeterminate
V
DD2
V
OA
V
OB
GND
2
5459-003
Outputs return to the input state within 1 μs
power restoration.
of V
DDI
Outputs return to the input state within 1 μs
power restoration.
of V
DDO
Rev. D | Page 12 of 20
Page 13
Data Sheet ADuM1210
TYPICAL PERFORMANCE CHARACTERISTICS
10
20
8
6
4
5V
CURRENT/CHANNEL (mA)
2
0
0
102030
DATA RATE (Mb ps)
3V
Figure 4. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
4
3
2
5V
1
CURRENT/CHANNEL (mA)
3V
15
10
CURRENT (mA)
5
0
05459-004
Figure 7. Typical V
0
DD1
4
3
2
CURRENT (mA)
1
102030
DATA RATE (Mb ps)
Supply Current vs. Data Rate for 5 V and 3 V Operation
5V
5V
3V
05459-007
3V
0
0
102030
DATA RATE (Mb ps)
Figure 5. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
4
3
5V
2
1
CURRENT/CHANNEL (mA)
0
0
102030
DATA RATE (Mb ps)
3V
Figure 6. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
05459-005
Figure 8. Typical V
05459-006
Rev. D | Page 13 of 20
0
0
DD2
102030
DATA RATE (Mb ps)
05459-008
Supply Current vs. Data Rate for 5 V and 3 V Operation
Page 14
ADuM1210 Data Sheet
V
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM1210 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins. The
capacitor value should be between 0.01 μF and 0.1 μF. The total
lead length between both ends of the capacitor and the input
power supply pin should not exceed 20 mm.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high output.
INPUT (
OUTPUT (V
)
Ix
t
PLH
)
Ox
Figure 9. Propagation Delay Parameters
t
PHL
50%
50%
Pulse width distortion is the maximum difference between the
two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM1210 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM120x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is therefore either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions of more than ~1 μs at the input, a periodic set of
refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default state (see Table 12) by the
watchdog timer circuit.
The ADuM1210 is extremely immune to external magnetic
fields. The limitation on the ADuM1210 magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM1210 is examined because it represents
the most susceptible mode of operation.
05459-009
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑ π r
2
; n = 1, 2, … , N
n
where:
β is the magnetic flux density (gauss).
r
is the radius of the nth turn in the receiving coil (cm).
n
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1210 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 10.
100
10
1
0.1
DENSITY (kgauss)
0.01
MAXIMUM ALLOWABLE MAGNETIC FLUX
0.001
1k10k10M
Figure 10. Maximum Allowable External Magnetic Flux Density
MAGNETIC FIELD FREQUENCY (Hz)
1M
100M100k
05459-010
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse
(and had the worst-case polarity), it would reduce the received
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1210 transformers. Figure 11 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen in Figure 11, the ADuM1210 is extremely
immune and can be affected only by extremely large currents
operated at high frequency and very close to the component.
For the 1 MHz example, a 0.5 kA current would have to be
placed 5 mm away from the ADuM1210 to affect the
component’s operation.
Rev. D | Page 14 of 20
Page 15
Data Sheet ADuM1210
1000
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
MAXIMUM ALLOWABLE CURRENT (kA)
0.01
1k10k100M100k1M10M
MAGNETIC F I ELD FREQUENCY (Hz)
Figure 11. Maximum Allowable Current for Various
Current-to-ADuM1210 Spacings
05459-011
Note that, at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces
can induce sufficiently large error voltages to trigger the
threshold of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM1210
isolator is a function of the supply voltage, the channel data rate,
and the channel output load.
For each input channel, the supply current is given by
I
= I
DDI
DDI (Q)
= I
I
DDI
× (2f − fr) + I
DDI (D)
DDI (Q)
For each output channel, the supply current is given by
I
= I
DDO
I
= (I
DDO
f ≤ 0.5fr
DDO (Q)
+ (0.5 × 10−3) × CLV
DDO (D)
) × (2f − fr) + I
DDO
where:
I
, I
DDI (D)
are the input and output dynamic supply currents
DDO (D)
per channel (mA/Mbps).
C
is the output load capacitance (pF).
L
is the output supply voltage (V).
V
DDO
f is the input logic signal frequency (MHz, half the input data
rate, NRZ signaling).
f
is the input stage refresh rate (Mbps).
r
, I
I
DDI (Q)
are the specified input and output quiescent
DDO (Q)
supply currents (mA).
f ≤ 0.5fr
f > 0.5fr
DDO (Q)
f > 0.5fr
To calculate the total I
DD1
and I
supply current, the supply
DD2
currents for each input and output channel corresponding to
I
DD1
and I
are calculated and totaled. Figure 4 and Figure 5
DD2
show per-channel supply currents as a function of data rate for
an unloaded output condition. Figure 6 shows per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 7 and Figure 8 show total V
DD1
and V
DD2
supply current as a function of data rate.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM1210.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Tab le 10
summarize the peak voltage for 50 years of service life for a
bipolar ac operating condition and the maximum CSA/VDE
approved working voltages. In many cases, the approved
working voltage is higher than 50-year service life voltage.
Operation at these high working voltages can lead to shortened
insulation life in some cases.
The insulation lifetime of the ADuM1210 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 12, Figure 13, and Figure 14 illustrate these
different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
Rev. D | Page 15 of 20
Page 16
ADuM1210 Data Sheet
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life. The
working voltages listed in Table 1 0 can be applied while maintaining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 13
or Figure 14 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 1 0.
Note that the voltage presented in Figure 13 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
RATED PEAK VOL TAGE
0V
Figure 12. Bipolar AC Waveform
05459-014
RATED PEAK VOL TAGE
0V
Figure 13. Unipolar AC Waveform
05459-012
RATED PEAK VOL TAGE
0V
Figure 14. DC Waveform
05459-013
Rev. D | Page 16 of 20
Page 17
Data Sheet ADuM1210
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
85
1
1.27 (0.0500)
BSC
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 15. 8-Lead Standard Small Outline Package [SOIC_N]