Datasheet ADuM1100 Datasheet (Analog Devices)

a

iCoupler® Digital Isolator

ADuM1100

FEATURES
High Data Rate: DC to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V Operation/

Level Translation
125ⴗC Max Operating Temperature
Low Power Operation

5 V Operation

1.0 mA Max @ 1 Mbps

4.5 mA Max @ 25 Mbps

16.8 mA Max @ 100 Mbps

3.3 V Operation

0.4 mA Max @ 1 Mbps

3.5 mA Max @ 25 Mbps

7.1 mA Max @ 50 Mbps
8-Lead SOIC Package (lead-free version available)
High Common-Mode Transient Immunity: >25 kV/␮s
Safety and Regulatory Information

UL Recognized

2500 V rms for 1 Minute per UL 1577
CSA Component Acceptance Notice No. 5A
VDE Certificate of Conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–01

DIN EN 60950 (VDE 0805): 2001–12; EN 60950: 2000

= 560 V

V

IORM

PEAK

APPLICATIONS
Digital Fieldbus Isolation
Opto-Isolator Replacement
Computer-Peripheral Interface
Microprocessor System Interface
General Instrumentation and Data Acquisition

Applications

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADuM1100 is a digital isolator based on Analog Devices’
iCoupler technology. Combining high speed CMOS and mono­lithic air core transformer technology, this isolation component
provides outstanding performance characteristics superior to
alternatives such as optocoupler devices.

Configured as a pin compatible replacement for existing high speed
optocouplers, the ADuM1100 supports data rates as high as
25 Mbps and 100 Mbps.

The ADuM1100 operates with either voltage supply ranging from

3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge
asymmetry of <2 ns, and is compatible with temperatures up to
125°C. It operates at very low power, less than 0.9 mA of quiescent
current (sum of both sides), and a dynamic current of less than
160 µA per Mbps of data rate. Unlike other optocoupler alter­natives, the ADuM1100 provides dc correctness with a patented
refresh feature that continuously updates the output signal.

The ADuM1100 is offered in three grades. The ADuM1100AR
and ADuM1100BR can operate up to a maximum temperature
of 105°C and support data rates up to 25 Mbps and 100 Mbps,
respectively. The ADuM1100UR can operate up to a maximum
temperature of 125°C and supports data rates up to 100 Mbps.

V

DD1

(DATA IN)

V

DD1

GND

V

I

1

FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION,
DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.

UPDATE

E
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ADuM1100

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

V

D
E
C
O
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WATCHDOG

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

DD2

GND

2

V

O

(DATA OUT)

GND

2

ADuM1100–SPECIFICATIONS

(4.5 V ≤ V

1

ELECTRICAL SPECIFICATIONS, 5 V OPERATION

range, unless otherwise noted. All typical specifications are at TA = 25ⴗC, V

specifications apply over the entire recommended operation

= V

DD2

= 5 V.)

DD1

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current I
Output Supply Current I
Input Supply Current (25 Mbps) I

(See TPC 1)

Output Supply Current

2

(25 Mbps) I

DD1(Q)

DD2(Q)

DD1(25)

DD2(25)

0.3 0.8 mA VI = 0 V or V

0.01 0.06 mA VI = 0 V or V

2.2 3.5 mA 12.5 MHz Logic Signal Frequency

0.5 1.0 mA 12.5 MHz Logic Signal Frequency

(See TPC 2)

Input Supply Current (100 Mbps) I

(See TPC 1) ADuM1100BR/ADuM1100UR Only

Output Supply Current

2

(100 Mbps) I

DD1(100)

DD2(100)

9.0 14 mA 50 MHz Logic Signal Frequency,

2.0 2.8 mA 50 MHz Logic Signal Frequency,

(See TPC 2) ADuM1100BR/ADuM1100UR Only
Input Current I
Logic High Output Voltage V

Logic Low Output Voltage V

I

OH

OL

–10 +0.01 +10 µA0
V

– 0.1 5.0 V IO = –20 µA, VI = V

DD2

V

– 0.8 4.6 V IO = –4 mA, VI = V

DD2

0.0 0.1 V IO = 20 µA, VI = V

0.03 0.1 V IO = 400 µA, VI = V

0.3 0.8 V IO = 4 mA, VI = V

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width

Maximum Data Rate
For ADuM1100BR/ADuM1100UR

Minimum Pulse Width

Maximum Data Rate

3

4

3

4

PW 40 ns CL = 15 pF, CMOS Signal Levels

25 Mbps CL = 15 pF, CMOS Signal Levels

PW 6.7 10 ns CL = 15 pF, CMOS Signal Levels

100 150 Mbps CL = 15 pF, CMOS Signal Levels

For All Grades

Propagation Delay Time t

to Logic Low Output

5, 6

PHL

10.5 18 ns CL = 15 pF, CMOS Signal Levels

(See TPC 3)

Propagation Delay Time t

to Logic High Output

5, 6

PLH

10.5 18 ns CL = 15 pF, CMOS Signal Levels

(See TPC 3)

Pulse Width Distortion |t

Change versus Temperature

Propagation Delay Skew t

(Equal Temperature)

Propagation Delay Skew t

(Equal Temperature, Supplies)
Output Rise/Fall Time tR, t
Common-Mode Transient Immunity |CM

at Logic Low/High Output
Input Dynamic Power C

Dissipation Capacitance
Output Dynamic Power C

Dissipation Capacitance

See Notes on page 5.
Specifications subject to change without notice.

6, 8

PLH

10

10

– t

|6PWD 0.5 2 ns CL = 15 pF, CMOS Signal Levels

PHL

7

PSK1

PSK2

6, 8

F

|, 25 35 kV/µsV

9

L

|CMH|Transient Magnitude = 800 V

PD1

PD2

3 ps/°CC

8nsC

6nsC

3nsC

35 pF

8pF

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All min/max

DD2

DD1

DD1

≤ VIN ≤ V

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

= 0 or V

I

DD1

IH

IH

IL

IL

IL

, VCM = 1000 V,

DD1

–2–

REV. E

ADuM1100

ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION

range, unless otherwise noted. All typical specifications are at TA = 25ⴗC, V

DD1

(3.0 V ≤ V

1

specifications apply over the entire recommended operation

= V

= 3.3 V.)

DD2

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V. All min/max

DD2

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current I

Output Supply Current I

Input Supply Current (25 Mbps) I

(See TPC 1)

Output Supply Current

2

(25 Mbps) I

DD1(Q)

DD2(Q)

DD1(25)

DD2(25)

0.1 0.3 mA VI = 0 V or V

0.005 0.04 mA VI = 0 V or V

DD1

DD1

2.0 2.8 mA 12.5 MHz Logic Signal Frequency

0.3 0.7 mA 12.5 MHz Logic Signal Frequency

(See TPC 2)

Input Supply Current (50 Mbps) I

(See TPC 1) ADuM1100BR/ADuM1100UR Only

Output Supply Current

2

(50 Mbps) I

DD1(50)

DD2(50)

4.0 6.0 mA 25 MHz Logic Signal Frequency,

1.2 1.6 mA 25 MHz Logic Signal Frequency,

(See TPC 2) ADuM1100BR/ADuM1100UR Only
Input Current I
Logic High Output Voltage V

Logic Low Output Voltage V

I

OH

OL

–10 +0.01 +10 µA0
V

– 0.1 3.3 V IO = –20 µA, VI = V

DD2

V

– 0.5 3.0 V IO = –2.5 mA, VI = V

DD2

0.0 0.1 V IO = 20 µA, VI = V

0.04 0.1 V IO = 400 µA, VI = V

0.3 0.4 V IO = 2.5 mA, VI = V

≤ VIN ≤ V

DD1

IH

IH

IL

IL

IL

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width

Maximum Data Rate
For ADuM1100BR/ADuM1100UR

Minimum Pulse Width

Maximum Data Rate

3

4

3

4

PW 40 ns CL= 15 pF, CMOS Signal Levels

25 Mbps CL= 15 pF, CMOS Signal Levels

PW 10 20 ns CL= 15 pF, CMOS Signal Levels

50 100 Mbps CL= 15 pF, CMOS Signal Levels

For All Grades

Propagation Delay Time to t

Logic Low Output

5, 6

PHL

14.5 28 ns CL= 15 pF, CMOS Signal Levels

(See TPC 4)

Propagation Delay Time to t

Logic High Output

5, 6

PLH

15.0 28 ns CL= 15 pF, CMOS Signal Levels

(See TPC 4)

– t

Pulse Width Distortion |t

PLH

Change versus Temperature

Propagation Delay Skew t

(Equal Temperature)

6, 8

Propagation Delay Skew t

(Equal Temperature, Supplies)
Output Rise/Fall Time tR, t
Common-Mode Transient Immunity |CM

at Logic Low/High Output
Input Dynamic Power Dissipation C

Capacitance
Output Dynamic Power Dissipation C

Capacitance

See Notes on page 5.
Specifications subject to change without notice.

10

10

|6PWD 0.5 3 ns CL= 15 pF, CMOS Signal Levels

PHL

7

PSK1

6, 8

9

PSK2

F

|, 25 35 kV/µsVI=0 or V

L

|CMH|Transient Magnitude = 800 V

PD1

PD2

10 ps/°CCL= 15 pF, CMOS Signal Levels

15 ns CL= 15 pF, CMOS Signal Levels

12 ns CL= 15 pF, CMOS Signal Levels

3nsC

= 15 pF, CMOS Signal Levels

L

, VCM= 1000 V,

DD1

47 pF

14 pF

REV. E

–3–

ADuM1100

(5 V/3 V operation: 4.5 V ≤ V

= 5 V, V

1

≤ 5.5 V, 3.0 V ≤ V

= 3.3 V.)

DD2

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

= 15 pF, CMOS Signal Levels

L

DD2

ID

IL

IH

IL

IL

≤ 3.6 V.

≤ V

IH

IH

IL

IL

IH

IL

DD1

ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V or 3 V/5 V OPERATION

3 V/5 V operation: 3.0 V ≤ V
unless otherwise noted. All typical specifications are at TA = 25ⴗC, V

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, Quiescent I

5 V/3 V Operation 0.3 0.8 mA
3 V/5 V Operation 0.1 0.3 mA

Output Supply Current, Quiescent I

5 V/3 V Operation 0.005 0.04 mA
3 V/5 V Operation 0.01 0.06 mA

Input Supply Current, 25 Mbps I

5 V/3 V Operation 2.2 3.5 mA 12.5 MHz Logic Signal Frequency
3 V/5 V Operation 2.0 2.8 mA 12.5 MHz Logic Signal Frequency

Output Supply Current, 25 Mbps I

5 V/3 V Operation 0.3 0.7 mA 12.5 MHz Logic Signal Frequency
3 V/5 V Operation 0.5 1.0 mA 12.5 MHz Logic Signal Frequency

Input Supply Current, 50 Mbps I

5 V/3 V Operation 4.5 7.0 mA 25 MHz Logic Signal Frequency
3 V/5 V Operation 4.0 6.0 mA 25 MHz Logic Signal Frequency

Output Supply Current, 50 Mbps I

5 V/3 V Operation 1.2 1.6 mA 25 MHz Logic Signal Frequency

3 V/5 V Operation 1.0 1.5 mA 25 MHz Logic Signal Frequency
Input Currents I
Logic High Output Voltage, V

5 V/3 V Operation V
Logic Low Output Voltage, V

5 V/3 V Operation 0.04 0.1 V IO = 400 µA, VI = V

Logic High Output Voltage, V

3 V/5 V Operation V
Logic Low Output Voltage, V

3 V/5 V Operation 0.03 0.1 V IO = 400 µA, VI = V

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width

Maximum Data Rate
For ADuM1100BR/ADuM1100UR

Minimum Pulse Width

Maximum Data Rate
For All Grades

Propagation Delay Time to Logic t

Low/High Output

5 V/3 V Operation (See TPC 5) 13 21 ns CL = 15 pF, CMOS Signal Levels
3 V/5 V Operation (See TPC 6) 16 26 ns C

Pulse Width Distortion, |t

5 V/3 V Operation 0.5 2 ns C
3 V/5 V Operation 0.5 3 ns C
Change versus Temperature

5 V/3 V Operation 3 ps/ºC C
3 V/5 V Operation 10 ps/ºC C

Propagation Delay Skew t

(Equal Temperature)

5 V/3 V Operation 12 ns CL = 15 pF, CMOS Signal Levels
3 V/5 V Operation 15 ns CL = 15 pF, CMOS Signal Levels

≤ 3.6 V, 4.5 V ≤ V

DD1

3

4

3

4

5, 6

PLH

6, 8

– t

PHL

≤ 5.5 V. All min/max specifications apply over the entire recommended operation range,

DD2

DDI(Q)

DDO(Q)

DDI(25)

DDO(25)

DDI(50)

DDO(50)

IA

OH

OL

= 3.3 V, V

DD1

–10 +0.01 +10 µA0≤ VIA, VIB, VIC, V
V

– 0.1 3.3 V IO = –20 µA, VI = V

DD2

– 0.5 3.0 V IO = –2.5 mA, VI = V

DD2

= 5 V or V

DD2

DD1

0.0 0.1 V IO = 20 µA, VI = V

0.3 0.4 V IO = 2.5 mA, VI = V

V

OH

OL

– 0.1 5.0 V IO = –20 µA, VI = V

DD2

– 0.8 4.6 V IO = –4 mA, VI = V

DD2

0.0 0.1 V IO = 20 µA, VI = V

0.3 0.8 V IO = 4 mA, VI = V

PW 40 ns CL = 15 pF, CMOS Signal Levels

25 Mbps CL = 15 pF, CMOS Signal Levels

PW 20 ns CL = 15 pF, CMOS Signal Levels

50 Mbps CL = 15 pF, CMOS Signal Levels

PHL, tPLH

6

|

PWD

PSK1

DD1

or V

DD2

–4–

REV. E

ADuM1100

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS (continued)

Propagation Delay Skew t

(Equal Temperature, Supplies)

6, 8

5 V/3 V Operation 9 ns CL = 15 pF, CMOS Signal Levels

3 V/5 V Operation 12 ns C
Output Rise/Fall Time (10% to 90%) t
Common-Mode Transient Immunity at

Logic Low/High Output

8

Input Dynamic Power Dissipation Capacitance10C

5 V/3 V Operation 35 pF

3 V/5 V Operation 47 pF

Output Dynamic Power Dissipation Capacitance

5 V/3 V Operation 8 pF

3 V/5 V Operation 14 pF

NOTES

1

All voltages are relative to their respective ground.

2

Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by

I

= I

+ V

DD2(L)

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t
the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.

6

Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion

DD2

is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. t

PHL

× f × CL, where I

DD2

may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figures 3 to 7 for information on the impact of given input
rise/fall times on these parameters.

7

Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

8

t

is the magnitude of the worst-case difference in t

PSK1

the recommended operating conditions. t
temperature, supply voltages, and output load within the recommended operating conditions.

9

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the
range over which the common-mode is slewed.

10

The dynamic power dissipation capacitance is given by

C

= (I

PDi

The supply current consumptions at a given frequency and output load are calculated as

I

= C

DD1

DDi(100)

× V

PD1

– I

DD1

DDi(Q)

× f + I

)/(V

× f), where i = 1 or 2 and f is the input signal frequency.

DDi

DD1(Q)

Specifications subject to change without notice.

is the unloaded output supply current, f is the input signal frequency, and CL is the output load capacitance.

DD2

and/or t

PHL

is the magnitude of the worst-case difference in t

PSK2

; I

= (C

DD2(L)

+ CL) × V

PD2

DD2

PSK2

= 15 pF, CMOS Signal Levels

, t

R

f

3nsC

|CML|, 25 35 kV/µsVI = 0 or V

|Transient Magnitude = 800 V

|CM

H

PD1

10

C

PD2

that will be measured between units at the same operating temperature and output load within

× f + I

PLH

, where CL is the output load capacitance.

DD2(Q)

PHL

and/or t

that will be measured between units at the same operating

PLH

. CML is the maximum common-mode voltage slew

DD2

L

= 15 pF, CMOS Signal Levels

L

, VCM = 1000 V,

DD1

is measured from the 50% level of

PLH

PACKAGE CHARACTERISTICS

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)
Capacitance (Input-Output)
Input Capacitance

2

1

1

Input IC Junction-to-Case θ

R

I–O

C

I–O

C

I

JCI

12

10

Ω

1pFf = 1 MHz

4.0 pF
46 °C/W Thermocouple Located at Center

Thermal Resistance Underside of Package

Output IC Junction-to-Case θ

JCO

41 °C/W

Thermal Resistance

Package Power Dissipation P

NOTES

1

Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.

2

Input capacitance is measured at Pin 2 (VI).

REV. E

PD

–5–

240 mW

ADuM1100

REGULATORY INFORMATION

The ADuM1100 has been approved by the following organizations:

UL CSA VDE

Recognized under 1577 Approved under CSA Component Certified according to
Component Recognition Program1Acceptance Notice No. 5A, C22.2 No. 1-98, DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–1

C22.2 No. 14-95, and C22.2 No. 950-95 DIN EN 60950 (VDE 0805): 2001–12; EN60950: 2000

File E214100 File 205078 File 2471900-4880-0002

NOTES

1

In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (leakage detection current limit, I

2

In accordance with DIN EN 60747-5-2, each ADuM1100 is proof tested by applying an insulation test voltage ≥ 1050 V
limit ≤ 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.

for 1 second (partial discharge detection

PEAK

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Parameter Symbol Value Unit Conditions

Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals,

shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.016 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

≤ 5 µA).

I–O

2

DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS

Description Symbol Characteristic Unit

I

nstallation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II

Climatic Classification

ADuM1100AR and ADuM1100BR 40/105/21

ADuM1100UR 40/125/21
Pollution Degree (DIN VDE 0110, Table I) 2
Maximum Working Insulation Voltage V

IORM

560 V

PEAK

Input-to-Output Test Voltage, Method b1

V

× 1.875 = VPR, 100% Production Test, tM = 1 sec, Partial Discharge < 5 pC V

IORM

Input-to-Output Test Voltage, Method a V

PR

PR

1050 V
672 V

PEAK

PEAK

After Environmental Tests Subgroup 1

V

× 1.6 = VPR, tM = 10 sec, Partial Discharge < 5 pC V

IORM

PR

896 V

PEAK

After Input and/or Output Safety Test Subgroup 2/3

× 1.2 = VPR, tM = 10 sec, Partial Discharge < 5 pC V

V

IORM

Highest Allowable Overvoltage (Transient Overvoltage, t

INI

= 60 sec) V

PR

TR

672 V
4000 V

PEAK

PEAK

Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure,

See Thermal Derating Curve, Figure 1

Case Temperature T

Input Current I

Output Current I

S

S, INPUT

S, OUTPUT

Insulation Resistance at TS, VIO = 500 V Rs >10

This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits.
The * marking on the package denotes DIN EN 60747-5-2 approval for 560 V

working voltage.

PEAK

150 °C
160 mA
170 mA

9

Ω

–6–

REV. E

ADuM1100

180

160

140

120

100

INPUT CURRENT

80

60

40

SAFETY-LIMITING CURRENT (mA)

20

0

0

OUTPUT CURRENT

50 100 150 200

CASE TEMPERATURE (ⴗC)

Figure 1. Thermal Derating Curve, Dependence of
Safety-Limiting Values with Case Temperature per
DIN EN 60747-5-2

ABSOLUTE MAXIMUM RATINGS

1

Parameter Symbol Min Max Unit

Storage Temperature T
Ambient Operating T

Temperature
Supply Voltages
Input Voltage
Output Voltage
Average Current, per Pin

2

2

2

3

ST

A

V

DD1, VDD2

V

I

V

O

–55 +150 °C
–40 +125 °C

–0.5 +6.5 V
–0.5 V
–0.5 V

DD1

DD2

+ 0.5 V
+ 0.5 V

Temperature ≤ 105°C –25 +25 mA

Temperature ≤ 125°C

Input Current –7 +7 mA
Output Current –20 +20 mA

Common-Mode Transients

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device at
these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability. Ambient temperature = 25°C, unless otherwise noted.

2

All voltages are relative to their respective ground.

3

See Figure 1 for information on maximum allowable current for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-mode
transients exceeding the Absolute Maximum Rating may cause latch-up or permanent
damage.

4

–100 +100 kV/µs

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Operating Temperature

ADuM1100AR and ADuM1100BR T

ADuM1100UR T
Supply Voltages
Logic High Input Voltage, 5 V Operation
Logic Low Input Voltage, 5 V Operation
Logic High Input Voltage, 3.3 V Operation
Logic Low Input Voltage, 3.3 V Operation

1

1, 2

(See TPCs 7 and 8) V

1, 2

(See TPCs 7 and 8) V

1, 2

(See TPCs 7 and 8) V

1, 2

(See TPCs 7 and 8) V

A

A

V

DD1, VDD2

IH

IL

IH

IL

–40 +105 °C
–40 +125 °C

3.0 5.5 V

2.0 V

DD1

V

0.0 0.8 V

1.5 V

DD1

V

0.0 0.5 V

Input Signal Rise and Fall Times 1.0 ms

NOTES

1

All voltages are relative to their respective ground.

2

Input switching thresholds have 300 mV of hysteresis.

See the Method of Operation, DC Correctness, and Magnetic Field Immunity section and Figures 8 and 9 for information on immunity to external magnetic fields.

REV. E

–7–

ADuM1100

Table I. Truth Table (Positive Logic)

VI Input V

DD1

H Powered Powered H
L Powered Powered L
X Unpowered Powered H*
X Powered Unpowered X*

*VO returns to VI state within 1 µs of power restoration.

Note: Package branding is as follows:

ADuM1100AR,
ADuM1100AR-RL7

8

AD1100A

R YYWW

*

XXXXXX

1

ADuM1100BR,
ADuM1100BR-RL7

8

AD1100B

R YYWW

1

XXXXXX

*

ADuM1100UR,
ADuM1100UR-RL7

8

AD1100U

R YYWW

XXXXXX

1

where:

* = DIN EN 60747-5-2 mark
R= Package Designator (R denotes SOIC)
YYWW = Date Code
XXXXXX = Lot Code

State V

*

State VO Output

DD2

PIN CONFIGURATION

1

1

V

DD1

2

V

I

ADuM1100

1

3

V

DD1

GND

NOTES

1

PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. EITHER OR BOTH

MAY BE USED FOR V

2

PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. EITHER OR BOTH

MAY BE USED FOR GND2.

4

1

DD1

TOP VIEW

(Not to Scale)

.

8

V

DD2

2

7

GND

2

V

6

O

2

5

GND

2

ORDERING GUIDE

Temperature Max Data Min Pulse Package

Model Range Rate (Mbps) Width (ns) Package Description Option

ADuM1100AR –40°C to +105°C25408-Lead SOIC R-8
ADuM1100AR-RL7 –40°C to +105°C25408-Lead SOIC, 1,000 Piece Reel R-8
ADuM1100ARZ* –40°C to +105°C25408-Lead SOIC R-8
ADuM1100ARZ-RL7* –40°C to +105°C25408-Lead SOIC, 1,000 Piece Reel R-8
ADuM1100BR –40°C to +105°C 100 10 8-Lead SOIC R-8
ADuM1100BR-RL7 –40°C to +105°C 100 10 8-Lead SOIC, 1,000 Piece Reel R-8
ADuM1100BRZ* –40°C to +105°C 100 10 8-Lead SOIC R-8
ADuM1100BRZ-RL7* –40°C to +105°C 100 10 8-Lead SOIC, 1,000 Piece Reel R-8
ADuM1100UR –40°C to +125°C 100 10 8-Lead SOIC R-8
ADuM1100UR-RL7 –40°C to +125°C 100 10 8-Lead SOIC, 1,000 Piece Reel R-8
ADuM1100URZ* –40°C to +125°C 100 10 8-Lead SOIC R-8
ADuM1100URZ-RL7* –40°C to +125°C 100 10 8-Lead SOIC, 1,000 Piece Reel R-8
ADuM1100EVAL Evaluation Board

*Z = Lead Free

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADuM1100 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–8–

REV. E

TEMPERATURE (ⴗC)

18

–50 –25 125

PROPAGATION DELAY (ns)

16

14

13

12

0255075100

t

PHL

t

PLH

17

15

Typical Performance Characteristics—

ADuM1100

20

18

16

14

12

10

8

CURRENT (mA)

6

4

2

0

0

25 50 75 100 125 150

5V

3.3V

DATA RATE (Mbps)

TPC 1. Typical Input Supply Current vs. Logic
Signal Frequency for 5 V and 3.3 V Operation

5

4

3

5V

2

CURRENT (mA)

1

3.3V

18

17

16

t

PHL

15

14

PROPAGATION DELAY (ns)

13

12

–50

–25 25 50 100 125

075

TEMPERATURE (ⴗC)

t

PLH

TPC 4. Typical Propagation Delays vs. Temperature,

3.3 V Operation

14

13

t

PLH

12

t

PHL

11

PROPAGATION DELAY (ns)

10

0

0

25 50 75 100 125 150

DATA RATE (Mbps)

TPC 2. Typical Output Supply Current vs. Logic
Signal Frequency for 5 V and 3.3 V Operation

13

12

11

t

PHL

PROPAGATION DELAY (ns)

10

9

–50

TPC 3. Typical Propagation Delays vs. Temperature,
5 V Operation

05075100 125

–25 25

TEMPERATURE (ⴗC)

t

PLH

9

–25 25 50 100 125

–50

075

TEMPERATURE (ⴗC)

TPC 5. Typical Propagation Delays vs. Temperature,
5 V/3 V Operation

TPC 6. Typical Propagation Delays vs. Temperature,
3 V/5 V Operation

REV. E

–9–

ADuM1100

1.7

1.6

(V)

INPUT THRESHOLD, V

ITH

1.5

1.4

1.3

1.2

1.1

3.0

–40ⴗC

+25ⴗC

+125ⴗC

3.5 4.0 4.5 5.0 5.5
INPUT SUPPLY VOLTAGE, V

DD1

(V)

TPC 7. Typical Input Voltage Switching Threshold,
Low-to-High Transition

APPLICATION INFORMATION
PC Board Layout

The ADuM1100 digital isolator requires no external interface
circuitry for the logic interfaces. A bypass capacitor is recom­mended at the input and output supply pins. The input bypass
capacitor may most conveniently be connected between Pins 3
and 4 (Figure 2). Alternatively, the bypass capacitor may be located
between Pins 1 and 4. The output bypass capacitor may be con­nected between Pins 7 and 8 or Pins 5 and 8. The capacitor value
should be between 0.01 µF and 0.1 µF. The total lead length
between both ends of the capacitor and the power supply pins
should not exceed 20 mm.

V

(DATA)

1

GND

V

DD1

1

V

(OPTIONAL)

VO (DATA OUT)

GND

DD2

2

Figure 2. Recommended Printed Circuit Board Layout

INPUT (VI)

OUTPUT (V

t

PLH

)

O

t

PHL

50%

50%

Figure 3. Propagation Delay Parameters

Propagation Delay-Related Parameters

Propagation delay time describes the length of time it takes for a
logic signal to propagate through a component. Propagation delay

(V)

ITH

INPUT THRESHOLD, V

1.4

1.3

1.2

1.1

1.0

0.9

0.8

3.0

3.5 4.0 4.5 5.0 5.5
INPUT SUPPLY VOLTAGE, V

–40ⴗC

+25ⴗC

DD1

+125ⴗC

(V)

TPC 8. Typical Input Voltage Switching Threshold,
High-to-Low Transition

time to logic low output and propagation delay time to logic high
output refer to the duration between an input signal transition and
the respective output signal transition (Figure 3).

Pulse width distortion is the maximum difference between t
t

and provides an indication of how accurately the input signal’s

PHL

PLH

and

timing is preserved in the component’s output signal. Propagation
delay skew is the difference between the minimum and maximum
propagation delay values among multiple ADuM1100 compo­nents operated at the same operating temperature and having
the same output load.

Depending on the input signal rise/fall time, the measured propa­gation delay based on the input 50% level can vary from the true
propagation delay of the component (as measured from its input
switching threshold). This is due to the fact that the input threshold,
as is the case with commonly used optocouplers, is at a different
voltage level than the 50% point of typical input signals. This
propagation delay difference is given by

∆

tt tVVV

=−=

'/..

LH PLH PLH r I

=−=

∆

tt tVVV

'/..

HL PHL PHL f I

08 05

()

08 05

()

−

1

()

1

()

−

ITH L H

ITH H L

−

()

−

()

where:

t

PLH

, t

PHL

= propagation delays as measured from the

input 50% level.

, t ′

t′

PLH

PHL

= propagation delays as measured from the

input switching thresholds.

, t

t

r

f

V

I

= input 10% to 90% rise/fall time.
=amplitude of input signal (0 to VI levels

assumed).

V

ITH(L–H)

, V

= input switching thresholds.

ITH(H–L)

INPUT (VI)

V

ITH(L–H)

⌬

LH

V

I

OUTPUT (VO)

⌬

HL

50%

t

PLH

t'

PLH

50%

V

ITH(H–L)

t'

t

PHL

PHL

Figure 4. Impact of Input Rise/Fall Time on Propagation Delay

–10–

REV. E

(ns)

INPUT RISE/FALL TIME (10%–90%, ns)

6

1

PULSEWIDTH DISTORTION ADJUSTMENT,

⌬

PWD

(ns)

3

0

36810

5

1

5V INPUT SIGNAL

24579

3.3V INPUT SIGNAL

2

4

LH

PROPAGATION DELAY CHANGE, ⌬

4

3

5V INPUT SIGNAL

2

1

3.3V INPUT SIGNAL

0

1

24579

36810

INPUT RISE TIME (10%–90%, ns)

ADuM1100

Figure 5. Typical Propagation Delay Change due to
Input Rise Time Variation (for V

0

= 3.3 V and 5 V)

DD1

Figure 7. Typical Pulse Width Distortion Adjustment due
to Input Rise/Fall Time Variation (at V

= 3.3 V and 5 V)

DD1

Method of Operation, DC Correctness, and Magnetic Field Immunity

(ns)

HL

–1

5V INPUT SIGNAL

Referring to the functional block diagram, the two coils act as a
pulse transformer. Positive and negative logic transitions at the
isolator input cause narrow (2 ns) pulses to be sent via the trans­former to the decoder. The decoder is bistable and therefore

–2

3.3V INPUT SIGNAL

either set or reset by the pulses indicating input logic transitions.
In the absence of logic transitions at the input for more than 2 µs,
a periodic update pulse of the appropriate polarity is sent to ensure
dc correctness at the output. If the decoder receives none of

–3

PROPAGATION DELAY CHANGE, ⌬

–4

1

36810

24579

INPUT RISE TIME (10%–90%, ns)

Figure 6. Typical Propagation Delay Change due to
Input Fall Time Variation (for V

= 3.3 V and 5 V)

DD1

The impact of the slower input edge rates can also affect the
measured pulse width distortion as based on the input 50% level.
This impact may either increase or decrease the apparent pulse
width distortion depending on the relative magnitudes of t

, and PWD. The case of interest here is the condition

t

PLH

PHL

that leads to the largest increase in pulse width distortion. The
change in this case is given by

∆∆∆

()

PWD PWD

=′ = =

PWD LH HL

08

tVVV V for t t t

/. – – ,

1

––

==

()

––

ITH L H ITH H L

() ()

()

rf

where:

PWD t t

=

PLH PHL

This adjustment in pulse width distortion is plotted as a func­tion of input rise/fall time in Figure 7.

PWD t t

′= ′ ′––

PLH PHL

these update pulses for more than about 5 µs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a logic high state by the watchdog
timer circuit.

The limitation on the ADuM1100’s magnetic field immunity is set
by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The analysis that follows defines the conditions under
which this may occur. The ADuM1100’s 3.3 V operating condi­tion is examined because it represents the most susceptible mode
of operation.

,

The pulses at the transformer output are greater than 1.0 V in
amplitude. The decoder has sensing thresholds at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages can
be tolerated. The induced voltage induced across the receiving
coil is given by

Vddtrn N

=

βπ

()

2

Σ

=–/ ;,,....,

n

12

where:

β = magnetic flux density (Gauss).

N = number of turns in receiving coil.
r

= radius of nth turn in receiving coil (cm).

n

REV. E

–11–

ADuM1100

Given the geometry of the receiving coil in the ADuM1100 and an
imposed requirement that the induced voltage be at most 50% of
the 0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated as shown in Figure 8.

100

10

1

0.1

DENSITY (KGauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001
1k 10k 10M

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

Figure 8. Maximum Allowable External Magnetic Field

For example, at a magnetic field frequency of 1 MHz, the maximum
allowable magnetic field of 0.2 KGauss induces a voltage of

0.25 V at the receiving coil. This is about 50% of the sensing
threshold and will not cause a faulty output transition. Similarly,
if such an event were to occur during a transmitted pulse (and was
of the worst-case polarity), it would reduce the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.

The preceding magnetic flux density values correspond to specific
current magnitudes at given distances away from the ADuM1100
transformers. Figure 9 expresses these allowable current magnitudes
as a function of frequency for selected distances. As can be seen,
the ADuM1100 is extremely immune and can be affected only
by extremely large currents operated at high frequency and very
close to the component. For the 1 MHz example noted, one
would have to place a current of 0.5 kA 5 mm away from the
ADuM1100 to affect the component’s operation.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01
1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 9. Maximum Allowable Current for
Various Current-to-ADuM1100 Spacings

Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces could
induce sufficiently large error voltages to trigger the thresholds
of succeeding circuitry. Care should be taken in the layout of
such traces to avoid this possibility.

–12–

REV. E

OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

ADuM1100

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

REV. E

–13–

ADuM1100

Revision History

Location Page

10/03—Data Sheet changed from REV. D to REV. E.

Changes to Product Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changes to RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6/03—Data Sheet changed from REV. C to REV. D.

Changed DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4/03—Data Sheet changed from REV. B to REV. C.

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to Patent note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to INSULATION CHARACTERISTICS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changes to Package Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Changes to Method of Operation, DC Correctness, and Magnetic Field Immunity section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Replaced Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1/03—Data Sheet changed from REV. A to REV. B.

Added ADuM1100UR Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changed ADuM1100AR/ADuM1100BR to ADuM1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V Operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to VDE 0884 INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changes to Package Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Updated TPCs 3–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Deleted iCoupler in Field Bus Networks section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Added a new Figure 9 and related text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

11/02—Data Sheet changed from REV. 0 to REV. A.

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to VDE 0884 INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Added Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

–14–

REV. E

–15–

C02462–0–10/03(E)

–16–