Datasheet ADT7518 Datasheet (ANALOG DEVICES)

Page 1

SPI/I2C Compatible, Temperature Sensor,

4-Channel ADC and Quad Voltage Output DAC

FEATURES

Four 8-bit DACs Buffered voltage output Guaranteed monotonic by design over all codes 10-bit temperature-to-digital converter 10-bit 4-channel ADC

DC input bandwidth

Input range: 0 V to 2.25 V Temperature range: –40°C to +120°C Temperature sensor accuracy of typ: ±0.5°C Supply range: 2.7 V to 5.5 V DAC output range: 0 V to 2 V Power-down current: 1 µA Internal 2.25 V

option

REF

Double-buffered input logic Buffered reference input Power-on reset to 0 V DAC output Simultaneous update of outputs (

On-chip rail-to-rail output buffer amplifier

, I2C®, QSPI™, MICROWIRE™, and DSP-compatible

SPI

4-wire serial interface SMBus packet error checking (PEC)-compatible 16-lead QSOP package

GENERAL DESCRIPTION

The ADT7518 combines a 10-bit temperature-to-digital converter, a 10-bit 4-channel ADC, and a quad 8-bit DAC, in a 16-lead QSOP package. The part also includes a band gap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25°C.

The ADT7518 operates from a single 2.7 V to 5.5 V supply. The input voltage range on the ADC channels is 0 V to 2.25 V, and the input bandwidth is dc. The reference for the ADC channels is derived internally. The output voltage of the DAC ranges from 0 V to V typical.

The ADT7518 provides two serial interface options: a 4-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards, and a 2-wire SMBus/I It features a standby mode that is controlled through the serial interface.

, with an output voltage settling time of 7 ms

REF

LDAC

function)

C interface.

ADT7518

APPLICATIONS

Portable battery-powered instruments Personal computers Smart battery chargers Telecommunications systems Electronic text equipment Domestic appliances Process control

PIN CONFIGURATION

-B

OUT

-A

OUT

-IN

REF

D+/AIN1 D–/AIN2

GND

ADT7518

TOP VIEW

(Not to Scale)

6 7 8

Figure 1.

The reference for the four DACs is derived either internally or from a reference pin. The outputs of all DACs may be updated simultaneously using the software LDAC function or the exter-

LDAC

nal

pin. The ADT7518 incorporates a power-on reset circuit, which ensures that the DAC output powers up to 0 V and remains there until a valid write takes place.

The ADT7518’s wide supply voltage range, low supply current,

and SPI-/I

C-compatible interface make it ideal for a variety of applications, including personal computers, office equipment, and domestic appliances.

It is recommended that new designs use the ADT7519 rather than the ADT7518. The ADT7518’s internal and external temperature accuracy spec is only valid when not using the internal reference for the on-chip DAC. The ADT7519 does not have this limitation.

OUT

AIN4

SCL/SCLK

SDA/DIN

DOUT/ADD

INT/INT

LDAC/AIN3

-C

-D

04879-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

ADT7518

TABLE OF CONTENTS

Specifications..................................................................................... 3

Conversion Speed....................................................................... 17

DAC AC Characteristics .............................................................. 6

Functional Block Diagram .............................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Functional Descriptions.......................... 9

Te r m in o l o g y .................................................................................... 10

Typical Performance Characteristics ........................................... 12

Theory of Operation ...................................................................... 17

Power-Up Calibration................................................................ 17

REVISION HISTORY

8/04—Data Sheet Changed from Rev. 0 to Rev. A

Updated Format...................................................................... Universal

Separate ADT7518 from

ADT7516/ADT7517/ADT7518 Data Sheet........................ Universal

Function Description—Voltage Output.................................. 18

Functional Description—Analog Inputs................................. 20

ADC Transfer Function............................................................. 21

Functional Description—Measurement.................................. 22

ADT7518 Registers .................................................................... 25

Serial Interface............................................................................ 33

SMBus Alert Response............................................................... 38

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

Change to Equation.............................................................................25

7/03—Revision 0: Initial Version

Rev. A | Page 2 of 40

Page 3

ADT7518

SPECIFICATIONS

Table 1. Temperature range is as follows: A version: –40°C to +120°C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless otherwise noted.

Parameter

DAC DC PERFORMANCE

Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic over all codes. Offset Error ±0.4 ±2 % of FSR Gain Error ±0.3 ±2 % of FSR Lower Deadband 20 65 mV

Upper Deadband 60 100 mV

Offset Error Drift Gain Error Drift4 –5 ppm of FSR/°C DC Power Supply Rejection Ratio4 –60 dB ∆VDD = ±10%. DC Crosstalk4 200 µV See Figure 5.

ADC DC ACCURACY Max VDD = 5 V.

Resolution 10 Bits Total Unadjusted Error (TUE) 2 3 % of FSR Offset Error ±0.5 % of FSR

Gain Error ±2 % of FSR ADC BANDWIDTH DC Hz ANALOG INPUTS

Input Voltage Range 0 2.25 V AIN1 to AIN4. C4 = 0 in Control Configuration 3. 0 V

DC Leakage Current ±1 µA

Input Capacitance 5 20 pF

Input Resistance 10 MΩ THERMAL CHARACTERISTICS6

INTERNAL TEMPERATURE SENSOR

Accuracy @ VDD = 3.3 V ±10% ±1.5 °C TA = 85°C. ±0.5 ±3 °C TA= 0°C to +85°C. ±2 ±5 °C TA = –40°C to +120°C.

Accuracy @ VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C. ±3 ±5 °C TA = –40°C to +120°C.

Resolution 10 Bits Equivalent to 0.25°C.

Long-Term Drift 0.25 °C Drift over 10 years if part is operated at 55°C. THERMAL CHARACTERISTICS6 EXTERNAL TEMPERATURE SENSOR

Accuracy @ VDD = 3.3 V ± 10% ±1.5 °C TA = 85°C. ±3 °C T ±5 °C T

Accuracy @ VDD = 5 V ± 5% ±2 ±3 °C TA = 0°C to +85°C. ±3 ±5 °C TA = –40°C to +120°C.

Resolution 10 Bits Equivalent to 0.25°C.

Output Source Current 180 µA High Level. 11 µA Low Level. THERMAL CHARACTERISTICS6

Thermal Voltage Output

8-Bit DAC Output

2,3

Min Typ Max Unit Conditions/Comments

Lower deadband exists only if offset error is negative. See Figure 8.

Upper deadband exists if V plus gain error is positive. See Figure 9.

–12 ppm of FSR/°C

V AIN1 to AIN4. C4 = 0 in Control Configuration 3.

Internal reference used. Averaging on.

External transistor = 2N3906.

= 0°C to +85°C.

= –40°C to +120°C.

Resolution 1 °C

= VDD and offset

REF

Rev. A | Page 3 of 40

Page 4

ADT7518

Parameter

17.58 mV/°C 0 V to 2 V

Min Typ Max Unit Conditions/Comments

Scale Factor 8.97 mV/°C 0 V to V

output. TA = –40°C to +120°C.

REF

output. TA = –40°C to +120°C.

REF

CONVERSION TIMES Single channel mode.

Slow ADC

VDD/AIN 11.4 ms Averaging (16 samples) on.

712 µs Averaging off.

Internal Temperature 11.4 ms Averaging (16 samples) on.

712 µs Averaging off.

External Temperature 24.22 ms Averaging (16 samples) on.

1.51 ms Averaging off. Fast ADC

VDD/AIN 712 µs Averaging (16 samples) on.

44.5 µs Averaging off.

Internal Temperature 2.14 ms Averaging (16 samples) on.

134 µs Averaging off.

External Temperature 14.25 ms Averaging (16 samples) on. 890 µs Averaging off. ROUND ROBIN UPDATE RATE5

Time to complete one measurement cycle through all channels.

Slow ADC @ 25°C

Averaging On 79.8 ms AIN1 and AIN2 are selected on Pins 7 and 8.

Averaging Off 4.99 ms AIN1 and AIN2 are selected on Pins 7 and 8.

Averaging On 94.76 ms D+ and D– are selected on Pins 7 and 8.

Averaging Off 9.26 ms D+ and D– are selected on Pins 7 and 8.

Fast ADC @ 25°C

Averaging On 6.41 ms AIN1 and AIN2 are selected on Pins 7 and 8.

Averaging Off 400.84 µs AIN1 and AIN2 are selected on Pins 7 and 8.

Averaging On 21.77 ms D+ and D– are selected on Pins 7 and 8.

Averaging Off 3.07 ms D+ and D– are selected on Pins 7 and 8. DAC EXTERNAL REFERENCE INPUT4

Input Range 1 V

REF

Input Impedance >10 MΩ Buffered reference and power-down mode.

REF

V Buffered reference.

Reference Feedthrough –90 dB Frequency = 10 kHz. Channel-to-Channel Isolation –75 dB Frequency = 10 kHz.

ON-CHIP REFERENCE

Reference Voltage4 2.25 V Temperature Coefficient4 80 ppm/°C

OUTPUT CHARACTERISTICS4

Output Voltage

0.001 VDD − 0.1 V

This is a measure of the minimum and maximum

drive capability of the output amplifier. DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA VDD = 5 V.

16 mA VDD = 3 V.

Power-Up Time 2.5 µs Coming out of power-down mode. VDD = 5 V.

5 µs Coming out of power-down mode. VDD = 3.3 V. DIGITAL INPUTS4

Input Current ±1 µA VIN = 0 V to V

DD.

VIL, Input Low Voltage 0.8 V VIH, Input High Voltage 1.89 V Pin Capacitance 3 10 pF All digital inputs. SCL, SDA Glitch Rejection 50 ns

Input filtering suppresses noise spikes of less

than 50 ns. LDAC Pulse Width

20 ns Edge triggered input.

Rev. A | Page 4 of 40

Page 5

ADT7518

Parameter

Min Typ Max Unit Conditions/Comments

DIGITAL OUTPUT

Digital High Voltage, V Output Low Voltage, V Output High Current, I Output Capacitance, C

OUT

INT/INT Output Saturation Voltage

I2C TIMING CHARACTERISTICS 8,

Serial Clock Period, t

2.4 V I

SOURCE

= I

= 200 µA.

SINK

0.4 V IOL = 3 mA. 1 mA V

= 5 V.

50 pF

0.8 V I

= 4 mA.

OUT

2.5 µs Fast Mode I2C. See Figure 2. Data In Setup Time to SCL High, t250 ns Data Out Stable after SCL Low, t SDA Low Setup Time to SCL

Low (Start Condition), t

SDA High Hold Time after SCL High (Stop Condition), t

SDA and SCL Fall Time, t

SPI TIMING CHARACTERISTICS4,

CS to SCLK Setup Time, t SCLK High Pulse Width, t SCLK Low Pulse Width, t Data Access Time after SCLK

Falling Edge, t

Data Setup Time Prior to SCLK Rising Edge, t

Data Hold Time after SCLK Rising Edge, t

CS to SCLK Hold Time, t

CS to DOUT High Impedance, t

0 ns See Figure 2.

50 ns See Figure 2.

90 ns See Figure 2.

0 ns See Figure 3. 50 ns See Figure 3.

50 ns See Figure 3. 35 ns

20 ns See Figure 3.

0 ns See Figure 3.

0 µs See Figure 3. 40 ns See Figure 3.

POWER REQUIREMENTS

2.7 5.5 V VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level. IDD (Normal Mode)

3 mA V

= 3.3 V, VIH = VDD, and VIL = GND.

2.2 3 mA VDD = 5 V, VIH = VDD, and VIL = GND. IDD (Power-Down Mode) 10 µA VDD = 3.3 V, VIH = VDD, and VIL = GND.

10 µA VDD = 5 V, VIH = VDD, and VIL = GND.

Power Dissipation 10 mW VDD = 3.3 V. Normal mode.

33 µW VDD = 3.3 V. Shutdown mode.

See the section. Terminology

DC specifications are tested with the outputs unloaded.

Linearity is tested using a reduced code range: ADT7518 (Code 8 to 255).

Guaranteed by design and characterization, not production tested.

Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.

The temperature accuracy specifications are valid when the internal reference is not being used by the on-chip DAC. For new designs, the ADT7519 is recommended

as it does not have this limitation.

For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (V

plus gain error must be positive.

The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate

but has a negative effect on the EMC behavior of the part.

Guaranteed by design, not production tested.

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.

Measured with the load circuit shown in Figure 4.

The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.

= VDD), the offset

REF

Rev. A | Page 5 of 40

Page 6

ADT7518

DAC AC CHARACTERISTICS1

Table 2. VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND; CL = 200 pF to GND; 4.7 kΩ to VDD; all specifications T otherwise noted.

Parameter

Min Typ

Output Voltage Settling Time V

Max Unit Conditions/Comments

= VDD = 5 V

REF

ADT7518 6 8 µs 1/4 scale to 3/4 scale change (40h to C0h) Slew Rate 0.7 V/µs Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 1 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion –70 dB V

= 2 V ±0.1 V p-p

REF

= 2.5 V ±0.1 V p-p. Frequency = 10 kHz.

REF

Guaranteed by design and characterization, not production tested.

See the section. Terminology

@ 25°C.

SCL

04879-002

SDA

DATA IN

SDA

DATA OU

Figure 2. I

C Bus Timing Diagram

MIN

to T

MAX

, unless

SCLK

DIN

DOUT

XXXXXXXXD7D6D5D4D3D2D1 D0

D6 D5 D4 D3 D2 D1 D0 X X X X X X X X

Figure 3. SPI Bus Timing Diagram

TO OUTPUT

200µAI

50pF

200µAI

1.6V

04879-004

Figure 4. Load Circuit for Access Time and Bus Relinquish Time

TO DAC

UTPUT

4.7kΩ

200pF

04879-005

Figure 5. Load Circuit for DAC Outputs

04879-003

Rev. A | Page 6 of 40

Page 7

ADT7518

FUNCTIONAL BLOCK DIAGRAM

INTERNAL

D+/AIN1 D–/AIN2

LDAC/AIN3

AIN4

7 8 9

ON-CHIP

TEMPERATURE

SENSOR

ANALOG

MUX

SENSOR

TEMPERATURE

VALUE REGISTER

EXTERNAL

TEMPERATURE

VALUE REGISTER

A-TO-D

CONVERTER

VALUE REGISTER

AIN1

VALUE REGISTER

AIN2

VALUE REGISTER

AIN3

VALUE REGISTER

AIN4

VALUE REGISTER

COMPARATOR

DIGITAL MUX

LIMIT

STATUS

REGISTERS

ADDRESS POINTER

HIGH

REGISTERS

LOW

REGISTERS

VCCLIMIT

REGISTERS

AIN

DIGITAL MUX

SPI/SMBus INTERFACE

HIGH

REGISTERS

AIN

LOW

REGISTERS

CONTROL CONFIG. 1

CONTROL CONFIG. 2

CONTROL CONFIG. 3

DAC CONFIGURATION

REGISTERS

LDAC CONFIGURATION

REGISTERS

INTERRUPT MASK

REGISTERS

LIMIT

REGISTERS

DAC A

DAC B

DAC C

DAC D

ADT7518

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN

SELECT

LOGIC

POWER-

DOWN LOGIC

INTERNAL

REFERENCE

OUT

INT/INT

-A

-B

-C

-D

GND

SCL

SDA

ADD

LDAC/AIN33V

REF

-IN

04879-006

Figure 6.

Rev. A | Page 7 of 40

Page 8

ADT7518

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V Analog Input Voltage to GND –0.3 V to VDD + 0.3 V Digital Input Voltage to GND –0.3 V to VDD + 0.3 V Digital Output Voltage to GND –0.3 V to VDD + 0.3 V Reference Input Voltage to GND –0.3 V to VDD + 0.3 V Operating Temperature Range –40°C to +120°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 16-Lead QSOP Package

Power Dissipation

Thermal Impedance

Junction-to-Ambient 105.44°C/W

Junction-to-Case 38.8°C/W

IR Reflow Soldering

Peak Temperature 220°C (0°C/5°C)

Time at Peak Temperature 10 sec to 20 sec

Ramp-Up Rate 2°C/sec to 3°C/sec

Ramp-Down Rate –6°C/sec

(TJ max – TA)/θ

Table 4. I

C Address Selection

ADD Pin I2C Address

Low 1001 000 Float 1001 010 High 1001 011

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Values relate to package being used on a 4-layer board.

Junction-to-case resistance is applicable to components featuring a

preferential flow direction, e.g., components mounted on a heat sink. Junction-to-ambient resistance is more useful for air cooled PCB-mounted components.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 40

Page 9

ADT7518

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

-B

OUT

-A

OUT

-IN

REF

D+/AIN1 D–/AIN2

GND

ADT7518

TOP VIEW

(Not to Scale)

6 7 8

Figure 7. Pin Configuration QSOP

Table 5. Pin Function Descriptions

Pin No.

Mnemonic Description

1 V 2 V 3 V 4

-B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

-IN Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to VDD.

REF

CS SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables

the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial

clocks. It is recommended that this pin be tied high to V 5 GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground. 6 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. 7 D+/AIN1

8 D–/AIN2

D+. Positive Connection to External Temperature Sensor. AIN1. Analog Input. Single-ended analog input channel.

Input range is 0 V to 2.25 V or 0 V to V

D–. Negative Connection to External Temperature Sensor.

AIN2. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V 9

LDAC/AIN3 LDAC. Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A

falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum

pulse width of 20 ns must be applied to the

LDAC pin to ensure proper loading of a DAC register. This allows simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the with the

LDAC pin controlling the loading of the DAC registers.

AIN3. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V

11 DOUT/ADD

INT Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when

INT/

temperature,V

, or AIN limits are exceeded. The default is active low. Open-drain output—needs a pull-up resistor.

SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling edge of SCLK. Open-drain output—needs a pull-up resistor.

C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000; leaving it floating

ADD. I gives the address 1001 010; and setting it high gives the address 1001 011. The I not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent changes on this pin will have no effect on the

C serial bus address.

12 SDA/DIN

C Serial Data Input/Output. I2C serial data to be loaded into the part’s registers and read from these registers is

SDA. I provided on this pin. Open-drain configuration—needs a pull-up resistor. DIN. SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this pin. Data is clocked into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.

13 SCL/SCLK

Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of the ADT7518 and also to clock data into any register that can be written to. Open-drain configuration—needs a pullup resistor.

14 AIN4 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. 15 V 16 V

-D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

-C

OUT

-D

OUT

AIN4

SCL/SCLK

SDA/DIN

DOUT/ADD

INT/INT

LDAC/AIN3

when operating the serial interface in I2C mode.

04879-007

C address set up by the ADD pin is

LDAC pin. Default is

Rev. A | Page 9 of 40

Page 10

ADT7518

TERMINOLOGY

Relative Accuracy

Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the transfer function. Typical INL versus code plots can be seen in Figure 10, Figure 11, and Figure 12.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±0.9 LSB maximum ensures monotonicity. Typical DAC DNL versus code plots can be seen in Figure 13, Figure 14, and Figure 15.

Total Unadjusted Error (TUE)

Total unadjusted error is a comprehensive specification that includes the sum of the relative accuracy error, gain error, and offset error under a specified set of conditions.

Offset Error

This is a measure of the offset error of the DAC and the output amplifier (see Figure 8 and Figure 9). It can be negative or positive, and it is expressed in mV.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.

Gain Error Match

This is the difference in gain error between any two channels.

Offset Error Drift

This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Lo ng Ter m Tempera ture Drif t

This is a measure of the change in temperature error over time. It is expressed in °C. The concept of long-term stability has been used for many years to describe the amount an IC’s parameter shifts during its lifetime. This is a concept that has typically been applied to both voltage references and monolithic temperature sensors. Unfortunately, integrated circuits cannot be evaluated at room temperature (25°C) for 10 years or so to determine this shift. Manufacturers perform accelerated lifetime testing of integrated circuits by operating ICs at elevated temperatures (between 125°C and 150°C) over a shorter period (typically between 500 and 1,000 hours). As a result, the lifetime of an integrated circuit is significantly accelerated due to the

increase in rates of reaction within the semiconductor material.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V a change in V in dB. V

for full-scale output of the DAC. It is measured

is held at 2 V and VDD is varied ±10%.

REF

OUT

DC Crosstalk

This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in µV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dB.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011...1 to 100...00 or

100...00 to 011...11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to. It is specified in nV-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change

LDAC

(all 0s to all 1s and vice versa) while keeping

LDAC

pulse

low and monitor the output of the DAC whose

high. Then

digital code was not changed. The area of the glitch is expressed in nV-s.

Rev. A | Page 10 of 40

Page 11

ADT7518

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code

LDAC

change (all 0s to all 1s and vice versa) with

low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output, expressed in dB.

Round Robin

This term is used to describe the ADT7518 cycling through the available measurement channels in sequence, taking a measurement on each channel.

DAC Output Settling Time

This is the time required, following a prescribed data change, for the output of a DAC to reach and remain within ±0.5 LSB of the final value. A typical prescribed change is from 1/4 scale to 3/4 scale.

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

LOWER

DEADBAND

CODES

DAC CODE

Figure 8. DAC Transfer Function with Negative Offset

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

Figure 9. DAC Transfer Function with Positive Offset (V

DAC CODE FULL SCALE

GAIN ERROR

OFFSET ERROR

ACTUAL IDEAL

GAIN ERROR

OFFSET ERROR

UPPER DEADBAND CODES

ACTUAL IDEAL

REF

= VDD)

04879-008

04879-009

Rev. A | Page 11 of 40

Page 12

ADT7518

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

0.05

–0.05

INL ERROR (LSB)

–0.10

–0.15

–0.20

0 50 100 150 200 250

DAC CODE

Figure 10. ADT7518 Typical DAC INL Plot

04879-010

0.14

0.12

0.10

0.08

0.06

0.04

0.02

ERROR (LSB)

–0.02

–0.04

–0.06

–40 110805020–10

INL WCP

INL WCN

DNL WCP

DNL WCN

TEMPERATURE (°C)

Figure 13. ADT7518 DAC INL Error and DNL Error vs. Temperature

04879-013

0.10

0.08

0.06

0.04

0.02

–0.02

DNL ERROR (LSB)

–0.04

–0.06

–0.08

–0.10

0 50 100 150 200 250

DAC CODE

Figure 11. ADT7518 Typical DAC DNL Plot

0.30

0.25

0.20

0.15

0.10

0.05

ERROR (LSB)

–0.05

–0.10

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

INL WCP

DNL WCP

DNL WCN

INL WCN

(V)

REF

Figure 12. ADT7518 DAC INL and DNL Error vs, V

–0.2

OFFSET ERROR

GAIN ERROR

TEMPERATURE (°C)

04879-014

04879-011

–0.4

–0.6

–0.8

–1.0

ERROR (LSB)

–1.2

–1.4

–1.6

–1.8

–40 120100806040200–20

Figure 14. DAC Offset Error and Gain Error vs. Temperature

–5

ERROR (LSB)

–10

GAIN ERROR

04879-012

–15

–20

2.7 3.3 3.6 4.0

REF

Figure 15. DAC Offset Error and Gain Error vs. V

OFFSET ERROR

(V)

4.5 5.0

REF

= 2.25V

5.5

04879-015

Rev. A | Page 12 of 40

Page 13

ADT7518

2.505

2.500

2.495

2.490

2.485

2.480

DAC OUTPUT (V)

2.475

VDD=5V

=5V

REF

DAC OUTPUT

2.470 LOADED TO MIDSCALE

2.465

0123

Figure 16. DAC V

–0.2

–0.4

–0.6

–0.8

–1.0

ERROR (LSB)

–1.2

–1.4

–1.6

–1.8

–40 120100806040200–20

CURRENT (mA)

Source and Sink Current Capability

OUT

TEMPERATURE (

Figure 17. Supply Current vs. DAC Code

SOURCE CURRENT

SINK CURRENT

OFFSET ERROR

GAIN ERROR

04879-016

04879-017

(mA)

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 (V)

Figure 19. Power-Down Current vs. Supply Voltage @ 25°C

4.0

3.5

3.0

2.5

2.0

1.5

DAC OUTPUT (V)

1.0

0.5

02 4681

TIME (µs)

Figure 20. DAC Half-Scale Settling (1/4 to 3/4 Scale Code Change)

04879-019

04879-020

2.00 ADC OFF

DAC OUTPUTS AT 0V

1.95

1.90

(mA)

1.85

1.80

1.75

2.7 3.1 3.5 3.9 4.3 4.7 5.12.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5 (V)

Figure 18. Supply Current vs. Supply Voltage @ 25°C

04879-018

Rev. A | Page 13 of 40

1.8

1.6

1.4

1.2

1.0

0.8

DAC OUTPUT (V)

0.6

0.4

0.2 0

024

Figure 21. Exiting Power-Down to Midscale

TIME (µs)

04879-021

Page 14

ADT7518

0.4700

0.4695

0.4690

0.4685

0.4680

0.4675

0.4670

DAC OUTPUT (V)

0.4665

0.4660

0.4655

0.4650 02 4681

Figure 22. ADT7518 DAC Major Code Transition Glitch Energy;

TIME (µs)

0...11 to 100...00

04879-022

2.329 VDD= 5V

= 5V

REF

2.328

DAC OUTPUT LOADED TO MIDSCALE

2.327

2.326

2.325

DAC OUTPUT (V)

2.324

2.323

2.322

012 34

TIME (µs)

Figure 25. DAC-to-DAC Crosstalk

04879-025

0.4730

0.4725

0.4720

0.4715

0.4710

0.4705

DAC OUTPUT (V)

0.4700

0.4695

0.4690

0.4685 02 46810

TIME (µs)

Figure 23. ADT7518 DAC Major Code Transition Glitch Energy;

100…00 to 011…11

–2

–4

–6

–8

FULL-SCALE ERROR (mV)

–10

VDD=5V T

=25°C

04879-023

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 200 400 600 800 1000

Figure 26. ADC INL with Ref = V

±100mV RIPPLE ON V V

= 2.25V

REF

–10

= 3.3V

TEMPERATURE = 25°C

–20

–30

AC PSRR (dB)

–40

–50

ADC CODE

(3.3 V)

04879-026

–12

12 3

(V)

REF

Figure 24. DAC Full-Scale Error vs. V

04879-024

REF

Rev. A | Page 14 of 40

–60

1 10 100

FREQUENCY (kHz)

Figure 27. PSRR vs. Supply Ripple Frequency

04879-027

Page 15

ADT7518

1.5 EXTERNAL TEMPERATURE @ 5V

1.0

0.5

TEMPERATURE ERROR (

–0.5

–1.0

INTERNAL TEMPERATURE @ 3.3V

INTERNAL TEMPERATURE @ 5V

–30 0 40 85 120

EXTERNAL TEMPERATURE @ 3.3V

TEMPERATURE (°C)

Figure 28. Internal Temperature Error @ 3.3 V and 5 V

04879-028

–5

–10

–15

TEMPERATURE ERROR (°C)

–20

–25

01020

D+ TO GND

D+ TO V

30 40 50 60 70 80 90 100

PCB LEAKAGE RESISTANCE (MΩ)

VDD=3.3V TEMPERATURE = 25°C

Figure 31. External Temperature Error vs. PCB Leakage Resistance

04879-031

=3.3V

–1

ERROR (LSB)

–2

–3

–4

–40 –20 0

OFFSET ERROR

GAIN ERROR

20 40 60 80 100 120

TEMPERATURE (°C)

Figure 29. ADC Offset Error and Gain Error vs. Temperature

ERROR (LSB)

–1

–2

–3

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

Figure 30. ADC Offset Error and Gain Error vs. V

OFFSET ERROR

GAIN ERROR

VDD (V)

04879-029

04879-030

–10

–20

–30

–40

TEMPERATURE ERROR (°C)

–50

–60

0 5 10 15 20 25

CAPACITANCE (nF)

30 35 40 45 50

VDD=3.3V

04879-032

Figure 32. External Temperature Error vs. Capacitance between D+ and D–

VDD = 3.3V COMMON-MODE

VOLTAGE = 100mV

–2

TEMPERATURE ERROR (°C)

–4

–6

1 100 200 300 400 500 600

NOISE FREQUENCY (Hz)

04879-033

Figure 33. External Temperature Error vs. Common-Mode Noise Frequency

Rev. A | Page 15 of 40

Page 16

ADT7518

TEMPERATURE ERROR (°C)

–10

1 100 200

NOISE FREQUENCY (MHz)

Figure 34. External Temperature Error vs. Differential-Mode Noise Frequency

VDD = 3.3V DIFFERENTIAL-MODE VOLTAGE = 100mV

300 400 500 600

04879-034

140

120

100

TEMPERATURE (

EXTERNAL TEMPERATURE

10 20

INTERNAL TEMPERATURE

NME

I N

30 40 50

TIME (s)

Figure 36. Temperature Sensor Response to Thermal Shock

04879-036

0.6 VDD = 3.3V

0.4

0.2

–0.2

TEMPERATURE ERROR (°C)

–0.4

–0.6

1 100 200 300 400 500 600

±250mV

NOISE FREQUENCY (Hz)

04879-035

Figure 35. Internal Temperature Error vs. Power Supply Noise Frequency

–5

–10

–15

ATTENUATION (dB)

–20

–25

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

04879-037

Figure 37. DAC Multiplying Bandwidth (Small Signal Frequency Response)

Rev. A | Page 16 of 40

Page 17

ADT7518

THEORY OF OPERATION

Directly after the power-up calibration routine, the ADT7518 goes into idle mode. In this mode, the device is not performing any measurements and is fully powered up. All four DAC outputs are at 0 V.

To begin monitoring, write to the Control Configuration 1 register (Address 18h) and set Bit C0 = 1. The ADT7518 goes into its power-up default measurement mode, which is round robin. The device then to take measurements on the V

channel, internal temperature sensor channel, external temperature sensor channel, or AIN1 and AIN2, AIN3, and finally AIN4.

Once it finishes taking measurements on the AIN4 channel, the device immediately loops back to start taking measurements on

channel and repeats the same cycle as before. This loop

the V

continues until the monitoring is stopped by resetting Bit C0 of the Control Configuration 1 register to 0. It is also possible to continue monitoring as well as switching to single-channel mode by writing to the Control Configuration 2 register (Address 19h) and setting Bit C4 = 1. Further explanation of the single-channel and round robin measurement modes is given in later sections.

All measurement channels have averaging enabled on them on power-up. Averaging forces the device to take an average of 16 readings before giving a final measured result. To disable averaging and consequently decrease the conversion time by a factor of 16, set Bit C5 = 1 in the Control Configuration 2 register.

There are four single-ended analog input channels on the ADT7518: AIN1 to AIN4. AIN1 and AIN2 are multiplexed with the external temperature sensor terminals D+ and D–. Bits C1 and C2 of the Control Configuration 1 register (Address 18h) are used to select between AIN1/AIN2 and the external temperature sensor. The input range on the analog input channels is dependent on whether the ADC reference used is the internal V recommended that the maximum V

or VDD. To meet linearity specifications, it is

REF

value is 5 V. Bit C4 of the

Control Configuration 3 register is used to select between the internal reference or V

as the analog inputs’ ADC reference.

Controlling the DAC outputs can be done by writing to the DACs’ MSB and LSB registers (Addresses 10h to 17h). The power-up default setting is to have a low going pulse on the

pin (Pin 9) controlling the updating of the DAC outputs

LDAC from the DAC registers. Alternatively, one can configure the updating of the DAC outputs to be controlled by means other than the

pin by setting Bit C3 = 1 of the Control Config-

LDAC uration 3 register (Address 1Ah). The DAC Configuration register (Address 1Bh) and the LDAC Configuration register (Address 1Ch) can now be used to control the DAC updating. These two registers also control the output range of the DACs and selecting between the internal or external reference. DAC A

and DAC B outputs can be configured to give a voltage output proportional to the temperature of the internal and external temperature sensors, respectively.

The dual serial interface defaults to the I

C protocol on powerup. To select and lock in the SPI protocol, follow the selection process as described in the Serial Interface Selection section.

C protocol cannot be locked in, while the SPI protocol is

The I automatically locked in on selection. The interface can be

switched back to be I off and on. When using I

or GND.

C on selection when the device is powered

C, the CS pin should be tied to either

There are a number of different operating modes on the ADT7518 devices and all of them can be controlled by the configuration registers. These features consist of enabling and disabling interrupts, polarity of the INT/

INT

pin, enabling and disabling the averaging on the measurement channels SMBus timeout and software reset.

POWER-UP CALIBRATION

It is recommended that no communication to the part be initiated until approximately 5 ms after V

has settled to within

10% of its final value. It is generally accepted that most systems take a maximum of 50 ms to power up. Power-up time is directly related to the amount of decoupling on the voltage supply line.

During the 5 ms after V

has settled, the part is performing a

calibration routine. Any communication to the device during calibration will interrupt this routine, and could cause erroneous temperature measurements. If it is not possible to have

at its nominal value by the time 50 ms has elapsed or if

communication to the device has started prior to V is recommended that a measurement be taken on the V nel before a temperature measurement is taken. The V

settling, it

chan-

measurement is used to calibrate out any temperature measurement error due to different supply voltage values.

CONVERSION SPEED

The internal oscillator circuit used by the ADC has the capability to output two different clock frequencies. This means that the ADC is capable of running at two different speeds when doing a conversion on a measurement channel. Thus, the time taken to perform a conversion on a channel can be reduced by setting Bit C0 of the Control Configuration 3 register (Address 1Ah). This increases the ADC clock speed from 1.4 kHz to 22 kHz. At the higher clock speed, the analog filters on the D+ and D– input pins (external temperature sensor) are switched off. This is why the power-up default setting is to have the ADC working at the slow speed. The typical times for fast and slow ADC speeds are given in the specifications.

Rev. A | Page 17 of 40

Page 18

ADT7518

The ADT7518 powers up with averaging on. This means every channel is measured 16 times and internally averaged to reduce noise. The conversion time can also be sped up by turning off the averaging. This is done by setting Bit C5 of the Control Configuration 2 register (Address 19h) to 1.

FUNCTION DESCRIPTION—VOLTAGE OUTPUT

Digital-to-Analog Converters

The ADT7518 has four resistor string DACs fabricated on a CMOS process with resolutions of 12, 10, and 8 bits, respectively. They contain four output buffer amplifiers and are written to via I the Serial Interface section for more information.

The ADT7518 operates from a single supply of 2.7 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/µs. All four DACs share a common reference input, V draw virtually no current from the reference source because it offers the source a high impedance input. The devices have a power-down mode in which all DACs may be turned off completely with a high impedance output.

Each DAC output will not be updated until it receives the LDAC command. Therefore, while the DAC registers would have been written to with a new value, this value will not be represented by a voltage output until the DACs have received the LDAC command. Reading back from any DAC register prior to issuing an LDAC command will result in the digital value that corresponds to the DAC output voltage. Thus, the digital value written to the DAC register cannot be read back until after the LDAC command has been initiated. This LDAC command can be given by either pulling the

(falling edge loads DACs), setting up Bits D4 and D5 of the DAC configuration register (Address 1Bh), or using the LDAC register (Address 1Ch).

When using the

the low going pulse width should be 20 ns minimum. The

pin has to go high and low again before the DAC

LDAC registers can be reloaded.

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the V the reference voltage for the corresponding DAC. Figure 38 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by

OUT

C serial interface or SPI serial interface. See

-IN. The reference input is buffered to

REF

pin low

LDAC

pin to control the DAC register loading,

LDAC

-IN pin or the on-chip reference of 2.25 V provides

REF

where:

D = decimal equivalent of the binary code that is loaded to the DAC register: 0 to 255 for ADT7518 (8 bits) N = DAC resolution

Resistor String

The resistor string section is shown in Figure 39. It is simply a string of resistors, each of approximately 603 Ω. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

-IN

REF

REFERENCE BUFFER

INT V

INPUT

REF

DAC

Figure 38. Single DAC Channel Architecture

Figure 39. Resistor String

2.25V

INTERNAL V

Figure 40. DAC Reference Buffer Circuit

REF

RESISTOR

STRING

(GAIN = 1 OR 2)

OUTPUT BUFFER

TO OUTPUT AMPLIFIER

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN MODE

AMPLIFIER

04879-039

-IN

04879-040

-A

OUT

04879-038

Rev. A | Page 18 of 40

Page 19

ADT7518

DAC Reference Inputs

There is an input reference pin for the DACs. This reference input is buffered (see Figure 40).

The advantage with the buffered input is the high impedance it presents to the voltage source driving it. The user can have an external reference voltage as low as 1 V and as high as V

. The

restriction of 1 V is due to the footroom of the reference buffer.

LDAC

The

configuration register controls the option to select between internal and external voltage references. The default setting is for external reference selected.

Output Amplifier

The output buffer amplifier can generate output voltages to within 1 mV of either rail. Its actual range depends on the value

, gain, and offset error.

of V

REF

If a gain of 1 is selected (Bits 0 to 3 of the DAC configuration register = 0), the output range is 0.001 V to V

REF

If a gain of 2 is selected (Bits 0 to 3 of the DAC configuration register = 1), the output range is 0.001 V to 2 V clamping, however, the maximum output is limited to V

. Be cause of

REF

−

0.001 V.

The output amplifier can drive a load of 4.7 kΩ to GND or V in parallel with 200 pF to GND or V

(see Figure 5). The

source and sink capabilities of the output amplifier can be seen in the plot of Figure 16.

The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB (at 8 bits) of 6 µs.

Thermal Voltage Output

The ADT7518 can output voltages that are proportional to temperature. DAC A output can be configured to represent the temperature of the internal sensor while DAC B output can be configured to represent the external temperature sensor. Bits C5 and C6 of the Control Configuration 3 register select the temperature proportional output voltage. Each time a temperature measurement is taken, the DAC output is updated. The output resolution for the ADT7518 is 8 bits with a 1°C change corresponding to 1 LSB change. The default output range is 0 V to

and this can be increased to 0 V to 2 V

REF

output voltage span to 2 V

can be done by setting D0 = 1 for

REF

. Increasing the

REF

DAC A (internal temperature sensor) and D1 = 1 for DAC B (external temperature sensor) in the DAC configuration register (Address 1Bh).

The output voltage is capable of tracking a maximum temperature range of –128°C to +127°C, but the default setting is –40°C to +127°C. If the output voltage range is 0 V to V

-IN = 2.25 V), then this corresponds to 0 V representing

REF

-IN

–40°C, and 1.48 V representing +127°C. This, of course, will give an upper deadband between 1.48 V and V

REF

The internal and external analog temperature offset registers can be used to vary this upper deadband and, consequently, the temperature that 0 V corresponds to. Table 6 and Table 7 give examples of how this is done using a DAC output voltage span of V

and 2 V

REF

, respectively. Simply write in the temperature

REF

value, in twos complement format, at which 0 V is to start. For example, if using the DAC A output and 0 V to start at –40°C, program D8h into the internal analog temperature offset register (Address 21h). This is an 8-bit register and has a temperature offset resolution of only 1°C for all device models. Use the formulas following the tables to determine the value to program into the offset registers.

Table 6. Thermal Voltage Output (0 V to V

REF

)

O/P Voltage (V) Default °C Max °C Sample °C

0 –40 –128 0

0.5 +17 –71 +56 1 +73 –15 +113

1.12 +87 –1 +127

1.47 +127 +39

1.5 2

2.25

UDB UDB∗ UDB∗

∗

+42 +99

+127

UDB∗ UDB∗ UDB∗ UDB∗

∗ Upper deadband has been reached. DAC output is not capable of

increasing. See Fig . ure 9

I N × I I

OPTIONAL CAPACITOR, UP TO 3nF MAX. CAN BE ADDED TO IMPROVE HIGH FREQUENCY NOISE REJECTION IN NOISY ENVIRONMENTS

REMOTE

SENSING

TRANSISTOR

(2N3906)

Figure 41. Signal Conditioning for External Diode Temperature Sensor

D+ C1

D–

LOW-PASS

FILTER

= 65kHz

Rev. A | Page 19 of 40

DIODE

BIAS

OUT+

TO ADC

OUT–

04879-041

Page 20

ADT7518

(

)

(

)

()(

)

(

)

I N × I I

INTERNAL

SENSE

TRANSISTOR

Figure 42. Top Level Structure of Internal Temperature Sensor

BIAS

DIODE

Table 7. Thermal Voltage Output (0 V to 2 V

REF

)

O/P Voltage (V) Default °C Max °C Sample °C

0 –40 –128 0

0.25 –26 –114 +14

0.5 +12 –100 +28

0.75 +3 –85 +43 1 +17 –71 +57

1.12 +23 –65 +63

1.47 +43 –45 +83

1.5 +45 –43 +85 2 +73 –15 +113

2.25 +88 0 +127

2.5 +102 +14 UDB*

2.75 +116 +28 UDB* 3 UDB* +42 UDB*

3.25 UDB* +56 UDB*

3.5 UDB* +70 UDB*

3.75 UDB* +85 UDB* 4 UDB* +99 UDB*

4.25 UDB* +113 UDB*

4.5 UDB* +127 UDB*

* Upper deadband has been reached. DAC output is not capable of increasing.

See Figure 9.

Negative temperatures:

()

1280Re += TempVdCodegisterOffset

where: D7 of Offset Register Code is set to 1 for negative temperatures.

Example:

()

58h d8812840dRe ==+−=CodegisterOffset

Since a negative temperature has been inserted into the equation, DB7 (MSB) of the offset register code is set to 1. Therefore 58h becomes D8h.

58h + DB7(1) = D8h

Positive temperatures:

Offset Register Code (d) = 0 V Temp

BIAS

OUT+

TO ADC

OUT–

04879-042

Example:

Offset Register Code (d) = 10d = 0Ah

The following equation is used to work out the various temperatures for the corresponding 8-bit DAC output:

TempVLSBPODACTempBit- 01/8 +

For example, if the output is 1.5 V, V has an LSB size = 2.25 V/256 = 8.79 x 10

-IN = 2.25 V, 8-bit DAC

REF

–3

, and 0 V temperature

is at –128°C, then the resultant temperature is

−

()

C°+=−+×÷

431281079.85.1

Figure 43 shows a graph of the DAC output versus temperature for a V

-IN = 2.25 V.

REF

2.25

2.10

1.95

1.80

1.65

1.50

1.35

1.20

1.05

0.90

DAC OUTPUT (V)

0.75

0.60

0.45

0.30

0.15 0

–128–110 –90 –70 –50 –30 –10 10 30 50 70 90 110 127

Figure 43. DAC Output vs. Temperature V

TEMPERATURE (°C)

0V = –128°C

0V = –40°C

REF

0V = 0°C

-IN = 2.25 V

FUNCTIONAL DESCRIPTION—ANALOG INPUTS

Single-Ended Inputs

The ADT7518 offers four single-ended analog input channels. The analog input range is from 0 V to 2.25 V, or 0 V to V maintain the linearity specification, it is recommended that the maximum V input ranges is done by Bit C4 of the Control Configuration 3 register (Address 1Ah). Setting this bit to 0 sets up the analog input ADC reference to be sourced from the internal voltage reference of 2.25 V. Setting the bit to 1 sets up the ADC reference to be sourced from V

value be set at 5 V. Selection between the two

04879-043

. To

Rev. A | Page 20 of 40

Page 21

ADT7518

The ADC resolution is 10 bits and is mostly suitable for dc input signals. Bits C1:2 of the Control Configuration 1 register (Address 18h) are used to set up Pins 7 and 8 as AIN1 and AIN2. Figure 44 shows the overall view of the 4-channel analog input path.

AIN1

AIN2

AIN3

AIN4

U L T

I P L E X E R

10-BIT

ADC

TO ADC VALUE REGISTER

04879-044

Figure 44. Quad Analog Input Path

Converter Operation

The analog input channels use a successive approximation ADC based on a capacitor DAC. Figure 45 and Figure 46 show simplified schematics of the ADC. Figure 45 shows the ADC during acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on AIN.

REF

04879-045

04879-046

INT V

REF

SAMPLING

CAPACITOR

SW1

SW2

REF/2

ACQUISITION

COMPARATOR

PHASE

CAP DAC

CONTROL

LOGIC

Figure 45. ADC Acquisition Phase

INT V

REF

SAMPLING

CAPACITOR

SW1

SW2

REF/2

CONVERSION

COMPARATOR

PHASE

CAP DAC

CONTROL

LOGIC

Figure 46. ADC Conversion Phase

When the ADC eventually goes into conversion phase (see Figure 46), SW2 opens and SW1 moves to position B, causing the comparator to become unbalanced. The control logic and the DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 47 shows the ADC transfer function for the analog inputs.

ADC TRANSFER FUNCTION

The output coding of the ADT7518 analog inputs is straight binary. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB). The LSB is

/1024 or internal V

transfer characteristic is shown in Figure 47.

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

Figure 47. Single-Ended Transfer Function

To work out the voltage on any analog input channel, the following method can be used:

1 LSB = reference (v)/1024

Convert the value read back from the AIN value register into a decimal format.

d = decimal

Example:

Internal reference used. Therefore V

AIN value = 512d

Analog Input ESD Protection

Figure 48 shows the input structure on any of the analog input pins that provides ESD protection. The diode provides the main ESD protection for the analog inputs. Care must be taken that the analog input signal never drops below the GND rail by more than 200 mV. If this happens, the diode will become forward-biased and start conducting current into the substrate. The 4 pF capacitor is the typical pin capacitance and the resistor is a lumped component made up of the on-resistance of the multiplexer switch.

/1024, internal V

REF

4pF

1LSB = INT V 1LSB = V

ANALOG INPUT

()

−

REF

sizeLSBdvalueAINvoltageAIN ×

= 2.25 V.

REF

10197.21024/25.21

×== VsizeLSB

=××=

100Ω

= 2.25 V. The ideal

REF

/1024

REF

/1024

– 1LSB0V 1/2LSB

−

VvoltageAIN 125.110197.2512

04879-047

04879-048

Figure 48. Equivalent Analog Input ESD Circuit

Rev. A | Page 21 of 40

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ADT7518

S/W RESET

WATCHDOG

LIMIT

COMPARISONS

READ RESET

INTERRUPT

STATUS

(TEMP AND

AIN1 TO AIN4)

STATUS BITSSTATUS BIT

INTERRUPT

STATUS

)

INTERRUPT

MASK

REGISTERS

CONTROL

CONFIGURATION

Figure 49. Interrupt Structure

AIN Interrupts

The measured results from the AIN inputs are compared with the AIN V

(greater than comparison) and V

HIGH

(less than or

LOW

equal to comparison) limits. An interrupt occurs if the AIN inputs exceed or equal the limit registers. These voltage limits are stored in on-chip registers. Note that the limit registers are 8 bits long while the AIN conversion result is 10 bits long. If the voltage limits are not masked out, then any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register (Address = 00h) and one or more out-of-limit results will cause the INT/

output to pull either high or low

INT

depending on the output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application. Figure 49 shows the interrupt structure for the ADT7518. It gives a block diagram representation of how the various measurement channels affect the INT/

INT

pin.

FUNCTIONAL DESCRIPTION—MEASUREMENT

Temperat ure S ensor

The ADT7518 contains an ADC with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. When the ADT7518 is operating in single-channel mode, the ADC continually processes the measurement taken on one channel only. This channel is preselected by Bits C0:C2 in the Control Configuration 2 register (Address 19h). When in round robin mode, the analog input multiplexer sequentially selects the V on-chip temperature sensor to measure its internal temperature, either the external temperature sensor or AIN1 and AIN2, AIN3, and then AIN4. These signals are digitized by the ADC and the results are stored in the various value registers.

input channel, the

INTERNAL TEMP

EXTERNAL TEMP

INT/INT

DIODE FAULT

AIN1–AIN4

ENABLE BIT

INT/INT

04879-049

(LATCHED OUTPUT)

The measured results from the temperature sensors are compared with the internal and external T

HIGH

, T

LOW

limits. These temperature limits are stored in on-chip registers. If the temperature limits are not masked, any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register. One or more out-of-limit results will cause the INT/

INT

output

to pull either high or low depending on the output polarity setting.

Theoretically, the temperature measuring circuit can measure temperatures from –128°C to +127°C with a resolution of

0.25°C. However, temperatures outside T

are outside the

guaranteed operating temperature range of the device. Temperature measurement from –128°C to +127°C is possible using an external sensor.

Temperature measurement is initiated by three methods. The first method is applicable when the part is in single-channel measurement mode. The temperature is measured 16 times and internally averaged to reduce noise. In single-channel mode, the part is continuously monitoring the selected channel, i.e., as soon as one measurement is taken another one is started on the same channel. The total time to measure a temperature channel with the ADC operating at slow speed is typically 11.4 ms (712 µs × 16) for the internal temperature sensor and 24.22 ms (1.51 ms × 16) for the external temperature sensor. The new temperature value is stored in two 8-bit registers and is ready

for reading by the I

C or SPI interface. The user has the option of disabling the averaging by setting Bit 5 in the Control Configuration 2 register (Address 19h). The ADT7518 defaults on power-up with averaging enabled.

Rev. A | Page 22 of 40

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ADT7518

The second method is applicable when the part is in round robin measurement mode. The part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round robin mode, the part continuously measures all channels.

Temperature measurement is also initiated after every read or write to the part when the part is in either single-channel measurement mode or round robin measurement mode.

Once serial communication has started, any conversion in progress is stopped and the ADC is reset. Conversion starts again immediately after the serial communication has finished. The temperature measurement proceeds normally as described in the preceding section.

Monitoring

The ADT7518 also has the ability to monitor its own power supply. The part measures the voltage on its V

pin to a

resolution of 10 bits. The resulting value is stored in two 8-bit registers; the two LSBs are stored in register address 03h and the eight MSBs are stored in Register Address 06h. This allows the option of doing just a 1-byte read if 10-bit resolution is not important. The measured result is compared with the V

limits. If the VDD interrupt is not masked, any out-of-limit

LOW

HIGH

and

comparison generates a flag in the Interrupt Status 2 register and one or more out-of-limit results will cause the INT/

INT

output to pull either high or low, depending on the output polarity setting.

Measuring the voltage on the V

pin is regarded as monitoring

a channel along wit h the internal, external, and AIN channels. The user can select the V

channel for single-channel

measurement by setting Bit C4 = 1 and setting Bits C0:C2 to all 0s in the Control Configuration 2 register.

When measuring the V

value, the reference for the ADC is

sourced from the internal reference. Table 8 shows the data format. As the maximum V scaling is performed on the V

voltage measurable is 7 V, internal

voltage to match the 2.25 V

internal reference value. Below is an example of how the transfer function works.

= 5 V

ADC Reference = 2.25 V

1 LSB = ADC Reference/2 = 2.25/1024 = 2.226 mV Scale Factor = Full-Scale V

/ADC Reference

= 7/2.25 = 3.07 Conversion Result = V

/(Scale Factor × LSB size)

= 5/(3.07 × 2.226 mV) = 2 DCh

Table 8. VDD Data Format (V

= 2.25 V)

REF

Digital Output V

Value (V) Binary Hex

2.7 01 1000 1011 18B 3 01 1011 0111 1B7

3.5 10 0000 0000 200 4 10 0100 1001 249

4.5 10 1001 0010 292 5 10 1101 1100 2DC

5.5 11 0010 0101 325 6 11 0110 1110 36E

6.5 11 1011 0111 3B7 7 11 1111 1111 3FF

On-Chip Reference

The ADT7518 has an on-chip 1.2 V band gap reference, which is gained up by a switched capacitor amplifier to give an output of 2.25 V. The amplifier is powered up for the duration of the device monitoring phase and is powered down once monitoring is disabled. This saves on current consumption. The internal reference is used as the reference for the ADC. The ADC is used for measuring V

, internal temperature sensor, external temp-

erature sensor, and AIN inputs. The internal reference is always used when measuring V

, and the internal and external temp-

erature sensors. The external reference is the default power-up reference for the DACs.

Round Robin Measurement

On power-up, the ADT7518 goes into round robin mode but monitoring is disabled. Setting Bit C0 of the Configuration Register 1 to 1 enables conversions. It sequences through all the available channels, taking a measurement from each in the following order: V

, internal temperature sensor, external

temperature sensor/(AIN1 and AIN2), AIN3, and AIN4. Pin 7 and Pin 8 can be configured to be either external temperature sensor pins or standalone analog input pins. Once conversion is completed on the AIN4 channel, the device loops around for another measurement cycle. This method of taking a measurement on all the channels in one cycle is called round robin. Setting Bit C4 of Control Configuration 2 (Address 19h) disables the round robin mode and in turn sets up the singlechannel mode. The single-channel mode is where only one channel, e.g., the internal temperature sensor, is measured in each conversion cycle.

The time taken to monitor all channels will normally not be of interest, since the most recently measured value can be read at any time. For applications where the round robin time is important, typical times at 25°C are given in the specifications.

Single-Channel Measurement

Setting C4 of the Control Configuration 2 register enables the single-channel mode and allows the ADT7518 to focus on one channel only. A channel is selected by writing to Bits C0:C2 in the Control Configuration 2 register. For example, to select the

channel for monitoring, write to the Control Configuration

Rev. A | Page 23 of 40

Page 24

ADT7518

2 register and set C4 to 1 (if not done so already), then write all 0s to Bits C0:C2. All subsequent conversions will be done on the

channel only. To change the channel selection to the inter-

nal temperature channel, write to the Control Configuration 2 register and set C0 = 1. When measuring in single-channel mode, conversions on the channel selected occur directly after each other. Any communication to the ADT7518 stops the conversions, but they are restarted once the read or write operation is completed.

Internal Temperature Measurement

The ADT7518 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip ADC. The temperature data is stored in the Internal Temperature Value register. Because both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in Table 9. The thermal characteristics of the measurement sensor could change and, therefore, an offset is added to the measured value to enable the transfer function to match the thermal characteristics. This offset is added before the temperature data is stored. The offset value used is stored in the internal temperature offset register.

External Temperature Measurement

The ADT7518 can measure the temperature of one external diode sensor or diode-connected transistor.

The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about –2 mV/°C. Unfortunately, because the absolute value of V dual calibration is required to null this out, the technique is unsuitable for mass production.

The technique used in the ADT7518 is to measure the change in

when the device is operated at two different currents. This is

given by

where:

K is Boltzmann’s constant. q is the charge on the carrier. T is the absolute temperature in kelvins. N is the ratio of the two currents.

Figure 41 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor.

If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D– input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D– input and the base to the D+ input. A 2N3906 is recommended as the external transistor.

varies from device to device, and indivi-

()

NnqKTV

1/ ×=∆

To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D– input. As the sensor is operating in a noisy environment, C1 is provided as a noise filter. See the Layout Considerations section for more information on C1.

To m e as u re ∆ V

, the sensor is switched between operating cur-

rents of I and N × I. The resulting waveform is passed through a low-pass filter to remove noise, then to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional

. This voltage is measured by the ADC to give a temper-

to ∆V

ature output in 10-bit twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles.

Layout Considerations

Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken:

Place the ADT7518 as close as possible to the remote

sensing diode. Provided that the worst noise sources such as clock generators, data/address buses, and CRTs are avoided, this distance can be 4 inches to 8 inches.

Route the D+ and D– tracks close together, in parallel, with

grounded guard tracks on each side. Provide a ground plane under the tracks, if possible.

Use wide tracks to minimize inductance and reduce noise

pickup. A 10 mil track minimum width and spacing is recommended.

GND

D+

D–

GND

Figure 50. Arrangement of Signal Tracks

10 MIL 10 MIL

10 MIL 10 MIL 10 MIL 10 MIL

10 MIL

04879-050

4. Try to minimize the number of copper/solder joints, which

can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D– path and at the same temperature. Thermocouple effects should not be a major problem because 1°C corresponds to about 240 µV, and thermocouple voltages are about 3 µV/°C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV.

Rev. A | Page 24 of 40

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ADT7518

5. Place 0.1 µF bypass and 2,200 pF input filter capacitors

close to the ADT7518.

If the distance to the remote sensor is more than 8 inches,

6. the use of twisted-pair cable is recommended. This will work up to about 6 feet to 12 feet.

For long distances (up to 100 feet), use shielded twisted-

7. pair cable, such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D– and the shield to GND close to the ADT7518. Leave the remote end of the shield unconnected to avoid ground loops.

Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed.

Interrupts

The measured results from the internal temperature sensor, external temperature sensor, V compared with the T T

LOW/VLOW

(less than or equal to comparison) limits. An inter-

HIGH/VHIGH

pin, and AIN inputs are

(greater than comparison) and

rupt occurs if the measurement exceeds or equals the limit registers. These limits are stored in on-chip registers. Note that the limit registers are 8 bits long while the conversion results are 10 bits long. If the limits are not masked, any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register (Address 00h) and Interrupt Status 2 register (Address 01h). One or more out-of-limit results will cause the INT/

output to pull either high or low depending on the

INT

output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application.

Cable resistance can also introduce errors. Series resistance of 1 Ω introduces about 0.5°C error.

Temperature Value Format

One LSB of the ADC corresponds to 0.25°C. The ADC can theoretically measure a temperature span of 255°C. The internal temperature sensor is guaranteed to a low value limit of –40°C. It is possible to measure the full temperature span using the external temperature sensor. The temperature data format is shown in Table 9.

The result of the internal or external temperature measurements is stored in the temperature value registers, and is compared with limits programmed into the internal or external high and low registers.

Table 9. Temperature Data Format (Internal and External Temperature)

Temperature Digital Output

–40°C 11 0110 0000 –25°C 11 1001 1100 –10°C 11 1101 1000 –0.25°C 11 1111 1111 0°C 00 0000 0000 +0.25°C 00 0000 0001 +10°C 00 0010 1000 +25°C 00 0110 0100 +50°C 00 1100 1000 +75°C 01 0010 1100 +100°C 01 1001 0000 +105°C 01 1010 0100 +125°C 01 1111 0100

Temperature Conversion Formula:

Positive Temperature = ADC Code/4 Negative Temperature = (ADC Code

*where DB9 is removed from the ADC code.

* – 512)/4

Figure 49 shows the interrupt structure for the ADT7518. It gives a block diagram representation of how the various measurement channels affect the INT/

INT

pin.

ADT7518 REGISTERS

The ADT7518 contains registers that are used to store the results of external and internal temperature measurements, V value measurements, analog input measurements, high and low temperature limits, supply voltage and analog input limits, to set output DAC voltage levels, to configure multipurpose pins, and generally to control the device. A description of these registers follows.

The register map is divided into registers of 8 bits. Each register has its own individual address, but some consist of data that is linked to other registers. These registers hold the 10-bit conversion results of measurements taken on the temperature, V and AIN channels. For example, the eight MSBs of the V measurement are stored in Register Address 06h, while the two LSBs are stored in Register Address 03h. These types of registers are linked such that when the LSB register is read first, the MSB registers associated with that LSB register are locked to prevent any updates. To unlock these MSB registers, the user has only to read any one of them, which will have the effect of unlocking all previously locked MSB registers. So, for the preceding example, if Register 03h was read first, MSB Registers 06h and 07h would be locked to prevent any updates to them. If Register 06h were read, this register and Register 07h would be subsequently unlocked.

FIRST READ

COMMAND

Figure 51. Phase 1 of 10-Bit Read

LSB

LOCK ASSOCIATED

MSB REGISTERS

OUTPUT

DATA

04879-051

Rev. A | Page 25 of 40

Page 26

ADT7518

SECOND READ

COMMAND

Figure 52. Phase 2 of 10-Bit Read

If an MSB register is read first, its corresponding LSB register is not locked, leaving the user with the option of just reading back 8 bits (MSB) of a 10-bit conversion result. Reading an MSB register first does not lock other MSB registers, and likewise reading an LSB register first does not lock other LSB registers.

Table 10. ADT7518 Registers

RD/WR Address Name

00h Interrupt Status 1 00h 01h Interrupt Status 2 00h 02h Reserved 03h Internal Temp and VDD LSBs 00h 04h External Temp and AIN1 to AIN4 LSBs 00h 05h Reserved 00h 06h VDD MSBs xxh 07h Internal Temp MSBs 00h 08h External Temp MSBs/AIN1 MSBs 00h 09h AIN2 MSBs 00h 0Ah AIN3 MSBs 00h 0Bh AIN4 MSBs 00h 0Ch–10h Reserved 00h 11h DAC A MSBs 00h 12h Reserved 00h 13h DAC B MSBs 00h 14h Reserved 00h 15h DAC C MSBs 00h 16h Reserved 00h 17h DAC D MSBs 00h 18h Control Configuration 1 00h 19h Control Configuration 2 00h 1Ah Control Configuration 3 00h 1Bh DAC Configuration 00h 1Ch LDAC Configuration 00h 1Dh Interrupt Mask 1 00h 1Eh Interrupt Mask 2 00h 1Fh Internal Temp Offset 00h 20h External Temp Offset 00h 21h Internal Analog Temp Offset D8h 22h External Analog Temp Offset D8h 23h V 24h V 25h Internal T 26h Internal T 27h External T 28h External T 29h–2Ah Reserved 2Bh AIN2 V 2Bh AIN2 V 2Ch AIN2 V 2Dh AIN3 V 2Eh AIN3 V

Limit C7h

DD VHIGH

Limit 62h

DD VLOW

HIGH

LOW

HIGH

LOW

MSB

UNLOCK ASSOCI AT ED

MSB REGISTERS

OUTPUT

DATA

Power-On Default

Limit 64h

HIGH

Limit C9h

LOW

HIGH

LOW

/AIN1 V

Limits FFh

HIGH

Limits 00h

LOW

Limit FFh Limit FFh

Limit 00h

Limit FFh

Limit 00h

04879-052

RD/WR Address

Name

2Fh AIN4 V 30h AIN4 V

Limit FFh

HIGH

Limit 00h

LOW

Power-On Default

31h–4Ch Reserved 4Dh Device ID 03h/0Bh/

07h 4Eh Manufacturer’s ID 41h 4Fh Silicon Revision 04h 50h–7Eh Reserved 00h 7Fh SPI Lock Status 00h 80h–FFh Reserved 00h

Interrupt Status 1 Register (Read-Only) [Address = 00h]

This 8-bit read-only register reflects the status of some of the interrupts that can cause the INT/

pin to go active. This

INT

register is reset by a read operation, provided that any out-oflimit event has been corrected. It is also reset by a software reset.

Table 11. Interrupt Status 1 Register

D7 D6 D5 D4 D3 D2 D1 D0

0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

Table 12.

Bit Function

D0 1 when the internal temperature value exceeds T

limit. Any

HIGH

internal temperature reading greater than the set limit will cause an out-of-limit event.

D1 1 when internal temperature value exceeds T

limit. Any

LOW

internal temperature reading less than or equal to the set limit will cause an out-of-limit event.

D2 This status bit is linked to the configuration of Pins 7 and 8. If

configured for the external temperature sensor, this bit is 1 when the external temperature value the exceeds T

HIGH

limit. The default value for this limit register is –1°C, so any external temperature reading greater than the set limit will cause an out-of-limit event. If configured for AIN1 and AIN2, this bit is 1

or V

when AIN1 input voltage exceeds V

HIGH

D3 1 when external temperature value exceeds T

LOW

limits.

limit. The default value for this limit register is 0°C, so any external temperature reading less than or equal to the set limit will cause an out-of-limit event.

D4 1 Indicates a fault (open or short) for the external temperature

sensor.

D5 1 when AIN2 voltage is greater than its corresponding V

HIGH

limit. 1 when AIN2 voltage is less than or equal to its corresponding V

D6 1 when AIN3 voltage is greater than its corresponding V

LOW

limit.

HIGH

limit. 1 when AIN3 voltage is less than or equal to its corresponding V

D7 1 when AIN4 voltage is greater than its corresponding V

LOW

limit.

HIGH

limit. 1 when AIN4 voltage is less than or equal to its corresponding V

LOW

limit.

Interrupt Status 2 Register (Read-Only) [Address = 01h]

This 8-bit read-only register reflects the status of the VDD interrupt that can cause the INT/

pin to go active. This register is

INT

reset by a read operation, provided that any out-of-limit event has been corrected. It is also reset by a software reset.

Rev. A | Page 26 of 40

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ADT7518

Table 13. Interrupt Status 2 Register

D7 D6 D5 D4 D3 D2 D1 D0

N/A N/A N/A 0* N/A N/A N/A N/A

*Default settings at power-up.

Table 14.

Bit Function

1 when V limit. 1 when V V

LOW

value is greater than its corresponding V

is less than or equal to its corresponding

limit.

HIGH

Internal Temperature Value/VDD Value Register LSBs (ReadOnly) [Address = 03h]

This 8-bit read-only register stores the two LSBs of the 10-bit temperature reading from the internal temperature sensor and the two LSBs of the 10-bit supply voltage reading.

Table 15. Internal Temperature/VDD LSBs

D7 D6 D5 D4 D3 D2 D1 D0

N/A N/A N/A N/A V1 LSB T1 LSB N/A N/A N/A N/A 0* 0* 0* 0*

*Default settings at power-up

Table 16.

Bit Function

D0 LSB of Internal Temperature Value D1 B1 of Internal Temperature Value D2 LSB of VDD Value D3 B1 of VDD Value

External Temperature Value and Analog Inputs 1 to 4 Register LSBs (Read-Only) [Address = 04h]

This is an 8-bit read-only register. Bits D2:D7 store the two LSBs of the analog inputs AIN2 to AIN4. Bits D0:D1 store the two LSBs of either the external temperature value or AIN1 input value. The type of input for D0 and D1 is selected by Bits C1:C2 of the Control Configuration Register 1.

Table 17. External Temperature and AIN1 to AIN4 LSBs

D7 D6 D5 D4 D3 D2 D1 D0

A4 A4

A3 A3

LSB

A2 A2

LSB

T/A T/A

LSB

0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

Table 18.

Bit Function

D0 LSB of External Temperature Value or AIN1 Value D1 Bit 1 of External Temperature Value or AIN1 Value D2 LSB of AIN2 Value D3 Bit 1 of AIN2 Value D4 LSB of AIN3 Value D5 Bit 1 of AIN3 Value D6 LSB of AIN4 Value D7 Bit 1 of AIN4 Value

VDD Value Register MSBs (Read-Only) [Address = 6h]

This 8-bit read-only register stores the supply voltage value. The eight MSBs of the 10-bit value are stored in this register.

Table 19. VDD Value MSBs

D7 D6 D5 D4 D3 D2 D1 D0

V9 V8 V7 V6 V5 V4 V3 V2 x* x* x* x* x* x* x* x*

*Loaded with V

value after power-up.

Internal Temperature Value Register MSBs (Read-Only) [Address = 07h]

This 8-bit read-only register stores the internal temperature value from the internal temperature sensor in twos complement format. The eight MSBs of the 10-bit value are stored in this register.

Table 20. Internal Temperature Value MSBs

D7 D6 D5 D4 D3 D2 D1 D0

T9 T8 T7 T6 T5 T4 T3 T2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

External Temperature Value or Analog Input AIN1 Register MSBs (Read-Only) [Address = 08h]

This 8-bit read-only register stores, if selected, the external temperature value or the analog input AIN1 value. Selection is done in the Control Configuration 1 register. The external temperature value is stored in twos complement format. The eight MSBs of the 10-bit value are stored in this register.

Table 21. External Temperature Value/Analog Inputs MSBs

D7 D6 D5 D4 D3 D2 D1 D0

T/A9 T/A8 T/A7 T/A6 T/A5 T/A4 T/A3 T/A2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

AIN2 Register MSBs (Read) [Address = 09h]

This 8-bit read register contains the eight MSBs of the AIN2 analog input voltage word. The value in this register is combined with Bits D2:3 of the external temperature value and Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full 10-bit conversion result of the analog value on the AIN2 pin.

Table 22. AIN2 MSBs

D7 D6 D5 D4 D3 D2 D1 D0

MSB A8 A7 A6 A5 A4 A3 A2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

AIN3 Register MSBs (Read) [Address = 0Ah]

This 8-bit read register contains the eight MSBs of the AIN3 analog input voltage word. The value in this register is combined with Bits D4:5 of the external temperature value and Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full 10-bit conversion result of the analog value on the AIN3 pin.

Rev. A | Page 27 of 40

Page 28

ADT7518

Table 23. AIN3 MSBs

D7 D6 D5 D4 D3 D2 D1 D0

MSB A8 A7 A6 A5 A4 A3 A2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

AIN4 Register MSBs (Read) [Address = 0Bh]

This 8-bit read register contains the eight MSBs of the AIN4 analog input voltage word. The value in this register is combined with Bits D6:7 of the external temperature value and Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full 10-bit conversion result of the analog value on the AIN4 pin.

Table 24. AIN4 MSBs

D7 D6 D5 D4 D3 D2 D1 D0

MSB A8 A7 A6 A5 A4 A3 A2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

DAC A Register (Read/Write) [Address = 11h]

This 8-bit read/write register contains the eight bits of the DAC A word. The value in this register is converted to an analog voltage on the V the V

-A pin is 0 V.

OUT

Table 25. DAC A

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

DAC B Register (Read/Write) [Address = 13h]

This 8-bit read/write register contains the eight bits of the DAC B word. The value in this register is converted to an analog voltage on the V the V

-B pin is 0 V.

OUT

-A pin. On power-up, the voltage output on

OUT

-B pin. On power-up, the voltage output on

OUT

Table 26. DAC B

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

DAC C Register (Read/Write) [Address = 15h]

This 8-bit read/write register contains the eight bits of the DAC C word. The value in this register is converted to an analog voltage on the V the V

-C pin is 0 V.

OUT

-C pin. On power-up, the voltage output on

OUT

Table 27. DAC C

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

DAC D Register (Read/Write) [Address = 17h]

This 8-bit read/write register contains the eight bits of the DAC D word. The value in this register is converted to an analog voltage on the V the V

-D pin is 0 V.

OUT

-D pin. On power-up, the voltage output on

OUT

Table 28. DAC D

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

Control Configuration 1 Register (Read/Write) [Address = 18h]

This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7518.

Table 29. Control Configuration 1

D7 D6 D5 D4 D3 D2 D1 D0

PD C6 C5 C4 C3 C2 C1 C0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

Rev. A | Page 28 of 40

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ADT7518

Table 30.

Bit Function

This bit enables/disables conversions in round robin and single-channel mode. ADT7518 powers up in round robin mode but monitoring is not initiated until this bit is set. The default = 0.

0 = Stop monitoring. 1 = Start monitoring.

C2:C1

Selects between the two different analog inputs on Pins 7 and 8. ADT7518 powers up with AIN1 and AIN2 selected.

00 = AIN1 and AIN2 selected. 01 = Undefined. 10 = External TDM selected. 11 = Undefined.

Selects between digital (LDAC) and analog inputs (AIN3) on Pin 9. When AIN3 is selected, Bit C3 of the Control Configuration 3 register is masked and has no effect until LDAC is selected as the input on Pin 9.

0 = LDAC selected.

1 = AIN3 selected. C4 Reserved. Write 0 only. C5

0 = Enable INT/

1 = Disable INT/

Configures INT/

INT output.

INT output polarity. 0 = Active low. 1 = Active high.

Power-Down Bit. Setting this bit to 1 puts the ADT7518 into standby mode. In this mode, both ADC and DACs are fully powered down, but the serial interface is still operational. To power up the part again, just write 0 to this bit.

Control Configuration 2 Register (Read/Write) [Address = 19h]

This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7518.

Table 31. Control Configuration 2

D7 D6 D5 D4 D3 D2 D1 D0

C7 C6 C5 C4 C3 C2 C1 C0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

Table 32.

Bit Function

C2:0

In single-channel mode, these bits select between V

the internal temperature sensor, external temperature sensor/AIN1, AIN2, AIN3, and AIN4 for conversion. The default is V

000 = V

001 = Internal temperature sensor. 010 = External temperature sensor/AIN1. (Bits C1:C2 of

the Control Configuration 1 register affect this selection). 011 = AIN2. 100 = AIN3.

Bit Function

101 = AIN4.

110–111 = Reserved. C3 Reserved. C4

Selects between single-channel and round robin conver-

sion cycle. The default is round robin.

0 = Round robin.

1 = Single channel. C5

Default condition is to average every measurement on all

channels 16 times. This bit disables this averaging.

Channels affected are temperature, analog inputs, and

VDD.

0 = Enable averaging.

1 = Disable averaging. C6

SMBus timeout on the serial clock puts a 25 ms limit on

the pulse width of the clock, ensuring that a fault on the

master SCL does not lock up the SDA line.

0 = Disable SMBus timeout.

1 = Enable SMBus timeout. C7

Software Reset. Setting this bit to 1 causes a software

reset. All registers and DAC outputs will reset to their

default settings.

Control Configuration 3 Register (Read/Write) [Address = 1Ah]

This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7518.

Table 33. Control Configuration 3

D7 D6 D5 D4 D3 D2 D1 D0

C7 C6 C5 C4 C3 C2 C1 C0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

Table 34.

Bit Function

C0 Selects between fast and slow ADC conversion speeds.

0 = ADC clock at 1.4 kHz.

1 = ADC clock at 22.5 kHz. D+ and D– analog filters are

disabled. C2:1 Reserved. Write 0 only. C3

LDAC pin controls updating of DAC outputs.

0 =

1 = DAC configuration register and LDAC configuration

Selects the ADC reference to be either internal V

or VDD

REF

for analog inputs.

0 = Internal V

REF.

1 = VDD. C5

Setting this bit selects DAC A voltage output to be

proportional to the internal temperature measurement. C6

Setting this bit selects DAC B voltage output to be

proportional to the external temperature measurement. C7 Reserved. Write 0 only.

Rev. A | Page 29 of 40

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ADT7518

DAC Configuration Register (Read/Write) [Address = 1Bh]

This configuration register is an 8-bit read/write register that is used to control the output ranges of all four DACs and also to

LDAC

control the loading of the DAC registers if the disabled (Bit C3 = 1, Control Configuration 3 register).

Table 35. DAC Configuration

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

Table 36.

Bit Function

D0 Selects the output range of DAC A.

0 = 0 V to V 1 = 0 V to 2V

REF

D1 Selects the output range of DAC B.

0 = 0 V to V 1 = 0 V to 2V

REF

D2 Selects the output range of DAC C.

0 = 0 V to V 1 = 0 V to 2V

REF

D3 Selects the output range of DAC D.

D5:D4

0 = 0 V to V 1 = 0 V to 2V 00 = A write to any DAC register generates LDAC

REF

command that updates that DAC only. 01 = A write to DAC B or DAC D register generates

LDAC command that updates DACs A, B or DACs C, D, respectively.

10 = A write to DAC D register generates LDAC command that updates all four DACs.

11 = LDAC command generated from LDAC register.

D6:D7 Reserved. Write 0s only.

LDAC Configuration Register (Write-Only) [Address = 1Ch]

This configuration register is an 8-bit write register that is used to control the updating of the quad DAC outputs if the

pin is disabled and Bits D4:D5 of the DAC configuration register are both set to 1. Also selects either the internal or external

for all four DACs. Bits D0:D3 in this register are self-clear-

REF

ing, i.e., reading back from this register will always give 0s for these bits.

Table 37. LDAC Configuration

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

pin is

LDAC

Table 38.

Bit Function

Writing a 1 to this bit will generate the LDAC command to update DAC A output only.

Writing a 1 to this bit will generate the LDAC command to update DAC B output only.

Writing a 1 to this bit will generate the LDAC command to update DAC C output only.

Writing a 1 to this bit will generate the LDAC command to update DAC D output only.

Selects either internal V

or external V

REF

for DACs A

REF

and B.

0 = External V 1 = Internal V Selects either internal V

REF

or external V

REF

for DACs C

REF

and D. 0 = External V 1 = Internal V

REF

D6:D7 Reserved. Write 0s only.

Interrupt Mask 1 Register (Read/Write) [Address = 1Dh]

This mask register is an 8-bit read/write register that can be used to mask any interrupts that can cause the INT/

INT

pin to

go active.

Table 39. Interrupt Mask 1

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

Table 40.

Bit Function

D0 0 = Enable internal T

1 = Disable internal T

D1 0 = Enable internal T

1 = Disable internal T

D2 0 = Enable external T

1 = Disable external T

D3 0 = Enable external T

1 = Disable external T

interrupt.

HIGH

interrupt.

HIGH

interrupt.

LOW

interrupt.

LOW

interrupt or AIN1 interrupt.

HIGH

interrupt or AIN1 interrupt.

HIGH

interrupt.

LOW

interrupt.

LOW

D4 0 = Enable external temperature fault interrupt..

1 = Disable external temperature fault interrupt.

D5 0 = Enable AIN2 interrupt.

1 = Disable AIN2 interrupt.

D6 0 = Enable AIN3 interrupt.

1 = Disable AIN3 interrupt.

D7 0 = Enable AIN4 interrupt.

1 = Disable AIN4 interrupt.

Rev. A | Page 30 of 40

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ADT7518

Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]

This mask register is an 8-bit read/write register that can be used to mask any interrupts that can cause the INT/

INT

pin to

go active.

Table 41. Interrupt Mask 2

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

Table 42.

Bit Function

D0:D3 Reserved. Write 0s only. D4

0 = Enable V 1 = Disable V

interrupts.

D5:D7 Reserved. Write 0s only.

Internal Temperature Offset Register (Read/Write) [Address = 1Fh]

This register contains the offset value for the internal temperature channel. A twos complement number can be written to this register which is then added to the measured result before it is stored or compared to limits. In this way, a one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. Because it is an 8-bit register, the temperature resolution is 1°C.

Table 43. Internal Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

External Temperature Offset Register (Read/Write) [Address = 20h]

This register contains the offset value for the external temperature channel. A twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. In this way, a one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. Because it is an 8-bit register, the temperature resolution is 1°C.

Table 44. External Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

Internal Analog Temperature Offset Register (Read/Write) [Address = 21h]

This register contains the offset value for the internal thermal voltage output. A twos complement number can be written to this register, which is then added to the measured result before it is converted by DAC A. Varying the value in this register has the effect of varying the temperature span. For example, the output voltage can represent a temperature span of –128°C to +127°C or even 0°C to +127°C. In essence, this register changes the position of 0 V on the temperature scale. Temperatures other than –128°C to +127°C will produce an upper deadband on the DAC A output. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is –40°C.

Table 45. Internal Analog Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 1* 1* 0* 0* 0*

* Default settings at power-up

External Analog Temperature Offset Register (Read/Write) [Address = 22h]

This register contains the offset value for the external thermal voltage output. A twos complement number can be written to this register which is then added to the measured result before it is converted by DAC B. Varying the value in this register has the effect of varying the temperature span. For example, the output voltage can represent a temperature span of –128°C to +127°C or even 0°C to +127°C. In essence, this register changes the position of 0 V on the temperature scale. Temperatures other than –128°C to +127°C will produce an upper deadband on the DAC B output. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is –40°C.

Table 46. External Analog Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 1* 1* 0* 0* 0*

* Default settings at power-up

VDD V

Limit Register (Read/Write) [Address = 23h]

HIGH

This limit register is an 8-bit read/write register that stores the

upper limit, which will cause an interrupt and activate the

INT/

output (if enabled). For this to happen, the measured

INT

value has to be greater than the value in this register. The

default value is 5.46 V.

Table 47. VDD V

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 0* 0* 1* 1* 1*

* Default settings at power-up

Rev. A | Page 31 of 40

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ADT7518

VDD V

This limit register is an 8-bit read/write register that stores the V INT/

V register. The default value is 2.7 V.

Table 48. VDD V

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 1* 1* 0* 0* 0* 1* 0*

* Default settings at power-up

Internal T

This limit register is an 8-bit read/write register that stores the twos complement of the internal temperature upper limit, which will cause an interrupt and activate the INT/

(if enabled). For this to happen, the measured internal temperature value has to be greater than the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is +100°C.

Table 49. Internal T

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 1* 1* 0* 0* 1* 0* 0*

* Default settings at power-up

Internal T

This limit register is an 8-bit read/write register that stores the twos complement of the internal temperature lower limit, which will cause an interrupt and activate the INT/

enabled). For this to happen, the measured internal temperature value has to be more negative than or equal to the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is –55°C.

Table 50. Internal T

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 0* 1* 0* 0* 1*

* Default settings at power-up

External T [Address = 27h]

If Pins 7 and 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature upper limit, which will cause an interrupt and activate the INT/

output (if enabled). For this to happen, the measured external temperature value has to be greater than the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is –1°C.

If Pins 7 and 8 are configured for AIN1 and AIN2 inputs, this limit register is an 8-bit read/write register that stores the AIN1

Limit Register (Read/Write) [Address = 24h]

LOW

lower limit, which will cause an interrupt and activate the

output (if enabled). For this to happen, the measured

INT

value has to be less than or equal to the value in this

Limit

LOW

Limit Register (Read/Write) [Address = 25h]

HIGH

output

INT

Limit

HIGH

Limit Register (Read/Write) [Address = 26h]

LOW

output (if

INT

Limit

LOW

HIGH

/AIN1 V

Limit Register (Read/Write)

HIGH

INT

input upper limit, which will cause an interrupt and activate the INT/

output (if enabled). For this to happen, the measured

INT

AIN1 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. Because the power-up default settings for Pins 7 and 8 are AIN1 and AIN2 inputs, the default value for this limit register is full-scale voltage.

Table 51. AIN1 V

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 1* 1* 1* 1* 1* 1*

* Default settings at power-up

External T

/AIN1 V

LOW

Limit Register (Read/Write)

LOW

[Address = 28h]

If Pins 7 and 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature lower limit, which will cause an interrupt and activate the INT/

INT

output (if enabled). For this to happen, the measured external temperature value has to be more negative than or equal to the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is 0°C.

If Pins 7 and 8 are configured for AIN1 and AIN2 inputs, this limit register is an 8-bit read/write register that stores the AIN1 input lower limit, which will cause an interrupt and activate the INT/

output (if enabled). For this to happen, the measured

INT AIN1 value has to be less than or equal to the value in this register. As it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. Because the power-up default settings for Pins 7 and 8 are AIN1 and AIN2 inputs, the

default value for this limit register is 0 V.

Table 52. AIN1 V

LOW

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

AIN2 V

Limit Register (Read/Write) [Address = 2Bh]

HIGH

This limit register is an 8-bit read/write register that stores the AIN2 input upper limit, which will cause an interrupt and activate the INT/

output (if enabled). For this to happen, the

INT

measured AIN2 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage.

Table 53. AIN2 V

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 1* 1* 1* 1* 1* 1*

* Default settings at power-up

Rev. A | Page 32 of 40

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ADT7518

AIN2 V

This limit register is an 8-bit read/write register that stores the AIN2 input lower limit, which will cause an interrupt and activate the INT/

measured AIN2 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V.

Table 54. AIN2 V

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

AIN3 V

This limit register is an 8-bit read/write register that stores the AIN3 input upper limit, which will cause an interrupt and activate the INT/

measured AIN3 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage.

Table 55. AIN3 V

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 1* 1* 1* 1* 1* 1*

* Default settings at power-up

AIN3 V

This limit register is an 8-bit read/write register that stores the AIN3 input lower limit, which will cause an interrupt and activate the INT/

the measured AIN3 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V.

Table 56. AIN3 V

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

AIN4 V

This limit register is an 8-bit read/write register that stores the AIN4 input upper limit, which will cause an interrupt and activate the INT/

measured AIN4 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage.

Limit Register (Read/Write) [Address = 2Ch]

LOW

output (if enabled). For this to happen, the

INT

Limit

LOW

Limit Register (Read/Write) [Address = 2Dh]

HIGH

output (if enabled). For this to happen, the

INT

Limit

HIGH

Limit Register (Read/Write) [Address = 2Eh]

LOW

output (if enabled). For this to happen,

INT

Limit

LOW

Limit Register (Read/Write) [Address = 2Fh]

HIGH

output (if enabled). For this to happen, the

INT

Table 57. AIN4 V

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 1* 1* 1* 1* 1* 1*

* Default settings at power-up

AIN4 V

Limit Register (Read/Write) [Address = 30h]

LOW

This limit register is an 8-bit read/write register that stores the AIN4 input lower limit, which will cause an interrupt and activate the INT/

output (if enabled). For this to happen,

INT

the measured AIN4 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V.

Table 58. AIN4 V

LOW

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

* Default settings at power-up

Device ID Register (Read-Only) [Address = 4Dh]

This 8-bit read-only register contains a device identifier byte: ADT7518 = 0Bh.

Manufacturer’s ID Register (Read-Only) [Address = 4Eh]

This register contains the manufacturer’s identification number. ADI’s ID number is 41h.

Silicon Revision Register (Read-Only) [Address = 4Fh]

This register is divided into four LSBs representing the stepping and the four MSBs representing the version. The stepping contains the manufacturer’s code for minor revisions or steppings to the silicon. The version is the ADT7518 version number.

SPI Lock Status Register (Read-Only) [Address = 7Fh]

Bit D0 (LSB) of this read-only register indicates whether or not the SPI interface is locked. Writing to this register will cause the device to malfunction. The default value is 00h.

C interface.

0 = I 1 = SPI interface selected and locked.

SERIAL INTERFACE

There are two serial interfaces that can be used on this part: I2C and SPI. The device will power up with the serial interface in

C mode, but it is not locked into this mode. To stay in I2C

I mode, it is recommended that the user tie the

or GND. It is not possible to lock the I2C mode, but it is

possible to select and lock the SPI mode.

line to either

Rev. A | Page 33 of 40

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ADT7518

(START HIGH)

A B

(START LOW)

A B

Figure 53. Serial Interface—Selecting and Locking SPI Protocol

To select and lock the interface into the SPI mode, a number of pulses must be sent down the

line (Pin 4). The following

section describes how this is done.

Once the SPI communication protocol has been locked in, it cannot be unlocked while the device is still powered up. Bit D0 of the SPI lock status register (Address 7Fh) is set to 1 when a successful SPI interface lock has been accomplished. To reset the serial interface, the user must power down the part and power it up again. A software reset does not reset the serial interface.

Serial Interface Selection

The CS line controls the selection between I2C and SPI.

Figure 53 shows the selection process necessary to lock the SPI interface mode.

To communicate to the ADT7518 using the SPI protocol, send three pulses down the

line as shown in Figure 53. On the

CS third rising edge (marked as C in Figure 53), the part selects and locks the SPI interface. The user is now limited to communi-

cating to the device using the SPI protocol.

As per most SPI standards, the CS line must be low during every SPI communication to the ADT7518 and high all other times. Typical examples of how to connect the dual interface as

C or SPI is shown in Figure 54 and Figure 55. The following

I sections describe in detail how to use the I

C and SPI protocols

associated with the ADT7518.

ADT7518

SDA

SCL

ADD

Figure 54. Typical I

I2C ADDRESS = 1001 000

10kΩ10kΩ

C Interface Connection

04879-053

SPI LOCKE D ON

THIRD RISI NG EDGE

SPI LOCKED ON

THIRD RISI NG EDGE

ADT7518

I2C Serial Interface

Like all I2C-compatible devices, the ADT7518 has a 7-bit serial address. The four MSBs of this address for the ADT7518 are set to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin can be configured three ways to give three different address options: low, floating, and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010, and setting it high gives the address 1001 011. The recommended pull-up resistor value is 10 kΩ.

There is an enable/disable bit for the SMBus timeout. When this is enabled, the SMBus will time out after 25 ms of no activity. To enable it, set Bit 6 of the Control Configuration 2 register. The power-on default is with the SMBus timeout disabled.

The ADT7518 supports SMBus packet error checking (PEC), but its use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC is calculated using CRC-8. The frame clock sequence (FCS) conforms to CRC-8 by the polynominal

Consult the SMBus specification (www.smbus.org) for more information.

()

SPI FRAMING

EDGE

SPI FRAMING

EDGE

820Ω820Ω820

DIN

SCLK

DOUT

Ω

Figure 55. Typical SPI Interface Connection

128

+++= xxxxC

LOCK AND

SELECT SPI

SPI FRAMING

EDGE

04879-055

04879-054

Rev. A | Page 34 of 40

Page 35

ADT7518

The serial bus protocol operates as follows:

The master initiates a data transfer by establishing a start

condition, defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/

bit, which deter-

mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device.

The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/

the slave device. If the R/

bit is 0 the master will write to

bit is 1, the master will read

from the slave device.

Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, since a low to high transition when the clock is high may be interpreted as a stop signal.

When all data bytes have been read or written, stop

3. conditions are established. In write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device will pull the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

C address set up by the ADD pin is not latched by the

The I device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. This is the SCL cycle directly after the

device has seen its own I changes on this pin will have no effect on the I

C serial bus address. Any subsequent

C serial bus

address.

Writing to the ADT7518

Depending on the register being written to, there are two different writes for the ADT7518. It is not possible to do a block

write to this par t, i.e., no I

C autoincrement.

Writing to the Address Pointer Register for a Subsequent Read

To read data from a particular register, the address pointer register must contain the address of that register. If it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in Figure 56. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation is then performed to read the register.

Writing Data to a Register

All registers are 8-bit registers, so only one byte of data can be written to each register. Writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, followed by the data byte written to the selected data register. This is illustrated in Figure 57. To write to a different register, another start or repeated start is required. If more than one byte of data is sent in one communication operation, the addressed register will repeatedly load until the last data byte is sent.

Reading Data from the ADT7518

Reading data from the ADT7518 is done in a 1-byte operation. Reading back the contents of a register is shown in Figure 58. The register address had previously been set up by a single-byte write operation to the address pointer register. To read from another register, write to the address pointer register again to set up the relevant register address. Thus, block reads are not

possible, i.e., no I

C autoincrement.

SPI Serial Interface

The SPI serial interface of the ADT7518 consists of four wires:

, SCLK, DIN, and D OUT. The CS line is used to select the

CS device when more than one device is connected to the serial

clock and data lines. The

line is also used to distinguish

between any two separate serial communications (see Figure 63 for a graphical explanation). The SCLK line is used to clock data in and out of the part. The D

line is used to write to the regis-

ters, and the DOUT line is used to read data back from the registers. The recommended pull-up resistor value is between 500 Ω and 820 Ω.

The part operates in slave mode and requires an externally applied serial clock to the SCLK input. The serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data.

There are two types of serial operations, read and write. Command words are used to distinguish read operations from write operations. These command words are given in Table 59. Address autoincrement is possible in SPI mode.

Table 59. SPI Command Words

Write Read

90h (1001 0000) 91h (1001 0001)

Rev. A | Page 35 of 40

Page 36

ADT7518

SDA

SCL

191

START BY

MASTER

SCL

START BY

MASTER

SCL

0 0 1 A2 A1 A P7 P6 P5 P4 P3 P2 P1 P0

FRAME 1

SERIAL BUS ADDRESS BYTE

Figure 56. I

1 0 0 1 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

Figure 57. I

C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register

01 R/W

ACK. BY

ADT7518

ADDRESS POINTER REGISTER BYTE

191

R/W

ACK. BY ADT7518

ADDRESS POINTER REGISTER BYTE

D7 D6 D5 D4 D3 D2 D1 D0

191

FRAME 2

FRAME 3

DATA BYTE

ACK. BY ADT7518

STOP BY

MASTER

STOP BY MASTER

04879-056

04879-057

1SDA

0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

Figure 58. I

C—Reading a Single Byte of Data from a Selected Register

ACK. BY

ADT7518

Write Operation

Figure 59 shows the timing diagram for a write operation to the ADT7518. Data is clocked into the registers on the rising edge of SCLK. When the

are in three-state mode. Only when the

line is high, the DIN and DOUT lines

goes from a high to a

CS low does the part accept any data on the DIN line. In SPI mode, the address pointer register is capable of autoincrementing to the next register in the register map without having to load the address pointer register each time. In Figure 59, the register address portion gives the first register that will be written to. Subsequent data bytes will be written into sequential writable registers. Thus, after each data byte has been written into a register, the address pointer register autoincrements its value to the next available register. The address pointer register will autoincrement from 00h to 3Fh and will loop back to start again

at 00h when it reaches 3Fh.

STOP BY

MASTER

04879-058

SINGLE DATA BYTE FROM ADT7518

FRAME 2

NO ACK. BY

MASTER

Read Operation

Figure 60 to Figure 62 show the timing diagrams necessary to accomplish correct read operations. To read back from a register, first write to the address pointer register with the address of the register to be read from. This operation is shown in Figure 60. Figure 61 shows the procedure for reading back a single byte of data. The read command is first sent to the part during the first eight clock cycles. During the following eight clock cycles, the data contained in the register selected by the address pointer register is output onto the D output onto the D

line on the falling edge of SCLK. Figure 62

OUT

line. Data is

OUT

shows the procedure when reading data from two sequential registers. Multiple data reads are possible in the SPI interface mode as the address pointer register is autoincremental. The address pointer register will autoincrement from 00h to 3Fh and will loop back to start again at 00h when it reaches 3Fh.

Rev. A | Page 36 of 40

Page 37

ADT7518

SCLK

DIN

181

START

CS (CONTINUED)

SCLK (CONTINUED)

DIN (CONTINUED)

DATA BYTE

Figure 59. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register

181

CLK

D0 STOP

04879-059

DIN

START

WRITE COMMAND

STOP

04879-060

Figure 60. SPI—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

STOP

04879-061

SCLK

DIN

DOUT

START

XXXX

READ COMMAND

XD7

DATA BYTE 1

Figure 61. SPI—Reading a Single Byte of Data From a Selected Register

Rev. A | Page 37 of 40

Page 38

ADT7518

SCLK

DIN

DOUT

START

READ COMMAND

181

CS (CONTINUED)

SCLK (CONTINUED)

DIN (CONTINUED)

DOUT (CONTINUED)

XD7

D6 D5

D6 D5 D4 D 3

DATA BYTE 1

DATA BYTE 2

Figure 62. SPI—Reading Two Bytes of Data From Two Sequential Registers

STOP

04879-062

SPI READ OPERATION WRITE OPERATION

Figure 63. SPI—Correct Use of

SMBus/SPI INT/

The ADT7518 INT/

INT

output is an interrupt line for devices

INT that want to trade their ability to master for an extra pin. It is a slave device and uses the SMBus/SPI INT/ device that it wants to talk to. The SMBus/SPI INT/

to signal the host

INT

on the

ADT7518 is used as an over/under limit indicator.

The INT/

pin has an open-drain configuration that allows

INT the outputs of several devices to be wired-AND’ed together when the INT/

pin is active low. Use C6 of the Control

INT Config-uration 1 register to set the active polarity of the INT/ INT/

out-put. The power-up default is active low. The

INT

output can be disabled or enabled by setting C5 of the

INT

Control Config-uration 1 register to 1 or 0, respectively.

The INT/ temperature value, the external temperature value, V

output becomes active when either the internal

INT

value, or

any of the AIN input values exceed the values in their corresponding T

HIGH/VHIGH

or T

LOW/VLOW

registers. The INT/

INT

out-

put goes inactive again when a conversion result has the measured value back within the trip limits and when the status register associated with the out-of-limit event is read. The two

04879-063

During SPI Communication

interrupt status registers show which event caused the INT/ pin to go active.

The INT/ can be connected to a voltage different from V

maximum voltage rating of the INT/

output requires an external pull-up resistor. This

INT

, provided the

output pin is not

INT

exceeded. The value of the pull-up resistor depends on the application but should be large enough to avoid excessive sink currents at the INT/

output, which can heat the chip and

INT

affect the temperature reading.

SMBUS ALERT RESPONSE

The INT/ when the SMBus/I

output and requires a pull-up to V

can be wire-AND’ed together, so that the common line will go low if one or more of the INT/

ity of the INT/ outputs to be wire-AND’ed together.

pin behaves the same way as an SMBus alert pin

INT

C interface is selected. It is an open-drain

. Sever al INT/

outputs goes low. The polar-

INT

pin must be set active low for a number of

INT

outputs

Rev. A | Page 38 of 40

Page 39

ADT7518

The INT/

output can operate as an

INT

SMBALERT

function.

Slave devices on the SMBus cannot normally signal to the master that they want to talk, but the

allows them to do so.

SMBALERT

is used in conjunction with

SMBALERT

function

the SMBus general call address.

One or more INT/ mon

SMBALERT

line is pulled low by one of the devices, the

outputs can be connected to a com-

INT

line connected to the master. When the

following procedure occurs, as shown in Figure 64.

SMBALERT

Master initiates a read operation and sends the alert res-

pulled low.

ponse address (ARA = 0001 100). This is a general call address that must not be used as a specific device address.

The devices whose INT/

output is low responds to the

INT

alert response address and the master reads its device address. As the device address is seven bits long, an LSB of 1 is added. The address of the device is now known and it can be interrogated in the usual way.

of-limit event is read. If the

SMBALERT

line remains low,

the master will send the ARA again. It will continue to do this until all devices whose

SMBALERT

outputs were low

have responded.

MASTE RECEIVES SMBALERT

START

ALERT RESPONSE

ADDRESS

MASTER SENDS ARA AND READ

COMMAND

Figure 64. INT/

RD ACK DEVICE ADDRESS

DEVICE SENDS

ITS ADDRESS

INT

Responds to

SMBALERT

ARA

ACK

MASTER RECEIVES SMBALERT

START

ALERT RESPONSE

ADDRESS

MASTER SENDS

ARA AND READ

COMMAND

Figure 65. INT/

With Packet Error Checking (PEC)

DEVICE ACK

RD ACK

DEVICE SENDS

INT

Responds to

DEVICE

ADDRESS

ITS ADDRESS

SMBALERT

MASTE

ACK

ACK PEC

MASTE

DEVICE SENDS

ITS PEC DATA

ARA

NACK

ACK

STOP

04879-064

STOP

04879-065

If more than one device’s INT/

output is low, the one

INT with the lowest device address will have priority in accordance with normal SMBus specifications.

Once the ADT7518 has responded to the alert response

address, it will reset its INT/

output, provided that the

INT

condition that caused the out-of-limit event no longer exists and that the status register associated with the out-

Rev. A | Page 39 of 40

Page 40

ADT7518

OUTLINE DIMENSIONS

0.193 BSC

0.012

0.008

0.154 BSC

0.069

0.053

SEATING PLANE

0.236 BSC

0.010

0.006

8° 0°

0.050

0.016

0.065

0.049

0.010

0.004

COPLANARITY

0.004

PIN 1

0.025 BSC

COMPLIANT TO JEDEC STANDARDS MO-137AB

Figure 66. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions in Inches

ORDERING GUIDE

DAC

Model Temperature Range

Resolution

ADT7518ARQ –40°C to +120°C 8 Bits 16-Lead QSOP RQ-16 N/A ADT7518ARQ-REEL –40°C to +120°C 8 Bits 16-Lead QSOP RQ-16 2,500 ADT7518ARQ-REEL7 –40°C to +120°C 8 Bits 16-Lead QSOP RQ-16 1,000 ADT7518ARQZ

–40°C to +120°C 8 Bits 16-Lead QSOP RQ-16 N/A ADT7518ARQZ-REEL1 –40°C to +120°C 8 Bits 16-Lead QSOP RQ-16 2,500 ADT7518ARQZ-REEL71 –40°C to +120°C 8 Bits 16-Lead QSOP RQ-16 1,000

Z = Pb-free part.

Package Description Package Option

Minimum Quantities/Reel

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I

C04879-0-8/04(A)

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. A | Page 40 of 40

Datasheet ADT7518 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

APPLICATIONS

PIN CONFIGURATION

SPECIFICATIONS

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

TERMINOLOGY

Relative Accuracy

Differential Nonlinearity

Total Unadjusted Error (TUE)

Offset Error

Offset Error Match

Gain Error

Gain Error Match

Offset Error Drift

Gain Error Drift

Lo ng Ter m Tempera ture Drif t

DC Power Supply Rejection Ratio (PSRR)

DC Crosstalk

Reference Feedthrough

Channel-to-Channel Isolation

Major-Code Transition Glitch Energy

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

Round Robin

DAC Output Settling Time

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

POWER-UP CALIBRATION

CONVERSION SPEED

FUNCTION DESCRIPTION—VOLTAGE OUTPUT

Digital-to-Analog Converters

Digital-to-Analog Section

Resistor String

DAC Reference Inputs

Output Amplifier

Thermal Voltage Output

FUNCTIONAL DESCRIPTION—ANALOG INPUTS

Single-Ended Inputs

Converter Operation

ADC TRANSFER FUNCTION

Analog Input ESD Protection

AIN Interrupts

FUNCTIONAL DESCRIPTION—MEASUREMENT

Temperat ure S ensor

On-Chip Reference

Round Robin Measurement

Single-Channel Measurement

Internal Temperature Measurement

External Temperature Measurement

Layout Considerations

Interrupts

ADT7518 REGISTERS

Interrupt Status 1 Register (Read-Only) [Address = 00h]

Interrupt Status 2 Register (Read-Only) [Address = 01h]

VDD Value Register MSBs (Read-Only) [Address = 6h]

AIN2 Register MSBs (Read) [Address = 09h]

AIN3 Register MSBs (Read) [Address = 0Ah]

AIN4 Register MSBs (Read) [Address = 0Bh]

DAC A Register (Read/Write) [Address = 11h]

DAC B Register (Read/Write) [Address = 13h]

DAC C Register (Read/Write) [Address = 15h]

DAC D Register (Read/Write) [Address = 17h]

DAC Configuration Register (Read/Write) [Address = 1Bh]

LDAC Configuration Register (Write-Only) [Address = 1Ch]

Interrupt Mask 1 Register (Read/Write) [Address = 1Dh]

Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]

Device ID Register (Read-Only) [Address = 4Dh]

Manufacturer’s ID Register (Read-Only) [Address = 4Eh]