Datasheet ADT7475 Datasheet (ANALOG DEVICES)

Page 1

dBCool® Remote Thermal

FEATURES

Controls and monitors up to 4 fans High and low frequency fan drive signal 1 on-chip and 2 remote temperature sensors Extended temperature measurement range, up to 191°C Automatic fan speed control mode controls system cooling

based on measured temperature

Enhanced acoustic mode dramatically reduces user

perception of changing fan speeds

Thermal protection feature via

Monitors performance impact of Intel® Pentium® 4 processor Thermal control circuit via

THERM

3-wire and 4-wire fan speed measurement Limit comparison of all monitored values Meets SMBus 2.0 electrical specifications

(fully SMBus 1.1 compliant)

Fully ROHS compliant

THERM

input

output

FUNCTIONAL BLOCK DIAGRAM

Monitor and Fan Controller

ADT7475

GENERAL DESCRIPTION

The ADT7475 dBCool controller is a thermal monitor and multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The ADT7475 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans, so they operate at the lowest possible speed for minimum acoustic noise.

The automatic fan speed control loop optimizes fan speed for a given temperature. The effectiveness of the system’s thermal solution can be monitored using the

THERM

The ADT7475 also provides critical thermal protection to the system using the bidirectional

THERM

pin as an output to

prevent system or component overheating.

SCL

SDA SMBALERT

input.

PWM1 PWM2 PWM3

TACH1 TACH2 TACH3 TACH4

THERM

V D1+ D1– D2+ D2–

CCP

PWM

REGISTERS

AND

CONTROLLERS

(HF AND LF)

TO ADT7475

BAND GAP

TEMP. SENSOR

ADT7475

ACOUSTIC

ENHANCEMENT

CONTROL

COUNTER

PERFORMANCE

MONITORING

THERMAL

PROTECTION

CONDITIONING

MULTIPLEXER

FAN

SPEED

INPUT

SIGNAL

AND

ANALOG

GND

Figure 1.

AUTOMATIC

FAN SPEED

CONTROL

10-BIT

ADC

BAND GAP

REFERENCE

SERIAL BUS

INTERFACE

ADDRESS

POINTER

PWM

CONFIGURATION

REGISTERS

INTERRUPT

MASKING

INTERRUPT

STATUS

REGISTERS

LIMIT

COMPARATORS

VALUE AND

LIMIT

REGISTERS

05381-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

ADT7475

TABLE OF CONTENTS

Specifications..................................................................................... 3

Limits, Status Registers, and Interrupts....................................... 20

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Product Description ......................................................................... 9

Quick Comparison Between ADT7473 and ADT7475 .......... 9

Recommended Implementation................................................. 9

Serial Bus Interface..................................................................... 10

Write Operations ........................................................................ 11

Read Operations ......................................................................... 12

SMBus Timeout .......................................................................... 12

Virus Protection .......................................................................... 12

Voltage Measurement Input...................................................... 12

Analog-to-Digital Converter ....................................................12

Limit Values ................................................................................ 20

Status Registers ........................................................................... 21

THERM

Timer ........................................................................... 23

Fan Drive Using PWM Control ............................................... 26

Operating from 3.3 V Standby ................................................. 31

Standby Mode............................................................................. 31

XNOR Tree Test Mode .............................................................. 31

Power-On Default ...................................................................... 31

Programming the Automatic Fan Speed Control Loop ............ 32

Automatic Fan Control Overview............................................ 32

Step 1: Hardware Configuration .............................................. 33

Recommended Implementation 1 ........................................... 34

Recommended Implementation 2 ........................................... 35

Step 2: Configuring the Mux .................................................... 36

Step 3: T

Settings for Thermal Calibration Channels ...... 38

MIN

Input Circuitry............................................................................ 13

Voltage Measurement Registers................................................ 13

Limit Registers ...................................................................13

CCP

Extended Resolution Registers ................................................. 13

Additional ADC Functions for Voltage Measurements........ 13

Temperature Measurement Method ........................................ 15

Factors Affecting Diode Accuracy........................................... 17

Additional ADC Functions for Temperature

Measurement............................................................................... 18

REVISION HISTORY

7/05—Revision 0: Initial Version

Step 4: PWM

Step 5: PWM

Step 6: T

Step 7: T

Step 8: T

for Each PWM (Fan) Output ...................... 39

MIN

for PWM (Fan) Outputs.............................. 39

MAX

for Temperature Channels................................ 40

RANGE

for Temperature Channels ............................... 43

THERM

for Temperature Channels.................................. 44

HYST

Outline Dimensions ....................................................................... 64

Ordering Guide .......................................................................... 64

Rev. 0 | Page 2 of 64

Page 3

ADT7475

SPECIFICATIONS

TA = T

MIN

to T

, VCC = V

MAX

MIN

to V

, unless otherwise noted.

MAX

All voltages are measured with respect to GND, unless otherwise specified. Typicals are at T norm. Logic inputs accept input high voltages up to V logic levels of V

= 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and

even when device is operating down to V

MAX

= 25°C and represent most likely parametric

. Timing specifications are tested at

MIN

are not production tested.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage 3.0 3.3 3.6 V Supply Current, I

1.5 3 mA Interface inactive, ADC active

TEMP-TO-DIGITAL CONVERTER

Local Sensor Accuracy ±0.5 1.5 °C 0°C ≤ TA ≤ 85°C ±2.5 °C −40°C ≤ TA ≤ +125°C Resolution 0.25 °C Remote Diode Sensor Accuracy ±0.5 1.5 °C 0°C ≤ TA ≤ 85°C ±2.5 °C −40°C ≤ TA ≤ +125°C Resolution 0.25 °C

Remote Sensor Source Current 180 μA High Level 11 μΑ Low Level ANALOG-TO-DIGITAL CONVERTER

(INCLUDING MUX AND ATTENTUATORS)

Total Unadjusted Error (TUE) ±1.5 %

Differential Nonlinearity (DNL) ±1 LSB 8 bits

Power Supply Sensitivity ±0.1 %/V

Conversion Time (Voltage Input) 11 ms Averaging enabled

Conversion Time (Local Temperature) 12 ms Averaging enabled

Conversion Time (Remote Temperature) 38 ms Averaging enabled

Total Monitoring Cycle Time 145 ms Averaging enabled

19 ms Averaging disabled

Input Resistance 90 120 kΩ For V

channel

CCP

FAN RPM-TO-DIGITAL CONVERTER

Accuracy ±6 % 0°C ≤ TA ≤ 70°C

±10 % −40°C ≤ TA ≤ +120°C

Full-Scale Count 65,535

Nominal Input RPM 109 RPM Fan count = 0xBFFF

329 RPM Fan count = 0x3FFF

5,000 RPM Fan count = 0x0438

10,000 RPM Fan count = 0x021C OPEN-DRAIN DIGITAL OUTPUTS (PWM1 TO

PWM3, XTO)

Current Sink, I

Output Low Voltage, V

High Level Output Current, I

8.0 mA

0.4 V I

0.1 20 μA V

= −8.0 mA

OUT

= V

OUT

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

Output Low Voltage, V

High Level Output Current, I

0.4 V I

0.1 1.0 μA V

= −4.0 mA

OUT

= V

OUT

SMBus DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V

Input Low Voltage, V

2.0 V

0.4 V

Hysteresis 500 mV

Rev. 0 | Page 3 of 64

Page 4

ADT7475

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Input High Voltage, V

3.6 V Maximum input voltage

Input Low Voltage, V

−0.3 V Minimum input voltage Hysteresis 0.5 V p-p

DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+

Input High Voltage, V Input Low Voltage, V

DIGITAL INPUT CURRENT

Input High Current, I Input Low Current, I Input Capacitance, C

SERIAL BUS TIMING See Figure 2

Clock Frequency, f Glitch Immunity, t Bus Free Time, t SCL Low Time, t SCL High Time, t SCL, SDA Rise Time, t SCL, SDA Fall Time, t Data Setup Time, t Detect Clock Low Timeout, t

SCLK

BUF

LOW

HIGH

SU;DAT

TIMEOUT

LOW

SCL

2.0 V

0.8 V

0.75 × VCCV

0.4 V

±1 μA VIN = V

±1 μA VIN = 0 5 pF

10 400 kHz 50 ns

4.7 μs

4.0 50 μs 1,000 ns 300 μs 250 ns 15 35 ms Can be optionally disabled

HD; STA

BUF

HD; STA

HD; DAT

HIGH

SU; DAT

Figure 2. Serial Bus Timing Diagram

SU; STA

SU; STO

05381-002

Rev. 0 | Page 4 of 64

Page 5

ADT7475

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Positive Supply Voltage (VCC) 3.6 V Voltage on Any Input or Output Pin −0.3 V to +3.6 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (T Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering

IR Reflow Peak Temperature 260°C

Lead Temperature (Soldering 10 sec) 300°C ESD rating 1500 V

) 150°C

JMAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

16-lead QSOP package:

= 150°C/W

= 39°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 5 of 64

Page 6

ADT7475

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCL

GND

TACH3

PWM2/SMBALERT

TACH1 TACH2

PWM3

ADT7475

TOP VIEW

(Not to Scale)

SDA

PWM1/XTO

CCP

D1+ D1–

D2+

D2–

TACH4/THERM/GPIO/ SMBALERT

05381-003

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. 2 GND Ground Pin for the ADT7475. 3 V

Power Supply. VCC is also monitored through this pin. 4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. 5 PWM2/

Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control Fan 2

speed. Can be configured as a high or low frequency drive.

SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit

conditions. 6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. 7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. 8 PWM3

Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ

typical pull-up. Can be configured as a high or low frequency drive. 9 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.

THERM

Digital I/O (Open Drain). Alternatively, the pin can be reconfigured as a bidirectional THERM pin, which can be

used to time and monitor assertions on the

THERM input. For example, the pin can be connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. This pin can be used as an output to signal overtemperature conditions.

SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit

conditions.

GPIO General-Purpose Open Drain Digital I/O. 10 D2− Cathode Connection to Second Thermal Diode. 11 D2+ Anode Connection to Second Thermal Diode. 12 D1− Cathode Connection to First Thermal Diode. 13 D1+ Anode Connection to First Thermal Diode. 14 V

CCP

15 PWM1

Analog Input. Monitors processor core voltage (0 V − 3 V). Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical

pull-up.

XTO Also functions as the output from the XNOR tree in XNOR test mode. 16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.

Rev. 0 | Page 6 of 64

Page 7

ADT7475

TYPICAL PERFORMANCE CHARACTERISTICS

–10

–20

–30

–40

TEMPERATURE ERROR (°C)

–50

–60

0 2 4 6 8 10 12

CAPACITANCE (nF)

14 16 18 20 22

Figure 4. Temperature Error vs. Capacitance between D+ and D−

D+ TO GND

D+ TO V

–10

–20

TEMPERATURE ERROR (°C)

–30

–40

0204060

80 100

LEAKAGE RESISTANCE (MΩ)

Figure 5. Temperature Error vs. PCB Resistance

05381-004

05381-005

TEMPERATURE ERROR (°C)

–10

0 100M 200M 300M 400M 500M 600M

40mV

NOISE FREQUENCY (Hz)

100mV

60mV

05381-007

Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency

1.20

1.18

1.16

1.14

1.12

1.10

(mA)

1.08

1.06

1.04

1.02

1.00

0.98

3.0 3.1 3.2 3.3 3.4

Figure 8. Normal I

(V)

vs. Power Supply

3.5 3.6

05381-008

TEMPERATURE ERROR (°C)

–5

0 100M 200M 300M 400M 500M 600M

NOISE FREQUENCY (Hz)

100mV

60mV

40mV

05381-006

Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency

Rev. 0 | Page 7 of 64

100mV

–5

TEMPERATURE ERROR (

–10

–15

0 100M 200M 300M 400M 500M 600M

250mV

FREQUENCY (Hz)

Figure 9. Internal Temperature Error vs. Power Supply

05381-009

Page 8

ADT7475

–2

–4

–6

–8

TEMPERATURE ERROR (°C)

–10

–12

0 100M 200M 300M

Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency

3.0

2.5

2.0

1.5

1.0

0.5

TEMPERATURE ERROR (°C)

–0.5

–1.0

–1.5

Figure 11. Internal Temperature Error vs. ADT7475 Temperature

250mV

100mV

FREQUENCY (Hz)

–40 –20 0 20 40 60 85

OIL BATH TEMPERATURE (

400M 500M 600M

105 125

05381-010

05381-011

3.0

2.5

2.0

1.5

1.0

0.5 0

–0.5

TEMPERATURE ERROR (°C)

–1.0 –1.5 –2.0

–40 –20 0 20 40 60 85

OIL BATH TEMPERATURE (

Figure 12. Remote Temperature Error vs. ADT7475 Temperature

105 125

05381-012

Rev. 0 | Page 8 of 64

Page 9

ADT7475

PRODUCT DESCRIPTION

The ADT7475 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 16), and an input line for the serial clock (Pin 1). All control and programming functions for the ADT7475 are performed over the serial bus. In addition, a pin can be reconfigured as an SMBALERT

output to signal out-of-limit conditions.

QUICK COMPARISON BETWEEN ADT7473 AND ADT7475

• The ADT7473 supports Advanced Dynamic T

while the ADT7475 does not.

• Acoustic smoothing is improved on the ADT7475.

• THERM can be selected as an output only on the

ADT7475.

• The ADT7475 has two additional configuration registers.

• The ADT7475 has other minor register changes.

features

MIN

RECOMMENDED IMPLEMENTATION

• Configuring the ADT7475 as in Figure 13 allows the

system designer to use the following features:

• Two PWM outputs for fan control of up to three fans

(the front and rear chassis fans are connected in parallel).

• Three TACH fan speed measurement inputs.

• V

• CPU temperature measured using Remote 1 temperature

• Ambient temperature measured through Remote 2

• Bidirectional

measured internally through Pin 3.

channel.

temperature channel.

THERM

Pentium 4

PROCHOT

an overtemperature

pin. This feature allows Intel

monitoring and can function as

THERM

output. The

can alternatively be programmed as an

interrupt output.

THERM

SMBALERT

system

TACH2

PWM3 TACH3

D1+ D1–

ADT7475

SMBALERT

GND

PWM1

TACH1

D2+ D2–

THERM

SDA

SCL

PROCHOT

05381-015

FRONT CHASSIS FAN

REAR CHASSIS FAN

AMBIENT TEMPERATURE

Figure 13. ADT7475 Configuration

Rev. 0 | Page 9 of 64

Page 10

ADT7475

SERIAL BUS INTERFACE

On PCs and servers, control of the ADT7475 is carried out using the SMBus. The ADT7475 is connected to this bus as a slave device, under the control of a master controller, which is usually (but not necessarily) the ICH.

The ADT7475 has a fixed 7-bit serial bus address of 0101110 or 0x2E. The read/write bit must be added to get the 8-bit address (01011100 or 0x5C). Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle.

In the ADT7475, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, and then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register.

This write operation is shown in is sent over the bus, and then R/

Figure 14. The device address

is set to 0. This is followed

by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register.

When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as No Acknowledge. The master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

SCL

SDA

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

R/W

ACK. BY

ADT7475

When reading data from a register, there are two possibilities:

• If the ADT7475’s address pointer register value is unknown

or not the desired value, it must first be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7475 as before, but only the data byte containing the register address is sent, because no data is written to the register. This is shown in

Figure 15.

A read operation is then performed consisting of the serial bus address, R/

read from the data register. This is shown in

bit set to 1, followed by the data byte

Figure 16.

• If the address pointer register is known to be already at the

desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in

ADDRESS POINTER REGISTER BYTE

FRAME 2

Figure 16.

ACK. BY ADT7475

FRAME 3

ACK. BY

ADT7475

SDA (CONTINUED)

Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

Rev. 0 | Page 10 of 64

DATA BYTE

STOP BY MASTER

05381-016

Page 11

ADT7475

SDA

SCL

START BY

MASTER

1011

SERIAL BUS ADDRESS BYTE

FRAME 1

R/W

Figure 15. Writing to the Address Pointer Register Only

SCL

SDA

START BY

MASTER

SERIAL BUS ADDRESS BYTE

FRAME 1

Figure 16. Reading Data from a Previously Selected Register

It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register.

In addition to supporting the send byte and receive byte protocols, the ADT7475 also supports the read byte protocol. (See System Management Bus Specifications Rev. 2 for more information; this document is available from Intel.)

If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.

WRITE OPERATIONS

The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7475 are discussed below. The following abbreviations are used in the diagrams:

S—START P—STOP R—REA D W—W RI TE A—ACKNOWL EDGE

—NO ACKNOWLEDGE

The ADT7475 uses the following SMBus write protocols.

Send Byte

In this operation, the master device sends a single command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (low).

3. The addressed slave device asserts ACK on SDA.

ACK. BY

ADT7475

R/W

ACK. BY ADT7475

NO ACK. BY

MASTER

STOP BY MASTER

ADDRESS POINTER REGISTER BYTE

DATA BYTE FROM ADT745

FRAME 2

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA and the

transaction ends.

For the ADT7475, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This operation is illustrated in

23154

SLAVE

ADDRESS

Figure 17. Setting a Register Address for Subsequent Read

WASA

ADDRESS

Figure 17.

05381-019

If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition.

Write Byte

In this operation, the master device sends a command byte and one data byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master asserts a stop condition on SDA, and the

transaction ends.

05381-017

05381-018

Rev. 0 | Page 11 of 64

Page 12

ADT7475

The byte write operation is shown in Figure 18.

23154

SLAVE

ADDRESS

Figure 18. Single Byte Write to a Register

W A DATASA

ADDRESS

READ OPERATIONS

The ADT7475 uses the following SMBus read protocols.

Receive Byte

This operation is useful when repeatedly reading a single register. The register address must have been set up previously. In this operation, the master device receives a single byte from a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts ACK on SDA.

4. The master receives a data byte.

5. The master asserts NO ACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

In the ADT7475, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is shown in

Alert Response Address

Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus.

The output or an

nected to a common

If a device’s

occur:

Figure 19.

Figure 19. Single Byte Read from a Register

SMBALERT

24315

SLAVE

ADDRESS

DATAARSA

output can be used as either an interrupt

. One or more outputs can be con-

SMBALERT

line connected to the master.

line goes low, the following events

is pulled low.

678

05381-020

05381-021

4. If more than one device’s

SMBALERT

output is low, the

one with the lowest device address has priority in accordance with normal SMBus arbitration.

5. Once the ADT7475 has responded to the alert response

address, the master must read the status registers, and the SMBALERT

is cleared only if the error condition is gone.

SMBus TIMEOUT

The ADT7475 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7475 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled.

Configuration Register 1 (Reg. 0x40)

<6> TODIS = 0, SMBus timeout enabled (default).

<6> TODIS = 1, SMBus timeout disabled.

VIRUS PROTECTION

To prevent rogue programs or viruses from accessing critical ADT7475 register settings, the lock bit can be set. Setting Bit 1 of Configuration Register 1 (0x40) sets the lock bit and locks critical registers. In this mode, certain registers can no longer be written to until the ADT7475 is powered down and powered up again. For more information on which registers are locked, please see the ADT7475 Registers.

VOLTAGE MEASUREMENT INPUT

The ADT7475 has one external voltage measurement channel. It can also measure its own supply voltage, V measure V out through the V

. The VCC supply voltage measurement is carried

CCP

pin (Pin 3). The V

. Pin 14 can

input can be used to

CCP

monitor a chipset supply voltage in computer systems.

ANALOG-TO-DIGITAL CONVERTER

All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the input has built-in attenuators to allow measurement of V without any external components. To allow for the tolerance of the supply voltage, the ADC produces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and so has adequate headroom to deal with overvoltages.

CCP

2. The master initiates a read operation and sends the alert

response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address.

3. The device whose

SMBALERT

output is low responds to

the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way.

Rev. 0 | Page 12 of 64

Page 13

ADT7475

INPUT CIRCUITRY

The internal structure for the V Figure 20. The input circuit consists of an input protection diode, an attenuator, and a capacitor, to form a first-order low-pass filter that gives the input immunity to high frequency noise.

CCP

17.5kΩ

Figure 20. Structure of Analog Inputs

analog input is shown in

CCP

52.5kΩ 35pF

05381-022

VOLTAGE MEASUREMENT REGISTERS

Reg. 0x21 V

Reg. 0x22 V

LIMIT REGISTERS

CCP

Associated with the V low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate

Reg. 0x46 V

Reg. 0x47 V

Tabl e 5 shows the input ranges of the analog inputs and output codes of the 10-bit ADC.

When the ADC is running, it samples and converts a voltage input in 711 µs and averages 16 conversions to reduce noise; a measurement takes nominally 11.38 ms.

Reading = 0x00 default

CCP

Reading = 0x00 default

measurement channel is a high and

CCP

SMBALERT

Low Limit = 0x00 default

CCP

High Limit = 0xFF default

CCP

interrupts.

EXTENDED RESOLUTION REGISTERS

Voltage measurements can be made with higher accuracy using the extended resolution registers (0x76 and 0x77). Whenever the extended resolution registers are read, the corresponding data in the voltage measurement registers (0x20 to 0x 24) is locked until their data is read. That is, if extended resolution is required, then the extended resolution register must be read first, immediately followed by the appropriate voltage measurement register.

ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS

A number of other functions are available on the ADT7475 to offer the system designer increased flexibility.

Turn-Off Averaging

For each voltage measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. For instances where faster conversions are needed, setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This effectively gives a reading 16 times faster (711 µs), but the reading may be noisier.

Bypass Voltage Input Attenuator

Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes the attenuation circuitry from the V the user to directly connect external sensors, or to rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V.

Single Channel ADC Conversion

Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7475 into single channel ADC conversion mode. In this mode, the ADT7475 can be made to read a single voltage channel only. If the internal ADT7475 clock is used, the selected input is read every 711 µs. The appropriate ADC channel is selected by writing to Bits <7:5> of the TACH1 minimum high byte register (0x55).

Table 4. Single Channel ADC Conversion

Bits <7:5> Reg. 0x55 Channel Selected

001 V 010 V 101 Remote 1 Temperature 110 Local Temperature 111 Remote 2 Temperature

Configuration Register 2 (Reg. 0x73)

<4> = 1, averaging off.

<5> = 1, bypass input attenuators.

<6> = 1, single channel convert mode.

input. This allows

CCP

TACH1 Minimum High Byte (Reg. 0x55)

<7:5> selects ADC channel for single channel convert mode.

Rev. 0 | Page 13 of 64

Page 14

ADT7475

Table 5. 10-Bit A/D Output Code vs. V

(3.3 VIN)1 V

<0.0042 <0.00293 0 00000000 00

0.0042–0.0085 0.0293–0.0058 1 00000000 01

0.0085–0.0128 0.0058–0.0087 2 00000000 10

0.0128–0.0171 0.0087–0.0117 3 00000000 11

0.0171–0.0214 0.0117–0.0146 4 00000001 00

0.0214–0.0257 0.0146–0.0175 5 00000001 01

0.0257–0.0300 0.0175–0.0205 6 00000001 10

0.0300–0.0343 0.0205–0.0234 7 00000001 11

0.0343–0.0386 0.0234–0.0263 8 00000010 00

•

1.100–1.1042 0.7500–0.7529 256 (1/4-scale) 01000000 00

•

2.200–2.2042 1.5000–1.5029 512 (1/2-scale) 10000000 00

•

3.300–3.3042 2.2500–2.2529 768 (3/4 scale) 11000000 00

•

4.3527–4.3570 2.9677–2.9707 1013 11111101 01

4.3570–4.3613 2.9707–2.9736 1014 11111101 10

4.3613–4.3656 2.9736–2.9765 1015 11111101 11

4.3656–4.3699 2.9765–2.9794 1016 11111110 00

4.3699–4.3742 2.9794–2.9824 1017 11111110 01

4.3742–4.3785 2.9824–2.9853 1018 11111110 10

4.3785–4.3828 2.9853–2.9882 1019 11111110 11

4.3828–4.3871 2.9882–2.9912 1020 11111111 00

4.3871–4.3914 2.9912–2.9941 1021 11111111 01

4.3914–4.3957 2.9941–2.9970 1022 11111111 10 >4.3957 >2.9970 1023 11111111 11

The VCC output codes listed assume that VCC is 3.3 V, and VCC should never exceed 3.6 V.

A/D Output

Decimal Binary (10 Bits)

CCP

Rev. 0 | Page 14 of 64

Page 15

ADT7475

TEMPERATURE MEASUREMENT METHOD

Local Temperature Measurement

The ADT7475 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip, 10-bit ADC. The 8-bit MSB temperature data is stored in the temperature registers (Address 0x25, 0x26, and 0x27). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in

Tabl e 6 and Tabl e 7.

Theoretically, the temperature sensor and ADC can measure temperatures from −63°C to +127°C (or −61°C to +191°C in the extended temperature range) with a resolution of 0.25°C.

However, this exceeds the operating temperature range of the device, so local temperature measurements outside the ADT7475 operating temperature range are not possible.

CPU

I N× I

BIAS

Remote Temperature Measurement

The ADT7475 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pin 10 and Pin 11, or Pin 12 and Pin 13.

The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about –2 mV/°C. Unfortunately, the absolute value of V

varies from device to device and individual calibration is

required to null this out, so the technique is unsuitable for mass production.

REMOTE

SENSING

TRANSISTOR

THERMDA

THERMDC

D+

D–

BIAS

DIODE

LOW-PASS FILTER

= 65kHz

Figure 21. Signal Conditioning for Remote Diode Temperature Sensors

OUT+

OUT–

TO ADC

05381-023

Rev. 0 | Page 15 of 64

Page 16

ADT7475

The technique used in the ADT7475 is to measure the change in V

when the device is operated at two different currents.

This is given by

= KT/q × 1n(N)

V

where:

K is Boltzmann’s constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents.

Figure 21 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. It could also be a discrete transistor such as a 2N3904/2N3906.

If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D− input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D− input and the base to the D+ input. Figure 23 show how to connect the ADT7475 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D− input.

Figure 22 and

A remote temperature measurement takes nominally 38 ms. The results of remote temperature measurements are stored in 10-bit, twos complement format, as shown in

Tabl e 6 . The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (Reg. 0x77). This gives temperature readings with a resolution of 0.25°C.

Noise Filtering

For temperature sensors operating in noisy environments, previous practice was to place a capacitor across the D+ pin and D− pin to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF.

This capacitor reduces the noise, but does not eliminate it. Sometimes, this sensor noise is a problem in a very noisy environment. In most cases, a capacitor is not required as differential inputs, by their very nature, have a high immunity to noise.

ADT7475

N3904

NPN

Figure 22. Measuring Temperature Using an NPN Transistor

D+

D–

ADT7475

05381-025

To measure V

BE, the sensor is switched between operating

currents of I and N × I. The resulting waveform is passed

through a 65 kHz low-pass filter to remove noise, and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to V

BE. This voltage is measured

by the ADC to give a temperature output in 10-bit, twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles.

D+

N3906

PNP

Figure 23. Measuring Temperature Using a PNP Transistor

D–

05381-026

Rev. 0 | Page 16 of 64

Page 17

ADT7475

FACTORS AFFECTING DIODE ACCURACY

Remote Sensing Diode

The ADT7475 is designed to work with either substrate transistors built into processors or with discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). If an NPN transistor is used, the collector and base are connected to D+ and the emitter to D−. If a PNP transistor is used, the collector and base are connected to D− and the emitter is connected to D+.

To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration:

• The ideality factor, n

deviation of the thermal diode from ideal behavior. The ADT7475 is trimmed for an n following equation to calculate the error introduced at a temperature T (°C), when using a transistor whose n does not equal 1.008. See the processor data sheet for the

values.

ΔT = (n

To factor this in, the user can write the ∆T value to the offset register. The ADT7475 then automatically adds it to or subtracts it from the temperature measurement.

• Some CPU manufacturers specify the high and low current

levels of the substrate transistors. The high current level of the ADT7475, I I

, is 11 µA. If the ADT7475 current levels do not match

LOW

the current levels specified by the CPU manufacturer, it might be necessary to remove an offset. The CPU’s data sheet advises whether this offset needs to be removed and how to calculate it. This offset can be programmed to the offset register. If more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register.

If a discrete transistor is used with the ADT7475, the best accuracy is obtained by choosing devices according to the following criteria:

• Base-emitter voltage greater than 0.25 V at 11 µA, at the

highest operating temperature.

• Base-emitter voltage less than 0.95 V at 180 µA, at the

lowest operating temperature.

• Base resistance less than 100 Ω.

, of the transistor is a measure of the

value of 1.008. Use the

− 1.008) × (273.15 K + T)

, is 180 µA and the low level current,

HIGH

Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23 packages, are suitable devices to use.

Table 6. Twos Complement Temperature Data Format

Temperature Digital Output (10-Bit)

–128°C –50°C –25°C –10°C 0°C

10.25°C

25.5°C

50.75°C 75°C 100°C 125°C 127°C

Bold numbers denote 2 LSB of measurement in Extended Resolution

1000 0000 00 (diode fault) 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00

Table 7. Extended Range, Temperature Data Format

Temperature Digital Output (10-Bit)1

–64°C –1°C 0°C 1°C 10°C 25°C 50°C 75°C 100°C 125°C 191°C

Bold numbers denote 2 LSB of measurement in Extended Resolution

0000 0000 00 (diode fault) 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00

Nulling Out Temperature Errors

As CPUs run faster, it is more difficult to avoid high frequency clocks when routing the D+/D– traces around a system board. Even when recommended layout guidelines are followed, some temperature errors may still be attributable to noise coupled onto the D+/D– lines. Constant high frequency noise usually attenuates, or increases, temperature measurements by a linear, constant value.

The ADT7475 has temperature offset registers at Addresses 0x70, 0x72 for the Remote 1 and Remote 2 temperature channels. By doing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement.

• Small variation in h

indicates tight control of V

(approximately 50 to 150) that

characteristics.

Rev. 0 | Page 17 of 64

Page 18

ADT7475

Changing Bit 1 of Configuration Register 5 (0x7C) changes the resolution and therefore the range of the temperature offset as either having a range of –63°C to +127°C, with a resolution of 1°C, or having a range of -63°C to +64°C, with a resolution of

0.5°C. This temperature offset can be used to compensate for linear temperature errors introduced by noise.

Reading Temperature from the ADT7475

It is important to note that temperature can be read from the ADT7475 as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25°C resolution). If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order.

Temperature Offset Registers

Reg. 0x70, Remote 1 Temperature Offset = 0x00 (0°C default)

Reg. 0x71, Local Temperature Offset = 0x00 (0°C default)

Reg. 0x72, Remote 2 Temperature Offset = 0x00 (0°C default)

ADT7463/ADT7475 Backwards Compatible Mode

By setting Bit 0 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temp value registers (0x25, 0x26, and 0x27) in twos complement in the range −63°C to +127°C. The temperature limits must be reprogrammed in twos complement.

If a twos complement temperature below −63°C is entered, the temperature is clamped to −63°C. In this mode, the diode fault condition remains −128°C = 1000 0000, while in the extended temperature range (−63°C to +191°C), the fault condition is represented by −64°C = 0000 0000.

Temperature Measurement Registers

Reg. 0x25, Remote 1 Temperature

Reg. 0x26, Local Temperature

Reg. 0x27, Remote 2 Temperature

Reg. 0x77, Extended Resolution 2 = 0x00 default

<7:6> TDM2, Remote 2 Temperature LSBs.

<5:4> LTMP, Local Temperature LSBs.

<3:2> TDM1, Remote 1 Temperature LSBs.

Temperature Measurement Limit Registers

Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate

way the interrupt mask register is programmed and assuming that

SMBALERT

is set as an output on the appropriate pin).

interrupts (depending on the

If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution register (Reg. 0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read and vice versa.

ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT

A number of other functions are available on the ADT7475 to offer the system designer increased flexibility.

Turn-Off Averaging

For each temperature measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. Sometimes it is necessary to take a very fast measurement. Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. The default round-robin cycle time takes 146.5 ms.

Table 8. Conversion Time with Averaging Disabled

Channel Measurement Time (ms)

Voltage Channels 0.7 Remote Temperature 1 7 Remote Temperature 2 7 Local Temperature 1.3

When bit 7 of configuration register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms.

Table 9. Conversion Time with Averaging Enabled

Channel Measurement Time (ms)

Voltage Channels 11 Remote Temperature 39 Local Temperature 12

Reg. 0x4E, Remote 1 Temperature Low Limit = 0x81 default

Reg. 0x4F, Remote 1 Temperature High Limit = 0x7F default

Reg. 0x50, Local Temperature Low Limit = 0x81 default

Reg. 0x51, Local Temperature High Limit = 0x7F default

Reg. 0x52, Remote 2 Temperature Low Limit = 0x81 default

Reg. 0x53, Remote 2 Temperature High Limit = 0x7F default

Rev. 0 | Page 18 of 64

Page 19

ADT7475

Single Channel ADC Conversions

Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7475 into single channel ADC conversion mode. In this mode, the ADT7475 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits <7:5> of the TACH1 minimum high byte register (0x55).

Table 10. Programming Single Channel ADC Mode for Temperatures

Bits <7:5> Reg. 0x55 Channel Selected

101 Remote 1 temperature 110 Local temperature 111 Remote 2 temperature

Configuration Register 2 (Reg. 0x73)

<4> = 1, averaging off.

<6> = 1, single channel convert mode.

TACH1 Minimum High Byte (Reg. 0x55)

<7:5> selects ADC channel for single channel convert mode.

Overtemperature Events

Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Register 0x6A to Register 0x6C are the

temperature limits. When a temperature exceeds its

THERM

temperature limit, all PWM outputs run at the maximum

PWM duty cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A). This effectively runs the fans at the fastest allowed speed.

The fans run at this speed until the temperature drops below THERM

minus hysteresis. This can be disabled by setting the

boost bit in Configuration Register 3, Bit 2, Reg. 0x78. The hysteresis value for the

THERM

temperature limit is the value

programmed into Reg. 0x6D and Reg. 0x6E (hysteresis registers). The default hysteresis value is 4°C.

THERM LIMIT

HYSTERESIS (°C)

TEMPERATURE

FANS

Figure 24.

THERM

can be disabled on specific temperature channels using

bits <7:5> of configuration register 5 (0x7C).

100%

THERM

Temperature Limit Operation

THERM

can also

be disabled by:

• In offset 64 mode, writing −64°C to the appropriate

temperature limit.

THERM

• In twos complement mode, writing −128°C to the

appropriate

THERM

temperature limit.

05381-027

Rev. 0 | Page 19 of 64

Page 20

ADT7475

LIMITS, STATUS REGISTERS, AND INTERRUPTS

LIMIT VALUES

Associated with each measurement channel on the ADT7475 are high and low limits. These can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and detected by polling the device. Alternatively, SMBALERT or microcontroller of out-of-limit conditions.

8-Bit Limits

The following is a list of 8-bit limits on the ADT7475.

Volt ag e Li m it R eg ist ers

Reg. 0x46 V

Reg. 0x47 V

Reg. 0x48 V

interrupts can be generated to flag a processor

Low Limit = 0x00 default

CCP

High Limit = 0xFF default

CCP

Low Limit = 0x00 default

Reg. 0x57 TAC H2 M ini m um H i gh B yte = 0x00 default

Reg. 0x58 TAC H3 M ini m um L ow B yte = 0x00 default

Reg. 0x59 TAC H3 M ini m um H i gh B yte = 0x00 default

Reg. 0x5A TAC H4 M ini m um L ow B yte = 0x00 default

Reg. 0x5B TAC H4 M ini m um H i gh B yte = 0x00 default

Out-of-Limit Comparisons

Once all limits have been programmed, the ADT7475 can be enabled for monitoring. The ADT7475 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit for out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently, depending on whether the measured value is being compared to a high or low limit.

Reg. 0x49 V

High Limit = 0xFF default

Temperature Limit Registers

Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default

Reg. 0x4F Remote 1 Temperature High Limit = 0x7F default

Reg. 0x6A Remote 1

THERM

Limit = 0x64 default

Reg. 0x50 Local Temperature Low Limit = 0x01 default

Reg. 0x51 Local Temperature High Limit = 0x7F default

Reg. 0x6B Local

THERM

Limit = 0x64 default

Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default

Reg. 0x53 Remote 2 Temperature High Limit = 0x7F default

Reg. 0x6C Remote 2

THERM

Reg. 0x7A

Limit Register

THERM

Limit = 0x00 default

Limit = 0x64 default

16-Bit Limits

The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Because fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan TACHs. Because the fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan.

High Limit: > Comparison Performed

Low Limit: ≤ Comparison Performed

Voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. Fan speed measurements use only a low limit. This fan limit is needed only in manual fan control mode.

Analog Monitoring Cycle Time

The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). By default, the ADT7463 powers up with this bit set. The ADC measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1.

As the ADC is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read out at any time.

For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured is

• One dedicated supply voltage input (V

• Supply voltage (V

pin)

CCP

)

Fan Limit Registers

Reg. 0x54 TAC H1 M ini m um L ow B yte = 0x00 default

Reg. 0x55 TAC H1 M ini m um H i gh B yte = 0x00 default

Reg. 0x56 TAC H2 M ini m um L ow B yte = 0x00 default

• Local temperature

• Two remote temperatures

Rev. 0 | Page 20 of 64

Page 21

ADT7475

As mentioned previously, the ADC performs round-robin conversions. The total monitoring cycle time for averaged voltage and temperature monitoring is 146 ms. The total monitoring cycle time for voltage and temperature monitoring with averaging disabled is 19 ms. The ADT7475 is a derivative of the ADT7467. As a result, the total conversion time in the ADT7475 is the same as the total conversion time of the ADT7467.

Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way.

STATUS REGISTERS

The results of limit comparisons are stored in Status Register 1 and Status Register 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out-of-limits, the corresponding status register bit is set to 1.

The state of the various measurement channels can be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit event has been flagged in Status Register 2. This means that the user needs only to read Status Register 2 when this bit is set. Alternatively, Pin 5 or Pin 9 can be configured as an

SMBALERT

This automatically notifies the system supervisor of an out-oflimit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared.

Status register bits are sticky. Whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the status bit is to read the status register after the event has gone away. Interrupt status mask registers (Reg. 0x74, 0x75) allow individual interrupt sources to be masked from causing an

SMBALERT

. However, if one of these masked interrupt

sources goes out-of-limit, its associated status bit is set in the interrupt status registers.

Status Register 1 (Reg. 0x41)

Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and Status Register 2 should be read.

Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has been exceeded.

Bit 5 (LT) = 1, local temperature high or low limit has been exceeded.

output.

Status Register 2 (Reg. 0x42)

Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.

Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.

Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum

speed. Alternatively, indicates the

exceeded, if the

THERM

function is used.

THERM

limit has been

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum speed.

Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum speed.

Bit 1 (OVT) = 1, indicates a

THERM

overtemperature limit has

been exceeded.

SMBALERT

The ADT7475 can be polled for status, or an

Interrupt Behavior

SMBALERT

interrupt can be generated for out-of-limit conditions. Note how the

SMBALERT

output and status bits behave when

writing interrupt handler software.

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

“STICKY”

STATUS BIT

TEMP BACK IN LIMIT

SMBALERT

(STATUS BIT STAYS SET)

Figure 25.

SMBALERT

Figure 25 shows how the

and Status Bit Behavior

SMBALERT

(TEMP BELOW LIMIT)

output and sticky status

bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky, because they remain set until read by software. This ensures an out-of-limit event cannot be missed, if software is polling the device periodically. Note the

SMBALERT

output

remains low for the entire duration that a reading is out-of-limit and until the status register has been read. This has implications on how software handles the interrupt.

05381-028

Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has been exceeded.

Bit 2 (V

Bit 1 (V

) = 1, VCC high or low limit has been exceeded.

CCP

) = 1, V

high or low limit has been exceeded.

CCP

Rev. 0 | Page 21 of 64

Page 22

ADT7475

Handling

SMBALERT

To prevent the system from being tied up servicing interrupts, it is recommended to handle the

1. Detect the

Interrupts

SMBALERT

assertion.

interrupt as follows:

Bit 2 (V

Bit 0 (V

) = 1, masks

CCP

SMBALERT

for VCC channel.

for V

Interrupt Mask Register 2 (Reg. 0x75)

Bit 7 (D2) = 1, masks

SMBALERT

for Diode 2 errors.

channel.

CCP

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt source.

4. Mask the interrupt source by setting the appropriate mask

bit in the interrupt mask registers (Reg. 0x74, Reg. 0x75).

5. Take the appropriate action for a given interrupt source.

6. Exit the interrupt handler.

7. Periodically poll the status registers. If the interrupt status

bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the

behave as shown in .

HIGH LIMIT

TEMPERATURE

“STICKY” TATUS BI

SMBALERT

Figure 26. How Masking the Interrupt Source

Figure 26

TEMP BACK IN LIMIT (STATUS BIT STAYS SET)

Affects

SMBALERT

INTERRUPT MASK BIT SET

SMBALERT

output and status bits to

CLEARED ON READ

(TEMP BELOW LIMIT)

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Output

Masking Interrupt Sources

Interrupt Mask Registers 1 and 2 are located at Address 0x74 and Address 0x75. These allow individual interrupt sources to be masked out to prevent

SMBALERT

masking an interrupt source prevents only the

interrupts. Note that

SMBALERT

output from being asserted; the appropriate status bit is set normally.

05381-029

Bit 6 (D1) = 1, masks

Bit 5 (FAN4) = 1, masks

SMBALERT

If the TACH4 pin is being used as the masks

SMBALERT

Bit 4 (FAN3) = 1, masks

Bit 3 (FAN2) = 1, masks

Bit 2 (FAN1) = 1, masks

Bit 1 (OVT) = 1, masks

(exceeding

Enabling the

The

SMBALERT

for a

THERM

SMBALERT

THERM

limits).

SMBALERT

interrupt function is disabled by default. Pin 5

or Pin 9 can be reconfigured as an

for Diode 1 errors.

for Fan 4 failure.

THERM

event.

for Fan 3.

for Fan 2.

for Fan 1.

for overtemperature

Interrupt Output

SMBALERT

input, this bit

output to signal

out-of-limit conditions.

Table 11. Configuring Pin 5 as

Configuration Register 3 (Reg. 0x78) <0> ALERT = 1

Assigning

THERM

Functionality to a Pin

SMBALERT

Output

Pin 9 on the ADT7475 has four possible functions: SMBus ALERT,

THERM

, GPIO, and TACH4. The user chooses the

required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D.

Table 12. Pin 9 Configuration

Bit 0 Bit 1 Function

0 0 TACH4 0 1 1 0 SMBus ALERT 1 1 GPIO

Once Pin 9 is configured as

THERM

, it must be enabled (Bit 1,

Configuration Register 3 at Address 0x78).

Interrupt Mask Register 1 (Reg. 0x74)

Bit 7 (OOL) = 1, masks

SMBALERT

for any alert condition

flagged in Status Register 2.

Bit 6 (R2T) = 1, masks

Bit 5 (LT) = 1, masks

Bit 4 (R1T) = 1, masks

SMBALERT

for Remote 2 temperature.

for local temperature.

for Remote 1 temperature.

Rev. 0 | Page 22 of 64

THERM

When assertions on the

ing to the

performance.

as an Input

THERM

is configured as an input, the user can time

PROCHOT

THERM

pin. This can be useful for connect-

output of a CPU to gauge system

Page 23

ADT7475

The user can also set up the ADT7475 so when the

THERM

is driven low externally, the fans run at 100%. The fans run at 100% for the duration of the time that the

THERM

pin is

pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (Address = 0x78) to 1. This works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above T T

or if the duty cycle in manual mode is set to 0x00, then pull-

MIN

ing the

THERM

low externally has no effect. See for

. If the temperature is below

MIN

Figure 27

more information.

MIN

The 8-bit

THERM that the Bit 0 is set to 1 on the first

cumulative

of the

THERM

the timer with a resolution of 22.76 ms (see ).

When using the

After a

THERM

timer register (Reg. 0x79) is designed so

assertion. Once the

THERM

assertion time has exceeded 45.52 ms, Bit 1

timer is set and Bit 0 now becomes the LSB of

Figure 28

THERM

timer, be aware of the following.

timer read (Reg. 0x79):

1. The contents of the timer are cleared on read.

2. The F4P bit (Bit 5) of Status Register 2 needs to be cleared

(assuming that the

THERM

timer limit has been

exceeded).

THERM

THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS BELOW T

Figure 27. Asserting

THERM

TIMER

The ADT7475 has an internal timer to measure assertion time. For example, the

nected to the

PROCHOT

measure system performance. The

MIN

THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS ABOVE T ARE ALREADY RUNNING

THERM

Low as an Input in Automatic Fan Speed Control

Mode

MIN

THERM

input can be con-

output of a Pentium 4 CPU to

THERM

input can also be

AND FANS

connected to the output of a trip point temperature sensor.

The timer is started on the assertion of the ADT7475’s

input and stopped when

THERM on the next

accumulate

times cumulatively, that is, the timer resumes counting

THERM

assertion. The

assertion times until the timer is read (it is

THERM

is unasserted. The timer counts

THERM

timer continues to

THERM

cleared on read) or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared.

05381-030

If the

THERM

timer is read during a

THERM

assertion, the

following happens:

1. The contents of the timer are cleared.

2. Bit 0 of the

THERM

timer is set to 1 (because a

THERM

assertion is occurring).

3. The

4. If the

THERM

timer increments from zero.

THERM

timer limit (Reg. 0x7A) = 0x00, then the

F4P bit is set.

THERM

TIMER

(REG. 0x79)

THERM

TIMER

(REG. 0x79)

THERM

TIMER

(REG. 0x79)

000 00010 765 32104

ACCUMULATE THERM LOW

ASSERTION TIMES

000 00100 765 32104

ACCUMULATE THERM LOW

ASSERTION TIMES

000 01010 765 32104

Figure 28. Understanding the

THERM ASSERTED

≤ 22.76ms

THERM ASSERTED

≥ 45.52ms

THERM ASSERTED ≥ 113.8ms

(91.04ms + 22.76ms)

THERM

Timer

05381-031

Rev. 0 | Page 23 of 64

Page 24

ADT7475

Generating

SMBALERT

Events

The ADT7475 can generate ble

THERM

timer limit has been exceeded. This allows the

system designer to ignore brief, infrequent

while capturing longer the

THERM

timer limit register. This 8-bit register allows a

limit from 0 sec (first

before an

SMBALERT

compared with the contents of the

Interrupts from

SMBALERT

THERM

is generated. The

THERM TIMER LIMIT (REG. 0x7A)

728.32ms

364.16ms

182.08ms

s when a programma-

timer events. Register 0x7A is

assertion) to 5.825 sec to be set

THERM

2.914s

1.457s

91.04ms

45.52ms

22.76ms

THERM

Timer

assertions,

timer value is

timer limit register.

If the

THERM

timer value exceeds the

THERM

timer limit

value, then the F4P bit (Bit 5) of Status Register 2 is set, and an

SMBALERT

is generated. Note the F4P bit (Bit 5) of Mask

SMBALERT

s, if this bit is set

to 1; although the F4P bit of Interrupt Status Register 2 still is set, if the

THERM

Figure 29 is a functional block diagram of the

timer limit is exceeded.

THERM

timer,

limit, and associated circuitry. Writing a value of 0x00 to the THERM be generated on the first

limit value of 0x01 generates an

THERM

timer limit register (Reg. 0x7A) causes

THERM

assertion. A

SMBALERT

, once cumulative

assertions exceed 45.52 ms.

2.914s

1.457s

728.32ms

364.16ms

182.08ms

91.04ms

45.52ms

22.76ms

THERM TIMER

(REG. 0x79)

SMBALERT

THERM

timer

Figure 29. Functional Block Diagram of ADT7475’s

543

COMPARATOR

543210

CLEARED

ON READ

OUT

LATCH RESET

THERM TIMER CLEARED ON READ

F4P BIT (BIT 5)

STATUS REGISTER 2

1 = MASK

F4P BIT (BIT 5)

MASK REGISTER 2

(REG. 0x75)

THERM

Monitoring Circuitry

THERM

SMBALERT

05381-032

Rev. 0 | Page 24 of 64

Page 25

ADT7475

Configuring the

THERM

1. Configure the relevant pin as the

Setting Bit 1 ( Register 3 (Reg. 0x78) enables the

monitoring functionality. This is disabled on Pin 9 by default.

Setting Bit 0 and Bit 1 (PIN9FUNC) of Configuration Register 4 (Reg. 0x7D) enables

functionality on Pin 9 (Bit 1 of Configuration Register 3,

be used as TACH4.

2. Select the desired fan behavior for

events.

Assuming that the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (Reg. 0x78) causes all fans to run at 100% duty cycle whenever THERM

gets asserted. This allows fail-safe system

cooling. If this bit is 0, the fans run at their current settings and are not affected by

fans are not already running when

asserted, the fans do not run to full speed.

3. Select whether

SMBALERT

Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks out

value gets exceeded. This bit should be cleared if SMBALERT

4. Select a suitable

This value determines whether an

generated on the first

cumulative

A value of 0x00 causes an on the first

5. Select a

THERM

Behavior

THERM

, must also be set). Pin 9 can also

THERM

interrupts.

SMBALERT

s based on

THERM

assertion time limit is exceeded.

assertion.

monitoring time.

THERM

timer input.

timer enable) of Configuration

THERM

timer

timer/output

timer

events. If the

timer events should generate

s when the

THERM

events are required.

THERM

timer limit

limit value.

THERM

SMBALERT

assertion, or only if a

to be generated

Alternatively, OS- or BIOS-level software can timestamp when the system is powered on. If an SMBALERT is generated due to the

THERM

timer limit being exceeded,

another timestamp can be taken. The difference in time can be calculated for a fixed

THERM

For example, if it takes one week for a

timer limit time.

THERM

timer limit

of 2.914 sec to be exceeded and the next time it takes only 1 hour, then this is an indication of a serious degradation in system performance.

Configuring the

THERM

In addition to monitoring can optionally drive

PROCHOT

is bidirectional,

processor by asserting

Pin as an Output

THERM

low as an output. In cases where

THERM

PROCHOT

as an input, the ADT7475

can be used to throttle the

. The user can preprogram

system-critical thermal limits. If the temperature exceeds a thermal limit by 0.25°C,

THERM

asserts low. If the tempera-

ture is still above the thermal limit on the next monitoring cycle,

THERM

stays low.

THERM

remains asserted low until

the temperature is equal to or below the thermal limit. Because the temperature for that channel is measured only once for every monitoring cycle, after

THERM

asserts it is guaranteed

to remain low for at least one monitoring cycle.

The

THERM local, or Remote 2

by 0.25°C. The

pin can be configured to assert low, if the Remote 1,

THERM

temperature limits are exceeded

temperature limit registers are at

Registers 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of Registers 0x5F, 0x60, and 0x61 enables the

THERM

output

feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 33 shows how the

THERM

asserts low as an output in the event of a critical overtemperature.

THERM LIMIT

0.25°C

THERM LIMIT

TEMP

THERM

This value specifies how often OS or BIOS level software checks the

BIOS could read the

THERM

THERM determine the cumulative

If, for example, the total

timer. For example,

timer once an hour to

THERM

assertion time.

assertion time is

<22.76 ms in Hour 1, >182.08 ms in Hour 2, and >5.825 s in Hour 3, this can indicate that system performance is degrading significantly because THERM

is asserting more frequently on an hourly

basis.

An alternative method of disabling

THERM or −128°C or less in twos complement mode; that is, for THERM respectively,

Rev. 0 | Page 25 of 64

MONITORING

CYCLE

Figure 30. Asserting

THERM

as an Output, Based on Tripping

THERM

Limits

THERM

is to program the

temperature limit to −64°C or less in Offset 64 mode,

temperature limit values less than −63°C or −128°C,

THERM

is disabled.

05381-033

Page 26

ADT7475

Enabling and Disabling

THERM

can be enabled/disabled for individual or combina-

THERM

tions of temperature channels using bits <7:5> of Configuration Register 5 (0x7C).

THERM

Hysteresis

Setting Bit 0 of Configuration Register 7 (0x11) disables THERM

hysteresis.

on Individual Channels

The only other stipulation is that the MOSFET should have a gate voltage drive, V

< 3.3 V, for direct interfacing to the

PWM output pin. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan.

Figure 31 shows how to drive a 3-wire fan using PWM control.

12V 12V

THERM of Configuration Register 4, 0x7D), the

assert low when a is disabled and

hysteresis is enabled and

THERM

event occurs. If

is disabled (Bit 2 of Configuration

THERM

is disabled (Bit 2

pin does not

THERM

hysteresis

THERM

), the

THERM

pin asserts low when a

THERM

event occurs.

THERM

and

THERM

output asserts as expected.

Operation in Manual mode

In Manual mode,

hysterisis are both enabled, the

THERM

events do not cause fans to go to full

speed, unless Bit 3 of Configuration Register 6 (0x10) is set to 1.

Additionally, Bit 3 of Configuration Register 4 (0x7D) can be used to select PWM speed on THERM event (100% or maximum PWM).

Bit 2 in Configuration Register 4 (0x7D) can be set to disable THERM

events from affecting the fans.

FAN DRIVE USING PWM CONTROL

The ADT7475 uses pulse-width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4-wire fans, the PWM drive might need only a pull-up resistor. In many cases, the 4-wire fan PWM input has a built-in pull-up resistor.

The ADT7475 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are usually used for 3-wire fans, while the high frequency option us usually used with 4-wire fans.

For 3-wire fans, a single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven. Typical notebook fans draw a nominal 170 mA, so SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250 mA to 300 mA each. If you drive several fans in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements.

10kΩ

TACH/AIN

ADT7475

Figure 31. Driving a 3-Wire Fan Using an N-Channel MOSFET

PWM

10kΩ

4.7kΩ

3.3V

10kΩ

12V FAN

Q1 NDT3055L

1N4148

05381-034

Figure 31 uses a 10 kΩ pull-up resistor for the TACH signal. This assumes that the TACH signal is an open-collector from the fan. In all cases, the TACH signal from the fan must be kept below

3.6 V maximum to prevent damaging the ADT7475. If in doubt as to whether the fan used has an open-collector or totem pole TACH output, use one of the input signal conditioning circuits shown in the

Fan Speed Measurement section.

Figure 32 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan’s current requirements.

Ensure that the base resistor is chosen, so the transistor is saturated when the fan is powered on.

12V 12V

10kΩ

TACH

ADT7475

PWM

Figure 32. Driving a 3-Wire Fan Using an NPN Transistor

10kΩ

4.7kΩ

665Ω

TACH

3.3V

12V FAN

Q1 MMBT2222

1N4148

05381-035

Rev. 0 | Page 26 of 64

Page 27

ADT7475

Because 4-wire fans are powered continuously, the fan speed is not switched on or off as with previous PWM driven/powered fans. This enables it to perform better than 3-wire fans, especially for high frequency applications.

Figure 33 shows a typical

drive circuit for 4-wire fans.

12V

12V, 4-WIRE FAN

TACH PWM

05381-036

TACH

ADT7475

PWM

10kΩ

4.7kΩ

2kΩ

10kΩ

TACH

3.3V

Figure 33. Driving a 4-Wire Fan

Driving Two Fans from PWM3

The ADT7475 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan.

Figure 34 shows how to drive two fans in parallel using low cost NPN transistors.

Figure 35 shows the equivalent circuit using a

MOSFET.

12V

ADT7475

Figure 34. Interfacing Two Fans in Parallel to the PWM3 Output Using Low

TACH4

ADT7475

TACH3

PWM3

Figure 35. Interfacing Two Fans in Parallel to the PWM3 Output Using a

PWM3

3.3V 3.3V TACH3 TACH4

1kΩ

2.2kΩ

MMBT3904

10Ω

Cost NPN Transistors

3.3V

10kΩ TYPICAL

3.3V

10kΩ TYPICAL

+V +V

5V OR

TACH TACH

12V FAN

Q1 NDT3055L

Single N-Channel MOSFET

Q2 MMBT2222

MMBT2222

1N4148

5V OR 12V FAN

05381-037

05381-038

Because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 8 mA maximum current specified on the data sheet.

Driving up to Three Fans from PWM3

TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH 3 a n d TAC H 4 are bot h s y nchronized t o P WM3, so PWM3 can drive two fans. Alternatively, PWM3 can be programmed t o s ynchronize TAC H 2 , TAC H3, and TACH4 t o t he PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry looks the same, as shown in Figure 37 and Figure 38. The SYNC bit in Register 0x62 enables this function.

Synchronization is not required in high frequency mode when used with 4-wire fans.

<4> (SYNC) Enhance Acoustics Register 1 (Reg. 0x62)

SYNC = 1, s y nchronizes TAC H 2 , TAC H3, and TACH4 to PWM3.

TACH Inputs

Pin 4, Pin 6, Pin 7, and Pin 9, when configured as TACH inputs, are open-drain TACH inputs intended for fan speed measurement.

Signal conditioning in the ADT7475 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 3.6 V. In the event these inputs are supplied from fan outputs that exceed 0 V to 3.6 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range.

Figure 36 to Figure 39 show circuits for most common fan TACH outputs. If the fan TACH output has a resistive pull-up to V

, it can be connected directly to the fan input, as shown

Figure 36.

12V

PULL-UP

4.7kΩ

TYPICAL

TACH OUTPUT

Figure 36. Fan with TACH Pull-Up to V

TACH

FAN SPEED

COUNTER

ADT7475

05381-039

Rev. 0 | Page 27 of 64

Page 28

ADT7475

If the fan output has a resistive pull-up to 12 V, or other voltage greater than 3.6 V, the fan output can be clamped with a Zener diode, as shown in be chosen so that it is greater than V less than 3.6 V, allowing for the voltage tolerance of the Zener. A value between 3 V and 3.6 V is suitable.

12V

Figure 37. Fan with TACH Pull-Up to Voltage > 3.6 V (for example, 12 V)

Figure 37. The Zener diode voltage should

of the TACH input but

PULL-UP

4.7kΩ

TYPICAL

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8

TACH OUTPUT

TACH

ZD1*

Clamped with Zener Diode

FAN SPEED

COUNTER

ADT7475

05381-040

Fan Speed Measurement

The fan counter does not count the fan TACH output pulses directly, because the fan speed could be less than 1,000 RPM and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (

Figure 40), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed.

N, the number of pulses counted, is determined by the settings of Register 0x7B (TACH pulses per revolution register). This register contains two bits for each fan, allowing one, two (default), three, or four TACH pulses to be counted.

If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a totem-pole output, then a series resistor can be added to limit

10kΩ

TACH OUTPUT

Figure 38.

TACH

ZD1 ZENER*

FAN SPEED

COUNTER

ADT7475

or Totem-Pole Output,

the Zener current, as shown in

5V OR 12V FAN

PULL-UP TYP

<1kΩ OR

TOTEM POLE

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8

Figure 38. Fan with Strong TACH Pull-Up to > V

Clamped with Zener and Resistor

Alternatively, a resistive attenuator can be used, as shown in Figure 39. R1 and R2 should be chosen such that

2 V < V

PULL-UP

× R2/(R

+ R1 + R2) < 3.6 V

PULL-UP

The fan inputs have an input resistance of nominally 160 kΩ to ground, which should be taken into account when calculating resistor values.

With a pull-up voltage of 12 V and pull-up resistor less than 1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ, respectively. This gives a high input voltage of 3.83 V.

12V

05381-041

CLOCK

PWM

TACH

Figure 40. Fan Speed Measurement

Fan Speed Measurement Registers

The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADT7475.

Reg. 0x28 TAC H1 L ow B yte = 0x00 default

Reg. 0x29 TAC H1 H i gh B yte = 0x00 default

Reg. 0x2A TAC H2 L ow Byte = 0x00 default

Reg. 0x2B TAC H2 H ig h Byte = 0x00 default

Reg. 0x2C TAC H3 L ow Byte = 0x00 default

Reg. 0x2D TAC H3 H ig h Byte = 0x00 default

Reg. 0x2E TAC H4 L ow B yte = 0x00 default

Reg. 0x2F TAC H4 H i gh B yte = 0x00 default

05381-043

<1kΩ

R1*

TACH OUTPUT

TACH

R2*

*SEE TEXT

Figure 39. Fan with Strong TACH Pull-Up to > V

Attenuated with R1/R2

FAN SPEED

COUNTER

ADT7475

or Totem-Pole Output,

05381-042

Rev. 0 | Page 28 of 64

Page 29

ADT7475

Reading Fan Speed from the ADT7475

The measurement of fan speeds involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous TACH readings. The fan tachometer reading registers report back the number of

11.11 µs period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). Because the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or is running very slowly (<100 RPM).

High Limit: > Comparison Performed

Because the actual fan TACH period is being measured, falling below a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an

SMBALERT

Calculating Fan Speed

Assuming a fan with a two pulses per revolution (and two pulses per revolution being measured) fan speed is calculated by the following:

Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading

where Fan TACH Reading is the 16-bit fan tachometer reading.

Example

TACH1 High Byte (Reg. 0x29) = 0x17

TACH1 Low Byte (Reg. 0x28) = 0xFF

What is Fan 1 speed in RPM?

Fan 1 TACH Reading = 0x17FF = 6143 (decimal)

RPM = (f × 60)/Fan 1 TACH R eadin g

RPM = (90000 × 60)/6143

Fan Speed = 879 RPM

Fan TACH Limit Registers

The fan TACH limit registers are 16-bit values consisting of two bytes.

Reg. 0x54 TAC H1 M ini m um L ow B yte = 0xFF default

Reg. 0x55 TAC H1 M ini m um H i gh B yte = 0xFF default

Reg. 0x56 TAC H2 M ini m um L ow B yte = 0xFF default

Reg. 0x57 TAC H2 M ini m um H i gh B yte = 0xFF default

Reg. 0x58 TAC H3 M ini m um L ow B yte = 0xFF default

Reg. 0x59 TAC H3 M ini m um H i gh B yte = 0xFF default

Reg. 0x5A TAC H4 M ini m um L ow B yte = 0xFF default

Reg. 0x5B TAC H4 M ini m um H i gh B yte = 0xFF default

Fan Speed Measurement Rate

The fan TACH readings are normally updated once every second. The FAST bit (Bit 3) of Configuration Register 3 (Reg. 0x78), when set, updates the fan TACH readings every 250 ms.

If any of the fans are not being driven by a PWM channel but are powered directly from 5 V or 12 V, their associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. For optimal results, the associated dc bit should always be set when using 4-wire fans.

Fan Pulses per Revolution

Different fan models can output either 1, 2, 3, or 4 TACH pulses per revolution. Once the number of fan TACH pulses has been determined, it can be programmed into the fan pulses per revolution register (Reg. 0x7B) for each fan.

Alternatively, this register can be used to determine the number or pulses per revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value.

Fan Pulses per Revolution Register

<1:0> Fan 1 default = 2 pulses per revolution.

<3:2> Fan 2 default = 2 pulses per revolution.

<5:4> Fan 3 default = 2 pulses per revolution.

<7:6> Fan 4 default = 2 pulses per revolution.

00 = 1 pulse per revolution.

01 = 2 pulses per revolution.

10 = 3 pulses per revolution.

11 = 4 pulses per revolution.

Rev. 0 | Page 29 of 64

Page 30

ADT7475

Fan Spin-Up

The ADT7475 has a unique fan spin-up function. It spins the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. Once two TACH pulses have been detected, the PWM duty cycle goes to the expected running value, for example, 33%. The advantage is that fans have different spin-up characteristics and take different times to overcome inertia. The ADT7475 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spin up for a given spin-up time.

Fan Startup Timeout

To prevent the generation of false interrupts as a fan spins up (because it is below running speed), the ADT7475 includes a fan startup timeout function. During this time, the ADT7475 looks for two TACH pulses. If two TACH pulses are not detected, an interrupt is generated. Using Configuration Register 4 (0x40) Bit 5 (FSPDIS), this functionality can be changed (see the

PWM1, 2, 3 Configuration (Reg. 0x5C, 0x5D, 0x5E)

<2:0> SPIN, startup timeout for PWM1=0x5C, PWM2=0x5D and PWM3=0x5E.

000 = No startup timeout

001 = 100 ms

010 = 250 ms default

011 = 400 ms

100 = 667 ms

101 = 1 sec

110 = 2 sec

111 = 4 sec

Disabling Fan Startup Timeout

Although fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1 (Reg. 0x40) disables the spin-up for two TACH pulses. Instead, the fan spins up for the fixed time as selected in Reg. 0x5C to Reg. 0x5E.

PWM Logic State

The PWM outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted).

PWM1 Configuration (Reg. 0x5C)

<4> INV

0 = Logic high for 100% PWM duty cycle. 1 = Logic low for 100% PWM duty cycle.

Disabling Fan Startup Timeout section).

PWM2 Configuration (Reg. 0x5D)

<4> INV 0 = Logic high for 100% PWM duty cycle. 1 = Logic low for 100% PWM duty cycle.

PWM3 Configuration (Reg. 0x5E)

<4> INV 0 = Logic high for 100% PWM duty cycle. 1 = Logic low for 100% PWM duty cycle.

Low Frequency Mode PWM Drive Frequency

The PWM drive frequency can be adjusted for the application. Reg. 0x5F to Reg. 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. In high frequency mode, the PWM drive frequency is always 22.5 kHz.

High Frequency Mode PWM Drive

Setting Bit 3 of registers 0x5F, 0x60, 0x61 enables high frequency mode for fan1, fan 2 and fan 3, respectively.

PWM1 Frequency Registers (Reg. 0x5F to Reg. 0x61)

<2:0> FREQ

000 = 11.0 Hz

001 = 14.7 Hz

010 = 22.1 Hz

011 = 29.4 Hz

100 = 35.3 Hz default

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

Fan Speed Control

The ADT7475 controls fan speed using two modes: automatic and manual, as follows:

In automatic fan speed control mode, fan speed is automatically varied with temperature and without CPU intervention, once initial parameters are set up. The advantage of this is, if the system hangs, the user is guaranteed the system is protected from overheating. For more information and how to program the automatic fan speed control loop, see the Automatic Fan Speed Control Loop

In manual fan speed control mode, the ADT7475 allows the duty cycle of any PWM output to be manually adjusted. This can be useful, if the user wants to change fan speed at the software level, or adjust PWM duty cycle output for test purposes. Bits <7:5> of Reg. 0x5C to Reg. 0x5E (PWM Configuration) control the behavior of each PWM output.

section.

Programming the

Rev. 0 | Page 30 of 64

Page 31

ADT7475

PWM Configuration Register (Reg. 0x5C to Reg. 0x5E)

<7:5> BHVR

111 = manual mode.

Once under manual control, each PWM output can be manually updated by writing to Reg. 0x30 to Reg. 0x32 (PWMx current duty cycle registers).

Programming the PWM Current Duty Cycle Registers

The PWM current duty cycle registers are 8-bit registers, which allow the PWM duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%.

The value to be programmed into the PWM

MIN

given by

Va lu e (decimal) = PWM

MIN

/0.39

Example 1: For a PWM duty cycle of 50%,

Va lu e (decimal) = 50/0.39 = 128 (decimal) Va lu e = 128 (decimal) or 0x80 (hex)

Example 2: For a PWM duty cycle of 33%,

Va lu e (decimal) = 33/0.39 = 85 (decimal) Va lu e = 85 (decimal) or 0x54 (hex)

When the V following occurs:

1. Status Bit 1 (V

SMBALERT

THERM should hold its value prior to the S3 or S5 state.

Once the core voltage, V everything is re-enabled and the system resumes normal operation.

XNOR TREE TEST MODE

The ADT7475 includes an XNOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XNOR tree, it is possible to detect opens or shorts on the system board.

Figure 41 shows the signals that are exercised in the XNOR tree test mode. The XNOR tree test is invoked by setting Bit 0 (XEN) of the XNOR tree test enable register (Reg. 0x6F).

voltage drops below the V

CCP

) in Status Register 1 is set.

CCP

is generated, if enabled.

monitoring is disabled. The

, goes above the V

CCP

TACH1 TACH2

TACH3

low limit, the

CCP

THERM

timer

low limit,

CCP

PWM Duty Cycle Registers

Reg. 0x30 PWM1 Duty Cycle = 0x00 (0% default)

Reg. 0x31 PWM2 Duty Cycle = 0x00 (0% default)

Reg. 0x32 PWM3 Duty Cycle = 0x00 (0% default)

By reading the PWMx current duty cycle registers, the user can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. See the Automatic Fan Speed Control Loop

Programming the

section for details.

OPERATING FROM 3.3 V STANDBY

The ADT7475 has been specifically designed to operate from a

3.3 V STBY supply. In computers that support S3 and S5 states, the core voltage of the processor is lowered in these states. When monitoring

THERM

, the

THERM

timer should be

disabled during these states.

STANDBY MODE

The ADT7475 has been specifically designed to respond to the STBY supply. In computers that support S3 and S5 states, the core voltage of the processor is lowered in these states. When monitoring

THERM

during these states.

, the

THERM

timer should be disabled

TACH4

PWM2

PWM3

Figure 41. XNOR Tree Test

PWM1/XTO

05381-044

POWER-ON DEFAULT

When the ADT7475 is powered up, monitoring is off by default and the PWM outputs go to 100%. All necessary registers then need to be configured via the SMBus for the appropriate functions to operate.

Rev. 0 | Page 31 of 64

Page 32

ADT7475

PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP

To more efficiently understand the automatic fan speed control loop, it is strongly recommended to use the ADT7475 evaluation board and software while reading this section.

This section provides the system designer with an understanding of the automatic fan control loop, and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. To optimize the system characteristics, the designer needs to give some thought to system configuration, including the number of fans, where they are located, and what temperatures are being measured in the particular system.

The mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of this process.

AUTOMATIC FAN CONTROL OVERVIEW

The ADT7475 can automatically control the speed of fans based upon the measured temperature. This is done independently of CPU intervention once initial parameters are set up.

The ADT7475 has a local temperature sensor and two remote temperature channels that can be connected to a CPU on-chip thermal diode (available on Intel Pentium® class and other CPUs). These three temperature channels can be used as the basis for automatic fan speed control to drive fans using pulsewidth modulation (PWM).

Automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. Reducing fan speed can also decrease system current consumption.

The automatic fan speed control mode is very flexible owing to the number of programmable parameters, including T T

RANGE

. The T

MIN

and T

values for a temperature channel,

RANGE

MIN

and

and, therefore, for a given fan are critical because they define the thermal characteristics of the system. The thermal validation of the system is one of the most important steps in the design process, so select these values carefully.

Figure 42 gives a top-level overview of the automatic fan control circuitry on the ADT7475. From a systems-level perspective, up to three system temperatures can be monitored and used to control three PWM outputs. The three PWM outputs can be used to control up to four fans. The ADT7475 allows the speed of four fans to be monitored. Each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel.

For example, one can decide to run the CPU fan when CPU temperature increases above 60°C and a chassis fan when the local temperature increases above 45°C. At this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (PWM) channel. The right side of Figure 42 shows controls that are fan-specific. The designer has individual control over parameters such as minimum PWM duty cycle, fan speed failure thresholds, and even ramp control of the PWM outputs. Automatic fan control, then, ultimately allows graceful fan speed changes that are less perceptible to the system user.

REMOTE 1

TEMP

LOCAL

TEMP

REMOTE 2

TEMP

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

RANGE

100%

MUX

100%

PWM

MIN

PWM

MIN

PWM

MIN

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 1 MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 2 MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

Figure 42. Automatic Fan Control Block Diagram

Rev. 0 | Page 32 of 64

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM1

TACH1

PWM2

TACH2

PWM3

TACH3

05381-046

Page 33

ADT7475

STEP 1: HARDWARE CONFIGURATION

During system design, the motherboard sensing and control capabilities should be addressed early in the design stages. Decisions about how these capabilities are used should involve the system thermal/mechanical engineer. Ask the following questions:

1. What ADT7475 functionality will be used?

• PWM2 or

SMBALERT

• TACH4 fan speed measurement or overtemperature

THERM

function?

The ADT7475 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. These multifunction pins are software programmable.

2. How many fans will be supported in system, three or four?

This influences the choice of whether to use the TACH4 pin or to reconfigure it for the

THERM

function.

3. Is the CPU fan to be controlled using the ADT7475 or will

it run at full speed 100% of the time?

If run at 100%, this frees up a PWM output, but the system is louder.

4. Where will the ADT7475 be physically located in the

system?

This influences the assignment of the temperature measurement channels to particular system thermal zones. For example, locating the ADT7475 close to the VRM controller circuitry allows the VRM temperature to be monitored using the local temperature channel.

REMOTE 1 =

AMBIENT TEMP

LOCAL =

VRM TEMP

REMOTE 2 =

CPU TEMP

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

RANGE

100%

MUX

100%

PWM

MIN

PWM

MIN

PWM

MIN

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 1

MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 2

MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

Figure 43. Hardware Configuration Example

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM1

TACH1

CPU FAN SINK

PWM2

TACH2

FRONT CHASSIS

PWM3

TACH3

REAR CHASSIS

05381-047

Rev. 0 | Page 33 of 64

Page 34

ADT7475

RECOMMENDED IMPLEMENTATION 1

Configuring the ADT7475 as in Figure 44 provides the system designer with the following features:

1. Two PWM outputs for fan control of up to three fans. (The

front and rear chassis fans are connected in parallel.)

2. Three TACH fan speed measurement inputs.

3. V

measured internally through Pin 4.

6. CPU temperature measured using the Remote 1

temperature channel.

7. Ambient temperature measured through the Remote 2

temperature channel.

8. Bidirectional

PROCHOT

THERM

pin allows the monitoring

output from an Intel P4 processor,

for example, or can be used as an overtemperature THERM

output.

4. CPU core voltage measurement (V

CORE

5. VRM temperature using local temperature sensor.

FRONT

CHASSIS

FAN

REAR

HASSIS

FAN

AMBIENT

TEMPERATURE

Figure 44. Recommended Implementation 1

TACH2

PWM3

TACH3

D1+

D1–

ADT7475

SMBALERT

GND

PWM1

TACH1

D2+

D2–

THERM

SDA

SCL

SMBALERT

PROCHOT

system interrupt output.

CPU FAN

CPU

ICH

05381-048

Rev. 0 | Page 34 of 64

Page 35

ADT7475

RECOMMENDED IMPLEMENTATION 2

Configuring the ADT7475 as in Figure 45 provides the system designer with the following features:

1. Three PWM outputs for fan control of up to three fans.

(All three fans can be individually controlled.)

2. Three TACH fan speed measurement inputs.

3. V

measured internally through Pin 4.

5. CPU temperature measured using the Remote 1

temperature channel.

6. Ambient temperature measured through the Remote 2

temperature channel.

7. Bidirectional

PROCHOT

THERM

output from an Intel P4 processor, for

example, or can be used as an overtemperature

pin allows the monitoring of

THERM

output.

4. CPU core voltage measurement (V

FRONT

CHASSIS

FAN

REAR

CHASSIS

FAN

TEMPERATURE

CORE

AMBIENT

ADT7475

TACH2

PWM3

TACH3

D1+

D1–

GND

PWM1

TACH1

D2+

D2–

THERM

SDA SCL

PROCHOT

Figure 45. Recommended Implementation 2

CPU FAN

ICH

CPU

05381-049

Rev. 0 | Page 35 of 64

Page 36

ADT7475

STEP 2: CONFIGURING THE MUX

After the system hardware configuration is determined, the fans can be assigned to particular temperature channels. Not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. For example, fans can be run under automatic fan control, can be run manually, under software control, or can be run at the fastest speed calculated by multiple temperature channels. The mux is the bridge between temperature measurement channels and the three PWM outputs.

Bits <7:5> (BHVR) of Registers 0x5C, 0x5D, and 0x5E (PWM configuration registers) control the behavior of the fans connected to the PWM1, PWM2, and PWM3 outputs. The values selected for these bits determine how the mux connects a temperature measurement channel to a PWM output.

Automatic Fan Control Mux Options

<7:5> (BHVR), Registers 0x5c, 0x5d, 0x5e.

000 = Remote 1 temperature controls PWMx

001 = local temperature controls PWMx

010 = Remote 2 temperature controls PWMx

101 = Fastest speed calculated by local and Remote 2

temperature controls PWMx

110 = Fastest speed calculated by all three temperature

channels controls PWMx

The Fastest Speed Calculated options pertain to controlling one PWM output based on multiple temperature channels. The thermal characteristics of the three temperature zones can be set to drive a single fan. An example would be the fan turning on when Remote 1 temperature exceeds 60°C, or if the local temperature exceeds 45°C.

Other Mux Options

<7:5> (BHVR), Registers 0x5c, 0x5d, 0x5e.

011 = PWMx runs full speed

100 = PWMx disabled (default)

111 = manual mode. PWMx is running under software control. In this mode, PWM duty cycle registers (Registers 0x30 to 0x32) are writable and control the PWM outputs.

REMOTE 1 =

AMBIENT TEMP

LOCAL =

VRM TEMP

REMOTE 2 =

CPU TEMP

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

RANGE

Figure 46. Assigning Temperature Channels to Fan Channels

100%

MUX

PWM

MIN

PWM

MIN

PWM

MIN

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 1 MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 2 MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM1

TACH1

CPU FAN SINK

PWM2

TACH2

FRONT CHASSIS

PWM3

TACH3

REAR CHASSIS

05381-050

Rev. 0 | Page 36 of 64

Page 37

ADT7475

Mux Configuration Example

This is an example of how to configure the mux in a system using the ADT7475 to control three fans. The CPU fan sink is controlled by PWM1, the front chassis fan is controlled by PWM 2, and the rear chassis fan is controlled by PWM3. The mux is configured for the following fan control behavior:

Example Mux Settings

<7:5> (BHVR), PWM1 Configuration Register 0x5c.

101 = Fastest speed calculated by local and Remote 2 temperature controls PWM1

<7:5> (BHVR), PWM2 Configuration Register 0x5d.

• PWM1 (CPU fan sink) is controlled by the fastest speed

calculated by the local (VRM temperature) and Remote 2 (processor) temperature. In this case, the CPU fan sink is also being used to cool the VRM.

• PWM2 (front chassis fan) is controlled by the Remote 1

temperature (ambient).

• PWM3 (rear chassis fan) is controlled by the Remote 1

temperature (ambient).

REMOTE 2 =

CPU TEMP

LOCAL =

VRM TEMP

REMOTE 1 =

AMBIENT TEMP

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

RANGE

100%

MUX

100%

Figure 47. Mux Configuration Example

000 = Remote 1 temperature controls PWM2

<7:5> (BHVR), PWM3 Configuration Register 0x5e.

000 = Remote 1 temperature controls PWM3

These settings configure the mux, as shown in

PWM

MIN

PWM

MIN

PWM

MIN

CONFIG

PWM

GENERATOR

TACHOMETER 1 MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 2 MEASUREMENT

PWM

CONFIG

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM1

TACH1

CPU FAN SINK

PWM2

TACH2

FRONT CHASSIS

PWM3

TACH3

REAR CHASSIS

Figure 47.

05381-051

Rev. 0 | Page 37 of 64

Page 38

ADT7475

STEP 3: T CALIBRATION CHANNELS

is the temperature at which the fans start to turn on under

MIN

automatic fan control. The speed at which the fan runs at T programmed later in the process. The T temperature channel specific, for example, 25°C for ambient channel, 30°C for VRM temperature, and 40°C for processor temperature.

is an 8-bit value, either twos complement or Offset 64,

MIN

that can be programmed in 1°C increments. There is a T

MIN

ment channel: Remote 1 Local, and Remote 2 Temperature. Once the T the minimum PWM duty cycle. The fan turns off once the temperature has dropped below T

To overcome fan inertia, the fan is spun up until two valid TACH rising edges are counted. See the section for more details. In some cases, primarily for psychoacoustic reasons, it is desirable that the fan never switch off below T (Reg. 0x62), when set, keep the fans running at the PWM minimum duty cycle, if the temperature should fall below T

SETTINGS FOR THERMAL

MIN

values chosen are

MIN

value is exceeded, the fan turns on and runs at

MIN

− T

HYST

MIN

Fan Startup Timeout

. Bits <7:5> of Enhanced Acoustics Register 1

MIN

Registers

MIN

Reg. 0x67, Remote 1 Temperature T

Reg. 0x68, Local Temperature T

Reg. 0x69, Remote 2 Temperature T

= 0x9A (90°C)

MIN

= 0x9A (90°C)

MIN

= 0x9A (90°C)

MIN

Enhance Acoustics Register 1 (Reg. 0x62)

Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when temperature is below T

MIN

− T

HYST

Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below T

MIN

− T

HYST

Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when temperature is below T

MIN

− T

HYST

Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below T

MIN

− T

HYST

Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when temperature is below T

MIN

− T

HYST

Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below T

MIN

− T

HYST

100%

E L C Y C Y T U D

M W

REMOTE 2 =

CPU TEMP

LOCAL =

VRM TEMP

REMOTE 1 =

AMBIENT TEMP

MIN

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

THERMAL CALIBRATION

MIN

RANGE

100%

PWM

MIN

PWM

MIN

CONFIG

MUX

100%

PWM

MIN

CONFIG

Figure 48. Understanding the T

PWM

GENERATOR

TACHOMETER 1

MEASUREMENT

PWM

GENERATOR

TACHOMETER 2

MEASUREMENT

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

Parameter

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM1

TACH1

PWM2

TACH2

FRONT CHASSIS

PWM3

TACH3

REAR CHASSIS

CPU FAN SINK

05381-052

Rev. 0 | Page 38 of 64

Page 39

ADT7475

STEP 4: PWM

PWM

is the minimum PWM duty cycle at which each fan in

MIN

FOR EACH PWM (FAN) OUTPUT

MIN

the system runs. It is also the start speed for each fan under automatic fan control once the temperature rises above T For maximum system acoustic benefit, PWM

should be

MIN

as low as possible. Depending on the fan used, the PWM

MIN

setting is usually in the 20% to 33% duty cycle range. This value can be found through fan validation.

100%

Programming the PWM

The PWM

registers are 8-bit registers that allow the

MIN

minimum PWM duty cycle for each output to be configured

anywhere from 0% to 100%. This allows the minimum PWM duty cycle to be set in steps of 0.39%.

The value to be programmed into the PWM given by

Va lu e (decimal) = PWM

Example 1: For a minimum PWM duty cycle of 50%,

Va lu e (decimal) = 50/0.39 = 128 (decimal) Va lu e = 128 (decimal) or 80 (hex)

Registers

MIN

/0.39

MIN

PWM DUTY CYCLE

PWM

MIN

TEMPERATURE

05381-055

Figure 49. PWM

MIN

Determines Minimum PWM Duty Cycle

MIN

More than one PWM output can be controlled from a single temperature measurement channel. For example, Remote 1 temperature can control PWM1 and PWM2 outputs. If two different fans are used on PWM1 and PWM2, then the fan characteristics can be set up differently. As a result, Fan 1 driven by PWM1 can have a different PWM that of Fan 2 connected to PWM2. PWM1 20%, while PWM2

(front fan) is turned on at a minimum duty cycle of

MIN

(rear fan) turns on at a minimum of 40%

MIN

Figure 50 illustrates this as

value than

MIN

duty cycle. Note: Both fans turn on at exactly the same temperature, defined by T

100%

PWM2

MIN

PWM DUTY CYCLE

PWM1

MIN

Figure 50. Operating Two Different Fans from a Single Temperature Channel

MIN

TEMPERATURE

05381-056

Example 2: For a minimum PWM duty cycle of 33%,

Va lu e (decimal) = 33/0.39 = 85 (decimal) Va lu e = 85 (decimal)l or 54 (hex)

PWM

Registers

MIN

Reg. 0x64, PWM1 Minimum Duty Cycle = 0x80 (50% default) Reg. 0x65 PWM2 Minimum Duty Cycle = 0x80 (50% default) Reg. 0x66, PWM3 Minimum Duty Cycle = 0x80 (50% default)

Note on Fan Speed and PWM Duty Cycle

The PWM duty cycle does not directly correlate to fan speed in RPM. Running a fan at 33% PWM duty cycle does not equate to running the fan at 33% speed. Driving a fan at 33% PWM duty cycle actually runs the fan at closer to 50% of its full speed. This is because fan speed in %RPM generally relates to the square root of PWM duty cycle. Given a PWM square wave as the drive signal, fan speed in RPM approximates to

10% ×= cycledutyPWMfanspeed

STEP 5: PWM

PWM

is the maximum duty cycle that each fan in the system

MAX

FOR PWM (FAN) OUTPUTS

MAX

runs at under the automatic fan speed control loop. For maximum system acoustic benefit, PWM

should be as low as

MAX

possible, but should be capable of maintaining the processor temperature limit at an acceptable level. If the

THERM

temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling.

There is a PWM

limit for each fan channel. The default

MAX

value of this register is 0xFF and has no effect unless it is programmed.

Rev. 0 | Page 39 of 64

Page 40

ADT7475

100%

PWM

MAX

PWM DUTY CYCLE

PWM

MIN

STEP 6: T

is the range of temperature over which automatic fan

RANGE

control occurs once the programmed T been exceeded. T

FOR TEMPERATURE CHANNELS

RANGE

temperature has

MIN

is the temperature range between PWM

RANGE

MIN

and 100% PWM where the fan speed changes linearly. Otherwise stated, it is the line drawn between the Tmin/PWMmin and the (T

MIN

+ T

)/PWM 100% intersection points.

RANGE

TEMPERATURET

05381-057

THERM

Figure 51. PWM

MIN

Determines Maximum PWM Duty Cycle below the

MAX

Temperature Limit

Programming the PWM

The PWM

registers are 8-bit registers that allow the

MAX

Registers

MAX

maximum PWM duty cycle for each output to be configured anywhere from 0% to 100%. This allows the maximum PWM duty cycle to be set in steps of 0.39%.

The value to be programmed into the PWM

MAX

given by

Va lu e (decimal) = PWM

MAX

/0.39

Example 1: For a maximum PWM duty cycle of 50%,

Va lu e (decimal) – 50/0.39 = 128 (decimal) Va lu e = 128 (decimal) or 80 (hex)

Example 2: For a minimum PWM duty cycle of 75%,

Va lu e (decimal) = 75/0.39 = 85 (decimal)

Va lu e = 192 (decimal) or C0 (hex)

PWM

Registers

MAX

Reg. 0x38, PWM1 Maximum Duty Cycle = 0xFF (100% default)

100%

PWM DUTY CYCLE

PWM

MIN

The T

MIN

Figure 52. T

is determined by the following procedure:

RANGE

Parameter Affects Cooling Slope

RANGE

TEMPERATURE

05381-058

1. Determine the maximum operating temperature for that

channel (for example, 70°C).

2. Determine experimentally the fan speed (PWM duty cycle

value) that does not exceed the temperature at the worstcase operating points. (For example, 70°C is reached when the fans are running at 50% PWM duty cycle.)

3. Determine the slope of the required control loop to meet

these requirements.

4. Using the ADT7475 evaluation software, you can

graphically program and visualize this functionality. Ask your local Analog Devices representative for details.

Reg. 0x39, PWM2 Maximum Duty Cycle = 0xFF (100% default)

Reg. 0x3A, PWM3 Maximum Duty Cycle = 0xFF (100% default)

As PWM changes.

Rev. 0 | Page 40 of 64

is changed, the automatic fan control slope also

MIN

100%

50%

PWM DUTY CYCLE

33%

Figure 53. Adjusting PWM

30°C

MIN

Changes the Automatic Fan Control Slope

MIN

05381-059

Page 41

ADT7475

As T gets smaller, the fans will reach 100% speed with a smaller temperature change.

Selecting T

The T Remote 1, local, and Remote 2 temperature. Bits <7:4> (T of Registers 0x5F to 0x61 define the T temperature channel.

is changed, the slope also changes. As T

RANGE

100%

PWM DUTY CYCLE

10%

Figure 54. Increasing T

100%

MAX

PWM

PWM DUTY CYCLE

10%

MIN–HYST

30°C

40°C

45°C

54°C

MIN

Changes the AFC Slope

RANGE

Figure 55. Changing PWM Max Does Not Change the AFC Slope

RANGE

value can be selected for each temperature channel:

RANGE

value for each

RANGE

05381-060

05381-061

RANGE

Table 13. Selecting a T

Bits <7:4>1 T

RANGE

Value

RANGE

(°C)

0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80

; Register 0x61 configures Remote 2 T

RANGE

; Register 0x60 configures Local

RANGE

Actual Changes in PWM Output (Advanced Acoustics Settings)

While the automatic fan control algorithm describes the general response of the PWM output, the enhanced acoustics registers (0x62 and 0x63) can be used to set/clamp the maximum rate of change of PWM output for a given temperature zone. This means if T

is programmed with a steep AFC slope, a relatively small

RANGE

change in temperature can cause a large change in PWM output and an audible change in fan speed, which may be noticeable/ annoying to end users. Decreasing the PWM output’s maximum rate of change, by programming the smoothing on the appropriate temperature channels (Registers 0x62 and 0x63), will, in the event of a temperature spike, clamp the fan speed’s maximum rate

)

of change. Slowly the PWM duty cycle will increase, until the PWM duty cycle reaches the appropriate duty cycle as defined by the AFC curve.

Figure 56 shows PWM duty cycle versus temperature for each

setting. The lower graph shows how each T

RANGE

setting affects fan speed versus temperature. As can be seen from the graph, the effect on fan speed is nonlinear.

Rev. 0 | Page 41 of 64

Page 42

ADT7475

100

PWM DUTY CYCLE (%)

0 20 40 60 80 100 120

100

FAN SPEED (% OF MAX)

0 20406080100120

Figure 56. T

TEMPERATURE ABOVE T

MIN

(A)

TEMPERATURE ABOVE T

MIN

(B)

vs. Actual Fan Speed (not PWM drive) Profile Figure 57. T

RANGE

2°C

2.5°C

3.33°C 4°C 5°C

6.67°C 8°C 10°C

13.3°C 16°C 20°C

26.6°C 32°C 40°C

53.3°C 80°C

2°C

2.5°C

3.33°C 4°C 5°C

6.67°C 8°C 10°C

13.3°C 16°C 20°C

26.6°C 32°C 40°C

53.3°C 80°C

05381-062

100

PWM DUTY CYCLE (%)

0 20 40 60 80 100 120

TEMPERATURE ABOVE T

MIN

(A)

100

FAN SPEED (% OF MAX)

0 20406080100120

TEMPERATURE ABOVE T

MIN

(B)

and % Fan Speed Slopes with PWM

RANGE

MIN

2°C

2.5°C

3.33°C 4°C 5°C

6.67°C 8°C 10°C

13.3°C 16°C 20°C

26.6°C 32°C 40°C

53.3°C 80°C

2°C

2.5°C

3.33°C 4°C 5°C

6.67°C 8°C 10°C

13.3°C 16°C 20°C

26.6°C 32°C 40°C

53.3°C 80°C

05381-063

= 20%

The graphs in Figure 56 assume the fan starts from 0% PWM duty cycle. Clearly, the minimum PWM duty cycle, PWM

MIN

, needs to be factored in to see how the loop actually performs in the system. the PWM

Figure 57 shows how T

value is set to 20%. It can be seen that the fan

MIN

is affected when

RANGE

actually runs at about 45% fan speed when the temperature exceeds T

Example: Determining T

MIN

for Each Temperature

RANGE

Channel

The following example shows how the different T

MIN

and T

RANGE

settings can be applied to three different thermal zones. In this example, the following T

= 80°C for ambient temperature

RANGE

= 53.33°C for CPU temperature

RANGE

= 40°C for VRM temperature

RANGE

values apply:

RANGE

Rev. 0 | Page 42 of 64

This example uses the mux configuration described in Step 2, with the ADT7475 connected as shown in

Figure 47. Both CPU temperature and VRM temperature drive the CPU fan connected to PWM1. Ambient temperature drives the front chassis fan and rear chassis fan connected to PWM2 and PWM3. The front chassis fan is configured to run at PWM rear chassis fan is configured to run at PWM CPU fan is configured to run at PWM

MIN

= 10%.

= 20%. The

= 30%. The

Note: The control range for 4-wire fans is much wider than that of 3-wire fans. In many cases, 4-wire fans can start with a PWM drive of as little as 20% or less. In extreme cases some 3-wire fans will not run unless a PWM drive of 60% or more is applied.

Page 43

ADT7475

100

VRM TEMPERATURE

PWM DUTY CYCLE (%)

0 10203040 10050 60 70 80 90

TEMPERATURE ABOVE T

CPU TEMPERATURE

AMBIENT TEMPERATURE

MIN

The T

operating temperature of the system. Because exceeding any T

THERM

effects. Ultimately, this limit should be set up as a fail-safe, and one should ensure that it is not exceeded under normal system operating conditions.

Note: T

matter how automatic fan control settings are configured. This allows some flexibility, because a T based on its slope, while a hard limit (such as 70°C) can be programmed as T full speed) by setting T

limit should be considered the maximum worst-case

THERM

limit runs all fans at 100%, it has very negative acoustic

limits are nonmaskable and affect the fan speed no

THERM

value can be selected

RANGE

(the temperature at which the fan reaches

MAX

to that limit (for example, 70°C).

THERM

100

VRM TEMPERATURE

FAN SPEED (% MAX RPM)

0 10203040 10050 60 70 80 90

Figure 58. T

STEP 7: T

is the absolute maximum temperature allowed on a

THERM

RANGE

THERM

CPU TEMPERATURE

AMBIENT TEMPERATURE

TEMPERATURE ABOVE T

and % Fan Speed Slopes for VRM, Ambient, and

CPU Temperature Channels

MIN

FOR TEMPERATURE CHANNELS

temperature channel. Above this temperature, a component such as the CPU or VRM might be operating beyond its safe operating limit. When the temperature measured exceeds T

all fans are driven at 100% PWM duty cycle (full speed)

THERM

to provide critical system cooling.

The fans remain running at 100% until the temperature drops below T

minus hysteresis, where hysteresis is the number

THERM

programmed into the Hysteresis Registers 0x6D and 0x6E. The default hysteresis value is 4°C.

05381-064

THERM

Reg. 0x6A, Remote 1

Reg. 0x6B, Local

Reg. 0x6C, Remote 2

THERM

Registers

THERM

limit = 0x64 (100°C default)

Hysteresis

hysteresis on a particular channel is configured via the

hysteresis settings below (0x6D and 0x6E). For example, setting hysteresis on the remote 1 channel also sets the hysteresis on remote 1

THERM

Hysteresis Registers

Reg. 0x6D, Remote 1, Local Hysteresis Register

<7:4>, Remote 1 Temperature hysteresis (4°C default).

<3:0>, Local Temperature hysteresis (4°C default).

Reg. 0x6E, Remote 2 Temperature Hysteresis Register

<7:4>, Remote 2 Temperature hysteresis (4°C default).

Because each hysteresis setting is four bits, hysteresis values are programmable from 1°C to 15°C. It is not recommended that hysteresis values ever be programmed to 0°C, because this disables hysteresis. In effect, this causes the fans to cycle (during a THERM while operating close to T

event) between normal speed and 100% speed, or,

, between normal speed and off,

MIN

creating unsettling acoustic noise.

Rev. 0 | Page 43 of 64

Page 44

ADT7475

100%

E L C Y C Y T U D

M W

MIN

THERMAL CALIBRATION

REMOTE 2 =

CPU TEMP

LOCAL =

VRM TEMP

REMOTE 1 =

AMBIENT TEMP

THERMAL CALIBRATION

MIN

RANGE

THERM

100%

RANGE

100%

RANGE

100%

RANGE

Figure 59. How T

PWM

MIN

PWM

CONFIG

TACHOMETER 1

MEASUREMENT

PWM

MIN

PWM

CONFIG

MUX

TACHOMETER 2

MEASUREMENT

PWM

MIN

PWM

CONFIG

TACHOMETER 3

MEASUREMENT

Relates to Automatic Fan Control

THERM

PWM

GENERATOR

PWM

GENERATOR

PWM

GENERATOR

AND 4

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM1

TACH1

PWM2

TACH2

FRONT CHASSIS

PWM3

TACH3

CPU FAN SINK

REAR CHASSIS

05381-065

STEP 8: T

is the amount of extra cooling a fan provides after the

HYST

temperature measured has dropped back below T fan turns off. The premise for temperature hysteresis (T

FOR TEMPERATURE CHANNELS

HYST

before the

MIN

HYST

) is that, without it, the fan would merely chatter, or cycle on and off regularly, whenever the temperature is hovering at about the T

setting.

MIN

The T

value chosen determines the amount of time needed

HYST

for the system to cool down or heat up as the fan is turning on and off. Values of hysteresis are programmable in the range 1°C to 15°C. Larger values of T on and off. The T

The T

setting applies not only to the temperature hysteresis

HYST

default value is set at 4°C.

HYST

for fan on/off, but the same setting is used for the T

prevent the fans from chattering

HYST

THERM

hys-

teresis value, described in Step 6. Therefore, programming Registers 0x6D and 0x6E sets the hysteresis for both fan on/off and the

THERM

function.

Rev. 0 | Page 44 of 64

In some applications, it is required that fans not turn off below

, but remain running at PWM

MIN

. Bits <7:5> of Enhanced

MIN

Acoustics Register 1 (Reg. 0x62) allow the fans to be turned off or to be kept spinning below T T

value has no effect on the fan when the temperature drops

HYST

below T

THERM

MIN

Hysteresis

. If the fans are always on, the

MIN

Any hysteresis programmed via registers 0x6D and 0x6E will also apply hysteresis on the appropriate

THERM

channel.

Page 45

ADT7475

100%

E L C Y C Y T U D

M W

THERMAL CALIBRATION

LOCAL =

THERMAL CALIBRATION

REMOTE 2 =

CPU TEMP

VRM TEMP

REMOTE 1 =

AMBIENT TEMP

Figure 60. The T

RANGE

MIN

THERM

100%

RANGE

100%

MUX

RANGE

100%

RANGE

Value Applies to Fan On/Off Hysteresis and

HYST

PWM

MIN

PWM

MIN

PWM

MIN

PWM

CONFIG

GENERATOR

TACHOMETER 1

MEASUREMENT

PWM

CONFIG

GENERATOR

TACHOMETER 2

MEASUREMENT

PWM

CONFIG

GENERATOR

TACHOMETER 3 MEASUREMENT

PWM

AND 4

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

THERM

Hysteresis

PWM1

TACH1

PWM2

TACH2

FRONT CHASSIS

PWM3

TACH3

CPU FAN SINK

REAR CHASSIS

05381-066

Enhance Acoustics Register 1 (Reg. 0x62)

Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when temperature is below T

MIN

− T

HYST

Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below T

MIN

− T

HYST

Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when temperature is below T

MIN

− T

HYST

Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below T

MIN

− T

HYST

Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when temperature is below T

MIN

− T

HYST

Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below T

MIN

− T

HYST

Configuration Register 6 (Reg. 0x10)

<0> SLOW, 1 slows the ramp rate for PWM changes associated with the Remote 1 temperature channel by 4. Configuration Register 6(Reg. 0x10)

<1> SLOW, 1 slows the ramp rate for PWM changes associated with the Local temperature channel by 4.

Configuration Register 6(Reg. 0x10)

<2> SLOW, 1 slows the ramp rate for PWM changes associated with the Remote 2 temperature channel by 4.

Configuration Register 6 (Reg. 0x10)

<7> ExtraSlow, 1 slows the ramp rate for all fans by a factor of 39.2%.

The following sections list the ramp-up times when the SLOW bit is set for each temperature monitoring channel.

Enhanced Acoustics Register 1 (Reg. 0x62)

<2:0> ACOU, selects the ramp rate for PWM outputs associated with the Remote Temp 1 input.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 sec

011 = 7.5 sec

100 = 4.7 sec

101 = 3.1 sec

110 = 1.6 sec

111 = 0.8 sec

Rev. 0 | Page 45 of 64

Page 46

ADT7475

Enhance Acoustics Register 2 (Reg. 0x63)

<2:0> ACOU3, selects the ramp rate for PWM outputs associated with the Local temperature channel.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 sec

011 = 7.5 sec

100 = 4.7 sec

101 = 3.1 sec

110 = 1.6 sec

111 = 0.8 sec

<6:4> ACOU2, selects the ramp rate for PWM outputs associated with the Remote Temperature 2 input.

When Bit 7 of configuration register 6 (0x10) =1, then the above ramp rates change to the values below.

000=52.2 sec

001=26.1 sec

010=17.4 sec

011=10.4 sec

100=6.5 sec

101=4.4 sec

110=2.2 sec

111=1.1 sec

Setting the appropriate slow bit <2:0> of configuration register 6 (0x10) will slow the ramp rate further by a factor of 4.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 sec

011 = 7.5 sec

100 = 4.7 sec

101 = 3.1 sec

110 = 1.6 sec

111 = 0.8 sec

Rev. 0 | Page 46 of 64

Page 47

ADT7475

REGISTER TABLES

Table 14. ADT7475 Registers

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x10 R/W

0x11 R

0x21 R V

Configuration 6

Configuration 7

Reading 9 8 7 6 5 4 3 2 0x00

CCP

0x22 R VCC Reading 9 8 7 6 5 4 3 2 0x00 0x25 R Remote 1

Temperature

0x26 R Local

Temperature

0x27 R Remote 2

Temperature

0x28 R TACH 1 Low

Byte

0x29 R TACH 1 High

Byte

0x2A R TACH 2 Low

Byte

0x2B R TACH 2 High

Byte

0x2C R TACH 3 Low

Byte

0x2D R TACH 3 High

Byte

0x2E R TACH 4 Low

Byte

0x2F R TACH 4 High

Byte

0x30 R/W PWM1 Current

Duty Cycle

0x31 R/W PWM2 Current

Duty Cycle

0x32 R/W PWM3 Current

Duty Cycle

0x38 R/W Max PWM 1

Duty Cycle

0x39 R/W Max PWM 2

Duty Cycle

0x3A R/W Max PWM 3

Duty Cycle

0x3D R Device ID

0x3E R Company ID

Number

0x3F R Revision

Number

0x40 R/W Configuration

0x41 R Interrupt

Status Register 1

0x42 R Interrupt

Status

Low Limit 7 6 5 4 3 2 1 0 0x00

CCP

High

CCP

Limit 0x48 R/W VCC Low Limit 7 6 5 4 3 2 1 0 0x00

ExtraSlow VccpLow RES RES

RES RES RES RES RES RES RES DisTHERMHys 0x00

THERM in Manual

SLOW Remote 2

SLOW Local

SLOW Remote 1

0x00

9 8 7 6 5 4 3 2 0x80

7 6 5 4 3 2 1 0 0x00

15 14 13 12 11 10 9 8 0x00

7 6 5 4 3 2 1 0 0x00

15 14 13 12 11 10 9 8 0x00

7 6 5 4 3 2 1 0 0x00

15 14 13 12 11 10 9 8 0x00

7 6 5 4 3 2 1 0 0x00

15 14 13 12 11 10 9 8 0x00

7 6 5 4 3 2 1 0 0xFF

7 6 5 4 3 2 1 0 0x75

7 6 5 4 3 2 1 0 0x41

VER VER VER VER STP STP STP STP 0x69

RES TODIS FSPDIS Vx1 FSPD RDY LOCK STRT 0x04 Yes

OOL R2T LT R1T RES V

CCP

RES 0x00

D2 D1 F4P FAN3 FAN2 FAN1 OVT RES 0x00

7 6 5 4 3 2 1 0 0xFF

Rev. 0 | Page 47 of 64

Page 48

ADT7475

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x49 R/W VCC High Limit 7 6 5 4 3 2 1 0 0xFF 0x4E R/W Remote 1

Temp Low Limit

0x4F R/W Remote 1

Temp High Limit

0x50 R/W Local Temp

Low Limit

0x51 R/W Local Temp

High Limit

0x52 R/W Remote 2

Temp Low Limit

0x53 R/W Remote 2

Temp High Limit

0x54 R/W TACH1

Minimum Low Byte

0x55 R/W TACH1

Minimum High Byte

0x56 R/W TACH2

Minimum Low Byte

0x57 R/W TACH2

Minimum High Byte

0x58 R/W TACH3

Minimum Low Byte

0x59 R/W TACH3

Minimum High Byte

0x5A R/W TACH4

Minimum Low Byte

0x5B R/W TACH4

Minimum High Byte

0x5C R/W PWM1

Configuration Register

0x5D R/W PWM2

Configuration Register

0x5E R/W PWM3

Configuration Register

0x5F R/W Remote 1

/PWM 1

RANGE

Frequency

0x60 R/W Local

/PWM 2

RANGE

Frequency

0x61 R/W Remote 2

/PWM 3

RANGE

Frequency

0x62 R/W Enhance

Acoustics Reg 1

0x63 R/W Enhance

Acoustics Reg 2

7 6 5 4 3 2 1 0 0x81

7 6 5 4 3 2 1 0 0x7F

7 6 5 4 3 2 1 0 0x81

7 6 5 4 3 2 1 0 0x7F

7 6 5 4 3 2 1 0 0x81

7 6 5 4 3 2 1 0 0x7F

7 6 5 4 3 2 1 0 0xFF

15 14 13 12 11 10 9 8 0xFF

7 6 5 4 3 2 1 0 0xFF

15 14 13 12 11 10 9 8 0xFF

7 6 5 4 3 2 1 0 0xFF

15 14 13 12 11 10 9 8 0xFF

7 6 5 4 3 2 1 0 0xFF

15 14 13 12 11 10 9 8 0xFF

BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes

RANGE RANGE RANGE RANGE

HF/LF

FREQ FREQ FREQ 0xC4 Yes

MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0x00 Yes

EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0x00 Yes

Rev. 0 | Page 48 of 64

Page 49

ADT7475

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x64 R/W PWM1 Min

Duty Cycle 0x65 R/W PWM2 Min

Duty Cycle 0x66 R/W PWM3 Min

Duty Cycle 0x67 R/W Remote 1

Temp T

MIN

0x68 R/W Local Temp

MIN

0x69 R/W Remote 2

Temp T

MIN

0x6A R/W Remote 1

THERM

Temp

Limit 0x6B R/W

Local

THERM

Temp Limit 0x6C R/W Remote 2

THERM

Temp

Limit 0x6D R/W Remote 1 and

Local

Temp/T

MIN

Hysteresis 0x6E R/W Remote 2

Temp/T

MIN

Hysteresis 0x6F R/W XNOR Tree

Test Enable 0x70 R/W Remote 1

Temperature

Offset 0x71 R/W Local

Temperature

Offset 0x72 R/W Remote 2

Temperature

Offset 0x73 R/W Configuration

1 Register 0x75 R/W Interrupt Mask

2 Register 0x76 R/W Extended

Resolution 1 0x77 R/W Extended

Resolution 2 0x78 R/W Configuration

THERM

Timer

Status

THERM

Timer

Limit Register 0x7B R/W TACH Pulses

per

Revolution

7 6 5 4 3 2 1 0 0x80 Yes

7 6 5 4 3 2 1 0 0x5A Yes

7 6 5 4 3 2 1 0 0x64 Yes

HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0x44 Yes

HYSR2 HYSR2 HYSR2 HYRS RES RES RES RES 0x40 Yes

RES RES RES RES RES RES RES XEN 0x00 Yes

7 6 5 4 3 2 1 0 0x00 Yes

SHDN

CONV ATTN AVG

OOL R2T LT RIT RES V

RES RES RES RES

CCP

RES 0x00

0x00 Yes

D2 D1 F4P FAN3 FAN2 FAN1 OVT RES 0x00

RES RES V

CCP

RES RES 0x00

TDM2 TDM2 LTMP LTMP TDM1 TDM1 RES RES 0x00

DC4 DC3 DC2 DC1 FAST BOOST THERM ALERT

0x00 Yes

Enable

TMR TMR TMR TMR TMR TMR TMR ASRT/TMRO 0x00

LIMT LIMT LIMT LIMT LIMT LIMT LIMT LIMT 0x00

FAN4 FAN4 FAN3 FAN3 FAN2 FAN2 FAN1 FAN1 0x55

Rev. 0 | Page 49 of 64

Page 50

ADT7475

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x7C R/W Configuration

0x7D R/W Configuration

0x7E R Test Register 1 DO NOT WRITE TO THESE REGISTERS 0x00 Yes 0x7F R Test Register 2 DO NOT WRITE TO THESE REGISTERS 0x00 Yes

R2 THERM O/P Only

RES RES BpAtt

Table 15. Register 0x11—Configuration Register 7 (Power-On Default = 0x00)

Bit Name R/W Description

<0>

Dis

THERM

Hys

Read/write

<7:1> Reserved N/A Reserved. Do not write to these bits.

Table 16. Register 0x10—Configuration Register 6 (Power-On Default = 0x00)

Bit Name R/W Description

<0> SlowFan Remote 1 Read/write

<1> SlowFan Local Read/write

<2> SlowFan Remote 3 Read/write

<3>

THERM in Manual

Read/write

<5:4> Reserved N/A Reserved. Do not write to these bits. <6> V

Low Read/write

CCP

<7> ExtraSlow Read/write When this bit is set, all fan smoothing times are increased by a further 39.2%.

THERM

event will always override any fan setting (even when fans are disabled).

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 17. Register 0x11—Configuration Register 7 (Power-On Default = 0x00)

Bit Name R/W Description

<0>

Dis

THERM

Hys

<7:1> Reserved N/A Reserved. Do not write to these bits

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 18. Voltage Reading Registers (Power-On Default = 0x00)

0x21 Read-only Reflects the voltage measurement1 at the V 0x22 Read-only Reflects the voltage measurement2 at the VB

If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended

resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.

VCC (Pin 3) is the supply voltage for the ADT7475.

Local THERM O/P Only

Read/write

R1 THERM O/P Only

CCP

RES GPIOP GPIOD

RES Max/Full

Setting this bit to 1 disables

on THERM

THERM Disable

THERM

1, 2

Temp Offset

Pin 9 Func

hysteresis.

TWOS COMPL

Pin 9 Func 0x00 Yes

0x01 Yes

When this bit is set, Fan 1 smoothing times are multiplied ×4 for Remote 1 Temperature channel (as defined in Register 0x62).

When this bit is set, Fan 2 smoothing times are multiplied ×4 for Local Temperature channel (as defined in Register 0x63).

When this bit is set, Fan 3 smoothing times are multiplied ×4 for Remote 2 Temperature channel (as defined in Register 0x63).

When this bit is set,

LO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage

CCP

) drops below its V

CCP

is enabled in manual mode.

THERM

low limit value (Reg. 0x46), the following occurs:

CCP

• Status Bit 1 in Status Register 1 is set.

•

SMBALERT

•

PROCHOT

• Everything is re-enabled once V

• When V

•

PROCHOT

is generated, if enabled.

monitoring is disabled.

CCP

increases above the low limit:

CCP

monitoring is enabled.

increases above the V

low limit.

CCP

• Fans return to their programmed state after a spin-up cycle.

Setting this bit to 1 disables

1, 2

THERM

hysteresis.

input on Pin 14 (8 MSBs of reading).

CCP

input on Pin 3 (8 MSBs of reading).

CCB

Rev. 0 | Page 50 of 64

Page 51

ADT7475

Table 19. Temperature Reading Registers (Power-On Default = 0x80)

1, 2

0x25

Read-only

Remote 1 temperature reading

3, 4

(8 MSB of reading). 0x26 Read-only Local temperature reading (8 MSB of reading). 0x27 Read-only Remote 2 temperature reading (8 MSB of reading).

These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).

If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended

resolution registers have been read, all associated MSB reading registers get frozen until read. Both the extended resolution registers and the MSB registers are frozen.

In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.

In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.

Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00)

0x28 Read-only TACH1 low byte. 0x29 Read-only TACH1 high byte. 0x2A Read-only TACH2 low byte. 0x2B Read-only TACH2 high byte. 0x2C Read-only TACH3 low byte. 0x2D Read-only TACH3 high byte. 0x2E Read-only TACH4 low byte. 0x2F Read-only TACH4 high byte.

These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).

The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up.

A count of 0xFFFF indicates that a fan is one of the following:

Stalled or blocked (object jamming the fan). Failed (internal circuitry destroyed). Not populated. (The ADT7475 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be

set to 0xFFFF.)

Alternate function, for example, TACH4 reconfigured as a

THERM

pin.

Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)

0x30 Read/write PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). 0x31 Read/write PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). 0x32 Read/write PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7475 reports the PWM duty cycles

back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.

Table 22. Maximim PWM Duty Cycle (Power-On Default = 0xFF)

1, 2

0x38 Read/write Maximum duty cycle for PWM1 output, default = 100% (0xFF). 0x39 Read/write Maximum duty cycle for PWM2 output, default = 100% (0xFF). 0x3A Read/Write Maximum duty cycle for PWM3 output, default = 100% (0xFF).

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

These registers set the maximum PWM duty cycle of the PWM output.

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Table 23. Register 0x40—Configuration Register 1 (Power-On Default = 0x04)

Bit Name R/W Description

<0> STRT

<1> LOCK Write once

<2> RDY Read-only

<3> FSPD Read/write

<4> VxI Read/write

<5> FSPDIS Read/write

<6> TODIS Read/write

<7> RES Reserved.

Bit 0 (STRT) of 0x40, Configuration register 1 remains writable after lock bit is set.

When monitoring is disabled, PWM outputs will always go to 100% for thermal protection.

Table 24. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)

Bit Name R/W Description

<1> V

<2> V

<4> RIT Read-only

<5> LT Read-only

<6> R2T Read-only

<7> OOL Read-only

CCP

1, 2

Read/write Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.

Logic 0 disables monitoring and PWM control based on the default power-up limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default

settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has been set. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-

only and cannot be modified until the ADT7475 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.)

This bit is set to 1 by the ADT7475 to indicate only that the device is fully powered up and ready to begin system monitoring.

When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit does not get locked at any time.

BIOS should set this bit to a 1 when the ADT7475 is configured to measure current from an ADI ADOPT® VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display CPU watts usage. (Lockable.)

Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spinup timeout selected.

When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7475 to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)

Read-only

= 1 indicates that the V

CCP

high or low limit has been exceeded. This bit is cleared on a read of the status

CCP

Read-only

= 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the status

register only if the error condition has subsided. RIT = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read

of the status register only if the error condition has subsided. LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of the

status register only if the error condition has subsided. R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read

of the status register only if the error condition has subsided. OOL = 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all

status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are out-of-limit, which saves the need to read Status Register 2 every interrupt or polling cycle.

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Table 25. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)

Bit Name R/W Description

<1> OVT Read-only

<2> FAN1 Read-only

<3> FAN2 Read-only

<4> FAN3 Read-only

<5> F4P Read-only

Read/write When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO. Read-only

<6> D1 Read-only D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. <7> D2 Read-only D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.

Table 26. Voltage Limit Registers

0x46 Read/write V 0x47 Read/write V 0x48 Read/write VCC low limit. 0x00 0x49 Read/write VCC high limit. 0xFF

Setting the Configuration Register 1 lock bit has no effect on these registers.

High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its

low limit (≤ comparison).

Table 27. Temperature Limit Registers

0x4E Read/write Remote 1 temperature low limit. 0x81 0x4F Read/write Remote 1 temperature high limit. 0x7F 0x50 Read/write Local temperature low limit. 0x81 0x51 Read/write Local temperature high limit. 0x7F 0x52 Read/write Remote 2 temperature low limit. 0x81 0x53 Read/write Remote 2 temperature high limit. 0x7F

Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock

bit has no effect on these registers.

High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its

low limit (≤ comparison).

Table 28. Fan Tachometer Limit Registers

0x54 Read/write TACH1 minimum low byte. 0xFF 0x55 Read/write

0x56 Read/write TACH2 minimum low byte. 0xFF 0x57 Read/write TACH2 minimum high byte. 0xFF 0x58 Read/write TACH3 minimum low byte. 0xFF 0x59 Read/write TACH3 minimum high byte. 0xFF 0x5A Read/write TACH4 minimum low byte. 0xFF 0x5B Read/write TACH4 minimum high byte. 0xFF

Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2

to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.

OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a read of the status register when the temperature drops below

THERM – T

HYST

FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the PWM1 output is off.

FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the PWM2 output is off.

FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off.

F4P = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off.

If Pin 9 is configured as the

THERM timer input for THERM monitoring, then this bit is set when the THERM

assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A).

low limit. 0x00

CCP

high limit. 0xFF

CCP

TACH1 minimum high byte/single channel ADC

Power-On Default

0xFF

channel select.

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Table 29. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF)

Bits Name R/W Description

<4:0> Reserved Read-only

<7:5> SCADC Read/write

Table 30. PWM Configuration Registers

0x5C Read/write PWM1 configuration. 0x62 0x5D Read/write PWM2 configuration. 0x62 0x5E Read/write PWM3 configuration. 0x62

Bit Name R/W Description

<2:0> SPIN Read/write

000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec <4> INV Read/write

<7:5> BHVR Read/write These bits assign each fan to a particular temperature sensor for localized cooling. 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed. 100 = PWMx disabled (default). 101 = fastest speed calculated by local and Remote 2 temperature controls PWMx. 110 = fastest speed calculated by all three temperature channel controls PWMx. 111 = manual mode. PWM duty cycle registers (Reg. 0x30 to Reg. 0x32) become writable.

These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

These bits are reserved when Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode). Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.

When Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode), these bits are used to select the only channel from which the ADC makes measurements. Otherwise, these bits represent Bits <7:5> of the TACH1 minimum high byte.

These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement directly after the fan startup timeout period, then the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the status register 2 bit is not set, even if the fan has not started.

This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to a logic low output.

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ADT7475

Table 31. TEMP T

0x5F Read/write Remote 1 T 0x60 Read/write Local temperature T 0x61 Read/write Remote 2 T

Bit Name R/W Description

<2:0> FREQ Read/write These bits control the PWMx frequency. 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz <3> HF/LF Read/write

<7:4> RANGE Read/write

0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C

These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.

/PWM Frequency Registers

RANGE

/PWM1 frequency. 0xC4

RANGE

/PWM2 frequency. 0xC4

RANGE

/PWM3 frequency. 0xC4

RANGE

HF/LF =1, enables high frequency PWM output for 4-wire fans. Once enabled, 3-wire fan-specific settings have no effect (this means, pulse stretching).

These bits determine the PWM duty cycle vs. the temperature slope for automatic fan control.

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ADT7475

Table 32. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00)

Bit Name R/W1 Description

<2:0> ACOU1 Read/write

<3> EN1 Read/write When this bit is 1, smoothing is enabled on Remote 1 temperature channel. <4> SYNC Read/write

<5> MIN1 Read/write

<6> MIN2 Read/write

<7> MIN3 Read/write

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 1 Temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100%

000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100%

000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec

SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured.

SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output. When the ADT7475 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle)

or at PWM1 minimum duty cycle when the controlling temperature is below its T 0 = 0% duty cycle below T 1 = PWM1 minimum duty cycle below T

– hysteresis.

MIN

– hysteresis.

MIN

– hysteresis value.

MIN

When the ADT7475 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its T value.

0 = 0% duty cycle below T 1 = PWM 2 minimum duty cycle below T

– hysteresis.

MIN

– hysteresis.

MIN

When the ADT7475 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its T value.

0 = 0% duty cycle below T 1 = PWM3 minimum duty cycle below T

– hysteresis.

MIN

– hysteresis.

MIN

– hysteresis

MIN

– hysteresis

MIN

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Table 33. Register 0x63—Enhanced Acoustics Register 2 (Power-On Default = 0x00)

Bit Name R/W1 Description

<2:0> ACOU3 Read/write

< 3 > EN3 Read/write When this bit is 1, smoothing is enabled on the Local temperature channel. <6:4> ACOU2 Read/write

<7> EN2 Read/write When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Assuming that PWMx is associated with the Local temperature channel, these bits define the maximum rate of change of the PWMx output for Local Temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately y enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100%

000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100%

000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec

Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 2 Temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100%

000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100%

000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec

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Table 34. PWM Minimum Duty Cycle Registers

0x64 Read/write PWM1 minimum duty cycle. 0x80 (50% duty cycle) 0x65 Read/write PWM2 minimum duty cycle. 0x80 (50% duty cycle) 0x66 Read/write PWM3 minimum duty cycle. 0x80 (50% duty cycle)

Bit Name R/W

<7:0> PWM duty cycle Read/write These bits define the PWM 0x00 = 0% duty cycle (fan off ). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xFF = 100% duty cycle (fan full speed).

These registers become read-only when the ADT7475 is in automatic fan control mode.

Table 35. T

Registers

MIN

0x67 Read/write Remote 1 temperature T 0x68 Read/write Local temperatue T 0x69 Read/write Remote 2 temperature T

These are the T

with temperature according to T

These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.

registers for each temperature channel. When the temperature measured exceeds T

MIN

RANGE

Table 36.

THERM

Limit Registers

0x6A Read/write 0x6B Read/write 0x6C Read/write

If any temperature measured exceeds its

system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below a exceeding these limits by 0.25°C can cause the

These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.

Table 37. Temperature/T

MIN

0x6D Read/write Remote 1 and local temperature hysteresis. 0x44 <3:0> HYSL

<7:4> HYSR1

0x6E Read/write Remote 2 temperature hysteresis. 0x40 <7:4> HYSR2

Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its

value, the fan remains running at PWM

MIN

channel. The hysteresis value chosen also applies to that temperature channel, if its THERM

limit is exceeded and remains at 100% until the temperature drops below

value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to T

These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.

THERM

limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the

THERM

pin to assert low as an output.

Hysteresis Registers

duty cycle until the temperature = T

MIN

Description

duty cycle for PWMx.

MIN

. 0x5A (90°C)

MIN

. 0x5A (90°C)

MIN

. 0x5A (90°C)

MIN

, the appropriate fan runs at minimum speed and increases

MIN

Remote 1 THERM limit. Local

THERM limit.

Remote 2

THERM limit.

THERM

Limit − Hysteresis. If the

Local temperature hyseresis. 0°C to 15°C of hysteresis can be applied to the local temperature and AFC loops.

Remote 1 temperature hyseresis. 0°C to 15°C of hysteresis can be applied to the Remote 1 temperature and AFC loops.

Local temperature hyseresis. 0°C to 15°C of hysteresis can be applied to the local temperature and AFC loops.

− hysteresis. Up to 15°C of hysteresis can be assigned to any temperature

MIN

THERM

limit is exceeded. The PWM output being controlled goes to 100%, if the

THERM

− hysteresis. For acoustic reasons, it is recommended that the hysteresis

0x64 (100°C) 0x64 (100°C) 0x64 (100°C)

THERM

pin is programmed as an output, then

MIN

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ADT7475

Table 38. XNOR Tree Test Enable

0x6F Read/write XNOR tree test enable register. 0x00 <0> XEN

<7:1> Reserved Unused. Do not write to these bits.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Table 39. Remote 1 Temperature Offset

0x70 Read/write Remote 1 temperature offset. 0x00 <7:0> Read/write

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Table 40. Local Temperature Offset

0x71 Read/write Local temperature offset. 0x00 <7:0> Read/write

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Description Power-On Default

If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR tree test mode.

Description Power-On Default

Allows a twos complement offset value to be automatically added to or subtracted from the Remote 1 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C.

Description Power-On Default

Allows a twos complement offset value to be automatically added to or subtracted from the local temperature reading. LSB value = 0.5°C.

Table 41. Remote 2 Temperature Offset

Description Power-On Default

0x72 Read/write Remote 2 temperature offset. 0x00 <7:0> Read/write

Allows a twos complement offset value to be automatically added to or subtracted from the Remote 2 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

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Table 42. Register 0x73—Configuration Register 2 (Power-On Default = 0x00)

Bit Name R/W

<0:3> RES Reserved. 4 AVG Read/write

5 ATTN Read/write

6 CONV Read/write

7 SHDN Read/write

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Description

AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster.

ATTN = 1, the ADT7475 removes the attenuators from the V

input. The V

CCP

can be used for other functions such as connecting up external sensors. CONV = 1, the ADT7475 is put into a single channel ADC conversion mode. In this

mode, the ADT7475 can be made to read continuously from one input only, for example, Remote 1 temperature. The appropriate ADC channel is selected by writing to bits <7:5> of TACH1 minimum high byte register (0x55).

Bits <7:5> Reg. 0x55

000 Reserved 001 V

CCP

010 VCC (3.3 V) 011 Reserved 100 Reserved 101 Remote 1 temperature 110 Local temperature 111 Remote 2 temperature SHDN = 1, ADT7475 goes into shutdown mode. All PWM outputs assert low (or

high depending on state of INV bit) to switch off all fans. The PWM current duty cycle registers read 0x00 to indicate that the fans are not being driven.

CCP

input

Table 43. Register 0x74—Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)

Bit Name R/W Description

1 V

2 VCC Read/write 4 RIT Read/write 5 LT Read/write 6 R2T Read/write 7 OOL Read/write

Read/write

CCP

= 1, masks SMBALERT for out-of-limit conditions on the V

CCP

= 1, masks SMBALERT for out-of-limit conditions on the V

RIT = 1, masks LT = 1, masks R2T = 1, masks OOL = 1, masks

SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.

SMBALERT for out-of-limit conditions on the local temperature channel.

SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.

SMBALERT for any out-of-limit condition in Status Register 2.

Table 44. Register 0x75—Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)

Bit Name R/W Description

1 OVT Read only

2 FAN1 Read/write 3 FAN2 Read/write 4 FAN3 Read/write

5. F4P Read/write

OVT = 1, masks SMBALERT for overtemperature THERM conditions. FAN1 = 1, masks FAN2 = 1, masks FAN3 = 1, masks F4P = 1, masks

SMBALERT for a Fan 1 fault. SMBALERT for a Fan 2 fault. SMBALERT for a Fan 3 fault.

SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM input,

this bit masks SMBALERT for a THERM timer event. 6 D1 Read/write 7 D2 Read/write

D1 = 1, masks

D2 = 1, masks

SMBALERT for a diode open or short on a Remote 1 channel. SMBALERT for a diode open or short on a Remote 2 channel.

Table 45. Register 0x76—Extended Resolution Register 1

Bit Name R/W Description

<3:2> V

Read-only V

CCP

LSBs. Holds the 2 LSBs of the 10-bit V

CCP

measurement.

CCP

<5:4> VCC Read-only VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.

If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

channel.

CCP

channel.

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Table 46. Register 0x77—Extended Resolution Register 2

Bit Name R/W Description

<3:2> TDM1 Read-only Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. <5:4> LTMP Read-only Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. <7:6> TDM2 Read-only Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.

If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 47. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)

Bit Name R/W1 Description

<0> ALERT Read/write

ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions.

<1>

THERM

Read/write

THERM Enable = 1 enables THERM timer monitoring functionality on Pin 9. Also determined by Bits 0 and 1 (PIN9FUNC) of Configuration Register 4. When

THERM is asserted, if the fans are running

and the boost bit is set, the fans run at full speed. Alternatively, THERM can be programmed so that

<2> BOOST Read/write

a timer is triggered to time how long

THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum

When

THERM has been asserted.

programmed duty cycle for fail-safe cooling.

<3> FAST Read/write

FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second to once every 250 ms (4 ×).

<4> DC1 Read/write

DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.

<5> DC2 Read/write

DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.

<6> DC3 Read/write

DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.

<7> DC4 Read/write

DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Table 48. Register 0x79—

THERM

Timer Status Register (Power-On Default = 0x00)

Bit Name R/W Description

<7:1> TMR Read-only

Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time exceeds 45.52 ms.

<0>

ASRT/ TMR0

Read-only

This bit is set high on the assertion of the assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms.

Table 49. Register 0x7A—

THERM

Timer Limit Register (Power-On Default = 0x00)

Bit Name R/W Description

<7:0> LIMT Read/write

Sets maximum limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be programmed. If the Register 2 (Reg. 0x42) is set. If the limit value is 0x00, then an interrupt is generated immediately on the assertion of the

THERM input, and is cleared on read. If the THERM

THERM assertion length allowed before an interrupt is generated. This is an 8-bit

THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status

THERM input.

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ADT7475

Table 50. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55)

Bit Name R/W Description

<1:0> FAN1 Read/write

Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <3:2> FAN2 Read/write

Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <5:4> FAN3 Read/write

Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <7:6> FAN4 Read/write

Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4

Table 51. Register 0x7C—Configuration Register 5 (Power-On Default = 0x00)

Bit Name R/W

<0> 2sC Read/write Twos complement = 1, sets the temperature range to twos complement temperature range.

<1> TempOffset TempOffset = 0, sets offset range to −63°C to +64°C with 0.5˚C resolution.

<2> GPIOD

<3> GPIOP

<4> RES Reserved <5>

THERM

Read/write

Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Description

Twos complement = 0, changes the temperature range to Offset 64. When this bit is changed, the ADT7475 interprets all relevant temperature register values as defined by this bit.

TempOffset = 1, sets offset range to −63°C to +127°C with 1˚C resolution. These settings apply to registers 0x70, 0x71, and 0x72 (remote 1, internal, and Remote 2 temperature

offset registers. GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an

output (1). GPIO polarity. When the GPIO function is enabled and is programmed as an output, this bit

determines whether the GPIO is active low (0) or high (1).

THERM = 0 , THERM temperature limit functionality enabled for Remote 1 temperature channel.

R1 THERM can also be disabled on any channel by the following:

In offset 64 mode, writing −64˚C to the appropriate In twos complement mode, writing −128˚C to the appropriate

THERM temperature limit.

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ADT7475

Bit Name R/W

<6>

Local THERM

Read/write

Description

THERM = 0, THERM temperature limit functionality enabled for local temperature channel.

Local THERM can also be disabled on any channel by the following:

In Offset 64 mode, writing −64˚C to the appropriate

THERM temperature limit.

In twos complement mode, writing −128˚C to the appropriate THERM temperature limit.

<7>

THERM

Read/write

THERM = 0, THERM temperature limit functionality enabled for Remote 2 temperature channel.

R2 THERM can also be disabled on any channel by the following:

In offset 64 mode, writing −64˚C to the appropriate

THERM temperature limit.

In twos complement mode, writing −128˚C to the appropriate THERM temperature limit.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Table 52. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00)

Bit Name R/W

Description

<1:0> Pin9FUNC Read/write These bits set the functionality of Pin 9: 00 = TACH4 (default)

01 = Bidirectional

SMBALERT

10 =

THERM

11 = GPIO <2>

THERM Disable

Read/write

THERM Disable = 0, THERM overtemperature output is enabled assuming THERM is correctly configured (registers 0x78, 0x7C, 0x7D).

THERM Disable = 1, THERM overtemperature output is disabled on all channels. THERM can also be disabled on any channel by the following: In offset 64 mode, writing −64˚C to the appropriate THERM temperature limit

THERM temperature limit

<3>

Max/Full on

THERM

Read/write

In twos complement mode, writing −128˚C to the appropriate Max/Full on

THERM = 0. When THERM limit is exceeded, fans will go to full speed.

Max/Full on

THERM = 1. When THERM limit is exceeded, fans will go to max speed as defined in

Read/write

CCP

Bypass V

attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to

CCP

2.2965 V (0xFF) .

<6:7> RES Unused.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Table 53. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)

Bit Name R/W Description

<7:0> Reserved Read-only

Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not

be written to under normal operation.

Table 54. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)

Bit Name R/W Description

<7:0> Reserved Read-only

Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not

be written to under normal operation.

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ADT7475

OUTLINE DIMENSIONS

0.193 BSC

0.012

0.008

0.154 BSC

0.069

0.053

SEATING PLANE

0.236 BSC

0.010

0.006

8° 0°

0.050

0.016

0.065

0.049

0.010

0.004

COPLANARITY

0.004

PIN 1

0.025 BSC

COMPLIANT TO JEDEC STANDARDS MO-137-AB

Figure 61. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADT7475ARQZ1 –40°C to +125°C 16-Lead QSOP RQ-16 ADT7475ARQZ-REEL1 –40°C to +125°C 16-Lead QSOP RQ-16 ADT7475ARQZ-REEL71 –40°C to +125°C 16-Lead QSOP RQ-16

Z = Pb-free part.

Rev. 0 | Page 64 of 64

Datasheet ADT7475 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

PRODUCT DESCRIPTION

QUICK COMPARISON BETWEEN ADT7473 AND ADT7475

RECOMMENDED IMPLEMENTATION

SERIAL BUS INTERFACE

WRITE OPERATIONS

Send Byte

Write Byte

READ OPERATIONS

Receive Byte

Alert Response Address

SMBus TIMEOUT

Configuration Register 1 (Reg. 0x40)

VIRUS PROTECTION

VOLTAGE MEASUREMENT INPUT

ANALOG-TO-DIGITAL CONVERTER

INPUT CIRCUITRY

VOLTAGE MEASUREMENT REGISTERS

EXTENDED RESOLUTION REGISTERS

ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS

Turn-Off Averaging

Bypass Voltage Input Attenuator

Single Channel ADC Conversion

Configuration Register 2 (Reg. 0x73)

TACH1 Minimum High Byte (Reg. 0x55)

TEMPERATURE MEASUREMENT METHOD

Local Temperature Measurement

Remote Temperature Measurement

Noise Filtering

FACTORS AFFECTING DIODE ACCURACY

Remote Sensing Diode

Nulling Out Temperature Errors

Reading Temperature from the ADT7475

Temperature Offset Registers

ADT7463/ADT7475 Backwards Compatible Mode

Temperature Measurement Registers

Temperature Measurement Limit Registers

ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT

Turn-Off Averaging

Single Channel ADC Conversions

Configuration Register 2 (Reg. 0x73)

TACH1 Minimum High Byte (Reg. 0x55)

Overtemperature Events

LIMITS, STATUS REGISTERS, AND INTERRUPTS

LIMIT VALUES

8-Bit Limits

Volt ag e Li m it R eg ist ers

Out-of-Limit Comparisons

Temperature Limit Registers

16-Bit Limits

Analog Monitoring Cycle Time

Fan Limit Registers

STATUS REGISTERS

Status Register 1 (Reg. 0x41)

Status Register 2 (Reg. 0x42)

Interrupt Mask Register 2 (Reg. 0x75)

Masking Interrupt Sources

Interrupt Mask Register 1 (Reg. 0x74)

FAN DRIVE USING PWM CONTROL

Driving Two Fans from PWM3

Driving up to Three Fans from PWM3

<4> (SYNC) Enhance Acoustics Register 1 (Reg. 0x62)

TACH Inputs

Fan Speed Measurement

Fan Speed Measurement Registers

Reading Fan Speed from the ADT7475

Calculating Fan Speed

Fan TACH Limit Registers