Datasheet ADT7318ARQ, ADT7317ARQ, ADT7316ARQ Datasheet (Analog Devices)

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PRELIMINARY TECHNICAL DA T A





SPI/I2C



Compatible, 10-Bit Digital Temperature

Sensor and Quad Voltage Output 12/10/8-Bit DAC

Preliminary Technical Data

FEATURES ADT7316 - Four 12-Bit DACs ADT7317 - Four 10-Bit DACs ADT7318 - Four 8-Bit DACs Buffered Voltage Output Guaranteed Monotonic By Design Over All Codes 10-Bit Temperature to Digital Converter Temperature range: -40 Temperature Sensor Accuracy of ±0.5 Supply Range : + 2.7 V to + 5.5 V

DAC Output Range: 0 - 2V Power-Down Current 1 Internal 2.25 V

Option

Ref

Double-Buffered Input Logic Buffered / Unbuffered Reference Input Option Power-on Reset to Zero Volts Simultaneous Update of Outputs ( On-Chip Rail-to-Rail Output Buffer Amplifier







, SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4wire Serial Interface 16-Lead QSOP Package

APPLICATIONS Portable Battery Powered Instruments Personal Computers Telecommunications Systems Electronic Test Equipment Domestic Appliances Process Control

INTERNAL T EMPERAT URE

VALUE REGISTER

A-TO-D

CONVERTER

EXTERNAL TEMPERATURE

VALUE REGISTER

D+

D-

TEMPERATURE

7 8

ON-CHIP SENSOR

ANAL OG

MUX

SENSOR

ADT7316/17/18

µµ

µA

µµ

REF

VALU E

C to +125oC

LDAC Function)

X U M L A T

COMPARATOR

I D

LIMIT

STATUS

REGISTERS

ADDRESSPOINTER

X U M L A T

I G

I D

CONTROL CONFIG. 1

CONTROL CONFIG. 2

CONTROL CONFIG. 3

DAC CONFIGURATION

LDAC C ONF IGURA TION

INTERRUPT MASK

ADT7316/7317/7318

GENERAL DESCRIPTION

The ADT7316/7317/7318 combines a 10-Bit Temperature-to-Digital Converter and a quad 12/10/8-Bit DAC respectively, in a 16-Lead QSOP package. This includes a bandgap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of

C. The ADT7316/17/18 operates from a single

0.25 +2.7V to +5.5V supply. The output voltage of the DAC ranges from 0 V to 2V time of typ 7 msec. The ADT7316/17/18 provides two serial interface options, a four-wire serial interface which is compatible with SPI DSP interface standards; and a two-wire I features a standby mode that is controlled via the serial interface.

The reference for the four DACs is derived either internally or from two reference pins (one per DAC pair) .The outputs of all DACs may be updated simultaneously using the software

LDAC

function or external LDAC pin. The ADT7316/7317/7318 incorporates a power-on-reset circuit, which ensures that the DAC output powers-up to zero volts and it remains there until a valid write takes place.

The ADT7316/7317/7318’s wide supply voltage range, low supply current and SPI/I make it ideal for a variety of applications, including personal computers, office equipment and domestic appliances.

LIMIT

HIGH

REGISTERS

LIMIT

LOW

REGISTERS

VDDLim it

REGISTERS

, with an output voltage settling

REF

, QSPITM, MICROWIRETM and

C-compatible interface,

DAC A

DAC B

DAC C

REGISTERS

DAC D

REGISTERS

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

C interface. It

GAIN

SELECT

LOGIC

POWER

DOWN LOGIC

-A

OUT

-B

OUT

-C

OUT

-D

OUT

INTERRUP

SMBus/SPI INTERFACE

6 5

VDDGND

4 13 12 11

SCL/SCLK SDA/DIN

DOUT /ADD

FUNCTIONAL BLOCK DIAGRAM

REV. PrN 02/02

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

INTERNAL TEMP

LDAC

-AB

REF

SENSOR

-CD

REF

I2C is a registered trademark of Philips Corporation * Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, INC. MICROWIRE is a trademark of National Semiconductor Corporation.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL D A T A

ADT7316/ADT7317/ADT7318-SPECIFICATIONS

(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted)

Parameter

DAC DC PERFORMANCE

3,4

Min Typ Max Units Conditions/Comments

ADT7318

Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Relative Accuracy tbd tbd LSB Excluding Offset and Gain errors Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic by design over all codes

ADT7317

Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Relative Accuracy tbd tbd LSB Excluding Offset and Gain errors Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic by design over all codes

ADT7316

Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Relative Accuracy tbd tbd LSB Excluding Offset and Gain errors

Differential Nonlinearity ±0.02 ±0.9 LSB Guaranteed Monotonic by design over all codes Offset Error ±0.4 ±3 % of FSR Offset Error Match ±0.5 LSB Gain Error ±0.3 ±1.25 % of FSR Gain Error Match ±0.5 LSB Lower Deadband 20 60 mV Lower Deadband exists only if Offset Error is

Negative. See Figure 5.

Upper Deadband tbd tbd mV Upper Deadband exists if V

Offset Error Drift Gain Error Drift

DC Power Supply Rejection Ratio

DC Crosstalk

THERMAL CHARACTERISTICS

-12

-5

ppm of FSR/°C ppm of FSR/°C

-60 dB ∆V

200 µV R

plus Gain Error is positive. See Figure 6.

= ±10%

= 2 KΩ to GND or V

Internal Reference used.

= VDD and Offset

REF

INTERNAL TEMPERATURE SENSOR

Accuracy @ VDD=3.3V ±2 °C TA = 0°C to +85°C

±3 °C T

Accuracy @ V

Resolution 10 Bits Long Term Drift 0.5 °C/1000hrs

EXTERNAL TEMPERATURE SENSOR External Transistor = 2N3906.

Accuracy @ V

Resolution 10 Bits

Update Rate, t

Temperature Conversion Time

=5V ±2 °C TA = 0°C to +85°C

=3.3V ±2 °C TA = 0°C to +85°C.

=5V ±2 °C TA = 0°C to +85°C

±3 °C T

TBD µ s Round Robin5 enabled TBD µs Round Robin disabled TBD

µs

= -40°C to +125°C

Output Source Current 180 µA High Level

11 µA Low Level

VOLTAGE OUTPUT

8-Bit DAC Output

Resolution 1 °C Scale Factor 8.79 mV/°C 0-V

17.58 mV/°C 0-2V

Output. TA = -40°C to +125°C

REF

Output. TA = -40°C to +125°C

REF

10-Bit DAC Output

Resolution 0.25 °C

–2–

REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

Parameter

DAC ERTERNAL REFERENCE INPUT

Scale Factor 2.2 mV/°C 0-V

Input Range 1 V

REF

Input Range 0.25 V

REF

Input Impedance 37 45 k Ω Unbuffered Reference Mode. 0-2 V

REF

Min Typ Max Units Conditions/Comments

Output. TA = -40°C to +125°C

4.39 mV/°C 0-2V

DD DD

74 90 kΩ Unbuffered Reference Mode. 0- V

V Buffered Reference Mode V Unbuffered Reference Mode

REF

Output. TA = -40°C to +125°C

REF

>10 MΩ Buffered reference mode and Power-Down Mode

Output Range.

REF

Output Range.

REF

Reference Feedthrough -90 dB Frequency=10KHz Channel-toChannel Isolation -75 dB Frequency=10KHz

ON-CHIP REFERENCE

Reference Voltage Temperature Coefficient

OUTPUT CHARACTERISTICS

Output Voltage

0.001 VDD-0.001 V This is a measure of the minimum and maximum drive

2.25 V 80 ppm/

°C

capability of the output amplifier

DC Output Impedance 0.5 Ω Short Circuit Current 25 mA V

16 mA V

Power Up Time 2.5 µs Coming out of Power Down Mode. V

5 µs Coming out of Power Down Mode. VDD = +3 V

DIGITAL INPUTS

Input Current ±1 µ A VIN = 0V to V VIL, Input Low Voltage 0.8 V V

0.6 V V

, Input High Voltage 1.89 V

Pin Capacitance 3 10 pF All Digital Inputs

= +5V

= +3V

= +5V±10%

= +3V±10%

= +5 V

SCL, SDA Glitch Rejection 50 ns Input Filtering Suppresses Noise Spikes of Less than 50

DIGITAL OUTPUT

Output High Voltage, V Output Low Voltage, V Output High Current, I

Output Capacitance, C

ALERT Output Saturation Voltage

I2C TIMING CHARACTERISTICS

Serial Clock Period, t

OUT

8,9

Data In Setup Time to SCL High, t Data Out Stable after SCL Low, t

2.4 V I

0.4 V IOL = 3 mA 1mAV

50 pF

0.8 V I

2.5 µs Fast-Mode I2C. See Figure 1

0 ns See Figure 1

SOURCE

= 5 V

= 4 mA

OUT

= I

SINK

= 200 µA

SDA Low Setup Time to SCL Low

(Start Condition), t

50 ns See Figure 1

SDA High Hold Time after SCL High

(Stop Condition), t

SDA and SCL Fall Time, t

SPI TIMING CHARACTERISTICS

CS to SCLK Setup Time, t SCLK High Pulsewidth, t SCLK Low Pulse, t Data Access Time after

SCLK Falling edge, t

50 ns See Figure 1

90 ns See Figure 1

10, 11

0 ns See Figure 2 50 ns See Figure 2 50 ns See Figure 2

35 ns See Figure 2

Data Setup Time Prior

to SCLK Rising Edge, t

20 ns See Figure 2

Data Hold Time after

SCLK Rising Edge, t

CS to SCLK Hold Time, t

CS to DOUT High Impedance, t

0 ns See Figure 2 0 ns See Figure 2

40 ns See Figure 2

POWER REQUIREMENTS

Settling Time 50 ms VDD settles to within 10% of it’s final voltage

2.7 5.5 V

level.

–3–REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

(Normal Mode)

(Power Down Mode) 1 3 µA V

Power Dissipation tbd tbd tbd µW V

Notes:

Temperature ranges are as follows: A Version: -40°C to +125°C.

See Terminology.

DC specifications tested with the outputs unloaded.

Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)

See Terminology.

Guaranteed by Design and Characterization, not production tested

In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V "Offset plus Gain" Error must be positive.

The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I rate but has a negative affect on the EMC behaviour of the part.

Guaranteed by design. Not tested in production.

Guaranteed by design and characterization, not production tested.

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Measured with the load circuit of Figure 3.

IDD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Specifications subject to change without notice.

0.85 1.3 mA VIH = VDD and V = +4.5V to +5.5V, VIH=VDD and VIL=GND

0.5 1 µA V

= +2.7V to +3.6V, VIH=VDD and VIL=GND

= +2.7 V. Using Normal Mode

= GND

tbd tbd tbd µW VDD = +2.7 V. Using Shutdown Mode

C specification. Switching off the input filters improves the transfer

REF=VDD

DAC AC CHARACTERISTICS

Parameter

Min Typ @ 25°C M ax Units Conditions/Comments

Output Voltage Settling Time V

(VDD = +2.7V to +5.5 V; R 4K7Ω to V

; All specifications T

=4k7Ω to GND; C

to T

MIN

REF=VDD

MAX

=+5V

=200pF to GND;

unless otherwise noted.)

ADT7318 6 8 µs 1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex) ADT7317 7 9 µs 1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex) ADT7316 8 10 µs 1/4 Scale to 3/4 Scale change (400 Hex to

C00 Hex) Slew Rate 0.7 V/µs Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry. Digital Feedthrough 0.5 nV-s Digital Crosstalk 1 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion -70 dB V

NOTES

Guaranteed by Design and Characterization, not production tested

See Terminology

=2V±0.1Vpp

REF

=2.5V±0.1Vpp. Frequency=10kHz.

REF

Specifications subject to change without notice.

SCL

SDA

DATA IN

SDA

DATA O U T

Figure 1. Diagram for I2C Bus Timing

–4– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

SCLK

DOUT DBX

DIN

DB7

MSB L SB

DBX DBX

DB6 DB0

DBX

DB5

DB7 MSB

DB8

MSB

Figure 2. Diagram for SPI Bus Timing

200

␮

OUTPUT

50pF

1.6V

200

␮

Figure 3. Load Circuit for Access Time and Bus Relinquish Time

To DAC

Outp ut

4Κ7Ω

4Κ7Ω 200

Figure 4. Load Circuit for DAC Outputs

–5–REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

ABSOLUTE MAXIMUM RATINGS*

VDD to GND –0.3 V to +7 V Digital Input Voltage to GND –0.3 V to V Digital Output Voltage to GND –0.3 V to V Reference Input voltage to GND –0.3 V to V Operating Temperature Range –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature +150°C 16-Lead QSOP Package Power Dissipation (T

Thermal Impedance 150 °C/W (QSOP)

Reflow Soldering Peak Temperature +220 +/- 0°C

Time of Peak Temperature 10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DD DD

max - T

+ 0.3 V + 0.3 V

+ 0.3V

) / θ

Table 1. I

C Address Selection

ADD Pin I2C Address

Low 1001 000

Float 1001 010

High 1001 011

PIN CONFIGURATION

QSOP

-B

out

-A

out

ref

-AB V

ADT7316/

GND

D+

D-

7317/7318

TOP VIEW

(Not to Scale)

SCL/SCLK

SDA/D IN DOUT/ADDVDD

INTERRUPT

LDAC

out out ref

-C1

-D

-CD

ORDERING GUIDE

Model Temperature Range DAC Resolution Package Description Package Options

ADT7318ARQ –40°C to +125°C 8-Bits 16-Lead QSOP RQ-16 ADT7317ARQ -40°C to +125°C 10-Bits 16-Lead QSOP RQ-16 ADT7316ARQ -40°C to +125°C 12-Bits 16-Lead QSOP RQ-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although

ADT7316/7317/7318

the

feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–6– REV. PrN

WARNING!

ESD SENSITIVE DEVICE

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

ADT7316/7317/7318 PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1V 2V 3V

4 CS SPI Active low control Input. This is the frame synchronization signal for the input data.

5 GN D Ground Reference Point for All Circuitry on the part. Analog and Digital Ground. 6VDDPositive Supply Voltage, +2.7 V to +5.5 V.The supply should be decoupled to ground. 7 D+ Positive connection to external temperature sensor 8 D- Negative connection to external temperature sensor 9 LDAC Active low control input that transfers the contents of the input registers to their respective

10 INTERRUPT Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active

11 DOUT/ADD SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is

12 SDA/DIN SDA - I

13 SCL/SCLK Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock

14 V

15 V 16 V

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

AB Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input

REF

to each or both of the DACs A and B. It has an input range from 0.25 V to V

in unbuffered

mode and from 1 V to VDD in buffered mode.

When CS goes low, it enables the input register and data is transferred in and out on the rising edges of the following serial clocks. This pin must be kept high for I

C mode of operation.

CS is also used as a control pin when selecting the serial interface type after power-up.

DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Bit C3 of Control Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the loading of DAC registers.

high interrupt when temperature, VDD and AIN limits are exceeded. Default is active low.

clocked out at the falling edge of SCLK. ADD, I nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/

18. Any subsequent changes on this pin will have no affect on the I

C serial bus address selection pin. Logic input. During the first valid I2C bus commu-

C serial bus address. A low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011.

C Serial Data Input. I2C serial data to be loaded into the parts registers is provided on this input. DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on this input. Data is clocked into a register on the rising edge of SCLK.

data out of any register of the ADT7316/7317/7318 and also to clock data into any register that can be written to.

CD Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input

REF

to each or both of the DACs C and D. It has an input range from 0.25 V to V

in unbuffered

mode and from 1 V to VDD in buffered mode.

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

–7–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

TERMINOLOGY RELATIVE ACCURACY

Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus Code plots can be seen in TPCs 1, 2, and 3.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC and Temperature Sensor ADC is guaranteed monotonic by design. Typical DAC DNL versus Code plots can be seen in TPCs 4, 5, and 6.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output amplifier. (See Figures 5 and 6.) It can be negative or positive. It is expressed in mV.

OFFSET ERROR MATCH

This is the difference in Offset Error between any two channels.

GAIN ERROR

This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.

GAIN ERROR MATCH

This is the difference in Gain Error between any two channels.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of fullscale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of fullscale range)/°C.

DC POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V the DAC. It is measured in dBs. V V

is varied ±10%.

DC CROSSTALK

to a change in VDD for full-scale output of

OUT

is held at 2 V and

REF

This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in µV.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.

CHANNEL-TO-CHANNEL ISOLATION

This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dBs.

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to the. It is specified in nV secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa.

DIGITAL CROSSTALK

This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in stand-alone mode and is expressed in nV secs.

ANALOG CROSSTALK

This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV secs.

DAC-TO-DAC CROSSTALK

This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs.

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.

–8– REV. PrN

PRELIMINARY TECHNICAL D A T A

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.

ROUND ROBIN

This term is used to describe the ADT7316/17/18 cycling through the available measurement channels in sequence taking a measurement on each channel.

GAIN ERROR

OFFSE T ERROR

ADT7316/7317/7318

OUTP UT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AM PL IFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

LOWER

DEADBAND

CODES

DAC CODE

ACTUAL IDEAL

Figure 5. Transfer Function with Negative Offset

GAIN ERROR

OFFSET ERROR

UPPER

OUTP UT

VOLTAGE

DEADBA ND CODES

ACTUAL IDEAL

POSITIVE

OFFSET

ERROR

DAC CODE

FULL SCALE

Figure 6. Transfer Function with Positive Offset (V

–9–REV. PrN

REF

= VDD)

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

1.0

TA=25ⴗC

=5V

0.5

R R E L N

-0.5

-1.0 050 250100 150 200

CODE

TPC 1. ADT7318 Typical INL Plot

0. 3

TA=25ⴗC V

=5V

0. 2

s B S

0. 1

R O

R R E

-0.1

N D

-0.2

TA=25ⴗC

=5V

O R R E L

-1

-2

-3 0 200 1000400 600 800

CODE

TA=25ⴗC

=5V

s B

S L

O R R E L

-4

-8

-12 040001000 2000 3000

CODE

TPC 2. ADT7317 Typical INL Plot TPC 3. ADT7316 Typical INL Plot

0.6

TA=25ⴗC

=5V

0.4

s B

0.2

S L

R R E L

-0.2

N D

-0.4

TA=25ⴗC

=5V

0.5

s B S L

R R E L N D

-0.5

-0.3 050 25100 150 200

CODE

TPC 4. ADT7318 Typical DNL Plot

0.5

VDD=5V T

=25ⴗC

0.25

s B S L

O R R E

-0.25

-0.5 01 5234

MAX INL

MIN DNL

MIN INL

REF

MAX DNL

-V

TPC 7. ADT7318 INL and DNL

Error vs V

REF

-0.6 2000

CODE

600400

800 100

-1 10000

2000

CODE

3000 4000

TPC 5. ADT7317 Typical DNL Plot TPC 6. ADT7316 Typical DNL Plot

0.5

VDD=5V

0.4

=3V

REF

0.3

0.2

s B

0.1

S L

R O R

-0.1

R E

-0.2

-0.3

-0.4

-0.5

ⴚ

40 0 40

MAX INL

MAX DNL

MIN DNL

MIN INL

80 120

TEMPERATURE -ⴰC

TPC 8. ADT7318 INL Error and DNL

Error vs Temperature

VDD=5V V

=2V

REF

0.5

R S F

R O R R E

-0.5

-1

ⴚ

GAIN E RROR

OFFS ET ER ROR

40 0 40

TEMPERATURE -ⴰC

80 120

TPC 9. ADT7318 Offset Error and Gain

Error vs Temperature

–10– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

0.2

TA=25ⴗC

0.1

=2V

REF

R S

-0.1

F %

-0.2

R O R

-0.3

R E

-0.4

-0.5

-0.6 01 3

GAIN ERROR

OFFS ET ER ROR

VDD-Volts

TPC 10. Offset Error and Gain

Error vs V

600

500

400

␮

300

D D

200

+25ⴗC

-40ⴗC

+105ⴗC

5V SOURCE

o V

T U O

01 3446

TPC 11. V

OUT

3V SOURCE

5V SINK

SINK/SOURCE CURRENT - mA

3V SINK

Source and Sink Current

Capability

0.5

0.4

0.3

␮

D D

0.2

-40ⴗC

+25ⴗC

600

500

TA=25ⴗC

=5V

400

␮

300

D D

200

100

ZERO-SCALE

CODE

=2V

REF

FULL-SCAL

TPC 12. Supply Current vs. DAC Code

=25ⴗC

5µs

=5V

REF

CH1

OUT

SCLK

CH2

100

2.5

3.0 3.5 4.0 4.5 5.0 5.5 VDD-Volts

TPC 13. Supply Current vs. Supply Volt-

age

TA=25ⴗC

=5V

=2V

REF

CH1

OUT

CH2

CH1 500mV, CH2 5.00V, TIME BASE = 1␮s/DIV

TPC 16. Exiting Power-Down to Midscale

0.1

2.5

3. 0

+105ⴗC

4.0

VDD-Volts

4.5 5.53.5

5.0

TPC 14. Power-Down Current vs. Supply

Voltage

2.50

2.49

l o V

T U O

2.4 8

2.47

1␮s/DIV

TPC 17. ADT7316 Major-Code Transition

Glitch Energy

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV

TPC 15. Half-Scale Settling (1/4 to 3/4

Scale Code Change)

-10

-20

B d

-30

-40

-50

-60

0.01

0.1 1 10 100 1k 10k FREQUENCY - k Hz

TPC 18. Multiplying Bandwidth (Small-

Signal Frequency Response)

–11–REV. PrN

ADT7316/7317/7318

0.02

VDD=5V T

=25ⴗC

l o

0.01

O R R E

E L A C S

L L

-0.01

U F

-0.02 01 3

PRELIMINARY TECHNICAL D A T A

I D

/ V m 1

REF

-Volts

150ns /DIV

TPC 19. Full-Scale Error vs. V

E L T

I T

000

0000

TITLE

REF

TPC 21. PSRR vs Supply Ripple Frequency

TPC 20. DAC-to-DAC Crosstalk

1.5

0.5

-30 - 20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120

TEMPERATURE ERROR ('

-0.5

-1

-1.5

-2

TEMPERATURE ('C)

5.5V

3.3

TPC 22. Temperature Error @ 3.3 V and 5.5 V

–12– REV. PrN

PRELIMINARY TECHNICAL D A T A

FUNCTIONAL DESCRIPTION - DAC

The ADT7316/7317/7318 has quad resistor-string DACs fabricated on a CMOS process with a resolutions of 12, 10 and 8 bits respectively. They contain four output buffer amplifiers and is written to via I2C serial interface or SPI serial interface. See Serial Interface Selection section for more information.

The ADT7316/7317/7318 operates from a single supply of 2.7 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7V/µs. DACs A and B share a common reference input, namely

AB. DACs C and D share a common reference input,

REF

namely V draw virtually no current from the reference source, or unbuffered to give a reference input range from GND to

. The devices have a power-down mode, in which all

DACs may be turned off completely with a high-impedance output.

Each DAC output will not be updated until it receives the LDAC command. Therefore while the DAC registers would have been written to with a new value, this value will not be represented by a voltage output until the DACs have received the LDAC command. Reading back from any DAC register prior to issuing an LDAC command will result in the digital value that corresponds to the DAC output voltage. Thus the digital value written to the DAC register cannot be read back until after the LDAC command has been initiated. This LDAC command can be given by either pulling the LDAC pin low, setting up Bits D4 and D5 of DAC Configuration register(Address = 1Bh) or using the LDAC register(Address = 1Ch).

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the V

2.25 V provides the reference voltage for the corresponding DAC. Figure 7 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by:

where D=decimal equivalent of the binary code which is loaded to the DAC register;

0-255 for ADT7318 (8-Bits) 0-1023 for ADT7317 (10-Bits) 0-4095 for ADT7316 (12-Bits)

N = DAC resolution.

CD. Each reference input may be buffered to

REF

pin or the on-chip reference of

REF

OUT

* D

REF

= ----------

ADT7316/7317/7318

REF

Int V

REF

GAIN MODE (GAIN=1 OR 2)

OUTPUT BUFFER AMPLIFIER

since

OUT

INPUT REGISTER

BUF

DAC REGISTER

RESISTOR STRING

REFERENCE BUFFER

Figure 7. Single DAC channel architecture

Resistor String

The resistor string section is shown in Figure 9. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

DAC Reference Inputs

There is a reference pin for each pair of DACs. The reference inputs are buffered but can also be individually configured as unbuffered.

-AB

REF

2.25 V

Internal V

REF

STRING

DAC A

STRING

DAC B

Figure 8. DAC Reference Buffer Circuit

The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as V there is no restriction due to headroom and footroom of the reference amplifier.

–13–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

nominal value by the time 50ms has elasped then it is recommended that a measurement be taken on the V channel before a temperature measurement is taken.

TO OUTPUT AMPLIFIER

Figure 9. Resistor String

If there is a buffered reference in the circuit , there is no need to use the on-chip buffers. In unbuffered mode the input impedance is still large at typically 90 kΩ per reference input for 0-V

output mode and 45 kΩ for 0-2V

REF

output mode. The buffered/unbuffered option is controlled by the DAC

Configuration Register (address 1Bh, see data register descriptions). The LDAC Configuration register controls the option to select between internal and external voltage references. The default setting is for external reference selected.

Output Amplifier

The output buffer amplifier is capable of generating output voltages to within 1mV of either rail. Its actual range depends on the value of V

, GAIN and offset error.

REF

If a gain of 1 is selected (Bits 0-3 of DAC Configuration register = 0) the output range is 0.001 V to V

REF

. If a gain of 2 is selected (Bits 0-3 of DAC Configuration register = 1) the output range is 0.001 V to 2V

REF

. However because of clamping the maximum output is limited to V

- 0.001V.

The output amplifier is capable of driving a load of 2kΩ to GND or V

in parallel with 500pF to GND or VDD.

DD,

The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11.

The slew rate is 0.7V/µs with a half-scale settling time to +/-0.5 LSB (at 8 bits) of 6µs.

FUNCTIONAL DESCRIPTION

POWER-UP TIME

On power-up it is important that no communication to the part is initiated until 200ms after Vcc has settled. During this 200ms the part is performing a calibration routine and any communication to the device will interrupt this routine and could cause erroneous temperature measurements.

must have settled to within 10% of it’s final value

after 50ms power-on time has elasped. Therefore once power is applied to the ADT7316/17/18, it can be addressed 250ms later. If it not possible to have V

at it’s

TEMPERATURE SENSOR

The ADT7316/7317/7318 contains a two-channel A to D converter with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. When the ADT7316/7317/7318 is operating normally, the A to D converter operates in a free-running mode. When in Round Robin mode the analog input multiplexer sequently selects the V

input channel, on-chip

temperature sensor to measure its internal temperature and then the external temperature sensor. These signals are digitized by the ADC and the results stored in the various Value Registers.

The measured results are compared with the Internal and External, T

HIGH

, T

limits. These temperature limits are

LOW

stored in on-chip registers. If the temperature limits are not masked out then any out of limit comparisons generate flags that are stored in Interrupt Status 1 Register and one or more out-of limit results will cause the INTERRUPT output to pull either high or low depending on the output polarity setting.

Theoretically, the temperature sensor and ADC can measure temperatures from -128 tion of 0.25

C. However, temperatures outside TA are outside the guaranteed operating temperature range of the device. Temperature measurement from -128

C is possible using an external sensor.

+127

C to +127oC with a resolu-

C to

Temperature measurement is initiated by three methods. The first method is applicable when the part is in single channel measurement mode. It uses an internal clock countdown of 20ms and then a conversion is preformed. The internal oscillator is the only circuit that’s powered up between conversions and once it times out, every 20ms, a wake-up signal is sent to power-up the rest of the circuitry. A monostable is activated at the beginning of the wake-up signal to ensure that sufficient time is given to the power-up process. The monostable typically takes 4 µs to time out. It then takes typically 25µs for each conversion to be completed. The temperature is measured 16 times and internally averaged to reduce noise. The total time to measure a temperature channel is typically 400us (25us x 16). The new temperature value is loaded into the Temperature Value Register and ready for reading by the

C or SPI interface. The user has the option of disabling

I the averaging by setting a bit (Bit 5) in the Control Configuration Register 2 (address 19h). The ADT7316/7317/ 7318 defaults on power-up with the averaging enabled.

Temperature measurement is also initiated after every read or write to the part when the part is in single channel measurement mode. Once serial communication has started, any conversion in progress is stopped and the ADC reset. Conversion will start again immediately after the serial communication has finished. The temperature measurement proceeds normally as described above.

The third method is applicable when the part is in round robin measurement mode. The part measures both the

–14– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round robin mode the part is continously measuring.

VDD MONITORING

The ADT7316/17/18 also has the capability of monitoring it’s own power supply. The part measures the voltage on it’s V

pin to a resolution of 10 bits. The resultant value

is stored in two 8-bit registers, the two LSBs stored in register address 03h and the eight MSBs are stored in register address 06h. This allows the user to have the option of just doing a one byte read if 10-bit resolution is not important. The measured result is compared with V and V

limits. If the VDD interrupt is not masked out

LOW

HIGH

then any out of limit comparison generates a flag in Interrupt Status 2 Register and one or more out-of-limit results will cause the INTERRUPT output to pull either high or low depending on the output polarity setting.

Measuring the voltage on the V

pin is regarded as moni-

toring a channel. Therefore, along with the Internal and External temperature sensors the V

voltage makes up

the third and final monitoring channel. You can select the V

channel for single channel measurement by setting Bit

C4 = 1 and setting Bit 0 to Bit 2 to all 0’s in Control Configuration 2 register.

When measuring the V

value the reference for the ADC

is sourced from the Internal Reference. Table 2 shows the data format. As the max V internal scaling is performed on the V

voltage measurable is 7 V,

voltage to match

the 2.25V internal reference value. Below is an example of how the transfer function works.

= 5 V

ADC Reference = 2.25 V 1 LSB = ADC Reference / 2^10 = 2.25 / 1024 =

2.197mV Scale Factor = Fullscale V

/ ADC Reference = 7 / 2.25

= 3.11

Conversion Result = V

/ ((7/Scale Factor) x LSB size)

= 5 / (3.11 x 2.197mV)

= 2DBh

6 V 11 0110 1101 36D

6.5 V 11 1011 0110 3B6 7 V 11 1111 1111 3 FF

ON-CHIP REFERENCE

The ADT7316/17/18 has an on-chip 1.2 V band-gap refernece which is gained up by a switched capacitor amplifier to give an output of 2.25 V. The amplifier is only powered up at the start of the conversion phase and is powered down at the end of conversion. On power-up the default mode is to have the internal reference selected as the reference for the DAC and ADC. The internal reference is always used when measuring the internal and external temperature sensors.

ROUND ROBIN MEASUREMENT

On power-up the ADT7316/17/18 goes into Round Robin mode but monitoring is disabled. Setting Bit C0 of Configuration Register 1 to a 1 enables conversions. It sequences through the three channels of V

, Internal

temperature sensor and External temperature sensor and takes a measurement from each. At intervals of tbd ms another measurement cycle is performed on all three channels. This method of taking a measurement on all three channels in one cycle is called Round Robin. Setting Bit 4 of Control Configuration 2 (address 19h) disables the Round Robin mode and in turn sets up the single channel mode. The single channel mode is where only one channel, eg. Internal temperature sensor, is measured in each conversion cycle.

The time taken to monitor all channels will normally not be of interest, as the most recently measured value can be read at any time.

For applications where the Round Robin time is important, it can be easily calculated.

As mentioned previously a conversion on each temperature channel takes 25 us and on the V

channel it takes 15 us.

Each channel is measured 16 times and internally averaged to reduce noise.

The total cycle time for voltage and temperature channels is therefore nominally :

(2 x 16 x 25) + (16 x 15) = 1.04 ms

TABLE 2. VDD Data Format, V

= 2.25V

REF

VDD Value Digital Output

Binary Hex

2.5 V 01 0110 1110 16E 3 V 01 1011 0111 1B7

3.5 V 10 0000 0000 200 4 V 10 0100 1001 249

4.5 V 10 1001 0010 292 5 V 10 1101 1011 2DB

5.5 V 11 0010 0100 324

SINGLE CHANNEL MEASUREMENT

Setting C4 of Control Configuration 2 register enables the single channel mode and allows the ADT7316/17/18 to focus on one channel only. A channel is selected by writing to Bits 0:2 in register Control Configuration 2 register. For example, to select the V

channel for monitoring

write to the Control Configuration 2 register and set C4 to 1 (if not done so already), then write all 0’s to bits 0 to 2 . All subsequent conversions will be done on the V

channel only. To change the channel selection to the Internal temperature channel, write to the Control Configuration 2 register and set C0 = 1. When measuring in single channel mode there is a time delay of TBD us between each measurement. A measurement is also initiated after every read or write operation.

–15–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

OPTIONAL CAPACITOR,UP TO

3nF MAX. CAN BE ADDED TO

IMPROVE HIGHFREQUENCY

NOISE REJECTION IN NOISY

ENVIRONMENTS

D+

REMOTE

SENSING

TRANSISTOR

(2N3906)

D-

LOWPAS S FILTER

= 65kHz

Figure 10. Signal Conditioning for External Diode temperature Sensors

MEASUREMENT METHOD

INTERNAL TEMPERATURE MEASUREMENT The ADT7316/7317/7318 contains an on-chip bandgap

temperature sensor, whose output is digitized by the onchip ADC. The temperature data is stored in the Internal Temperature Value Register. As both positive and negative temperatures can be measured, the temperature data is stored in two's complement format, as shown in Table 3. The thermal characteristics of the measurement sensor could change and therefore an offset is added to the measured value to enable the transfer function to match the thermal characteristics. This offset is added before the temperature data is stored. The offset value used is stored in the Internal Temperature Offset Register.

EXTERNAL TEMPERATURE MEASUREMENT The ADT7316/7317/7318 can measure the temperature of

one external diode sensor or diode-connected transistor. The forward voltage of a diode or diode-connected tran-

sistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mV/ the absolute value of V

, varies from device to device, and

C. Unfortunately,

individual calibration is required to null this out, so the technique is unsuitable for mass-production.

The time taken to measure the external temperature can be reduced by setting C0 of Control Config. 3 register (1Ah). This increases the ADC clock speed from 1.4KHz to 22KHz but the analog filters on the D+ and D- input pins are switched off to accommodate the higher clock speeds. Running at the slower ADC speed, the time taken to measure the external temperature is TBD while on the fast ADC this time is reduced to TBD.

The technique used in the ADT7316/7317/7318 is to measure the change in V

when the device is operated at

two different currents. This is given by: ∆V

= KT/q x ln(N)

NxI

BIAS

OUT+

TO AD

BIAS

DIODE

OUT-

where: K is Boltzmann’s constant q is charge on the carrier T is absolute temperature in Kelvins N is ratio of the two currents Figure 10 shows the input signal conditioning used to

measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor.

If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input.

We recommend that a 2N3906 be used as the external transistor.

To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. As the sensor is operating in a noisy environment, C1 is provided as a noise filter. See the section on layout considerations for more information on C1.

To measure ∆V

, the sensor is switched between operating

currents of I and N x I. The resulting waveform is passed through a lowpass filter to remove noise, thence to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to ∆V sured by the ADC to give a temperature output in 8-bit two’s complement format. To further reduce the effects of

. This voltage is mea-

noise, digital filtering is performed by averaging the results of 16 measurement cycles.

–16– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

INTERNAL

SENSE

TRANSISTOR

NxII

BIAS

DIODE

BIAS

Figure 11. Top Level Structure of Internal Temperature Sensor

LAYOUT CONSIDERATIONS

Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken:

1. Place the ADT7316/17/18 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses and CRTs are avoided, this distance can be 4 to 8 inches.

2. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible.

3. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended.

GND

D+

D-

GND

10 mil. 10 mil.

10 mil. 10 mil. 10 mil. 10 mil.

10 mil.

Figure 12. Arrangement of Signal Tracks

4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature.

Thermocouple effects should not be a major problem as

C corresponds to about 240µV, and thermocouple

voltages are about 3µV/

C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200mV.

OUT+

TO AD

OUT-

5. Place 0.1µF bypass and 2200pF input filter capacitors close to the ADT7316/17/18.

6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet.

7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADT7316/17/18. Leave the remote end of the shield unconnected to avoid ground loops.

Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed.

Cable resistance can also introduce errors. 1⍀ series resistance introduces about 0.5

C error.

TEMPERATURE VALUE FORMAT

One LSB of the ADC corresponds to 0.25°C. The ADC can theoretically measure a temperature span of 255 °C. The internal temperature sensor is guaranteed to a low value limit of -40 °C. It is possible to measure the full temperature span using the external temperature sensor. The temperature data format is shown in Tables 3.

The result of the internal or external temperature measurements is stored in the temperature value registers, and is compared with limits programmed into the Internal or External High and Low Registers.

TABLE 3. Temperature Data Format (Internal and External Temperature)

Temperature Digital Output

DB9..........DB0

-40 °C 11 0110 0000

–17–REV. PrN

ADT7316/7317/7318

)

S/W Reset

PRELIMINARY TECHNICAL D A T A

INTERRUPT

STATUS

(TEMP and Ext.

Diod e Check)

S T

I B

S U T A T

WATCHDOG

LIMIT

COMPARISONS

Read Reset

INTERRUPT

STATUS

(VDD)

I B

S U T A T S

INTERRUPT

MASK

REGISTERS

CONTROL

CONFIGURATION

Figure 13. ADT7316/17/18 Interrupt Structure

-25 °C 11 1001 1100

-10 °C 11 1101 1000

-0.25 °C 11 1111 1111 0 °C 00 0000 0000 +0.25 °C 00 0000 0001 +10 °C 00 0010 1000 +25 °C 00 0110 0100 +50 °C 00 1100 1000 +75 °C 01 0010 1100 +100 °C 01 1001 0000 +105 °C 01 1010 0100 +125 °C 01 1111 0100

Temperature Conversion Formula:

1. Positive Temperature = ADC Code/4

2. Negative Temperature = (ADC Code* - 512)/4

*DB9 is removed from the ADC Code

INTERRUPTS

The measured results from the inetrnal temperature sensor, external temperature sensor and the V pared with the T

HIGH/VHIGH

and T

LOW/VLOW

pin are com-

limits. These limits are stored in on-chip registers. Please note that the limit registers are 8 bits long while the conversion results are 10 bits long. If the limits are not masked out then any out of limit comparisons generate flags that are stored in

Internal

Temp

External

Tem p

Diode Fault

INTERRUPT ENABLE BIT

INTERRUPT (Latched Output

Interrupt Status 1 Register (address = 00h) and Interrupt Status 2 Register (address = 01h). One or more out-of limit results will cause the INTERRUPT output to pull either high or low depending on the output polarity setting.

Figure 13 shows the interrupt structure for the ADT7316/ 17/18. It gives a block diagram representation of how the various measurement channels affect the INTERRUPT pin.

THERMAL VOLTAGE OUTPUT

The ADT7316/17/18 has the capability of outputting a voltage that is proportional to temperature. DAC A output can be configured to reperesent the temperature of the internal sensor while DAC B output can be configured to reperesent the external temperature sensor. Bits 5 and 6 of Control Configuration 3 register select the temperature proportional output voltage. Each time a temperature measurement is taken the DAC output is updated. The output resolution ADT7318 is 8 bits with 1°C change corresponding to one LSB change. The output resolution for the ADT7316 and ADT7317 is capable of 10 bits with

0.25°C change corresponding to one LSB change. The default output resolution for the ADT7316 and ADT7317 is 8 bits. To increase this to 10 bits, set bit 1=1 of Control Configuration 3 register. The default output range is 0V-V

and this can be increased to 0V-2V

REF

the outout voltage span to 2V

can be done by setting

REF

. Increasing

REF

D0 = 1 for DAC A (Internal Temperature Sensor) and D1 = 1 for DAC B (External Temperature Sensor) in DAC Configuration register (address 1Bh).

The output voltage is capable of tracking a max temperature range of -128°C to +127°C but the default setting is 40°C to +127°C. If the output voltage range is 0V-V

REF

–18– REV. PrN

PRELIMINARY TECHNICAL D A T A

= 2.25 V) then this corresponds to 0V representing -

REF

40°C and 1.48V representing +127°C. This of course will give an upper deadband between 1.48V and V

The Internal and External Analog Temperature Offset registers can be used to vary this upper deadband and consequently the temperature that 0V corresponds to. Tables 4 and 5 give examples of how this is done using a DAC output voltage span of V

REF

and 2V

respectivily. Simply

REF

write in the temperature value, in 2’s complement format, that you want 0V to start at. For example, if you are using the DAC A output and you want 0V to start at -40°C then program D8h into the Internal Analog Temperature Offset register (address 21h). This is an 8-bit register and thus only has a temperature offset resolution of 1°C for all device models. Use the following formulas to determine the value to program into the offset registers.

Negative temperatures : -

Offset Register Code(d)* = (0V Temp) + 128

*D7 of Offset Register Code is set to 1 for negative temperatures.

Example : -

Offset Register Code(d) = (-40) + 128

= 88d = 58h

Since a negative temperature has been inputted into the equation, DB7 (MSB) of the Offset Register code is set to a 1. Therefore 58h becomes D8h.

58h + DB7(1) ⇒ D8h

Positive temperatures : -

Offset Register Code(d) = 0V Temp

Example : -

Offset Register Code (d) = 10d = 0Ah

Table 4. Thermal Voltage Output (0V-V

REF

)

ADT7316/7317/7318

0.75V +3 -85 43 1V +17 -71 +57

1.12V +23 -65 +63

1.47V +43 -45 +83

1.5V +45 -43 +85 2V +73 -15 +113

2.25V +88 0 +127

2.5V +102 +14 UDB*

2.75V +116 +28 UDB* 3V UDB* +42 UDB*

3.25V UDB* +56 UDB*

3.5V UDB* +70 UDB*

3.75V UDB* +85 UDB* 4V UDB* +99 UDB*

4.25V UDB* +113 UDB*

4.5V UDB* +127 UDB*

* Upper deadband has been reached. DAC output is not capable of increasing.

Reference Figure 6.

The following equation is used to work out the various temperatures for the corresponding 8-bit DAC output :-

8-Bit Temp = (DAC O/P ÷ 1 LSB) + ( 0V Temp)

For example, if the output is 1.5V, V DAC has an LSB size = 2.25V/255 = 8.82x10 Temp is at -128°C then the resultant temperature works out to be :-

(1.5 ÷8.82x10-3) + (-128) = +42°C

= 2.25 V, 8-bit

REF

-3

, and 0V

O/P Voltage Default °C Max °C Sample °C

0V -40 -128 0

0.5V +17 -71 +56 1V +73 -15 +113

1.12V +87 -1 +127

1.47V +127 +39 UDB*

1.5V UDB* +42 UDB* 2V UDB* +99 UDB*

2.25V UDB* +127 UDB*

* Upper deadband has been reached. DAC output is not capable of increasing.

Reference Figure 6.

Table 5. Thermal Voltage Output, (0V-2V

REF

)

O/P Voltage Default °C Max °C Sample °C

0V -40 -128 0

0.25V -26 -114 14

0.5V +12 -100 +28

–19–REV. PrN

The following equation is used to work out the various temperatures for the corresponding 10-bit DAC output :-

10-Bit Temp = ((DAC O/P ÷ 1 LSB)x0.25) + ( 0V Temp)

For example, if the output is 0.4991V, V bit DAC has an LSB size = 2.25V/1024 = 2.197x10

= 2.25 V, 10-

REF

-3

, and 0V Temp is at -40°C then the resultant temperature works out to be :-

((0.4991 ÷2.197x10-3)x0.25) + (-40) = +16.75°C

Figure 14 shows a graph of DAC output vs temperature for a V

= 2.25 V.

REF

ADT7316/7317/7318

)

(

)

PRELIMINARY TECHNICAL D A T A

2.25

2.10

1.95

1.80

1.65

1.50

1.35

DAC OUTPUT

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0.00

Temperature ('C

0 V = -128'C

0 V = 0'C

0 V = -40'C

2nd READ

COMMAND

Figure 16. Phase 2 of 10-Bit Read

If an MSB register is read first, it’s corresponding LSB register is not locked thus leaving the user with the option of just reading back 8 bits (MSB) of a 10-bit conversion result. Reading an MSB register first does not lock up other MSB registers and likewise reading an LSB register first does not lock up other LSB registers.

Table 6. List of ADT7316/7317/7318 Registers

RD/WR Name Power-on Address Default

00h Interrupt Status 1 00h

1271201101009080706050403020100-10-20-30-40-50-60-70-80-90-100-110-120-128

01h Interrupt Status 2 00h

MSB

UNLOCK ASSOCIATED

MSBREGISTERS

OUTPUT

DATA

02h RESERVED

Figure 14. DAC Output vs Temperature, V

= 2.25 V

REF

03h Internal Temp & VDD LSBs 00h 04h External Temp LSBs 00h

ADT7316/7317/7318 REGISTERS

The ADT7316/17/18 contains registers that are used to store the results of external and internal temperature measurements, V

value measurements, high and low tem-

perature and supply voltage limits, set output DAC voltage levels, configure multipurpose pins and generally

05h RESERVED 06h VDD MSBs 00h 07h Internal Temperature MSBs 00h 08h External Temp MSBs 00h

control the device. A description of these registers follows. The register map is divided into registers of 8-bits long.

09h-0Fh RESERVED

Each register has it’s own indvidual address but some consist of data that is linked with other registers. These registers hold the 10-bit conversion results of measurements taken on the Temperature and V example, the 8 MSBs of the V

measurement are stored

channels. For

in register address 06h while the 2 LSBs are stored in register address 03h. The link involved between these types of registers is that when the LSB register is read first then the MSB registers associated with that LSB register are locked to prevent any updates. To unlock these MSB registers the user has only to read any one of them, which will have the affect of unlocking all previously locked MSB registers. So for the example given above if register 03h was read first then MSB registers 06h and 07h would be locked to prevent any updates to them. If register 06h was read then this register and register 07h would be subsequently unlocked.

10h DAC A LSBs (ADT7316/17 only) 00h 11h DAC A MSBs 00h 12h DAC B LSBs (ADT7316/17 only) 00h 13h DAC B MSBs 00h 14h DAC C LSBs (ADT7316/17 only) 00h 15h DAC C MSBs 00h 16h DAC D LSBs (ADT7316/17 only) 00h 17h DAC D MSBs 00h 18h Control CONFIG 1 00h 19h Control CONFIG 2 00h 1Ah Control CONFIG 3 00h

1st READ

COMMAND

Figure 15. Phase 1 of 10-Bit Read

LSB

LOCK AS SOCIATED

MSB REGISTERS

OUTPUT

DATA

1Bh DAC CONFIG 00h 1Ch LDAC CONFIG 00h 1Dh Interrupt Mask 1 00h 1Eh Interrput Mask 2 00h 1Fh Internal Temp Offset 00h 20h External Temp Offset 00h 21h Internal Analog Temp Offset D8h

–20– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

22h External Analog Temp Offset D8h 23h VDD V 24h VDD V 25h Internal T 26h Internal T 27h External T 28h External T

Limit C9h

HIGH

Limit 62h

LOW

Limit 64h

HIGH

Limit C9h

LOW

HIGH

LOW

FFh

00h

29h-4CH RESERVED

4Dh Device ID 01h/05h/09h 4Eh Manufacturer’s ID 41h 4Fh Silicon Revision 00h

50h-FFh RESERVED

Interrupt Status 1 Register (Read only) [Add. = 00h]

This 8-bit read only register reflects the status of some of the interrupts that can cause the INTERRUPT pin to go active. This register is reset by a read operation or by a software reset.

Table 7. Interrupt Status 1 Register

Bit Function

D4 1 when VDD value exceeds corrosponding V

limits

LOW

INTERNAL TEMPERATURE VALUE/VDD VALUE REGISTER LSBs (Read only) [Add. = 03h]

HIGH

and

This Internal Temperature Value and VDD Value Register is a 8-bit read-only register. It stores the two LSBs of the 10-bit temperature reading from the internal temperature sensor and also the two LSBs of the 10-bit supply voltage reading.

Table 9. Internal Temp/VDD LSBs

D7 D6 D5 D4 D3 D2 D1 D0

N/A N/A N/A N/A V1 LSB T1 LSB N/A N/A N/A N/A 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

D0 LSB of Internal Temperature Value D1 B1 of Internal Temperature Value D2 LSB of VDD Value D3 B1 of VDD Value

D7 D6 D5 D4 D3 D2 D1 D0

N/A N/A N/A 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

D0 1 when Internal Temp Value exceeds T D1 1 when Internal Temp Value exceeds T D2 1 when External Temp Value exceeds T D3 1 when External Temp Value exceeds T

HIGH

LOW

HIGH

LOW

limit

D4 1 indicates a fault (open or short) for the external

temperature sensor.

Interrupt Status 2 Register (Read only) [Add. = 01h]

This 8-bit read only register reflects the status of the V

interrupt that can cause the INTERRUPT pin to go active. This register is reset by a read operation or by a software reset.

Table 8. Interrupt Status 1 Register

D7 D6 D5 D4 D3 D2 D1 D0

N/A N/A N/A 0* N/A N/A N/A N/A

*Default settings at Power-up.

EXTERNAL TEMPERATURE VALUE REGISTER LSBS (Read only) [Add. = 04h]

This External Temperature Value is a 8-bit read-only register. It stores the two LSBs of the 10-bit temperature reading from the external temperature sensor.

Table 10. External Temperature LSBs

D7 D6 D5 D4 D3 D2 D1 D0

N/A N/A N/A N/A N/A N/A T1 LSB N/A N/A N/A N/A N/A N/A 0* 0*

*Default settings at Power-up.

Bit Function

D0 LSB of External Temperature Value D1 B1 of External Temperature Value

VDD VALUE REGISTER MSBS (Read only) [Add. = 06h]

This 8-bit read only register stores the supply voltage value. The 8 MSBs of the 10-bit value are stored in this register.

Table 11. VDD Value MSBs

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ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

D7 D6 D5 D4 D3 D2 D1 D0

V9 V8 V7 V6 V5 V4 V3 V2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

INTERNAL TEMPERATURE VALUE REGISTER MSBS (Read only) [Add. = 07h]

This 8-bit read only register stores the Internal Temperature value from the internal temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register.

Table 12. Internal Temperature Value MSBs

D7 D6 D5 D4 D3 D2 D1 D0

T9 T8 T7 T6 T5 T4 T3 T2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

EXTERNAL TEMPERATURE VALUE REGISTER MSBS (Read only) [Add. = 08h]

This 8-bit read only register stores the External Temperature value from the external temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register.

Table 13. External Temperature Value MSBs

DAC A REGISTER MSBS (Read/Write) [Add. = 11h]

This 8-bit read/write register contains the 8 MSBs of the DAC A word. The value in this register is combined with the value in the DAC A Register LSBs and converted to an analog voltage on the V voltage output on the V

Table 16. DAC A MSBs

A pin. On power-up the

OUT

A pin is 0 V.

OUT

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

DAC B REGISTER LSBS (Read/Write) [Add. = 12h]

This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC B word respectivily. The value in this register is combined with the value in the DAC B Register MSBs and converted to an analog voltage on the

B pin. On power-up the voltage output on the V

OUT

pin is 0 V.

Table 17. DAC B (ADT7316) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B3 B2 B1 LSB N/A N/A N/A N/A 0* 0* 0* 0* N/A N/A N/A N/A

*Default settings at Power-up.

D7 D6 D5 D4 D3 D2 D1 D0

T9 T8 T7 T6 T5 T4 T3 T2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

DAC A REGISTER LSBS (Read/Write) [Add. = 10h]

This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC A word respectivily. The value in this register is combined with the value in the DAC A Register MSBs and converted to an analog voltage on the

A pin. On power-up the voltage output on the V

OUT

pin is 0 V.

Table 14. DAC A (ADT7316) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B3 B2 B1 LSB N/A N/A N/A N/A 0* 0* 0* 0* N/A N/A N/A N/A

*Default settings at Power-up.

Table 15. DAC A (ADT7317) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B2 LSB N/A N/A N/A N/A N/A N/A 0* 0* N/A N/A N/A N/A N/A N/A

*Default settings at Power-up.

Table 18. DAC B (ADT7317) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B2 LSB N/A N/A N/A N/A N/A N/A 0* 0* N/A N/A N/A N/A N/A N/A

*Default settings at Power-up.

DAC B REGISTER MSBS (Read/Write) [Add. = 13h]

This 8-bit read/write register contains the 8 MSBs of the DAC B word. The value in this register is combined with the value in the DAC B Register LSBs and converted to an analog voltage on the V voltage output on the V

Table 19. DAC B MSBs

B pin. On power-up the

OUT

B pin is 0 V.

OUT

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

DAC C REGISTER LSBS (Read/Write) [Add. = 14h]

This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC C word respectivily. The value in this register is combined with the value in the DAC C Register MSBs and converted to an analog voltage on the

C pin. On power-up the voltage output on the V

OUT

pin is 0 V.

–22– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

Table 20. DAC C (ADT7316) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B3 B2 B1 LSB N/A N/A N/A N/A 0* 0* 0* 0* N/A N/A N/A N/A

*Default settings at Power-up.

Table 21. DAC C (ADT7317) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B2 LSB N/A N/A N/A N/A N/A N/A 0* 0* N/A N/A N/A N/A N/A N/A

*Default settings at Power-up.

DAC C REGISTER MSBS (Read/Write) [Add. = 15h]

This 8-bit read/write register contains the 8 MSBs of the DAC C word. The value in this register is combined with the value in the DAC C Register LSBs and converted to an analog voltage on the V voltage output on the V

Table 22. DAC C MSBs

C pin. On power-up the

OUT

C pin is 0 V.

OUT

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

DAC D REGISTER LSBS (Read/Write) [Add. = 16h]

This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC D word respectivily. The value in this register is combined with the value in the DAC D Register MSBs and converted to an analog voltage on the

D pin. On power-up the voltage output on the V

OUT

pin is 0 V.

Table 23. DAC D (ADT7316) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B3 B2 B1 LSB N/A N/A N/A N/A 0* 0* 0* 0* N/A N/A N/A N/A

*Default settings at Power-up.

Table 24. DAC D (ADT7317) LSBs

D7 D6 D5 D4 D3 D2 D1 D0

B2 LSB N/A N/A N/A N/A N/A N/A 0* 0* N/A N/A N/A N/A N/A N/A

*Default settings at Power-up.

DAC D REGISTER MSBS (Read/Write) [Add. = 17h]

This 8-bit read/write register contains the 8 MSBs of the DAC D word. The value in this register is combined with the value in the DAC D Register LSBs and converted to an analog voltage on the V voltage output on the V

OUT

D pin. On power-up the

OUT

D pin is 0 V.

Table 25. DAC D MSBs

D7 D6 D5 D4 D3 D2 D1 D0

MSB B8 B7 B6 B5 B4 B3 B2 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

CONTROL CONFIGURATION 1 REGISTER (Read/ Write) [Add. = 18h]

This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18.

Table 26. Control Configuration 1

D7 D6 D5 D4 D3 D2 D1 D0

PD C6 C5 C4 C3 C2 C1 C0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

C0 This bit enables/disables conversions in Round

Robin mode. ADT7316/17/18 powers up in Round Robin mode but monitoring is not initiated until this bit is set. Default = 0. 0 = Disable Round Robin monitoring.

1 = Enable Round Robin monitoring. C1:4 RESERVED. Only write 0’s. C5 0 Enable INTERRUPT

1 Disable INTERRUPT C6 Configures INTERRUPT output polarity.

0 Active low

1 Active High C7 Power-down Bit. Setting this bit to 1 puts the

ADT7316/17/18 into standby mode. In this

mode both ADC and DACs are fully powered

down, but serial interface is still operational. To

power up the part again just write 0 to this bit

CONTROL CONFIGURATION 2 REGISTER (Read/ Write) [Add. = 19h]

This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18.

Table 27. Control Configuration 2

D7 D6 D5 D4 D3 D2 D1 D0

C7 C6 C5 C4 C3 C2 C1 C0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

–23–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

C2:0 In single channel mode these bits select between

, the internal temperature sensor and the

external temperature sensor for conversion. De-

fault is V 000 = V 001 = Internal Temperature Sensor. 010 = External Temperature Sensor

011 - 111 = RESERVED C3 RESERVED C4 Selects between single channel and Round Robin

conversion cycle. Default is Round Robin.

0 = Round Robin.

1 = Single Channel. C5 Default condition is to average every measure-

ment on all channels 16 times. This bit disables

this averaging. Channels consist of temperature,

analog inputs and VDD.

0 = Enable averaging.

1 = Disable averaging. C6 SMBus timeout on the serial clock puts a max

limit on the pulse width of the clock. Ensures

that a fault on the master SCL does not lock up

the SDA line.

0 = Disable SMBus Timeout.

1 = Enable SMBus Timeout. C7 Software Reset. Setting this bit to a 1 causes a

software reset. All registers and DAC outputs

will reset to their default settings.

CONTROL CONFIGURATION 3 REGISTER (Read/ Write) [Add. = 1Ah]

This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18.

Table 28. Control Configuration 3

D7 D6 D5 D4 D3 D2 D1 D0

C7 C6 C5 C4 C3 C2 C1 C0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

C0 Selects between fast and normal ADC conver-

sion speeds for all three monitoring channels.

0 = ADC clock at 1.4 KHz.

1 = ADC clock at 22.5 KHz. C1 On the ADT7316 and ADT7317, this bit selects

between 8 bits and 10 bits DAC output resolu-

tion on the Thermal Voltage Output feature.

Default = 8 bits. This bit has no affect on the

ADT7318 output as this part has only an 8-bit

DAC. In the ADT7318 case, write 0 to this bit.

0 = 8 bits resolution.

1 = 10 bits resolution. C2 RESERVED. Only write 0’s.

C3 0 = LDAC pin controls updating of DAC out-

puts. 1 = DAC Configration register and LDAC Configuration register control updating of DAC

outputs. C4 RESERVED. Only write 0. C5 Setting this bit selects DAC A voltage output to

be proportional to the internal temperature mea-

surement. C6 Setting this bit selects DAC B voltage output to

be proportional to the external temperature mea-

surement. C7 RESERVED. Only write 0.

DAC CONFIGURATION REGISTER (Read/Write) [Add. = 1Bh]

This configuration register is an 8-bit read/write register that is used to control the output ranges of all four DACs and also to control the loading of the DAC registers if the LDAC pin is disabled (bit C3 = 1, Control Configuration 3 register).

Table 29. DAC Configuration

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

D0 Selects the output range of DAC A.

0 = 0 V to V

1 = 0 V to 2V

REF

D1 Selects the output range of DAC B.

0 = 0 V to V

1 = 0 V to 2V

REF

D2 Selects the output range of DAC C.

0 = 0 V to V

1 = 0 V to 2V

REF

D3 Selects the output range of DAC D.

0 = 0 V to V

1 = 0 V to 2V

REF

D5:D4 00 MSB write to any DAC register generates

LDAC command which updates that DAC only.

01 MSB write to DAC B or DAC D register

generates LDAC command which updates DACs A, B or DACs C, D.

10 MSB write to DAC D register generates

LDAC command which updates all 4 DACs.

11 LDAC command generated from LDAC

–24– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

D6 Setting this bit allows the external V

to bypass

REF

the reference buffer when supplying DACs A and B.

D7 Setting this bit allows the external V

to bypass

REF

the reference buffer when supplying DACs C and D.

LDAC CONFIGURATION REGISTER (Write only) [Add. = 1Ch]

This configuration register is an 8-bit write register that is used to control the updating of the quad DAC outputs if the LDAC pin is disabled and Bits 4 and 5 of DAC Configuration register are both set to 1. Also selects V

REF

for all four DACs. All of the bits in this register are self clearing i.e. reading back from this register will always give 0’s.

Table 30. LDAC Configuration

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

D0 Writing a 1 to this bit will generate the LDAC

command to update DAC A output only.

D1 Writing a 1 to this bit will generate the LDAC

command to update DAC B output only.

D2 Writing a 1 to this bit will generate the LDAC

command to update DAC C output only.

D3 Writing a 1 to this bit will generate the LDAC

command to update DAC D output only.

D4 Selects either internal or external V

REF

AB for DACs A and B. 0 = External V 1 = Internal V

D5 Selects either internal or external V

REF

CD for

REF

DACs C and D. 0 = External V 1 = Internal V

REF

D6:D7 RESERVED. Only write 0’s.

INTERRUPT MASK 1 REGISTER (Read/Write) [Add. = 1Dh]

This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can can cause the INTERRUPT pin to go active.

*Default settings at Power-up.

Bit Function

D0 0 = Enable internal T

1 = Disable internal T

D1 0 = Enable internal T

1 = Disable internal T

D2 0 = Enable external T

1 = Disable external T

D3 0 = Enable external T

1 = Disable external T

interrupt.

HIGH

interrupt.

HIGH

interrupt.

LOW

interrupt.

LOW

interrupt.

HIGH

interrupt.

HIGH

interrupt.

low

interrupt.

low

D4 0 = Enable external temperature fault interrupt.

1 = Disable external temperature fault interrupt.

D5:D7 RESERVED. Only write 0’s.

INTERRUPT MASK 2 REGISTER (Read/Write) [Add. = 1Eh]

This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can can cause the INTERRUPT pin to go active.

Table 32. Interrupt Mask 2

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

Bit Function

D0:D3 RESERVED. Only write 0’s. D4 0 = Enable V

interrupts.

1 = Disable VDD interrupts.

D5:D7 RESERVED. Only write 0’s.

INTERNAL TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 1Fh]

This register contains the Offset Value for the Internal Temperature Channel. A 2's complement number can be written to this register which is then 'added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register the temperature resolution is 1

Table 31. Interrupt Mask 1

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

Table 33. Internal Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

–25–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

EXTERNAL TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 20h]

Table 34. External Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

INTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 21h]

This register contains the Offset Value for the Internal Thermal Voltage output. A 2's complement number can be written to this register which is then 'added' to the measured result before it is converted by DAC A. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128

+127

C. In essence this register changes the position of 0V on the temperature scale. Anything other than -128 to +127 output. As it is an 8-bit register the temperature resolution is 1

C will produce an upper deadband on the DAC A

C. Default value is -40oC.

C to +127oC or even 0oC to

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 1* 1* 0* 0* 0*

*Default settings at Power-up.

VDD V

LIMIT REGISTER (Read/Write) [Add. = 23h]

HIGH

This limit register is an 8-bit read/write register which stores the V

upper limit that will cause an interrupt and

activate the INTERRUPT output (if enabled). For this to happen the measured V

value has to be greater than the

value in this register. Default value is 5.5 V.

Table 37. VDD V

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 0* 1* 0* 0* 1*

*Default settings at Power-up.

VDD V

LIMIT REGISTER (Read/Write) [Add. = 24h]

LOW

This limit register is an 8-bit read/write register which stores the V

lower limit that will cause an interrupt and

activate the INTERRUPT output (if enabled). For this to happen the measured V

value has to be less than the

value in this register. Default value is 2.7 V.

Table 38. VDD V

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 1* 1* 0* 0* 0* 1* 0*

*Default settings at Power-up.

Table 35. Internal Analog Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 1* 1* 0* 0* 0*

*Default settings at Power-up.

EXTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write)[Add. = 22h]

This register contains the Offset Value for the External Thermal Voltage output. A 2's complement number can be written to this register which is then 'added' to the measured result before it is converted by DAC B. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128

+127

C. In essence this register changes the position of 0V on the temperature scale. Anything other than -128 to +127 output. As it is an 8-bit register the temperature resolution is 1

C will produce an upper deadband on the DAC B

C. Default value is -40oC.

C to +127oC or even 0oC to

Table 36. External Analog Temperature Offset

INTERNAL T

LIMIT REGISTER (Read/Write) [Add.

HIGH

= 25h]

This limit register is an 8-bit read/write register which stores the 2’s complement of the internal temperature upper limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured Internal Temperature Value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1

Table 39. Internal T

C. Default value is +100oC.

Limit

HIGH

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0* 1* 1* 0* 0* 1* 0* 0*

*Default settings at Power-up.

INTERNAL T

LIMIT REGISTER (Read/Write) [Add.

LOW

26h]

This limit register is an 8-bit read/write register which stores the 2’s complement of the internal temperature lower limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured Internal Temperature Value has to be more

–26– REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

negative than the value in this register. As it is an 8-bit register the temperature resolution is 1

-55

Table 40. Internal T

C. Default value is

Limit

LOW

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 0* 0* 1* 0* 0* 1*

*Default settings at Power-up.

EXTERNAL T

LIMIT REGISTER (Read/Write) [Add.

HIGH

= 27h]

If pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write register which stores the 2’s complement of the external temperature upper limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured External Temperature Value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1

Table 41. External T

HIGH

Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 1* 1* 1* 1* 1* 1* 1* 1*

*Default settings at Power-up.

EXTERNAL T

LIMIT REGISTER (Read/Write) [Add.

LOW

= 28h]

If pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write register which stores the 2’s complement of the external temperature lower limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured External Temperature Value has to be more negative than the value in this register. As it is an 8-bit register the temperature resolution is 1

Table 42. External T

LOW

Limit

D7 D6 D5 D4 D3 D2 D1 D0

SCL

SDA

START BY

MASTER

191

0 0 1 A2A1A0 P7P6P5P4P3P2P1

FRAME 1

SERIAL BUS ADDRESS B YTE

ACK. BY

ADT7316/17/18

ADDRESS POINTER REGISTER BYTE

FRAME 2

ACK. BY

ADT7316/17/18

STOP BY MASTER

Figure 17. I2C - Writing to the Address Pointer Register to select a register for a subsequent Read operation

191

SCL

SDA 0 0 1 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESSBYTE

SCL (CONTINUED)

ACK.BY

ADT7316/17/18

ADDRESS POINTER REGISTER BYTE

FRAME 2

ACK. BY

ADT7316/17/18

SDA (CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ADT7316/17/18

ACK. BY

STOP BY MASTER

Figure 18. I2C - Writing to the Address Pointer Register followed by a single byte of data to the selected register

–27–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at Power-up.

DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]

This 8-bit read only register indicates which part the device is in the model range. ADT7316 = 01h, ADT7317 = 05h and ADT7318 = 09h.

MANUFACTURER’S ID REGISTER (Read only) [Add. = 4Eh]

This register contains the manufacturers identification number. ADI’s is 41h.

SILICON REVISION REGISTER (Read only) [Add. = 4Fh]

This register is divided into the four lsbs representing the Stepping and the four msbs representing the Version. The Stepping contains the manufacturers code for minor revisions or steppings to the silicon. The Version is the

191 9

SCL

ADT7316/17/18 version number. The ADT7316/17/18’s version number is 0000b.

ADT7316/7317/7318 SERIAL INTERFACE

There are two serial interfaces that can be used on this

part, I

C and SPI. A valid serial communication protocol

selects the type of interface.

SERIAL INTERFACE SELECTION

The CS line controls the selection between I2C and SPI. If CS is held high during a valid I

the serial interface selects the I

C communication then

C mode once the correct serial bus address has been recognised. To set the interface to SPI mode the CS line must be low during a valid SPI communication. This will cause the interface to select the SPI mode once the correct read or write command has been recognised. As per most SPI standards the CS line must be low during every SPI communication to the ADT7316/17/18 and high all other times.

SDA

START BY

MASTER

SCLK

START

FRAME 1

SERIAL BUS ADDRESS BYTE

A0A1A2101

ADT7316/17/18

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

SINGLE DATA B YTE FROM A DT7316/17/18

FRA ME 2

Figure 19. I2C - Reading a single byte of data from a selected register

1818

D6 D5

WRITE COMMAND

CS( CONTINUED)

SCLK (CONTINUED)

D4 D3

NO ACK.BY

MASTER

STOP BY MASTER

DIN(CONTINUED)

D5 D4

DATA BYTE

Figure 20. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register

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PRELIMINARY TECHNICAL D A T A

The following sections describe in detail how to use these interfaces.

I2C SERIAL INTERFACE

Like all I2C-compatible devices, the ADT7316/7317/7318 has an 7-bit serial address. The four MSBs of this address for the ADT7316/7317/7318 are set to 1001. The three LSBs are set by pin 11, ADD. The ADD pin can be configured three ways to give three different address options; low, floating and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011.

There is a programmable SMBus timout. When this is enabled the SMBus will timeout after 25 ms of no activity. To enable it, set Bit 6 of Control Configuration 2 register. The power-up default is with the SMBus timeout disabled.

The ADT7316/17/18 supports SMBus Packet Error Checking (PEC) and it’s use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC is calculated using CRC-8. The Frame Clock Sequence (FCS) conforms to CRC-8 by the polynominal :

C(x) = x8 + x2 + x1 + 1

Consult SMBus specification for more information.

ADT7316/7317/7318

data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device.

2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal.

3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will pull the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition.

Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device.

The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle whilst the selected device waits for

SCLK

D6 D5

START

WRITE COMMAND

WRITING TO THE ADT7316/7317/7318

Depending on the register being written to, there are two different writes for the ADT7316/7317/7318. It is not possible to do a block write to this part i.e no I

C auto-

increment.

Writing to the Address Pointer Register for a subsequent read.

In order to read data from a particular register, the Address Pointer Register must contain the address of that register. If it does not, the correct address must be written to the Address Pointer Register by performing a singlebyte write operation, as shown in Figure 17. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation is then performed to read the register.

STOP

D4 D3

Figure 21. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation

–29–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

Writing data to a Register.

All registers are 8-bit registers so only one byte of data can be written to each register. Writing a single byte of data to one of these Read/Write registers consists of the serial bus address, the data register address written to the Address Pointer Register, followed by the data byte written to the selected data register. This is illustrated in Figure

18. To write to a different register, another START or repeated START is required. If more than one byte of data is sent in one communication operation, the addressed register will be repeately loaded until the last data byte has been sent.

READING DATA FROM THE ADT7316/7317/7318

Reading data from the ADT7516/7517/7518 is done in a one byte operation. Reading back the contents of a register is shown in Figure 19. The register address previously

1818

SCLK

D6 D5

D7D

having been set up by a single byte write operation to the Address Pointer Register. If you want to read from another register then you will have to write to the Address Pointer Register again to set up the relevant register address. Thus block reads are not possible i.e. no I2C auto-increment.

SPI SERIAL INTERFACE

The SPI serial interface of the ADT7316/7317/7318 consists of four wires, CS, SCLK, DIN and DOUT. The CS is used to select the device when more than one device is connected to the serial clock and data lines. The SCLK is used to clock data in and out of the part. The DIN line is used to write to the registers and the DOUT line is used to read data back from the registers.

The part operates in a slave mode and requires an externally applied serial clock to the SCLK input. The serial

XD0

OUT

SCLK

OUT

START

READ COMMAND

X X X D6D5D4D3D2D1D0

XD7

DATA B YTE 1

Figure 22. SPI - Reading a single byte of data from a selected register

D6 D5

D7D

READ COMMAND

X X X D6D5D4D3D2D1D0

CS (CONTINUED)

SCLK (CONTINUED)

XD7

DATA BYTE 1

STOP

XD0

(CONTINUED)

OUT

XXXXXXXX

D5 D4

DATA BYTE 2

Figure 23. SPI - Reading a two bytes of data from two sequential registers

–30– REV. PrN

D0D

STOP

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data.

There are two types of serial operations, a read and a write. Command words are used to distinguish between a read and a write operation. These command words are given in Table 43. Address auto-increment is possible in SPI mode

Table 43. SPI COMMAND WORDS

WRITE READ

90h (1001 0000) 91h (1001 0001)

Write Operation

Figures 20 and 21 show the timing diagrams for a write operation to the ADT7316/7317/7318. Data is clocked into the registers on the rising edge of SCLK. When the CS line is high the DIN and DOUT lines are in threestate mode. Only when the CS goes from a high to a low does the part accept any data on the DIN line. In SPI mode the Address Pointer Register is capable of autoincrementing to the next register in the register map without having to load the Address Pointer register each time. In Figure 20 the register address portion of the diagram gives the first register that will be written to. Subsequent data bytes will be written into sequential writable registers. Thus after each data byte has been written into a register, the Address Pointer Register auto increments it’s value to the next available register. The Address Pointer Register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.

Read Operation

Figures 22 and 23 show the timing diagrams necessary to accomplish correct read operations. To read back from a register you first have to write to the Address Pointer Register with the address of the register you wish to read from. This operation is shown in Figure 21. Figure 22 shows the procedure for reading back a single byte of data. The read command is first sent to the part during the first 8 clock cycles, during the following 8 clock cycles the data contained in the register selected by the Address Pointer register is outputted onto the DOUT line. Data is outputted onto the DOUT line on the falling edge of SCLK. Figure 23 shows the procedure when reading data from two sequential registers. Multiple data reads are possible in SPI interface mode as the Address Pointer Register is auto-incremental. The Address Pointer Register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.

The INTERRUPT pin has an open-drain configuration which allows the outputs of several devices to be wiredAND together when the INTERRUPT pin is active low. Use D6 of the Control Configuration 1 Register to set the active polarity of the INTERRUPT output. The power-up default is active low. The INTERRUPT function can be disabled or enabled by setting D5 of Control Configuration 1 Register to a 1 or 0 respectively.

The INTERRUPT output becomes active when either the Internal Temperature Value, the External Temperature Value or the V sponding T TERRUPT output goes inactive again when a conversion result has the measured value back within the trip limits.

The INTERRUPT output requires an external pull-up resistor. This can be connected to a voltage different from V

provided the maximum voltage rating of the INTER-

RUPT output pin is not exceeded. The value of the pullup resistor depends on the application, but should be as large enough to avoid excessive sink currents at the INTERRUPT output, which can heat the chip and affect the temperature reading.

Value exceed the values in their corre-

HIGH/VHIGH

or T

LOW/VLOW

Registers. The IN-

SMBUS/SPI INTERRUPT

The ADT7316/17/18 INTERRUPT output is an interrupt line for devices that want to trade their ability to master for an extra pin. The ADT7316/17/18 is a slave only device and uses the SMBus/SPI INTERRUPT to signal the host device that it wants to talk. The SMBus/SPI INTERRUPT on the ADT7316/17/18 is used as an over/under limit indicator.

–31–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

Outline Dimensions

(Dimensions shown in inches and mm )

16-Lead QSOP Package

( RQ-16 )

0.197 (5.00)

0.189 (4.80)

16 9

0.157 (3.99)

0.150 (3.81)

0.244 (6.20)

0.228 (5.79)

0.059 (1.50)

0.010 (0.25)

0.004 (0.10)

MAX

PIN1

0.025 (0.64)

BSC

0.069 (1.75)

0.053 (1.35)

0.012 (0.30)

0.008 (0.20)

SEATING PLANE

0.010 (0.20)

0.007 (0.18)

–32– REV. PrN

Datasheet ADT7318ARQ, ADT7317ARQ, ADT7316ARQ Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

ORDERING GUIDE

TERMINOLOGY RELATIVE ACCURACY

DIFFERENTIAL NONLINEARITY

OFFSET ERROR

OFFSET ERROR MATCH

GAIN ERROR

GAIN ERROR MATCH

OFFSET ERROR DRIFT

GAIN ERROR DRIFT

DC POWER-SUPPLY REJECTION RATIO (PSRR)

DC CROSSTALK

REFERENCE FEEDTHROUGH

CHANNEL-TO-CHANNEL ISOLATION

MAJOR-CODE TRANSITION GLITCH ENERGY

DIGITAL FEEDTHROUGH

DIGITAL CROSSTALK

ANALOG CROSSTALK

DAC-TO-DAC CROSSTALK

MULTIPLYING BANDWIDTH

TOTAL HARMONIC DISTORTION

ROUND ROBIN

FUNCTIONAL DESCRIPTION - DAC

FUNCTIONAL DESCRIPTION

POWER-UP TIME

TEMPERATURE SENSOR

VDD MONITORING

ON-CHIP REFERENCE

ROUND ROBIN MEASUREMENT

SINGLE CHANNEL MEASUREMENT

MEASUREMENT METHOD

LAYOUT CONSIDERATIONS

TEMPERATURE VALUE FORMAT

INTERRUPTS

THERMAL VOLTAGE OUTPUT

ADT7316/7317/7318 REGISTERS

DAC B REGISTER LSBS (Read/Write) [Add. = 12h]

DAC A REGISTER LSBS (Read/Write) [Add. = 10h]

DAC B REGISTER MSBS (Read/Write) [Add. = 13h]

DAC C REGISTER MSBS (Read/Write) [Add. = 15h]

DAC D REGISTER LSBS (Read/Write) [Add. = 16h]

CONTROL CONFIGURATION 2 REGISTER (Read/ Write) [Add. = 19h]

INTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 21h]

DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]

ADT7316/7317/7318 SERIAL INTERFACE

SERIAL INTERFACE SELECTION

I2C SERIAL INTERFACE

WRITING TO THE ADT7316/7317/7318

READING DATA FROM THE ADT7316/7317/7318

SPI SERIAL INTERFACE

SMBUS/SPI INTERRUPT