Page 1
LCD Level Shifters with VCOM,
NRS Buffers, and High Voltage Edge Detector
FEATURES
Complete suite of level shifters
Eight inverting and three complementary level shifters for
LCD timing
High voltage edge detector
Integrated low offset buffer for VCOM drives high capacitive
loads
MUXed input, low offset buffer for 2-level precharge drives
high capacitive loads
High current buffer for precharge provides high current
drive into large capacitive loads
Low power dissipation: 576 mW
Available in 48-lead 7 mm × 7 mm LFCSP E-pad
PRODUCT DESCRIPTION
The ADSY8401 provides fast, 3 V to 15 V level shifters for LCD
panel timing signals. An integrated low offset analog buffer is
capable of driving the high capacitive loads. A 2:1 MUX input,
low offset buffer simplifies application of 2-level precharge
signals. A high current buffer provides high slew rates for large
capacitive loads.
The ADSY8401 is fabricated on ADI’s fast, 26 V XFHV process,
providing fast input logic, high voltage level shifters, and
precision drive amplifiers on the same chip.
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DTCTI
AMPI
SEL
MUXA
MUXB
ADSY8401
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCCL AVCC
ADSY8401
8
3
R
S
+1
+1
8
3
3
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9T
DO10T
DO11T
DO9C
DO10C
DO11C
DTCTO
AMPO
MUXO
The ADSY8401 dissipates 576 mW nominal static power.
The ADSY8401 is offered in a 48-lead 7 mm × 7 mm LFCSP
E-pad package and operates over the commercial temperature
range of 0°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
BFRI
GSW
DGND AGNDL AGND
+1
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
BFRO
04758-0-001
Page 2
ADSY8401
TABLE OF CONTENTS
Specifications..................................................................................... 3
Applications..................................................................................... 11
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Amplifier Applications..................................................................... 8
Amp Section as VCOM Buffer ................................................... 8
MUX and BFR Sections as NRS Buffer ..................................... 8
MUX Section as VCOM Buffer .................................................. 8
Level Shifter Characteristics............................................................ 9
Level Shifter Timing Characteristics ......................................... 9
Inverting and Complementary Level Shifter Timing.............. 9
Level Shifting Edge Detector Timing Characteristics ........... 10
Level Shifting Edge Detector Timing ...................................... 10
REVISION HISTORY
AMP Channel ............................................................................. 11
MUX Channel............................................................................. 11
Driving NRS................................................................................ 11
BFR Channel ............................................................................... 11
Grounded Output Mode ........................................................... 11
Driving VCOM........................................................................... 11
PCB Design for Optimized Thermal Performance ............... 13
Power Supply Sequencing ......................................................... 14
Layout Considerations............................................................... 14
Tot a l Po w er D is s ip a ti o n ............................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Page 3
ADSY8401
SPECIFICATIONS
At 25°C, AVCC = AVCCL = 15.5 V, DVCC = 3.3 V, TA min = 0°C, TA max = 85°C, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
Amp Section
INPUT/OUTPUT CHARACTERISTICS
Voltage Range
V
H
V
L
Output Voltage Grounded Mode GSW = LOW 45 mV
Input Current 100 nA
Output Current 20 mA
Output Offset Voltage VAMPI = 6 V, TA = 25°C 1.5 8 mV
Output Offset Voltage VAMPI = 6 V, TA min to TA max 11 mV
PSRR AVCC ± 10%, TA min to TA max 0.1 mV/V
Gain Error
OUTPUT DYNAMIC PERFORMANCE
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 5.2 MHz
Slew Rate 13 V/µs
Settling Time to 0.5% TA min to TA max 0.5 1 µs
Overshoot 0.05 %
MUX Section
INPUT/OUTPUT CHARACTERISTICS
Voltage Range
V
H
V
L
Output Voltage Grounded Mode GSW = LOW 45 mV
Input Current
II MUXA, MUXB 100 nA
Output Current 20 mA
Output Offset Voltage VMUXA, B = 7.5 V, TA = 25°C 1.5 8 mV
Output Offset Voltage VMUXA, B = 7.5 V, TA min to TA max 11 mV
PSRR AVCC ± 10%, TA min to TA max 0.1 mV/V
Gain Error
SEL INPUT CHARACTERISTICS
IIH SEL 0.05 µA
IIL SEL −0.7 µA
VTH SEL 1.65 V
VIH SEL 2 V
VIL SEL 0.8 V
OUTPUT DYNAMIC PERFORMANCE VO = 5 V step, CL = 1 nF
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 5.2 MHz
Slew Rate 13 V/µs
Settling Time to 0.5% TA min to TA max 0.5 1 µs
Overshoot 0.05 %
OUTPUT DYNAMIC PERFORMANCE VO = 5 V step, CL = 15 pF
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 27 MHz
Slew Rate 13 V/µs
Settling Time to 0.5% TA min to TA max 0.4 0.7 µs
Overshoot
AVCC − V
H
1.5 2.5 V
VL − AGND 1.1 1.5 V
VAMPI = 3 V to 10 V, TA min to TA max
TA min to TA max, VO = 5 V step, CL = 1 nF
0.07 0.12 %
AVCC − V
H
1.5 2.5 V
VL − AGND 1.1 1.5 V
VMUXA, B 1.5 V to 12 V, TA min to TA max
0.07 0.12 %
0.1
%
Rev. 0 | Page 3 of 16
Page 4
ADSY8401
Parameter Conditions Min Typ Max Unit
BFR Section
INPUT/OUTPUT CHARACTERISTICS
Voltage Range
V
H
V
L
Output Voltage Grounded Mode GSW = LOW 90 mV
Input Current 0.3 µA
Output Current 100 mA
Output Offset Voltage BFRI = 7.5 V, TA = 25°C 6 20 mV
Output Offset Voltage BFRI = 7.5 V, TA min to TA max 30 mV
PSRR, TA min to TA max AVCC ± 10% 1 mV/V
Gain Error, TA min to TA max BFRI = 1.5 V to 12 V 0.5 0.65 %
OUTPUT DYNAMIC PERFORMANCE VO = 6 V step, CL = 10 nF
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 1.3 MHz
Slew Rate 12 V/µs
Settling Time to 0.5% TA min to TA max 0.7 1 µs
Overshoot 0.3 %
MUX and BFR Sections as NRS Buffer
Settling Time to 0.5% CL = 10 nF 0.9 1.5 µs
Level Shifter Section
LEVEL SHIFTER LOGIC INPUTS
C
IN
I
IH
I
IL
V
IH
V
IL
V
TH
LEVEL SHIFTER OUTPUTS
V
OH
V
OL
LEVEL SHIFTER DYNAMIC PERFORMANCE TA min to TA max
Output Rise, Fall Times, tr, tf 10% to 90%
DO1–DO8, DO9T–DO11T, DO9C–DO11C CL = 40 pF 20 30 ns
DO1–DO8 CL = 300 pF 130 150 ns
Propagation Delay times, t11, t12, t13, t
14
DO1–DO8, DO9T–DO11T, DO9C–DO11C CL = 40 pF 23 50 ns
DO1–DO8 CL = 300 pF 60 80 ns
Propagation Delay Skew, t15, t
16
DO1–DO8 2 ns
Propagation Delay Skew, t15, t16, t17, t
18
DO1–DO8, DO9T–DO11T, DO9C–DO11C 4 ns
AVCC − VH 1.5 2.5 V
VL − AGND 1.1 1.5 V
See Figure 4
3 pF
0.05 µA
−0.6 µA
2 V
0.8 V
1.65 V
AVCCL − 0.5 AVCCL − 0.25
V
0.25 0.5 V
CL = 40 pF
CL = 40 pF
Rev. 0 | Page 4 of 16
Page 5
ADSY8401
Parameter Conditions Min Typ Max Unit
= 10 pF
Level Shifting Edge Detector Section
Input Low Voltage, V
Input High Voltage, V
IL
IH
Input Rising Edge Threshold Voltage, VTH LH AGND + 3 V
Input Falling Edge Threshold Voltage, VTH HL AVCC − 3 V
Output High Voltage, V
Output Low Voltage, V
Input Current High State, I
Input Current, I
IL
OH
OL
IH
Input Rising Edge Propagation Delay Time, t
Input Falling Edge Propagation Delay Time, t20 16.5 ns
t20 Variation with Temperature, ∆t20
Output Rise, Fall Time, t
r
Grounded-Mode Switch
GSW INPUT CHARACTERISTICS
C
IN
R
IN
I
IH
I
IL
V
IH
V
IL
V
TH
Power Supplies
Operating Range, DVCC 3 3.3 3.6 V
Quiescent Current, DVCC 20 25 mA
Operating Range, AVCC, AVCCL1, 2, 3 18 V
Quiescent Current, AVCCL1 12.5 15.5 mA
Quiescent Current, AVCCL2
Quiescent Current, AVCCL3
Quiescent Current, AVCCL2
Quiescent Current, AVCCL3
Quiescent Current, AVCC 10 12.8 mA
Operating Temperature
Ambient Temperature Range, T
A
C
L
AVCC − 1.5
V
DVCC − 0.5 DVCC − 0.25
AGND + 1.5
V
V
0.25 0.5 V
1.2 2.5 µA
15.5 ns
19
T
= 25°C to 85°C 2 ns
A
−
2.5
−
1.2 µA
10% to 90% 6 ns
3 pF
50 kΩ
0.6 µA
−70 µA
2 V
0.8 V
1.65 V
DI1 − DI11 ≤ V
DI1 − DI11 ≤ V
DI1 − DI11 ≥ V
DI1 − DI11 ≥ V
IL
IL
IH
IH
5.2 6.6 mA
5.2 6.6 mA
11.5 14.3 mA
11.5 14.3 mA
In still air 0 85 °C
Rev. 0 | Page 5 of 16
Page 6
ADSY8401
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Rating
Supply Voltages
AVCC to AGND 18 V
AVCCL to AGNDL 18 V
AGND to AGNDL ±0.5 V
AGND to DGND ±0.5 V
DVCC to DGND 4.5 V
Input Voltages
Maximum Digital Input Voltages DVCC + 0.5 V
Minimum Digital Input Voltages DGND − 0.5 V
Maximum Analog Input Voltages AVCCx + 0.5 V
Minimum Analog Input Voltages AGNDx − 0.5 V
Internal Power Dissipation
LFCSP Package at 25°C, Ambient 3.8 W
Operating Temperature Range 0°C to 85°C
Storage Temperature Range −65°C to +125°C
Lead Temperature Range (Soldering 10 s) 300°C
1
1
48-lead LFCSP package:
= 26°C/W (still air): JEDEC STD, 4-layer PCB, 0 CFM airflow
θ
JA
= 20°C/W
θ
JC
ΨJB =11.0°C/W (still air)
=0.4°C/W (still air)
Ψ
JT
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
Junction Temperature
The maximum power that can be safely dissipated by the
ADSY8401 is limited by its junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices as determined by the glass transition temperature of the
plastic is approximately 150°C. Exceeding this limit temporarily
might cause a shift in the parametric performance due to a
change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 150°C for an extended
period can result in device failure.
Exposed Paddle
The die paddle must be in good thermal contact with at least a
partial plane for proper operation in high ambient temperature
environments. The partial plane must be in good electrical
contact with AVCC or AGND for reliable electrical operation.
See the PCB Design for Optimized Thermal Performance
section for more information on the use of the exposed paddles
to dissipate excess heat.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 16
Page 7
ADSY8401
A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVCC
GSW
SEL
AGNDL
DO9T
DO9C
DO10T
DO10C
DO11T
DO11C
VCCL1
DI11
DTCTI48DGND47DTCTO46AGND45BFRO44AVCC43BFRI42MUXO41MUXB40MUXA39AMPI38AMPO
1
2
3
4
5
6
7
8
9
10
11
12
13
DI914DI815DI716DI6
DI10
ADSY8401
TOP VIEW
(Not to Scale)
17
18
19
DVCC
DGND
DI520DI421DI322DI223DI1
37
AVCCL3
36
DO1
35
DO2
34
DO3
33
32
DO4
31
AGNDL
AVCCL2
30
DO5
29
DO6
28
DO7
27
DO8
26
AGNDL
25
24
04758-0-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 18 DVCC Digital Power Supply.
2 GSW
Grounded Mode Switch. When the voltage on the GSW pin is tied to DGND, the AMPO, MUXO, and
BFRO outputs are pulled to near AGND. When the GSW input is left unconnected or tied to DVCC, all
outputs operate normally. The level shifters are not affected by the GSW input.
3, 39–41
SEL, MUXA, MUXB,
MUXO
Analog Precharge. Low offset unity gain amplifier with MUXed inputs. Drives large capacitive loads. For
driving large capacitive loads at high slew rates, connect MUXO to BFRI and the load capacitance to
BFRO.
SEL = HIGH selects MUXA.
4, 25, 31 AGNDL Level Shifter Ground.
5–10 DO9–11T, DO9–11C
Complementary Level Shifter Outputs. While the corresponding input voltage of these level shifters is
below the threshold voltage, the voltage at the noninverting output pins is at V
the inverting outputs is at V
the threshold voltage, the voltage at the noninverting output pins is at V
inverting outputs is at V
. While the corresponding input voltage of these level shifters is above
OH
.
OL
OH
and the voltage at
OL
and the voltage at the
11, 30, 36 AVCCL1, 2, 3 Level Shifter Power Supply.
12–14 DI9–11 Complementary Level Shifter Inputs. Low voltage input of the complementary level shifters.
15–17,
DI1–8 Inverting Level Shifter Inputs. Low voltage input of the inverting level shifters.
20–24
19, 47 DGND Digital Ground. This pin is normally connected to the digital ground plane.
26–29,
32–35
DO1-8
Inverting Level Shifter Outputs. While the corresponding input voltage of these level shifters is below
the threshold voltage, the output voltage at these pins is at V
of these level shifters is above the threshold voltage, the output voltage at these pins is at V
. While the corresponding input voltage
OH
.
OL
37–38 AMPO, AMPI Analog Amplifier. Low offset unity gain amplifier. Drives large capacitive loads such as VCOM.
42, 44 BFRI, BFRO Analog Buffer. High current output buffer.
43 AVCC Analog Power Supplies. Analog power supplies for the level shifter and the amplifiers.
45 AGND Analog Supply Returns. Analog supply returns for the level shifter and the amplifiers.
46 DTCTO Edge Detecting Level Shifter Output. Logic output of the inverting level shifting edge detector.
48 DTCTI Edge Detecting Level Shifter Input. High voltage input of the inverting level shifting edge detector.
Rev. 0 | Page 7 of 16
Page 8
ADSY8401
V
AMPLIFIER APPLICATIONS
AMP SECTION AS VCOM BUFFER
VCOMI
MUX AND BFR SECTIONS AS NRS BUFFER
SEL
NRSA
NRSB
GSW
Figure 4. MUX and BFR Sections as NRS Buffer
MUX SECTION AS VCOM BUFFER
COMI
+1
GSW
AMPO
Figure 3. Amp Section as VCOM Buffer
+1
MUXO
BFRI
+1
+1
GSW
MUXO
VCOM
VCOM
04758-0-003
BFRO
NRS
04758-0-004
GSW
04758-0-005
Figure 5. MUX Section as VCOM Buffer
Rev. 0 | Page 8 of 16
Page 9
ADSY8401
LEVEL SHIFTER CHARACTERISTICS
LEVEL SHIFTER TIMING CHARACTERISTICS
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
INVERTING
INVERTING AND COMPLEMENTARY LEVEL SHIFTER TIMING
INPUTS
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DI9
DI10
DI11
COMPLEMENTARY
DO9T
DO10T
DO11T
DO9C
DO10C
DO11C
Figure 6. Level Shifter Timing Characteristics
04758-0-006
t
12
t
16
t
18
t
14
04758-0-007
INVERTING
OUTPUTS
NONINVERTING
OUTPUTS
t
11
t
15
t
17
t
13
Figure 7. Inverting and Complementary Level Shifter Timing
Table 4.
Parameter Conditions Min Typ Max Unit
LEVEL SHIFTER SECTION TA min to TA max
Output Rise, Fall Times, tr, tf
DO1–DO8, DO9T–DO11T, DO9C–DO11C CL = 40 pF 20 30 ns
DO1–DO8 CL = 300 pF 130 150 ns
Propagation Delay times, t11, t12, t13, t
14
DO1–DO8, DO9T–DO11T, DO9C–DO11C CL = 40 pF 23 50 ns
DO1–DO8 CL = 300 pF 60 80 ns
Propagation Delay Skew, t15, t
16
CL = 40 pF
DO1–DO8 2 ns
Propagation Delay Skew, t15, t16, t17, t
18
CL = 40 pF
DO1–DO8 to DO9T–DO11T and DO9C–DO11C 4 ns
Rev. 0 | Page 9 of 16
Page 10
ADSY8401
LEVEL SHIFTING EDGE DETECTOR TIMING CHARACTERISTICS
S
DTCTI
R
Figure 8. Level Shifting Edge Detector Timing Characteristics
LEVEL SHIFTING EDGE DETECTOR TIMING
AVCCL
DTCTI
AGNDL
DVCC
DTCTO
DGND
Table 5.
Parameter Conditions Min Typ Max Unit
LEVEL SHIFTING EDGE DECTECTOR CL = 10 pF
Input Low Voltage, V
Input High Voltage, V
Input Rising Edge Threshold Voltage, VTH LH
Input Falling Edge Threshold Voltage, VTH HL
Output High Voltage, V
Output Low Voltage, V
Input Current High State, I
Input Current, I
Input Rising Edge Propagation Delay Time, t
Input Falling Edge Propagation Delay Time, t
IL
IH
OH
OL
IH
IL
19
20
t20 Variation with Temperature, ∆t20
Output Rise, Fall Time, t
r
t
19
Figure 9. Level Shifting Edge Detector Timing
T
= 25°C to 85°C 2 ns
A
DTCTO
04758-0-008
t
20
04758-0-009
AGND + 1.5 V
AVCC − 1.5 V
AGND + 3 V
AVCC − 3 V
DVCC − 0.5 DVCC − 0.25 V
0.25 0.5 V
1.2 2.5 µA
−2.5 −1.2 µA
15.5 ns
16.5 ns
6 ns
Rev. 0 | Page 10 of 16
Page 11
ADSY8401
APPLICATIONS
The ADSY8401 is designed as part of a DecDriver® based LCD
driver platform. The level shifters provide an interface between
the image processor and a timing loop, operating at 3.3 V, and
the LCD with high voltage timing input levels. The edge
detecting level shifter provides an interface between the LCD
monitor output at high voltage and a timing loop such as the
AD8389 at 3.3 V. Low offset buffers, AMP and MUX, are
capable of driving high capacitive loads such as VCOM and
NRS without additional buffering. The high current buffer BFR
is capable of 100 mA output current, providing high slew rates
into large capacitive loads, which are often required for the
precharge input, NRS of LCDs.
AMP CHANNEL
The AMP channel is a low offset unity gain buffer designed to
drive a wide range of capacitive loads with a clean settling
response. In LCD panel applications, it is most frequently used
as a VCOM buffer.
MUX CHANNEL
The MUX channel is a 2-input, buffered analog multiplexer. The
overall performance of its buffered output is very similar to that
of the AMP channel. It is ideally suited for driving a wide range
of capacitive loads, from very small up to several nF.
DRIVING NRS
Analog voltage switching capability is provided by the MUX
channel. To achieve rapid settling while driving the capacitive
NRS input, the output of the MUX is buffered by the high
current drive BFR channel.
BFR CHANNEL
The BFR channel comprises a high output current buffer. It can
be used to increase the output drive capability of either the
AMP or MUX channels. The BFR channel is most often used in
series with the MUX channel output to realize a high current
drive NRS switch.
GROUNDED OUTPUT MODE
In certain designs it is desirable to pull the amplifier and buffer
outputs to near ground during power-down. When the voltage
on the GSW pin is tied to DGND, the AMPO, MUXO, and
BFRO outputs are pulled to near AGND. When the GSW input
is left unconnected or tied to DVCC, all outputs operate
normally. The level shifters are not affected by the GSW input.
DRIVING VCOM
The AMP channel comprises a low offset, unity gain buffer. It
can be used to drive a large capacitive load, such as VCOM,
directly with low overshoot. In certain systems, it might be
desirable for a single ADSY8401 to drive the VCOM inputs of
more than one LCD panel. In such cases, the MUX channel can
be used to drive VCOM directly. The MUX’s switching function
is not used, and its output is tied directly to VCOM without the
use of the BFR channel. Offset errors and pulse response are the
same as that of the AMP channel.
IMAGE
PROCESSOR
DY, DIRY, NRG
DIRX, CLX,CLY
REFERENCE
VOLTAGES
10/12
1/3 AD8389
DXI, CLXI,
ENBX(1–4)I
CLK
ENBX(1–4)xO
DXxO
CLXxO
MONITxI
NRS1
NRS2
Figure 10. Typical Application—One ADSY8401 per Color
Rev. 0 | Page 11 of 16
AD8381/AD8382/AD8383
VRH, VRL,
V1, V2
DB(0:9/11)
STSQ, XFR,
CLK, R/L, INV
ADSY8401
DI1–DI8
DI9–DI11
DTCTO
AMPIVCOM
BFRI
MUXA
MUXB
SELINV
VID(0:6)
DO1–DO4
DO5–DO8
DO9T–DO11T,
DO9C–DO11C
DTCTI
AMPO
BFRO
MUXO
6
ENBX(1–4)
DX, DY, DIRY, NRG
CLX, CLXN
CLY, CLYN
DIRX
MONITOR
VCOM
NRS
LCD
04758-0-010
Page 12
ADSY8401
IMAGE
PROCESSOR
ENBXR(1:4)
ENBXB(1:4)
CLXR, CLYRB
ENBXG(1:4)
DX, DY, DIRY
CLXG, CLYG
CLXB
DIRX
DI1–DI4
DI5–DI8
DI9–DI10
DI11
DI1–DI4
DI5–DI7
DVCC DI8
DI9
DI10–DI11
DO1–DO4
DO5–DO8
DO9T–DO9C
DO10T–DO10C
DO11T, DO11C
DO1–DO4
DO5
DO6
DO7
DO8
DO9T
DO9C
DO10T–DO11T
DO11T–DO11C
RED LCD
ENBX(1–4)
DX
DY
DIRY
CLX, CLXN
CLY, CLYN
DIRX
BLUE LCD
ENBX(1–4)
DX
DY
DIRY
CLX, CLXN
CLY, CLYN
DIRX
GREEN LCD
ENBX(1–4)
DX
DY
DIRY
CLX, CLXN,
CLY, CLYN
DIRX
04758-0-011
Figure 11. Typical Application—Two ADSY8401 per System, Level Shifters
ADSY8401
AMPIVCOMR
BFRI
MUXANRSA
MUXBNRSB
SELSEL
AMPO
BFRO
MUXO
ADSY8401
AMPIVCOMG
BFRIDC INPUT ~ AVCC/2
MUXAVCOMB
MUXB
SELDVCC
AMPO
BFRO
MUXO
Figure 12. Typical Application—Two ADSY8401 per System, Amplifiers
RED LCD
VCOM
NRS
BLUE LCD
VCOM
NRS
GREEN LCD
VCOM
NRS
04758-0-012
Rev. 0 | Page 12 of 16
Page 13
ADSY8401
PCB DESIGN FOR OPTIMIZED THERMAL PERFORMANCE
The total maximum power dissipation of the ADSY8401 is
partly load-dependent. In a typical 60 Hz XGA system, the total
maximum power dissipation is ≈ 1 W. The ADSY8401 package
is designed to provide superior thermal characteristics, partly
through the exposed die paddle on the bottom surface of the
package. To take full advantage of this feature, the exposed
paddle must be in direct thermal contact with the PCB, which
then serves as a heat sink.
A thermally effective PCB must incorporate a thermal pad and
a thermal via structure. The thermal pad provides a solderable
contact surface on the top surface of the PCB. The thermal via
structure provides a thermal path to the inner and bottom
layers of the PCB to remove heat.
Thermal Pad Design
To minimize thermal performance degradation of production
PCBs, the contact area between the thermal pad and the PCB
should be maximized. Therefore, the size of the thermal pad on
the top PCB layer should match the exposed paddle. The second
thermal pad of the same size should be placed on the bottom
side of the PCB. At least one thermal pad should be in direct
thermal contact with an external plane such as AVCC or GND.
Thermal Via Structure Design
Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases logarithmically with the number of vias. Near optimum thermal
performance of production PCBs is attained only when tightly
spaced thermal vias are placed on the full extent of the thermal
pad.
Table 6. Recommended Land Pattern Dimensions
Land Pattern Dimensions
Top and Bottom Layers
Pad size 0.5 mm × 0.25 mm
Pad pitch 0.5 mm
Thermal pad size 5.25 mm × 5.25 mm
Thermal via structure
0.25 mm diameter vias on
0.5 mm grid
Thermal Pad and Thermal Via Connections
Thermal pads are connected to the AGND or AVCC plane. The
thermal pad on the solder side is connected to a plane. The use
of thermal spokes is not recommended when connecting the
thermal pads or via structure to the plane.
Solder Masking
To minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), the via diameter should be
small. Solder masking of the via holes on the top layer of the
PCB plugs the via holes, inhibiting solder flow into the holes. To
optimize the thermal pad coverage, the solder mask diameter
should be no more than 0.1 mm larger than the via diameter.
Table 7. Recommended Solder Mask Dimensions
Solder Mask Dimensions
Top layer
Pads Set by customer’s PCB design rules
Thermal vias
Bottom layer Set by customer’s PCB design rules
0.25 mm diameter circular mask centered
on the vias
7mm
7mm
LAND PATTERN–TOP LAYER
LAND PATTERN–BOTTOM LAYER
Rev. 0 | Page 13 of 16
SOLDER MASK–TOP LAYER
Figure 13. PCB Layers
04758-0-013
Page 14
ADSY8401
POWER SUPPLY SEQUENCING
As indicated in the Absolute Maximum Ratings section, the
voltage at any input pin cannot exceed its supply voltage by
more than 0.5 V. To ensure compliance with the absolute
maximum ratings, power-up and power-down sequencing
might be required.
During power-up, initial application of nonzero voltages to any
of the input pins must be delayed until the supply voltage ramps
up to at least the highest maximum operational input voltage.
During power-down, the voltage at any input pin must reach
zero during a period not exceeding the hold-up time of the
power supply.
Failure to comply with the absolute maximum ratings may
result in functional failure or damage to the internal ESD
diodes. Damaged ESD diodes can cause temporary parametric
failures, which can result in image artifacts. Damaged ESD
diodes cannot provide full ESD protection, reducing reliability.
Power-on sequence:
Layout and Grounding
The analog outputs and the digital inputs of the ADSY8401 are
on opposite sides of the package. Keep these sections separated
to minimize crosstalk and coupling of digital inputs into the
analog outputs.
All signal trace lengths should be made as short and direct as
possible to prevent signal degradation due to parasitic effects.
Note that a digital signal should not cross or be routed near
analog signals.
It is imperative to provide a solid analog ground plane under
and around the ADSY8401. All ground pins of the part should
be connected directly to this ground plane with no extra signal
path length. This includes AGND, AGNDL, and D GND. The
return traces for any of the signals should be routed close to the
ground pin for that section to prevent stray signals from
coupling into other ground pins.
Power Supply Bypassing
All power supply pins of the ADSY8401 must be properly
bypassed to the analog ground plane for optimum performance.
1. Apply power to supplies.
2. Apply inputs.
Power-off sequence:
1. Remove signal from inputs.
2. Remove power from supplies.
Power-Off Sequencing Using the GSW Pin
In certain designs it is desirable to pull the amplifier, buffer, and
level shifter outputs to near ground during power-down.
Power-off sequence with GSW:
1. Apply low to the GSW pin.
2. Apply high to all level shifter input pins.
3. Pull the MUXA, MUXB, AM PI, and BFRI inputs to AGND.
4. Remove AVCC.
5. Remove DVCC.
LAYOUT CONSIDERATIONS
The ADSY8401 is a mixed-signal, high speed, high accuracy
device. To fully realize its specifications, it is essential to use a
properly designed printed circuit board.
TOTAL POWER DISSIPATION
The total power dissipation of the ADSY8401 has three
components:
• Quiescent power dissipation when all digital inputs are low.
• Dynamic power dissipation due to the capacitance of
the LCD (typical C
= 40 pF for all other control inputs).
C
L
• Average power dissipation due to the toggling inputs.
When DI1–DI11 are at digital low, the quiescent power dissipation of the ADSY8401 is 576 mW. When DI1–DI11 are at digital
high, the quiescent power dissipation is 771 mW.
The typical dynamic power dissipation of each of the three
ADSY8401, due to the capacitance of the LCD, is 155 mW in a
typical 60 Hz XGA system, shown in Figure 10. It is 304 mW
and 153 mW, respectively, for the two ADSY8401s in the 60 Hz
XGA system shown in Figure 11.
The average power dissipation of each of the three ADSY8401
due to DI1–DI11 toggling is 23 mW in the system shown in
Figure 10. It is 32 mW and 22 mW, respectively, for the two
ADSY8401 in the system shown in Figure 11.
The total power dissipation of each of the three ADSY8401 in
the XGA system, shown in Figure 10, is 754 mW.
= 200 pF for all the NRG control inputs,
L
The total power dissipation of the two ADSY8401s in the XGA
system, shown in Figure 12, is 912 mW and 751 mW,
respectively.
Rev. 0 | Page 14 of 16
Page 15
ADSY8401
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
48
INDICATOR
1
BSC SQ
PIN 1
INDICATOR
7.00
0.60 MAX
37
36
0.60 MAX
5.25
5.10 SQ
4.95
12
13
0.25 MIN
1.00
0.85
0.80
12° MAX
SEATING
PLANE
TOP
VIEW
0.80 MAX
0.65 TYP
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
6.75
BSC SQ
0.20 REF
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
BOTTOM
VIEW
25
24
5.50
REF
Figure 14. 48-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADSYS8401JPCZ
1
Z = Pb-free part.
1
0°C to 85°C Lead Frame Chip Scale Package CP-48
Rev. 0 | Page 15 of 16
Page 16
ADSY8401
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04758–0–7/04(0)
Rev. 0 | Page 16 of 16
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