Datasheet ADSP-TS203S Datasheet (ANALOG DEVICES)

TigerSHARC

T

L0

4

8

4

8

4

8

4

8

4

IN

OUT

HOST

MULTI-

PROC

C-BUS

ARB

DATA

32

LINK PORTS

JTAG PORT

EXTERNAL

PORT

ADDR

32

6

SOC BUS

DMA

JTAG

SDRAM

CTRL

EXT DMA

REQ

J-BUS DATA

IAB

PC

BTB

ADDR

FETCH

PROGRAM

SEQUEN CER

COMPUTATIONAL BLOCKS

J-BUS ADDR

K-BUS DATA

K-BUS ADDR

I-BUS DATA

I-BUS ADDR

S-BUS DATA

S-BUS ADDR

INTEGER

KALU

INTEGER

JALU

32

32-BIT × 32-BIT

DATA ADDRESS GENERATION

X

REGISTER

FILE

32-BIT × 32-BIT

MULALUSHIFT

DAB

128

DAB

128

MEMORY BLOCKS

A

D

4M BITS INTERNAL MEMORY

4 × CROSSBAR CONNECT

(PAGE CACHE)

ADADA

D

SOC

I/F

Y

REGISTER

FILE

32-BIT × 32-BIT

MUL ALU SHIFT

L1

IN

OUT

CTRL

8

CTRL

10

32

128

32

128

32

128

21

128

4

32-BIT × 32-BIT

Embedded Processor

ADSP-TS203S

KEY FEATURES

500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm × 25 mm (576-ball) thermally enhanced ball grid array

package

Dual-computation blocks—each containing an ALU, a multi-

plier, a shifter, and a register file

Dual-integer ALUs, providing data addressing and pointer

manipulation

Single-precision IEEE 32-bit and extended-precision 40-bit

floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats

Integrated I/O includes 10-channel DMA controller, external

port, two link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

1149.1 IEEE-compliant JTAG test access port for on-chip emulation

On-chip arbitration for glueless multiprocessing

KEY BENEFITS

Provides high performance static superscalar DSP

operations, optimized for large, demanding multiprocessor DSP applications

Performs exceptionally well on DSP algorithm and I/O

benchmarks (see benchmarks in Table 1)

Supports low overhead DMA transfers between internal

memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs

Eases programming through extremely flexible instruction

set and high-level-language-friendly architecture

Enables scalable multiprocessing systems with low commu-

nications overhead

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Figure 1. Functional Block Diagram

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADSP-TS203S

REVISION HISTORY

5/12—Rev. C to Rev. D

Added model to Ordering Guide ................................ 47

Rev. D | Page 2 of 48 | May 2012

GENERAL DESCRIPTION

ADSP-TS203S

The ADSP-TS203S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The processor combines very wide memory widths with dual computation blocks—supporting floating-point (IEEE 32-bit and extended precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

Four independent 128-bit wide internal data buses, each connecting to the four 1M bit memory banks, enable quad-word data, instruction, and I/O access and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS203S processor’s core has a 2.0 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the processor can perform four billion 40-bit MACS or one billion 80-bit MACS per second. Table 1 shows the processor’s performance benchmarks.

Table 1. General-Purpose Algorithm Benchmarks at 500 MHz

Clock

Benchmark Speed

32-bit algorithm, 1 billion MACS/s peak performance 1K point complex FFT1(Radix2)

64K point complex FFT1(Radix2) 2.8 ms FIR filter (per real tap) 1 ns 0.5 [8 × 8][8 × 8] matrix multiply

(complex, floating-point) 2.8 µs 1399 16-bit algorithm, 4 billion MACS/s peak performance 256 point complex FFT1 (Radix 2) 1.9 µs 928 I/O DMA transfer rate External port 500M bytes/s n/a Link ports (each) 500M bytes/s n/a

1

Cache preloaded.

18.8 µs 9419

Cycles

13975 44

The ADSP-TS203S processor is code compatible with the other TigerSHARC processors.

The Functional Block Diagram on Page 1 shows the processor’s architectural blocks. These blocks include

• Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, and 32-word register file and associated data alignment buffers (DABs)

• Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing and a status register

• A program sequencer with instruction alignment buffer (IAB) and branch target buffer (BTB)

• An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts

• Four 128-bit internal data buses, each connecting to the four 1M-bit memory banks

•On-chip DRAM (4M-bit)

• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM

• A 10-channel DMA controller

• Two full-duplex LVDS link ports

• Two 64-bit interval timers and timer expired pin

• An 1149.1 IEEE-compliant JTAG test access port for onchip emulation

TM

*

The TigerSHARC uses a Static Superscalar

architecture. This architecture is superscalar in that the ADSP-TS203S processor’s core can execute simultaneously from one to four 32-bit instructions encoded in a very large instruction word (VLIW) instruction line using the processor’s dual compute blocks. Because the processor does not perform instruction reordering at runtime—the programmer selects which operations will execute in parallel prior to runtime—the order of instructions is static.

With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a 10-deep processor pipeline.

For optimal processor program execution, programmers must follow the processor’s set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the processor can execute in parallel each cycle depends both on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. The programmer has direct control of three core components—the IALUs, the compute blocks, and the program sequencer.

The ADSP-TS203S processor, in most cases, has a two-cycle execution pipeline that is fully interlocked, so—whenever a computation result is unavailable for another operation dependent on it—the processor automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies.

In addition, the processor supports SIMD operations two ways—SIMD compute blocks and SIMD computations. The programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution).

*

Static Superscalar is a trademark of Analog Devices, Inc.

Rev. D | Page 3 of 48 | May 2012

ADSP-TS203S

DUAL COMPUTE BLOCKS

The ADSP-TS203S processor has compute blocks that can execute computations either independently or together as a single-instruction, multiple-data (SIMD) engine. The processor can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, or shifter to perform independent, simultaneous operations. Each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with the operation in the other block. These computation units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating point, and 8-, 16-, 32-, and 64-bit fixed-point processing.

The compute blocks are referred to as X and Y in assembly syntax, and each block contains three computational units—an ALU, a multiplier, a 64-bit shifter—and a 32-word register file.

• Register File—each compute block has a multiported 32-word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned).

• ALU—the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic and permute operations.

• Multiplier—the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate.

• Shifter—the 64-bit shifter performs logical and arithmetic shifts, bit and bit stream manipulation, and field deposit and extraction operations.

Using these features, the compute blocks can

• Provide 8 MACS per cycle peak and 7.1 MACS per cycle sustained 16-bit performance and provide 2 MACS per cycle peak and 1.8 MACS per cycle sustained 32-bit performance (based on FIR)

• Execute six single-precision floating-point or execute 24 fixed-point (16-bit) operations per cycle, providing 3G FLOPS or 12.0G/s regular operations performance at 500 MHz

• Perform two complex 16-bit MACS per cycle

DATA ALIGNMENT BUFFER (DAB)

The DAB is a quad-word FIFO that enables loading of quadword data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR filters.

DUAL INTEGER ALU (IALU)

The processor has two IALUs that provide powerful address generation capabilities and perform many general-purpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features:

• Provide memory addresses for data and update pointers

• Support circular buffering and bit-reverse addressing

• Perform general-purpose integer operations, increasing programming flexibility

• Include a 31-word register file for each IALU

As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each IALU can specify either a single-, dual-, or quad-word access from memory.

The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location.

Because the IALU’s computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is unavailable in a given cycle.

PROGRAM SEQUENCER

The ADSP-TS203S processor’s program sequencer supports:

• A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles

• A 10-cycle instruction pipeline—four-cycle fetch pipe and six-cycle execution pipe—computation results available two cycles after operands are available

• Supply of instruction fetch memory addresses; the sequencer’s instruction alignment buffer (IAB) caches up to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution

• Management of program structures and program flow determined according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software exceptions

• Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty

• Compact code without the requirement to align code in memory; the IAB handles alignment

Rev. D | Page 4 of 48 | May 2012

ADSP-TS203S

Interrupt Controller

The processor supports nested and nonnested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either levelsensitive or edge-sensitive, except the IRQ3–0 rupts, which are programmable.

The processor distinguishes between hardware interrupts and software exceptions, handling them differently. When a software exception occurs, the processor aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the processor continues to execute instructions already in the instruction pipe.

hardware inter-

Flexible Instruction Set

The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the processor to conditionally execute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include:

• Algebraic assembly language syntax

• Direct support for all DSP, imaging, and video arithmetic types

• Eliminates toggling hardware modes because modes are supported as options (for example, rounding, saturation, and others) within instructions

• Branch prediction encoded in instruction; enables zerooverhead loops

• Parallelism encoded in instruction line

• Conditional execution optional for all instructions

• User-defined partitioning between program and data memory

MEMORY

The processor’s internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in Figure 2.

The memory map is divided into four memory areas—host space, external memory, multiprocessor space, and internal memory—and each memory space, except host memory, is subdivided into smaller memory spaces.

The ADSP-TS203S processor internal memory has 4M bits of on-chip DRAM memory, divided into four blocks of 1M bits (32K words × 32 bits). Each block—M0, M2, M4, and M6—can store program instructions, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the processor to access data while performing an instruction fetch. Each memory segment contains a 128K bit cache to enable single-cycle accesses to internal DRAM.

The four internal memory blocks connect to the four 128-bit wide internal buses through a crossbar connection, enabling the processor to perform four memory transfers in the same cycle. The processor’s internal bus architecture provides a total memory bandwidth of 28G bytes per second, allowing the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. Additional features are:

• Processor core and I/O access to different memory blocks in the same cycle

• Processor core access to three memory blocks in parallel— one instruction and two data accesses

• Programmable partitioning of program and data memory

• Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB

EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

The ADSP-TS203S processor’s external port provides the processor’s interface to off-chip memory and peripherals. The 4G word address space is included in the processor’s unified address space. The separate on-chip buses—four 128-bit data buses and four 32-bit address buses—are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction. The external system bus provides a single 32-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 500M bytes per second over the external bus.

The external bus is configured for 32-bit, little-endian operations. Unlike the ADSP-TS201, the ADSP-TS203S processor’s external port cannot support 64-bit operations; the external bus width control bits (Bits 21-19) must = 0 in the SYSCON register—all other values are illegal for the ADSP-TS203S. Because the external port is restricted to 32 bits on the ADSP-TS203S processor, there are a number of pinout differences between the ADSP-TS203S and the ADSP-TS201 processors.

The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals.

The ADSP-TS203S processor provides programmable memory, pipeline depth, and idle cycle for synchronous accesses, and external acknowledge controls to interface to pipelined or slow devices, host processors, and other memory-mapped peripherals with variable access, hold, and disable time requirements.

Host Interface

The ADSP-TS203S processor provides an easy and configurable interface between its external bus and host processors through the external port. To accommodate a variety of host processors, the host interface supports pipelined or slow protocols for processor access of the host as slave or pipelined for host access of the ADSP-TS203S processor as slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles.

Rev. D | Page 5 of 48 | May 2012

ADSP-TS203S

RESERVED

INTERNAL REGISTERS(UREGS)

INTERNAL MEMORYBLOCK 4

INTERNAL MEMORY BLO CK 2

INTERNAL MEMORY BLO CK 0

0x0 3FFF FFF

0x001E0000

0x001E03FF

0x000C7FFF

0x0 00C 0000

0x 00087 FFF

0x00080000

0x 00047 FFF

0x00040000

0x 00007 FFF

0 x000 00000

INTERNAL SPACE

PROCESSOR ID 7

PROCESSOR ID 6

PROCESSOR ID 5

PROCESSOR ID 4

PROCESSOR ID 3

PROCESSOR ID 2

PROCESSOR ID 1

PROCESSOR ID 0

BROADCAS T

HOST (MS H )

BANK1(MS1)

BANK0(MS0)

MSSD BANK 0 (MS S D0)

INTE RNAL MEMORY

0x50000000

0 x4000 0000

0x38000000

0x30000000

0x2C000000

0x28000000

0x24000000

0x20000000

0x1C000000

0x18000000

0x14000000

0x10000000

0x0C000000

0x03FFFFFF

0x00000000

0xFFFFFFFF

M

U

L

T

I

P

R

O

C

E

S

O

R

M

E

M

O

R

Y

S

P

A

C

E

X

T

E

R

N

A

L

M

E

M

O

R

Y

S

P

A

C

E

EACH IS A COPY

OF INTERNAL SPACE

RESERVED

INTERNAL MEMORYBLOCK 6

RESERVED

SOC REGISTERS (UREGS)

0x 001F00 00

0 x001F03 FF

MSSD BANK 1 (MS S D1)

MSS D BANK 2 (MS SD2)

MSSD BANK 3 (MS S D3)

0x60000000

0x70000000

0x80000000

RE SE RV E D

0x54000000

0 x4400 0000

0x64000000

0x74000000

RESERVED

The host interface supports burst transactions initiated by a host processor. After the host issues the starting address of the burst and asserts the BRST address internally while the host continues to assert BRST

signal, the processor increments the

.

The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the processor. The BOFF mechanism. When the host asserts BOFF off the current transaction and asserts HBG

signal provides the deadlock recovery

, the processor backs

and relinquishes the

external bus.

The host can directly read or write the internal memory of the ADSP-TS203S processor, and it can access most of the processor registers, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands.

Multiprocessor Interface

The processor offers powerful features tailored to multiprocessing processor systems through the external port and link ports. This multiprocessing capability provides the highest bandwidth for interprocessor communication, including

• Up to eight DSPs on a common bus

• On-chip arbitration for glueless multiprocessing

• Link ports for point-to-point communication

The external port and link ports provide integrated, glueless multiprocessing support.

GLOBAL SPACE

Figure 2. ADSP-TS203S Memory Map

Rev. D | Page 6 of 48 | May 2012

ADSP-TS203S

The external port supports a unified address space (see Figure 2) that enables direct interprocessor accesses of each ADSPTS203S processor’s internal memory and registers. The processor’s on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight ADSP-TS203S processors and a host processor. Bus arbitration has a rotating priority. Bus lock supports indivisible readmodify-write sequences for semaphores. A bus fairness feature prevents one processor from holding the external bus too long.

The processor’s two link ports provide a second path for interprocessor communications with throughput of 1G byte per second. The cluster bus provides 500M bytes per second throughput—with a total of 1.5G bytes per second interprocessor bandwidth.

SDRAM Controller

The SDRAM controller controls the processor’s transfers of data to and from external synchronous DRAM (SDRAM) at a throughput of 32 bits per SCLK cycle using the external port and SDRAM control pins.

The SDRAM interface provides a glueless interface with standard SDRAMs—16M bits, 64M bits, 128M bits, 256M bits and 512M bits. The processor supports directly a maximum of four banks of 64M words × 32 bits of SDRAM. The SDRAM interface is mapped in external memory in each processor’s unified memory map.

• External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the processor’s internal memory and any external memory or memory-mapped peripheral on the external bus. Master mode and handshake mode protocols are supported.

• Link port transfers. Four dedicated DMA channels (two transmit and two receive) transfer quad-word data only between link ports and between a link port and internal or external memory. These transfers only use handshake mode protocol. DMA priority rotates between the two receive channels.

• AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer.

The DMA controller provides these additional features:

• Flyby transfers. Flyby operations only occur through the external port (DMA channel 0) and do not involve the processor’s core. The DMA controller acts as a conduit to transfer data from an external I/O device to external SDRAM memory. During a transaction, the processor relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0 IOEN

, and RD/WR strobes; and responds to ACK.

); outputs the IORD, IOWR,

EPROM Interface

The processor can be configured to boot from an external 8-bit EPROM at reset through the external port. An automatic process (which follows reset) loads a program from the EPROM into internal memory. This process uses 16 wait cycles for each read access. During booting, the BMS EPROM chip select signal. The EPROM boot procedure uses DMA Channel 0, which packs the bytes into 32-bit instructions. Applications can also access the EPROM (write flash memories) during normal operation through DMA.

The EPROM or flash memory interface is not mapped in the processor’s unified memory map. It is a byte address space limited to a maximum of 16M bytes (24 address bits). The EPROM or flash memory interface can be used after boot via a DMA.

pin functions as the

DMA CONTROLLER

The ADSP-TS203S processor’s on-chip DMA controller, with 10 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor’s core, enabling DMA operations to occur while the processor’s core continues to execute program instructions.

The DMA controller performs DMA transfers between internal memory, external memory, and memory-mapped peripherals; the internal memory of other DSPs on a common bus, a host processor, or link port I/O; between external memory and external peripherals or link port I/O; and between an external bus master and internal memory or link port I/O. The DMA controller performs the following DMA operations:

• DMA chaining. DMA chaining operations enable applications to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes.

• Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions.

LINK PORTS (LVDS)

The processor’s two full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using low-voltage, differential-signal (LVDS) technology. With the ability to operate at a double data rate—latching data on both the rising and falling edges of the clock—running at 250 MHz, each link port can support up to 250M bytes per second per direction, for a combined maximum throughput of 1G byte per second.

The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also use the link ports for booting.

Each link port has its own triple-buffered quad-word input and double-buffered quad-word output registers. The processor’s core can write directly to a link port’s transmit register and read

Rev. D | Page 7 of 48 | May 2012

ADSP-TS203S

SCLKRATx

SCLK

SPD BI TS,

LCTLx REGISTER

PLL

/2

/CR

CCLK (INSTRUCTION RA TE)

SOCCLK (PERIPHERAL BUS RATE)

LxCLKOUT (LINK OUTPUT RATE)

EXTERNAL INTERFACE

V

DD_IO

V

SS

V

REF

R1

R2 C1 C2

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from a receive register, or the DMA controller can perform DMA transfers through four (two transmit and two receive) dedicated link port DMA channels.

Each link port direction has three signals that control its operation. For the transmitter, LxCLKOUT is the output transmit clock, LxACKI is the handshake input to control the data flow, and the LxBCMPO

output indicates that the block transfer is complete. For the receiver, LxCLKIN is the input receive clock, LxACKO is the handshake output to control the data flow, and the LxBCMPI

input indicates that the block transfer is complete. The LxDATO3–0 pins are the data output bus for the transmitter, and the LxDATI3–0 pins are the input data bus for the receiver.

Applications can program separate error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are transmitted.

TIMER AND GENERAL-PURPOSE I/O

The ADSP-TS203S processor has a timer pin (TMR0E) that generates output when a programmed timer counter has expired, and four programmable general-purpose I/O pins (FLAG3–0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching.

Table 2. No Boot, Run from Memory Addresses

Interrupt Address

IRQ0 IRQ1 IRQ2 IRQ3

0x3000 0000 (External Memory) 0x3800 0000 (External Memory) 0x8000 0000 (External Memory) 0x0000 0000 (Internal Memory)

For more information on boot options, see the EE-200: ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation on the Analog Devices website (www.analog.com)

CLOCK DOMAINS

The processor uses calculated ratios of the SCLK clock to operate, as shown in Figure 3. The instruction execution rate is equal to CCLK. A PLL from SCLK generates CCLK which is phaselocked. The SCLKRATx pins define the clock multiplication of SCLK to CCLK (see Table 4 on Page 11). The link port clock is generated from CCLK via a software programmable divisor, and the SOC bus operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. SCLK also provides clock input for the external bus interface and defines the ac specification reference for the external bus signals. The external bus interface runs at the SCLK frequency. The maximum SCLK frequency is one quarter the internal processor clock (CCLK) frequency.

RESET AND BOOTING

The processor has three levels of reset:

• Power-up reset – after power-up of the system (SCLK, all static inputs, and strap pins are stable), the RST_IN must be asserted (low).

• Normal reset – for any chip reset following the power-up reset, the RST_IN

• Processor-core reset – when setting the SWRST bit in EMUCTL, the processor core is reset, but not the external port or I/O.

For normal operations, tie the RST_OUT POR_IN

pin.

After reset, the processor has four boot options for beginning operation:

•Boot from EPROM.

• Boot by an external master (host or another ADSP-TS203S processor).

•Boot by link port.

• No boot—start running from memory address selected with one of the IRQ3–0 Using the this option, the processor must start running from memory when one of the interrupts is asserted.

The processor core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset.

pin must be asserted (low).

pin to the

interrupt signals. See Table 2.

Rev. D | Page 8 of 48 | May 2012

Figure 3. Clock Domains

FILTERING REFERENCE VOLTAGE AND CLOCKS

Figure 4 and Figure 5 show possible circuits for filtering V

and SCLK_V

. These circuits provide the reference voltages

REF

for the switching voltage reference and system clock reference.

Figure 4. V

Filtering Scheme

REF

,

CLOCK DRIVER

VOLTAGE OR

V

DD_IO

V

SS

SCLK_V

REF

R1

R2 C1 C2

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*IF CLOCK DRIVER VOLTAGE > V

DD_IO

Figure 5. SCLK_V

Filtering Scheme

REF

POWER DOMAINS

The ADSP-TS203S processor has separate power supply connections for internal logic (V buffer (V

), and internal DRAM (V

DD_IO

), analog circuits (V

DD

DD_DRAM

DD_A

) power

), I/O

supply.

Note that the analog (V

) supply powers the clock generator

DD_A

PLLs. To produce a stable clock, systems must provide a clean power supply to power input V attention to bypassing the V

DD_A

. Designs must pay critical

DD_A

supply.

DEVELOPMENT TOOLS

The ADSP-TS203S processor is supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS203S processor.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for theses tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the

®

software and hardware development tools,

®

devel-

ADSP-TS203S

program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

VCSE is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It is also used for downloading components from the Web, dropping them into the application, and publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Rev. D | Page 9 of 48 | May 2012

ADSP-TS203S

Use the expert linker to visually manipulate the placement of code and data on the embedded system, view memory use in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse, and examine runtime stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-TS203S processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the TigerSHARC processor family. Hardware tools include TigerSHARC processor PC plug-in cards. Third party software tools include DSP libraries, realtime operating systems, and block diagram design tools.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

processor must be halted to send data and commands, but once an operation has been completed by the emulator, the system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use the string “EE-68” in site search. This document is updated regularly to keep pace with improvements to emulator support.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection guides and application information

• Reference designs applying best practice design techniques

TM

site (www.analog.com/circuits)

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-TS203S processor’s architecture and functionality. For detailed information on the ADSP-TS203S processor’s core architecture and instruction set, see the ADSP-TS201 Tiger-

SHARC Processor Hardware Reference and the ADSP-TS201 TigerSHARC Processor Programming Reference. For detailed

information on the development tools for this processor, see the

VisualDSP++ User’s Guide for TigerSHARC Processors.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every developer needs to in order test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The

Rev. D | Page 10 of 48 | May 2012

PIN FUNCTION DESCRIPTIONS

ADSP-TS203S

While most of the ADSP-TS203S processor’s input pins are normally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. Use the ac specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals.

The output pins can be three-stated during normal operation. The processor three-states all output during reset, allowing these pins to get to their internal pull-up or pull-down state. Some pins have an internal pull-up or pull-down resistor (±30% tolerance) that maintains a known value during transitions between different drivers.

Table 3. Pin Definitions—Clocks and Reset

Signal Type Term Description

SCLKRAT2–0 I (pd) na Core Clock Ratio. The processor’s core clock (CCLK) rate = n × SCLK, where n is user-

programmable using the SCLKRATx pins to the values shown in Tabl e 4. These pins may change only during reset; connect these pins to V cations in Tab le 25 , Tab le 2 6, and Tab le 2 7 must be satisfied. The core clock rate (CCLK) is the instruction cycle rate.

SCLK I na System Clock Input. The processor’s system input clock for cluster bus. The core

clock rate is user-programmable using the SCLKRATx pins. For more information,

see Clock Domains on Page 8.

RST_IN

RST_OUT POR_IN I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

I/A na Reset. Sets the processor to a known state and causes program to be in idle state.

RST_IN must be asserted a specified time according to the type of reset operation. For details, see Reset and Booting on Page 8, Table 27 on Page 26, and Figure 12 on

Page 26.

O na Reset Output. Indicates that the processor reset is complete. Connect to POR_IN. I/A na Power-On Reset for internal DRAM. Connect to RST_OUT.

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

SS

or VSS. All reset specifi-

DD_IO

; epu = external pull-up

; VSS = connect

DD_IO

Table 4. SCLK Ratio

SCLKRAT2–0 Ratio

000 (default) 4 001 5 010 6 011 7 100 8 101 10 110 12 111 Reserved

Rev. D | Page 11 of 48 | May 2012

ADSP-TS203S

Table 5. Pin Definitions—External Port Bus Controls

Signal Type Term Description

ADDR31–0 I/O/T

(pu_ad)

DATA31–0 I/O/T

(pu_ad)

RD

I/O/T (pu_0)

WRL

I/O/T (pu_0)

ACK I/O/T/OD

(pu_od_0)

BMS O/T

(pu_0)

MS1–0

O/T (pu_0)

MSH

O/T (pu_0)

BRST

I/O/T (pu_0)

TM4 I/O/T epu Test Mode 4. Must be pulled up to V I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

1

This external pull-up may be omitted for the ID = 000 TigerSHARC processor.

SS

, nc = not connected; na = not applicable (always used); V

DD_IO

nc Address Bus. The processor issues addresses for accessing memory and peripherals

on these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS203S processors. The processor inputs addresses when a host or another processor accesses its internal memory or I/O processor registers.

nc External Data Bus. The processor drives and receives data and instructions on these

pins. Pull-up or pull-down resistors on unused DATA pins are unnecessary.

1

epu

Memory Read. RD is asserted whenever the processor reads from any slave in the system, excluding SDRAM. When the processor is a slave, RD

is an input and indicates read transactions that access its internal memory or universal registers. In a multiprocessor system, the bus master drives RD. RD changes concurrently with ADDR pins.

1

epu

Write Low. WRL is asserted when the ADSP-TS203S processor writes to the external bus (host, memory, or processor). An external master (host or processor) asserts WRL for writing to a processor’s internal memory. In a multiprocessor system, the bus master drives WRL is a slave, WRL

. WRL changes concurrently with ADDR pins. When the processor

is an input and indicates write transactions that access its internal

memory or universal registers.

1

epu

Acknowledge. External slave devices can deassert ACK to add wait states to external memory accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data phase. The processor can deassert ACK to add wait states to read and write accesses of its internal memory. The pull-up is 50  on low-to-high transactions and is 500  on all other transactions.

na Boot Memory S elect. BMS is the chip select for boot EPROM or flash memory. During

reset, the processor uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multiprocessor system, the processor bus master drives BMS

. For details, see Reset

and Booting on Page 8 and the EBOOT signal description in Table 16 on Page 18.

nc Memory Select. MS0 or MS1 is asserted whenever the processor accesses memory

banks 0 or 1, respectively. MS1–0 are decoded memory address pins that change concurrently with ADDR pins. When ADDR31:27 = 0b00110, MS0

is asserted. When ADDR31:27 = 0b00111, MS1 is asserted. In multiprocessor systems, the master processor drives MS1–0.

nc Memory Select Host. MSH is asserted whenever the processor accesses the host

address space (ADDR31 = 0b1). MSH

is a decoded memory address pin that changes concurrently with ADDR pins. In a multiprocessor system, the bus master processor drives MSH.

1

epu

Burst. The current bus master (processor or host) asserts this pin to indicate that it is reading or writing data associated with consecutive addresses. A slave device can ignore addresses after the first one and increment an internal address counter after each transfer. For host-to-processor burst accesses, the processor increments the address automatically while BRST

is asserted.

with a 5 k resistor.

DD_IO

= connect directly to V

DD_IO

; epu = external pull-up

SS

; VSS = connect

DD_IO

Rev. D | Page 12 of 48 | May 2012

Table 6. Pin Definitions—External Port Arbitration

ADSP-TS203S

Signal Type Term Description

BR7–0

I/O V

DD_IO

1

Multiprocessing Bus Request Pins. Used by the processors in a multiprocessor system to arbitrate for bus mastership. Each processor drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight processors, set the unused BRx

pins high (V

DD_IO

).

ID2–0 I (pd) na Multiprocessor ID. Indicates the processor’s ID, from which the processor deter-

mines its order in a multiprocessor system. These pins also indicate to the processor which bus request (BR0 001 = BR1

, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7.

–BR7) to assert when requesting the bus: 000 = BR0,

ID2–0 must have a constant value during system operation and can change during reset only.

BM

O na Bus Master. The current bus master processor asserts BM. For debugging only. At

reset this is a strap pin. For more information, see Table 16 on Page 18.

BOFF

I epu Back Off. A deadlock situation can occur when the host and a processor try to read

from each other’s bus at the same time. When deadlock occurs, the host can assert

to force the processor to relinquish the bus before completing its outstanding

BOFF transaction.

BUSLOCK

HBR

O/T (pu_0)

na Bus Lock Indication. Provides an indication that the current bus master has locked

the bus. At reset, this is a strap pin. For more information, see Table 16 on Page 18.

I epu Host Bus Request. A host must assert HBR to request control of the processor’s

external bus. When HBR

is asserted in a multiprocessing system, the bus master

relinquishes the bus and asserts HBG once the outstanding transaction is finished.

HBG

I/O/T (pu_0)

epu

2

Host Bus Grant. Acknowledges HBR and indicates that the host can take control of the external bus. When relinquishing the bus, the master processor three-states the ADDR31–0, DATA31–0, MSH

, MSSD3–0, MS1–0, RD, WRL, BMS, BRST, IORD, IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and TM4 pins, and the processor puts the SDRAM in self-refresh mode. The processor asserts HBG until the host deasserts

. In multiprocessor systems, the current bus master processor drives HBG, and

HBR all slave processors monitor it.

CPA

I/O/OD (pu_od_0)

epu

2

Core Priority Access. Asserted while the processor’s core accesses external memory. This pin enables a slave processor to interrupt a master processor’s background DMA transfers and gain control of the external bus for core-initiated transactions.

is an open-drain output, connected to all DSPs in the system. If not required in

CPA the system, leave CPA unconnected (external pull-ups will be required for processor ID = 1 through ID = 7).

DPA

I/O/OD (pu_od_0)

epu

2

DMA Priority Access. Asserted while a high priority processor DMA channel accesses external memory. This pin enables a high priority DMA channel on a slave processor to interrupt transfers of a normal priority DMA channel on a master processor and gain control of the external bus for DMA-initiated transactions. DPA

is an open-drain output, connected to all DSPs in the system. If not required in the system, leave DPA unconnected (external pull-ups will be required for processor ID = 1 through ID = 7).

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to VSS; epu = external pull-up approximately 5 k to V directly to V

1

The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V

2

This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.

SS

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; VSS = connect

DD_IO

.

Rev. D | Page 13 of 48 | May 2012

ADSP-TS203S

Table 7. Pin Definitions—External Port DMA/Flyby

Signal Type Term Description

DMAR3–0

IOWR O/T

IORD

IOEN

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

I/A epu DMA Request Pins. Enable external I/O devices to request DMA services from the

processor. In response to DMARx, the processor performs DMA transfers according to the DMA channel’s initialization. The processor ignores DMA requests from uninitialized channels.

nc I/O Write. When a processor DMA channel initiates a flyby mode read transaction,

(pu_0)

the processor asserts the IOWR signal during the data cycles. This assertion makes the I/O device sample the data instead of the TigerSHARC.

O/T (pu_0)

nc I/O Read. When a processor DMA channel initiates a flyby mode write transaction,

the processor asserts the IORD

signal during the data cycle. This assertion with the

IOEN makes the I/O device drive the data instead of the TigerSHARC.

O/T (pu_0)

nc I/O Device Output Enable. Enables the output buffers of an external I/O device for

fly-by transactions between the device and external memory. Active on flyby transactions.

; epu = external pull-up

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

SS

; VSS = connect

DD_IO

Table 8. Pin Definitions—External Port SDRAM Controller

Signal Type Term Description

MSSD3–0

I/O/T (pu_0)

nc Memor y Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the

processor accesses SDRAM memory space. MSSD3–0

are decoded memory address pins that are asserted whenever the processor issues an SDRAM command cycle (access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 2 on

.

RAS

I/O/T (pu_0)

Page 6). In a multiprocessor system, the master processor drives MSSD3–0

nc Row Address Select. When sampled low, RAS indicates that a row address is valid in

a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to SDRAM specification.

CAS

I/O/T (pu_0)

nc Column Address Select. When sampled low, CAS indicates that a column address is

valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to the SDRAM specification.

LDQM O/T

(pu_0)

nc Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ

buffers. LDQM is valid on SDRAM transactions when CAS

is asserted, and inactive

on read transactions.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; epu = external pull-up

SS

; VSS = connect

DD_IO

Rev. D | Page 14 of 48 | May 2012

ADSP-TS203S

Table 8. Pin Definitions—External Port SDRAM Controller (Continued)

Signal Type Term Description

SDA10 O/T

(pu_0)

SDCKE I/O/T

(pu_m/ pd_m)

SDWE I/O/T

(pu_0)

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

, nc = not connected; na = not applicable (always used); V

DD_IO

nc SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while

the processor executes non-SDRAM transactions.

nc SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend

modes. A slave processor in a multiprocessor system does not have the pull-up or pull-down. A master processor (or ID = 0 in a single processor system) has a pull-up before granting the bus to the host, except when the SDRAM is put in self refresh mode. In self refresh mode, the master has a pull-down before granting the bus to the host.

nc SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an

SDRAM write access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM specification.

; epu = external pull-up

= connect directly to V

DD_IO

SS

; VSS = connect

DD_IO

Table 9. Pin Definitions—JTAG Port

Signal Type Term Description

EMU

O/OD nc

1

Emulation. Connected to the processor’s JTAG emulator target board connector

only. TCK I epd or epu1Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. TDI I

nc

1

Test Data Input (JTAG). A serial data input of the scan path.

(pu_ad)

nc

1

Test Data Output (JTAG). A serial data output of the scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO O/T nc

TMS I

(pu_ad)

TRST

I/A (pu_ad)

na Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed

low after power-up for proper device operation. For more information, see Reset

and Booting on Page 8.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

1

See the reference on Page 10 to the JTAG emulation technical reference EE-68.

SS

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; epu = external pull-up

SS

; VSS = connect

DD_IO

Rev. D | Page 15 of 48 | May 2012

ADSP-TS203S

Table 10. Pin Definitions—Flags, Interrupts, and Timer

Signal Type Term Description

FLAG3–0 I/O/A

(pu)

IRQ3–0

I/A (pu)

TMR0E O na Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

DD_IO

Table 11. Pin Definitions—Link Ports

Signal Type Term Description

LxDATO3–0P O nc Link Ports 1–0 Data 1–0 Transmit LVDS P LxDATO3–0N O nc Link Ports 1–0 Data 1–0 Transmit LVDS N LxCLKOUTP O nc Link Ports 1–0 Transmit Clock LVDS P LxCLKOUTN O nc Link Ports 1–0 Transmit Clock LVDS N LxACKI I (pd) nc Link Ports 1–0 Receive Acknowledge. Using this signal, the receiver indicates to the

LxBCMPO

O (pu) nc Link Ports 1–0 Block Completion. When the transmission is executed using DMA,

LxDATI3–0P I V LxDATI3–0N I V LxCLKINP I/A V LxCLKINN I/A V LxACKO O nc Link Ports 1–0 Transmit Acknowledge. Using this signal, the receiver indicates to the

LxBCMPI

I (pd_l) V

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

DD_IO

nc FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin

can be configured individually for input or for output. FLAG3–0 are inputs after powerup and reset.

nc Interrupt Request. When asserted, the processor generates an interrupt. Each of the

pins can be independently set for edge-triggered or level-sensitive operation.

IRQ3–0 After reset, these pins are disabled unless the IRQ3–0 strap option and interrupt vectors are initialized for booting.

For more information, see Table 16 on Page 18.

; epu = external pull-up

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

SS

DD_IO

transmitter that it may continue the transmission.

this signal indicates to the receiver that the transmitted block is completed. The pull-up resistor is present on L0BCMPO

only. At reset, the L1BCMPO pin is a strap

pin. For more information, see Table 16 on Page 18.

DD_IO

Link Ports 1–0 Data 3–0 Receive LVDS P Link Ports 1–0 Data 3–0 Receive LVDS N Link Ports 1–0 Receive Clock LVDS P Link Ports 1–0 Receive Clock LVDS N

transmitter that it may continue the transmission.

SS

Link Ports 1–0 Block Completion. When the reception is executed using DMA, this signal indicates to the receiver that the transmitted block is completed.

; epu = external pull-up

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

SS

DD_IO

; VSS = connect

Rev. D | Page 16 of 48 | May 2012

ADSP-TS203S

Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable

Signal Type Term Description

CONTROLIMP0 CONTROLIMP1

DS2, 0 DS1

ENEDREG I (pu) V

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

I (pd) I (pu)

na na

Impedance Control. As shown in Tab le 1 3, the CONTROLIMP1–0 pins select between normal driver mode and A/D driver mode. When using normal mode (recommended), the output drive strength is set relative to maximum drive strength according to

Tab le 1 4. When using A/D mode, the resistance control operates in the analog mode,

where drive strength is continuously controlled to match a specific line impedance as shown in Tab le 1 4.

I (pu) I (pd)

na Digital Drive Strength Selection. Selected as shown in Tab le 1 4. For drive strength

calculation, see Output Drive Currents on Page 34. The drive strength for some pins is preset, not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%) include: CPA

, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin

is always ×2 drive strength 7 (100%).

SS

Connect the ENEDREG pin to VSS. Connect the V DRAM power supply.

, nc = not connected; na = not applicable (always used); V

DD_IO

DD_DRAM

= connect directly to V

DD_IO

pins to a properly decoupled

; epu = external pull-up

SS

; VSS = connect

DD_IO

Table 13. Impedance Control Selection

CONTROLIMP1-0 Driver Mode

00 (recommended) Normal 01 Reserved 10 (default) A/D Mode 11 Reserved

Table 14. Drive Strength/Output Impedance Selection

DS2–0 Pins

Drive Strength

1

Output Impedance

000 Strength 0 (11.1%) 26  001 Strength 1 (23.8%) 32  010 Strength 2 (36.5%) 40  011 Strength 3 (49.2%) 50  100 Strength 4 (61.9%) 62  101 (default) Strength 5 (74.6%) 70  110 Strength 6 (87.3%) 96  111 Strength 7 (100%) 120 

1

CONTROLIMP1 = 0, A/D mode disabled.

2

CONTROLIMP1 = 1, A/D mode enabled.

2

Rev. D | Page 17 of 48 | May 2012

ADSP-TS203S

Table 15. Pin Definitions—Power, Ground, and Reference

Signal Type Term Description

V

DD

V

DD_A

V

DD_IO

V

DD_DRAM

V

REF

SCLK_V

REF

V

SS

NC — nc No Connect. Do not connect these pins to anything (not to any supply, signal, or

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

SS

PnaV PnaV PnaV PnaV

pins for internal logic.

DD

pins for analog circuits. Pay critical attention to bypassing this supply.

DD

pins for I/O buffers.

DD

pins for internal DRAM.

DD

I na Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN,

, IRQ3–0, FLAG3–0, DMAR3–0, ID2–0, CONTROLIMP1–0, LxDATO3–0P/N,

POR_IN LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST. V

REF

can be connected to a power supply or set by a voltage divider circuit as shown in Figure 4.

For more information, see Filtering Reference Voltage and Clocks on Page 8.

I na System Clock Reference. Connect this pin to a reference voltage as shown in

Figure 5. For more information, see Filtering Reference Voltage and Clocks on Page 8.

GnaGround pins.

each other). These pins are reserved and must be left unconnected.

; epu = external pull-up

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

SS

; VSS = connect

DD_IO

STRAP PIN FUNCTION DESCRIPTIONS

Some pins have alternate functions at reset. Strap options set processor operating modes. During reset, the processor samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value. If a strap pin is not connected to an overdriving external pull-up, pull-down, or logic load, the processor samples the default value during reset. If strap pins

Table 16. Pin Definitions—I/O Strap Pins

Type (at

Signal

EBOOT I (pd_0) BMS

Reset) On Pin … Description

EPROM Boot.

0 = boot from EPROM immediately after reset (default) 1 = idle after reset and wait for an external device to boot processor through the

external port or a link port

IRQEN I (pd) BM Interrupt Enable.

0 = disable and set IRQ3–0 1 = enable and set IRQ3–0

LINK_DWIDTH I (pd) TMR0E Link Port Input Default Data Width.

0 = 1-bit (default) 1 = 4-bit

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

are connected to logic inputs, a stronger external pull-up or pull-down may be required to ensure default value depending on leakage and/or low level input current of the logic load. To set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pull-up or pull-down. Table 16 lists and describes each of the processor’s strap pins.

interrupts to edge-sensitive after reset (default)

interrupts to level-sensitive immediately after reset

Rev. D | Page 18 of 48 | May 2012

ADSP-TS203S

Table 16. Pin Definitions—I/O Strap Pins (Continued)

Type (at

Signal

SYS_REG_WE I (pd_0) BUSLOCK SYSCON and SDRCON Write Enable.

TM1 I (pu) L1BCMPO Test Mode 1. Do not overdrive default value during reset. TM2 I (pu) TM2 Test Mode 2. Do not overdrive default value during reset. TM3 I (pu) TM3 Test Mode 3. Do not overdrive default value during reset. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

When default configuration is used, no external resistor is needed on the strap pins. To apply other configurations, a 500 Ω resistor connected to V pull-downs, do not strap these pins directly to V pins require 500 Ω resistor straps.

All strap pins are sampled on the rising edge of RST_IN sertion edge). Each pin latches the strapped pin state (state of the strap pin at the rising edge of RST_IN sertion of RST_IN functionality.

These strap pins have an internal pull-down resistor, pull-up resistor, or no-resistor (three-state) on each pin. The resistor type, which is connected to the I/O pad, depends on whether RST_IN

is active (low) or if RST_IN is deasserted (high).

Table 17 shows the resistors that are enabled during active reset

and during normal operation.

Reset) On Pin … Description

0 = one-time writable after reset (default) 1 = always writable

is required. If providing external

DD_IO

; the strap

SS

(deas-

). Shortly after deas-

, these pins are reconfigured to their normal

Table 17. Strap Pin Internal Resistors—Active Reset (RST_IN

Pin RST_IN = 0 RST_IN = 1

BMS BM TMR0E (pd) Driven BUSLOCK (pd_0) (pu_0) L1BCMPO TM2 (pu) Driven TM3 (pu) Driven

pd = internal pull-down 5 k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0

= 0) vs. Normal Operation (RST_IN = 1)

(pd_0) (pu_0) (pd) Driven

(pu) Driven

Rev. D | Page 19 of 48 | May 2012

ADSP-TS203S

SPECIFICATIONS

Note that component specifications are subject to change with out notice. For information on link port electrical characteristics, see Link Port Low Voltage, Differential-Signal (LVDS)

Electrical Characteristics, and Timing on Page 29.

OPERATING CONDITIONS

Parameter Description Test Conditions Grade

V

DD

V

DD_A

V

DD_IO

V

DD_DRAM

T

CASE

T

CASE

V

IH1

V

IH2

V

IL

I

DD

Internal Supply Voltage @ CCLK = 500 MHz 050 1.00 1.05 1.10 V Analog Supply Voltage @ CCLK = 500 MHz 050 1.00 1.05 1.10 V I/O Supply Voltage (all) 2.38 2.50 2.63 V Internal DRAM Supply Voltage @ CCLK = 500 MHz 050 1.425 1.500 1.575 V Case Operating Temperature A –40 +85 °C Case Operating Temperature B 0 +85 °C High Level Input Voltage2, High Level Input Voltage3, Low Level Input Voltage3,

VDD Supply Current, Typical Activity

3

4

5

@ VDD, V @ VDD, V @ VDD, V @ CCLK = 500 MHz, VDD = 1.05 V,

6

= 25°C 050 2.06 A

T

CASE

= Max (all) 1.7 3.63 V

DD_IO

= Max (all) 1.9 3.63 V

DD_IO

= Min (all) –0.33 +0.8 V

DD_IO

1

Min Typ Max Unit

@ CCLK = 500 MHz, VDD = 1.05 V,

I

DD_A

I

DD_IO

I

DD_DRAM

V

REF

SCLK_V

1

Specifications vary for different grades (for example, SABP–060, SABP–050, SWBP–050). For more information on part grades, see Ordering Guide on Page 47.

2

V

specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0, RAS,

IH1

CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG.

3

Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in Table 18, based on the transient duty cycle. The dc case is

equivalent to 100% duty cycle.

4

V

specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.

IH2

5

Applies to input and bidirectional pins.

6

For details on internal and external power calculation issues, including other operating conditions, see EE-170, Estimating Power for the ADSP-TS203S.

V

Supply Current, Typical Activity

DD_A

V

Supply Current, Typical Activity

DD_IO

V Typical Activity

DD_DRAM

Supply Current,

6

T

= 25°C 050 20 50 mA

CASE

@ SCLK = 62.5 MHz, V

6

T

= 25°C (all) 0.15 A

CASE

@ CCLK = 500 MHz, V T

= 25°C 050 0.25 0.40 A

CASE

= 2.5 V,

DD_IO

DD_DRAM

= 1.5 V,

Voltage Reference (all) (V Voltage Reference (all) (V

REF

×0.56)±5% V

DD_IO

CLOCK_DRIVE

× 0.56) ±5% V

Table 18. Maximum Duty Cycle for Input Transient Voltage

2

VIN Max (V)

1

VIN Min (V)

1

Maximum Duty Cycle

+3.63 –0.33 100% +3.64 –0.34 90% +3.70 –0.40 50% +3.78 –0.48 30% +3.86 –0.56 17% +3.93 –0.63 10%

1

The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the voltages

specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle.

2

Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. This is equivalent to the measured duration of a single instance of overshoot or

undershoot as a percentage of the period of occurrence. The practical worst case for period of occurrence for either overshoot or undershoot is 2 × t

Rev. D | Page 20 of 48 | May 2012

SCLK

.

ADSP-TS203S

ELECTRICAL CHARACTERISTICS

ParameterDescription

V

OH

V

OL

I

High Level Input Current @ V

IH

I

IH_PU

I

IH_PD

I

IH_PD_L

I

Low Level Input Current @ V

IL

I

IL_PU

I

IL_PU_AD

I

OZH

I

OZH_PD

Three-State Leakage Current Low @ V

I

OZL

I

OZL_PU

I

OZL_PU_AD

I

OZL_OD

C

IN

High Level Output Voltage Low Level Output Voltage

High Level Input Current @ V High Level Input Current @ V

High Level Input Current @ V

Low Level Input Current @ V Low Level Input Current @ V Three-State Leakage Current High @ V Three-State Leakage Current High @ V

Three-State Leakage Current Low @ V Three-State Leakage Current Low @ V Three-State Leakage Current Low @ V Input Capacitance

2, 3

1

Parameter name suffix conventions: no suffix = applies to pins without pull-up or pull-down resistors, _PD = applies to pin types (pd) or (pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD, _PD_L = applies to pin types (pd_l)

1

Applies to output and bidirectional pins.

2

Applies to all signals.

3

Guaranteed but not tested.

Test Conditions Min Max Unit

@ V @ V

@ fIN=1 MHz, T

=Min, IOH = –2 mA 2.18 V

DD_IO

=Min, IOL=4 mA 0.4 V

DD_IO

=Max, VIN=VIH Max 20 µA

DD_IO

=Max, VIN=VIH Max 20 µA

DD_IO

=Max, VIN=V

DD_IO

=Max, VIN=VIH Max 30 76 µA

DD_IO

=Max, VIN=0 V 20 µA

DD_IO

=Max, VIN=0 V 0.3 0.76 mA

DD_IO

=Max, VIN= 0 V 30 100 µA

DD_IO

=Max, VIN=VIH Max 50 µA

DD_IO

=Max, VIN=V

DD_IO

=Max, VIN=0 V 20 µA

DD_IO

=Max, VIN=0 V 0.3 0.76 mA

DD_IO

=Max, VIN= 0 V 30 100 µA

DD_IO

=Max, VIN =0 V 4 7.6 mA

DD_IO

CASE

Max 0.3 0.76 mA

DD_IO

Max 0.3 0.76 mA

DD_IO

= 25°C, VIN=2.5 V 3 pF

Rev. D | Page 21 of 48 | May 2012

ADSP-TS203S

tppzccc 2.0

T

ADSP-TS203S

a

#yyww country_of_origin

BBPZ050

vvvvvv

ESD

(electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 6 provide details about the package branding for the ADSP-TS203S processors. For a complete listing of product availability, see Ordering Guide on

Page 47.

Figure 6. Typical Package Brand

Table 19. Package Brand Information

Brand Key Field Description

t Temperature Range pp Package Type Z Lead Free Option (optional) ccc See Ordering Guide tppzccc Silicon Lot Number

2.0 Silicon Revision yyww Date Code vvvvvv Assembly Lot Code

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 20 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 20. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V Analog (PLL) Supply Voltage (V External (I/O) Supply Voltage (V

)–0.3 V to +1.4 V

DD

)–0.3 V to +1.4 V

DD_A

)–0.3 V to +3.5 V

DD_IO

External (DRAM) Supply Voltage (V

DD_DRAM

Input Voltage Output Voltage Swing –0.5 V to V

)–0.3 V to +2.1 V

1

–0.63 V to +3.93 V

+0.5 V

DD_IO

Storage Temperature Range –65°C to +150°C

1

Applies to 10% transient duty cycle. For other duty cycles see Table 18.

ESD SENSITIVITY

Rev. D | Page 22 of 48 | May 2012

ADSP-TS203S

CCLK

t

CCLK

TIMING SPECIFICATIONS

With the exception of DMAR3–0, IRQ3–0, TMR0E, and FLAG3–0 (input only) pins, all ac timing for the ADSP-TS203S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSP-TS203S processor has few calculated (formula-based) values. For information on ac timing, see General AC Timing. For information on link port transfer timing, see Link Port Low

Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing on Page 29.

General AC Timing

Timing is measured on signals when they cross the 1.25 V level as described in Figure 13 on Page 28. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.25 V and the point that the second signal reaches

1.25 V.

Table 21. AC Asynchronous Signal Specifications

Name Description Pulse Width Low (Min) Pulse Width High (Min)

1

IRQ3–0 DMAR3–0 FLAG3–0 TMR0E

1

These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.

2

For output specifications on FLAG3–0 pins, see Table 29.

3

This pin is a strap option. During reset, an internal resistor pulls the pin low.

1

2

3

Interrupt Request DMA Request 2 × t FLAG3–0 Input 2× t Timer 0 Expired 4× t

The general ac timing data appears in Table 22 and Table 29. All ac specifications are measured with the load specified in

Figure 34 on Page 36, and with the output drive strength set to

strength 4. In order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to Figure 35 on Page 36 through Figure 42 on Page 38 (Rise and Fall Time vs. Load Capacitance) and Figure 43 on Page 38 (Output Valid vs. Load Capacitance and Drive Strength).

The ac asynchronous timing data for the IRQ3–0

, DMAR3–0,

FLAG3–0, and TMR0E pins appears in Table 21.

2× t

ns

SCLK

ns 2 × t

SCLK

ns 2× t

SCLK

ns

SCLK

2× t

SCLK

ns ns

ns

Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time

Grade = 050 (500 MHz)

Parameter Description

1

t

CCLK

1

CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t

(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 47.

Core Clock Cycle Time 2.0 12.5 ns

) divided by the system clock ratio

SCLK

Figure 7. Reference Clocks—Core Clock (CCLK) Cycle Time

UnitMin Max

Rev. D | Page 23 of 48 | May 2012

ADSP-TS203S

SCLK

t

SCLK

t

SCLKH

t

SCLKL

t

SCLKJ

t

SCLKF

t

SCLKR

TCK

t

TCK

t

TCKH

t

TCKL

Table 23. Reference Clocks—System Clock (SCLK) Cycle Time

SCLKRAT = 4×, 6×, 8×, 10×, 12× SCLKRAT = 5×, 7×

Parameter Description

1, 2, 3

t

SCLK

t

SCLKH

t

SCLKL

t

SCLKF

t

SCLKR

5, 6

t

SCLKJ

1

For more information, see Table 3 on Page 11.

2

For more information, see Clock Domains on Page 8.

3

The value of (t

4

System clock transition times apply to minimum SCLK cycle time (t

5

Actual input jitter should be combined with ac specifications for accurate timing analysis.

6

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

System Clock Cycle Time 8 50 8 50 ns System Clock Cycle High Time 0.40 × t System Clock Cycle Low Time 0.40 × t System Clock Transition Time—Falling Edge

4

System Clock Transition Time—Rising Edge 1.5 1.5 ns System Clock Jitter Tolerance 500 500 ps

/ SCLKRAT2-0) must not violate the specification for t

SCLK

CCLK

) only.

.

SCLK

UnitMin Max Min Max

0.60 × t

SCLK

0.45 × t

SCLK

0.55 × t

SCLK

ns ns

1.5 1.5 ns

Figure 8. Reference Clocks—System Clock (SCLK) Cycle Time

Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time

Parameter Description Min Max Unit

t

TCK

t

TCKH

t

TCKL

Test Clock (JTAG) Cycle Time Greater of 30 or t

× 4 ns

CCLK

Test Clock (JTAG) Cycle High Time 12 ns Test Clock (JTAG) Cycle Low Time 12 ns

Figure 9. Reference Clocks—JTAG Test Clock (TCK) Cycle Time

Rev. D | Page 24 of 48 | May 2012

ADSP-TS203S

V

DD

V

DD_A

V

DD_IO

V

DD_DRAM

t

VDD_DRAM

RST_OUT

t

RST_OUT_PWR

TRST

t

TRST_IN_PWR

SCLK, V

DD,VDD_A,

V

DD_IO,VDD_DRAM

STATIC/STRAP PINS

RST_IN

t

RST_IN_PWR

Table 25. Power-Up Timing

1

Parameter Min Max Unit

Timing Requirement

t

VDD_DRAM

1

For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing.

V

DD_DRAM

Stable After VDD, V

DD_A

, V

Stable >0 ms

DD_IO

Figure 10. Power-Up Timing

Table 26. Power-Up Reset Timing

Parameter Min Max Unit

Timing Requirements

t

RST_IN_PWR

RST_IN Deasserted After VDD, V

DD_A

, V

DD_IO

, V

DD_DRAM

, SCLK, and Static/

Strap Pins Stable 2 ms

t

TRST_IN_PWR

1

TRST Asserted During Power-Up Reset 100 × t

SCLK

ns

Switching Characteristic

t

RST_OUT_PWR

1

Applies after VDD, V

RST_OUT Deasserted After RST_IN Deasserted 1.5 ms

, V

DD_A

DD_IO

, V

, and SCLK are stable and before RST_IN deasserted.

DD_DRAM

Figure 11. Power-Up Reset Timing

Rev. D | Page 25 of 48 | May 2012

ADSP-TS203S

STRAP PINS

t

STRAP

RST_IN

t

RST_IN

RST_OUT

t

RST_OUT

Table 27. Normal Reset Timing

Parameter Min Max Unit

Timing Requirements

t

RST_IN

t

STRAP

Switching Characteristic

t

RST_OUT

RST_IN Asserted 2 ms RST_IN Deasserted After Strap Pins Stable 1.5 ms

RST_OUT Deasserted After RST_IN Deasserted 1.5 ms

Figure 12. Normal Reset Timing

Table 28. On-Chip DRAM Refresh

1

Parameter Min Max Unit

Timing Requirement

t

REF

1

For more information on setting the refresh rate for the on-chip DRAM, refer to the ADSP-TS201 TigerSHARC Processor Programming Reference.

On-chip DRAM Refresh Period 1.56 s

Rev. D | Page 26 of 48 | May 2012

ADSP-TS203S

Table 29. AC Signal Specifications

(All values in this table are in nanoseconds.)

1

Input Setup

(Min)

Input Hold

(Min)

Output Valid

(Max)

Output Hold

(Min)

Output Enable

(Min)

Output Disable

Name Description

ADDR31–0 External Address Bus 1.5 0.5 4.0 1.0 1.15 2.0 SCLK DATA31–0 External Data Bus 1.5 0.5 4.0 1.0 1.15 2.0 SCLK MSH MSSD3–0 MS1–0 RD WRL

Memory Select HOST Line — — 4.0 1.0 1.15 2.0 SCLK Memory Select SDRAM Lines 1.5 0.5 4.0 1.0 1.0 2.0 SCLK Memory Select for Static Blocks — — 4.0 1.0 1.15 2.0 SCLK Memory Read 1.5 0.5 4.0 1.0 1.15 2.0 SCLK Write Low Word 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

ACK Acknowledge for Data High to Low 1.5 0.5 3.6 1.0 1.15 2.0 SCLK

Acknowledge for Data Low to High 1.5 0.5 4.2 0.9 1.15 2.0 SCLK SDCKE SDRAM Clock Enable 1.5 0.5 4.0 1.0 1.15 2.0 SCLK RAS CAS SDWE

Row Address Select 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

Column Address Select 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

SDRAM Write Enable 1.5 0.5 4.0 1.0 1.15 2.0 SCLK LDQM Low Word SDRAM Data Mask — — 4.0 1.0 1.15 2.0 SCLK SDA10 SDRAM ADDR10 — — 4.0 1.0 1.15 2.0 SCLK HBR HBG BOFF BUSLOCK BRST BR7–0 BM IORD IOWR IOEN CPA

Host Bus Request 1.5 0.5 — — — — SCLK

Host Bus Grant 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

Back Off Request 1.50.5————SCLK

Bus Lock — — 4.0 1.0 1.15 2.0 SCLK

Burst Pin 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

Multiprocessing Bus Request Pins 1.5 0.5 4.0 1.0 — — SCLK

Bus Master Debug Aid Only — — 4.0 1.0 — — SCLK

I/O Read Pin — — 4.0 1.0 1.0 2.0 SCLK

I/O Write Pin — — 4.0 1.0 1.15 2.0 SCLK

I/O Enable Pin — — 4.0 1.0 1.15 2.0 SCLK

Core Priority Access High to Low 1.5 0.5 4.0 1.0 0.75 2.0 SCLK

Core Priority Access Low to High 1.5 0.5 29.5 2.0 0.75 2.0 SCLK DPA

DMA Priority Access High to Low 1.5 0.5 4.0 1.0 0.75 2.0 SCLK

DMA Priority Access Low to High 1.5 0.5 29.5 2.0 0.75 2.0 SCLK BMS FLAG3–0 RST_IN

2

3, 4

Boot Memory Select — — 4.0 1.0 1.15 2.0 SCLK

FLAG Pins — — 4.0 1.0 1.15 2.0 SCLK

Global Reset Pin 1.5 2.5 — — — — SCLK TMS Test Mode Select (JTAG) 1.5 0.5 — — — — TCK TDI Test Data Input (JTAG) 1.5 0.5 — — — — TCK TDO Test Data Output (JTAG) — — 4.0 1.0 0.75 2.0 TCK

3, 4

TRST

7

EMU

8

ID2–0 CONTROLIMP1–0

8

DS2–0 SCLKRAT2–0

8

Test Reset (JTAG) 1.5 0.5 — — — — TCK

Emulation High to Low — — 5.5 2.0 1.15 4.0 TCK or SCLK

Static Pins—Must Be Constant — — — — — — —

(Max)1Reference

Clock

5

6

Rev. D | Page 27 of 48 | May 2012

ADSP-TS203S

REFERENCE

CLOCK

INPUT

SIGNAL

OUTPUT

SIGNAL

THREE-

STATE

OUTPUT

VALID

OUTPUT

HOLD

OUTPUT ENABLE

OUTPUT

DISABLE

INPUT

HOLD

INPUT

SETUP

1.25V

t

SCLK

OR t

TCK

Table 29. AC Signal Specifications (Continued)

(All values in this table are in nanoseconds.)

1

Input Setup

(Min)

Input Hold

(Min)

Output Valid

(Max)

Output Hold

(Min)

Output Enable

(Min)

Output Disable

Name Description

(Max)1Reference

ENEDREG Static Pins—Must Be Connected to VSS——————— STRAP SYS JTAG SYS

1

The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The

apparent driver overlap, due to output disables being larger than output enables, is not actual.

2

For input specifications on FLAG3–0 pins, see Table 21.

3

These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.

4

For additional requirement details, see Reset and Booting on Page 8.

5

RST_IN clock reference is the falling edge of SCLK.

6

TDO output clock reference is the falling edge of TCK.

7

Reference clock depends on function.

8

These pins may change only during reset; recommend connecting it to V

9

STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, TM2, and TM3.

10

Specifications applicable during reset only.

11

JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN,

BUSLOCK, TMR0E, DATA31–0, ADDR31–0, RD, WRL, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0, L1DATOP3–0, L1DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L0ACKI, L1ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L0ACKO, L1ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L0BCMPI, L1BCMPI, ID2–0, CTRL_IMPD1–0, SCLKRAT2–0, DS2–0, ENEDREG, TM2, TM3, TM4.

12

JTAG system output timing clock reference is the falling edge of TCK.

9, 10

11, 12

Strap Pins 1.50.5————SCLK JTAG System Pins +2.5 +10.0 +12.0 –1.0 — — TCK

DD_IO/VSS

.

Clock

Figure 13. General AC Parameters Timing

Rev. D | Page 28 of 48 | May 2012

ADSP-TS203S

V

O_N

V

O_P

R

L

V

OCM

=

(V

O_P+VO_N

)

2

VOD=(V

O_P–VO_N

)

Lx<PIN>N

Lx<PIN>P

Lx<PIN>

DI FF EREN TIA L PA IR W AVE FORM S

DIFFERENTIAL VOLTAGE WAVEFORM

V

OD

=0V

V

O_N

V

O_P

VOD=V

O_P–VO_N

Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing

Table 30 and Table 31 with Figure 14 provide the electrical

characteristics for the LVDS link ports. The LVDS link port signal definitions represent all differential signals with a V level and use signal naming without N (negative) and P (positive) suffixes (see Figure 15).

Table 30. Link Port LVDS Transmit Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

V

OH

V

OL

|V

| Output Differential Voltage RL = 100  300 650 mV

OD

I

OS

V

OCM

Output Voltage High, V Output Voltage Low, V

O_P

or V

O_N

Short-Circuit Output Current V

Common-Mode Output Voltage 1.20 1.50 V

Table 31. Link Port LVDS Receive Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

| Differential Input Voltage t

|V

ID

V

ICM

Common-Mode Input Voltage 0.6 1.57 V

OD

=0V

RL = 100  1.85 V RL = 100  0.92 V

or V

O_P

V

= 0 V ±10 mA

OD

LDIS/tLDIH

t

LDIS/tLDIH

t

LDIS/tLDIH

t

LDIS/tLDIH

= 0 V +5/–55 mA

O_N

≥ 0.20 ns ≥ 0.25 ns ≥ 0.30 ns ≥ 0.35 ns

250 217 206 195

850 850 850 850

mV mV mV mV

Figure 14. Link Ports—Transmit Electrical Characteristics

Figure 15. Link Ports—Signals Definition

Rev. D | Page 29 of 48 | May 2012

ADSP-TS203S

LxCLKOUT

VOD=0V

t

COJT

t

LCLKOL

t

LCLKOH

t

LCLKOP

Link Port—Data Out Timing

Table 32 with Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, and Figure 21 provide the data out timing for the

LVDS link ports.

Table 32. Link Port—Data Out Timing

Parameter Description Min Max Unit

Outputs

t

REO

t

FEO

t

LCLKO P

t

LCLKO H

t

LCLKO L

t

COJT

t

LDOS

t

LDOH

t

LACKID

t

BCMPOV

t

BCMPOH

Inputs

t

LACKIS

t

LACKIH

1

Timing is relative to the 0 differential voltage (VOD = 0).

2

LCR (link port clock ratio) = 1, 1.5, 2, or 4. t

3

For the cases of t

4

LCR = 1.

5

LCR = 1.5.

6

LCR = 2.

7

LCR = 4.

8

The t

LDOS

9

TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × t

Rising Edge (Figure 17)350ps Falling Edge (Figure 17)350ps LxCLKOUT Period (Figure 16) Greater of 4.0 or

0.9 × LCR × t LxCLKOUT High (Figure 16)0.4×t LxCLKOUT Low (Figure 16)0.4×t

LCLKO P

CCLK

1

1, 2, 3

LxCLKOUT Jitter (Figure 16)±150

LxDATO Output Setup (Figure 18)0.25 × LCR×t

0.25 × LCR × t

0.25 × LCR × t LxDATO Output Hold (Figure 18)0.25 × LCR×t

0.25 × LCR × t

CCLK

–0.10 × t –0.15 × t –0.30 × t

CCLK

1, 4, 8

1, 5, 6, 8

1, 7, 8

1, 4, 8

1, 5, 6, 8

1, 7, 8

Delay from LxACKI rising edge to first trans-

Smaller of 12.5 or

1.1 × LCR × t

0.6 × t

±250

16 × LCR × t

LCLK OP

4, 5, 6

7

CCLK

1

CCLK

1, 2

1, 2, 3

ns

ns ns ps

ps ns

ns ns

ns ns ns

ns

mission clock edge (Figure 19) LxBCMPO Valid (Figure 19)2×LCR×t LxBCMPO Hold (Figure 20)3×TSW–0.5

1, 9

CCLK

1, 2

ns ns

LxACKI low setup to guarantee that the transmitter stops transmitting (Figure 20) LxACKI high setup to guarantee that the transmitter continues its transmission without any interruption (Figure 21)16×LCR×t

CCLK

1, 2

ns

LxACKI High Hold Time (Figure 21)0.51 ns

is the core period.

CCLK

= 12.5 ns, the effect of t

LCLKOP

specification on output period must be considered.

COJT

. For a 1-bit link, it is 8 × LCR × t

CCLK

ns.

and t

= 4.0 ns and t

LCLKOP

values include LCLKOUT jitter.

LDOH

Figure 16. Link Ports—Output Clock

Rev. D | Page 30 of 48 | May 2012

ADSP-TS203S

+|V

OD|

MIN

-

|

V

OD|

MIN

V

OD

=0V

t

REO

t

FEO

V

O_N

V

O_P

R

L

C

L

C

L_P

C

L_N

RL=100V

C

L

=0.1pF

C

L_P

=5pF

C

L_N

=5pF

LxCLKOUT

LxDATO

VOD=0V

V

OD

=0V

t

LDOStLDOHtLDOStLDOH

LxCLKOUT

LxDATO

VOD=0V

V

OD

=0V

t

LACK ID

t

BCMPOV

LxACKI

LxBCMPO

Figure 17. Link Ports—Differential Output Signals Transition Time

Figure 18. Link Ports—Data Output Setup and Hold

1

These parameters are valid for both clock edges.

1

Figure 19. Link Ports—Transmission Start

Rev. D | Page 31 of 48 | May 2012

ADSP-TS203S

LxCLKOUT

LxDATO

VOD=0V

V

OD

=0V

FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD

t

LACKIS

t

BCMPOH

LxACKI

LxBCMPO

t

LACKIH

LAST EDGE IN A QUAD WORD

LxCLKOUT

LxDATO

VOD=0V

V

OD

=0V

t

LACKIS

LxACKI

t

LACKIH

LAST EDGE IN A QUAD WORD

Figure 20. Link Ports—Transmission End and Stops

Figure 21. Link Ports—Back to Back Transmission

Rev. D | Page 32 of 48 | May 2012

ADSP-TS203S

LxCLKIN

LxDATI

VOD=0V

V

OD

=0V

t

BCMPIS

LxBCMPI

t

BCMPIH

FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD

Link Port—Data In Timing

Table 33 with Figure 22 and Figure 23 provide the data in

timing for the LVDS link ports.

Table 33. Link Port—Data In Timing

Parameter Description Min Max Unit

Inputs

t

LCLK IP

t

LDIS

t

LDIH

t

BCMPIS

t

BCMPIH

1

Timing is relative to the 0 differential voltage (VOD = 0).

2

|VID| = 250 mV.

3

|VID| = 217 mV.

4

|VID| = 206 mV.

5

|VID| = 195 mV.

LxCLKIN Period (Figure 23) Greater of 1.8

or 0.9 × t

LxDATI Input Setup (Figure 23)0.20

1, 2

0.251,

0.301,

0.351,

0.25

0.30

0.35

1, 2

1, 3

1, 4

1, 5

LCLK IP

LxDATI Input Hold (Figure 23)0.20

LxBCMPI Setup (Figure 22)2×t LxBCMPI Hold (Figure 22)2×t

1

CCLK

3

4

5

1

12.5 ns ns

ns ns ns

ns ns ns ns

ns ns

Figure 22. Link Ports—Last Received Quad Word

Rev. D | Page 33 of 48 | May 2012

ADSP-TS203S

LxCLKIN

LxDATI

VOD=0V

V

OD

=0V

t

LDIStLDIHtLDIStLDIH

t

LCLKIP

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–2.5

0

2.5

V

DD_IO

= 2.38V, +105°C

–5.0

–7.5

–10.0

–12.5

–15.0

5.0

7.5

10.0

12.5

15.0

STRENGTH 0

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

I

OL

I

OH

V

DD_IO

=2.38V,+105°C

V

DD_IO

=2.5V, +25°C

V

DD_IO

=2.63V,–40°C

OUTPUT PIN VOLTAGE (V)

02.80.4

0.8

1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–5

0

5

V

DD_IO

= 2.38V, +105°C

–10

–15

–20

–25

10

15

20

25

30

STRENGTH 1

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

I

OL

I

OH

V

DD_IO

= 2.38V, +105°C

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

–30

OUTPUT PIN VOLTAGE (V)

02.80.4

0.8

1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–9

0

9

V

DD_IO

= 2.38V, +105°C

–18

–27

–36

–45

18

36

45

STRENGTH 2

V

DD_IO

= 2.5V, +25°C

V

DD_IO

=2.63V,–40°C

I

OL

I

OH

V

DD_IO

=2.38V,+105°C

V

DD_IO

= 2.5V, +25°C

V

DD_IO

= 2.63V, –40°C

27

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–11

0

11

V

DD_IO

= 2.38V, +105°C

–22

–33

–44

–55

22

33

44

55

STRENGTH 3

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

I

OL

I

OH

V

DD_IO

= 2.38V, +105°C

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

Figure 23. Link Ports—Data Input Setup and Hold

1

These parameters are valid for both clock edges.

1

OUTPUT DRIVE CURRENTS

Figure 24 through Figure 31 show typical I–V characteristics for

the output drivers of the ADSP-TS203S processor. The curves in these diagrams represent the current drive capability of the output drivers as a function of output voltage over the range of drive strengths. For complete output driver characteristics, refer to the processor’s IBIS models, available on the Analog Devices website (www.analog.com).

Figure 25. Typical Drive Currents at Strength 1

Figure 26. Typical Drive Currents at Strength 2

Figure 24. Typical Drive Currents at Strength 0

Figure 27. Typical Drive Currents at Strength 3

Rev. D | Page 34 of 48 | May 2012

ADSP-TS203S

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–10

0

10

V

DD_IO

= 2.38V, +105°C

–20

–30

–40

–60

20

30

40

60

70

STRENGTH 4

V

DD_IO

=2.5V,+25°C

V

DD_IO

=2.63V,–40°C

I

OL

I

OH

V

DD_IO

= 2.38V, +105°C

V

DD_IO

=2.5V,+25°C

V

DD_IO

=2.63V,–40°C

50

–50

–70

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–11

0

11

V

DD_IO

= 2.38V, +105°C

–22

–33

–44

–66

22

33

44

66

88

STRENGTH 5

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

I

OL

I

OH

V

DD_IO

= 2.38V, +105°C

V

DD_IO

=2.5V, +25°C

V

DD_IO

= 2.63V, –40°C

77

55

–55

–88

–77

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

0

10

20

V

DD_IO

= 2.38V, +105°C

–10 –20 –30 –40

–100

30

40

50

60

100

STRENGTH 6

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

I

OL

I

OH

V

DD_IO

=2.38V,+105°C

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

70

80

90

–50 –60 –70 –80 –90

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

O

U

T

P

U

T

P

I

N

C

U

R

E

N

T

(

m

A

)

–10

0

10

V

DD_IO

= 2.38V, +105°C

–20 –30 –40 –50

–110

20

30

40

50

110

STRENGTH 7

V

DD_IO

=2.5V,+25°C

V

DD_IO

= 2.63V, –40°C

I

OL

I

OH

V

DD_IO

= 2.38V, +105°C

V

DD_IO

=2.5V,+25°C

V

DD_IO

=2.63V,–40°C

60

70

80

90

100

–60 –70 –80 –90

–100

INPUT

OR

OUTPUT

1.25V 1.25V

t

DECAY

CLVΔ()IL⁄=

Figure 28. Typical Drive Currents at Strength 4

Figure 29. Typical Drive Currents at Strength 5

Figure 31. Typical Drive Currents at Strength 7

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 29 on Page 27. These include output disable time, output

enable time, and capacitive loading. The timing specifications for the processor apply for the voltage reference levels in

Figure 32.

Figure 32. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load, C load current, I

. This decay time can be approximated by the

L

following equation:

and the

L

Figure 30. Typical Drive Currents at Strength 6

The output disable time t t

MEASURED_DIS

t

MEASURED_DIS

switches to when the output voltage decays ΔV from the measured output high or output low voltage. t with test loads C

Rev. D | Page 35 of 48 | May 2012

is the difference between

and t

DIS

as shown in Figure 33. The time

DECAY

is the interval from when the reference signal

is calculated

and IL, and with ΔV equal to 0.4 V.

L

DECAY

ADSP-TS203S

REFERENCE

SIGNAL

t

DIS

OUTPUT STARTS

DRIVING

V

OH (MEASURED)

– DV

V

OL (MEASURED)

+ DV

t

MEASURED_DIS

V

OH (MEASURED)

V

OL (MEASURED)

1.65V

0.85V

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.25V.

OUTPUT STOPS

DRIVING

t

DECAY

t

ENA

t

MEASURED_ENA

t

RAMP

t

RAMP

CLVΔ()ID⁄=

1.25V

TO

OUTPUT

30pF

50V

0

10 20 30 40 50 60 70 80 90 100

0

5

10

15

20

25

RISE TIME

Y = 0.259x + 3.0842

STRENGTH 0

(V

DD_IO

=2.5V)

LOAD CAPACITANCE (pF)

FALL TIME

Y = 0.251x + 4.2245

0 10203040506070 8090100

0

5

10

15

20

25

LOAD CAPACITANCE (pF)

STRENGTH 1

(V

DD_IO

=2.5V)

RISE TI ME

Y = 0.1501

x

+0.05

FALL TIME

Y = 0.1527x + 0.7485

Figure 33. Output Enable/Disable

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The time for the voltage on the bus to ramp by ΔV is dependent on the capacitive load, C This ramp time can be approximated by the following equation:

The output enable time t t

MEASURED_ENA

t

MEASURED_ENA

and t is the interval from when the reference signal

is the difference between

ENA

as shown in Figure 33. The time

RAMP

switches to when the output voltage ramps ΔV from the measured three-stated output level. t C

, drive current ID, and with ΔV equal to 0.4 V.

L

Capacitive Loading

Output valid and hold are based on standard capacitive loads: 30 pF on all pins (see Figure 34). The delay and hold specifications given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. Figure 35 through Figure 42 show how output rise time varies with capacitance. Figure 43 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on

Page 35.) The graphs of Figure 35 through Figure 43 may not be

linear outside the ranges shown.

, and the drive current, ID.

L

is calculated with test load

RAMP

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 35. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 0

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 36. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 1

DD_IO

=2.5V)

Figure 34. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

Rev. D | Page 36 of 48 | May 2012

ADSP-TS203S

0102030405060708090100

0

5

10

15

20

25

LOAD CAPACITANCE (pF)

STREN GTH 2

(V

DD_IO

=2.5V)

RISE TIME

Y = 0.0861

x

+ 0.4712

FALL TIME

Y = 0.0949x + 0.8112

0 102030 40506070 8090100

0

5

10

15

20

25

LOAD CAPACITANCE (pF)

STRENGTH 3

(V

DD_IO

=2.5V)

RISE TIME

Y=0.06

x

+1.1362

FALL TIME

Y = 0.0691x + 1.1158

LOAD CAPACITANCE (pF)

0

10 20 30 40 50 60 70 80 90 100

0

5

10

15

20

25

STRENG TH 4

(V

DD_IO

=2.5V

)

RISE TIME

Y = 0.0573x + 0.9789

FALL TIME

Y = 0.0592x + 1.0629

LOAD CAPACITANCE (pF)

0

10 20 30 40 50 60 70 80 90 100

0

5

10

15

20

25

RISE TIME

Y = 0.0481

x

+0.7889

FALL TIME

Y = 0.0493x + 0.8389

STRENGTH 5

(V

DD_IO

=2.5V)

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 37. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 2

) s n

( S

E M

I T

L L A F

D N A

E S

I R

DD_IO

=2.5V)

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 39. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 4

) s n

( S

E M

I T

L L A F

D N A

E S

I R

DD_IO

=2.5V)

Figure 38. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 3

=2.5V)

DD_IO

Figure 40. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 5

Rev. D | Page 37 of 48 | May 2012

DD_IO

=2.5V)

ADSP-TS203S

LOAD CAPACITANCE (pF)

0

10 20 30 40 50 60 70 80 90 100

0

5

10

15

20

25

RISE TIME

Y = 0.0377

x

+0.7449

FALL TIME

Y = 0.0374x + 0.851

STREN GTH 6

(V

DD_IO

=2.5V)

LOAD CAPACITANCE (pF)

0

10 20 30 40 50 60 70 80 90 100

0

5

10

15

20

25

STRENGTH 7

(V

DD_IO

=2.5V)

RISE TIME

Y = 0.0321

x

+0.6512

FALL TIME

Y = 0.0313x + 0.818

0 102030405060708090100

0

5

10

15

O

U

T

P

U

T

V

A

L

I

D

(

n

s

)

LOAD CAPACITANCE (pF)

1

2

3

4

5

6

7

STRENGTH 0–7

(V

DD_IO

=2.5V)

0

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 41. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 6

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 42. Typical Output Rise and Fall Time (10% to 90%, V vs. Load Capacitance at Strength 7

DD_IO

=2.5V)

Figure 43. Typical Output Valid (V Max Case Temperature and Strength 0 to 7

1

The line equations for the output valid vs. load capacitance are:

= 2.5 V) vs. Load Capacitance at

DD_IO

1

Strength 0: y = 0.0956x + 3.5662 Strength 1: y = 0.0523x + 3.2144 Strength 2: y = 0.0433x + 3.1319 Strength 3: y = 0.0391x + 2.9675 Strength 4: y = 0.0393x + 2.7653 Strength 5: y = 0.0373x + 2.6515 Strength 6: y = 0.0379x + 2.1206 Strength 7: y = 0.0399x + 1.9080

ENVIRONMENTAL CONDITIONS

The ADSP-TS203S processor is rated for performance under T

environmental conditions specified in the Operating

CASE

Conditions on Page 20.

Thermal Characteristics

The ADSP-TS203S processor is packaged in a 25 mm × 25 mm, thermally enhanced ball grid array (BGA_ED). The processor is specified for a case temperature (T T

data sheet specification is not exceeded, a heat sink

CASE

and/or an air flow source may be required. Table 34 shows the thermal characteristics of the BGA_ED package. All parameters are based on a JESD51-9 four-layer 2s2p board. All data are based on 3 W power dissipation.

Table 34. Thermal Characteristics

). To ensure that the

CASE

Rev. D | Page 38 of 48 | May 2012

Parameter Condition Typical Unit

Airflow = 0 m/s 12.9

2

°C/W

Airflow = 1 m/s 10.2 °C/W

1

θ

JA

Airflow = 2 m/s 9.0 °C/W Airflow = 3 m/s 8.0 °C/W

3

θ

JB

4

θ

JC

1

θJA measured per JEDEC standard JESD51-6.

2

θJA = 12.9°C/W for 0 m/s is for vertically mounted boards. For horizontally

mounted boards, use 17.0°C/W for 0 m/s.

3

θJB measured per JEDEC standard JESD51-9.

4

θJC measured by cold plate test method (no approved JEDEC standard).

—7.7°C/W —0.7°C/W

576-BALL BGA_ED PIN CONFIGURATIONS

Figure 44 shows a summary of pin configurations for the

576-ball BGA_ED package, and Table 35 lists the signal-to-ball assignments.

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments

ADSP-TS203S

Ball No. Signal Name

A1 V

SS

A2 NC B2 V A3 V

SS

A4 NC B4 NC C4 NC D4 V

Ball No. Signal Name

B1 NC C1 V

C2 V C3 V

B3 V

SS

Ball No. Signal Name

SS

D1 NC D2 NC D3 NC

SS

A5 NC B5 NC C5 NC D5 NC A6 NC B6 NC C6 NC D6 NC A7 NC B7 NC C7 NC D7 NC A8 NC B8 NC C8 NC D8 NC A9 DATA29 B9 DATA30 C9 DATA31 D9 NC A10 DATA25 B10 DATA26 C10 DATA27 D10 DATA28 A11 DATA23 B11 DATA24 C11 DATA21 D11 DATA22 A12 DATA19 B12 DATA20 C12 DATA17 D12 DATA18 A13 DATA15 B13 DATA16 C13 V

SS

D13 V

SS

A14 DATA11 B14 DATA12 C14 DATA13 D14 DATA14 A15 DATA9 B15 DATA10 C15 DATA7 D15 DATA8 A16 DATA5 B16 DATA6 C16 DATA3 D16 DATA4 A17 DATA1 B17 DATA2 C17 ACK D17 DATA0 A18 WRL

B18 TM4 C18 RD D18 BRST A19 ADDR30 B19 ADDR31 C19 ADDR26 D19 ADDR27 A20 ADDR28 B20 ADDR29 C20 ADDR24 D20 ADDR25 A21 ADDR22 B21 ADDR23 C21 ADDR20 D21 V A22 V

SS

A23 ADDR21 B23 V A24 V

SS

B22 V

SS

C22 V C23 V

B24 ADDR18 C24 V

SS

DD_IO

D22 ADDR19 D23 ADDR17 D24 ADDR16

SS

Rev. D | Page 39 of 48 | May 2012

ADSP-TS203S

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)

Ball No. Signal Name

E1 NC F1 NC G1 MSSD1 H1 V E2 NC F2 MS1 G2 V

Ball No. Signal Name

SS

Ball No. Signal Name

SS

H2 MSH E3 NC F3 NC G3 MS0 H3 MSSD3 E4 NC F4 NC G4 BMS H4 SCLKRAT0 E5 V E6 V E7 V E8 V E9 V E10 V E11 V E12 V E13 V E14 V E15 V E16 V E17 V E18 V E19 V E20 V

SS

DD_IO

SS

DD_IO

SS

DD_IO

SS

DD_IO

SS

DD_IO

SS

F5 V F6 V F7 V F8 V F9 V F10 V F11 V F12 V F13 V F14 V F15 V F16 V F17 V F18 V F19 V F20 V

DD_IO

DD

DD_DRAM

DD

DD_DRAM

DD

DD_IO

G5 V G6 V G7 V G8 V G9 V G10 V G11 V G12 V G13 V G14 V G15 V G16 V G17 V G18 V G19 V G20 V

SS

DD

DD_DRAM

DD

DD_DRAM

DD

DD_IO

H5 V

H6 V

H7 V

H8 V

H9 V

H10 V

H11 V

H12 V

H13 V

H14 V

H15 V

H16 V

H17 V

H18 V

H19 V

H20 V

DD_IO

DD

SS

DD

DD_IO

E21 ADDR15 F21 ADDR13 G21 ADDR7 H21 ADDR3 E22 ADDR14 F22 ADDR12 G22 ADDR6 H22 ADDR2 E23 ADDR11 F23 ADDR9 G23 ADDR5 H23 ADDR1 E24 ADDR10 F24 ADDR8 G24 ADDR4 H24 ADDR0

Rev. D | Page 40 of 48 | May 2012

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)

ADSP-TS203S

Ball No. Signal Name

J1 RAS K1 SDA10 L1 SDWE M1 BR3 J2 CAS K2 SDCKE L2 BR0 M2 SCLKRAT1 J3 V J4 V J5 V J6 V J7 V J8 V J9 V J10 V J11 V J12 V J13 V J14 V J15 V J16 V J17 V J18 V J19 V J20 V

SS

REF

SS

DD

SS

DD

SS

J21 L0ACKO K21 L0DATI1_N L21 L0DATI3_N M21 V J22 L0BCMPI K22 L0DATI1_P L22 L0DATI3_P M22 V

K3 LDQM L3 BR1 M3 BR5 K4 NC L4 BR2 M4 BR6 K5 V K6 V K7 V K8 V K9 V K10 V K11 V K12 V K13 V K14 V K15 V K16 V K17 V K18 V K19 V K20 V

DD_IO

DD

SS

DD_DRAM

DD_IO

L5 V L6 V L7 V L8 V L9 V L10 V L11 V L12 V L13 V L14 V L15 V L16 V L17 V L18 V L19 V L20 V

DD_IO

DD

SS

DD_DRAM

DD_IO

M5 V M6 V M7 V M8 V M9 V M10 V M11 V M12 V M13 V M14 V M15 V M16 V M17 V M18 V M19 V M20 V

DD_IO

DD

SS

DD

DD_IO

SS

J23 L0DATI0_N K23 L0CLKINN L23 L0DATI2_N M23 L0DATO3_N J24 L0DATI0_P K24 L0CLKINP L24 L0DATI2_P M24 L0DATO3_P

Rev. D | Page 41 of 48 | May 2012

ADSP-TS203S

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)

Ball No. Signal Name

N1 ID0 P1 SCLK R1 V N2 V N3 V N4 V N5 V N6 V N7 V N8 V N9 V N10 V N11 V N12 V N13 V N14 V N15 V N16 V N17 V N18 V N19 V N20 V

SS

DD_A

DD_IO

DD

SS

DD

DD_IO

Ball No. Signal Name

P2 SCLK_VREF R2 NC (SCLK) P3 V

SS

Ball No. Signal Name

SS

1

R3 NC (SCLK_VREF)

Ball

No. Signal Name

T1 RST_IN

T2 SCLKRAT2

1

T3 BR4

P4 BM R4 BR7 T4 DS0 P5 V P6 V P7 V P8 V P9 V P10 V P11 V P12 V P13 V P14 V P15 V P16 V P17 V P18 V P19 V P20 V

DD_IO

DD

SS

DD_DRAM

DD_IO

R5 V R6 V R7 V R8 V R9 V R10 V R11 V R12 V R13 V R14 V R15 V R16 V R17 V R18 V R19 V R20 V

DD_IO

DD

SS

DD_DRAM

DD_IO

T5 V

T6 V

T7 V

T8 V

T9 V

T10 V

T11 V

T12 V

T13 V

T14 V

T15 V

T16 V

T17 V

T18 V

T19 V

T20 V

SS

DD

SS

DD

SS

N21 L0DATO2_N P21 L0DATO1_N R21 NC T21 L1DATI0_N N22 L0DATO2_P P22 L0DATO1_P R22 V

SS

N23 L0CLKON P23 L0DATO0_N R23 L0BCMPO

T22 L1DATI0_P

T23 L1ACKO N24 L0CLKOP P24 L0DATO0_P R24 L0ACKI T24 L1BCMPI

Rev. D | Page 42 of 48 | May 2012

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)

ADSP-TS203S

Ball No. Signal Name

U1 MSSD0 V1 MSSD2 W1 CONTROLIMP0 Y1 EMU U2 RST_OUT V2 DS2 W2 ENEDREG Y2 TCK U3 ID2 V3 POR_IN

W3 TDI Y3 TMR0E U4 DS1 V4 CONTROLIMP1 W4 TDO Y4 FLAG3 U5 V U6 V U7 V U8 V U9 V U10 V U11 V U12 V U13 V U14 V U15 V U16 V U17 V U18 V U19 V U20 V

DD_IO

DD

SS

DD

DD_DRAM

SS

DD

DD_IO

V5 V V6 V V7 V V8 V V9 V V10 V V11 V V12 V V13 V V14 V V15 V V16 V V17 V V18 V V19 V V20 V

SS

DD

DD_DRAM

DD

DD_DRAM

DD

DD_IO

W5 V

W6 V

W7 V

W8 V

W9 V

W10 V

W11 V

W12 V

W13 V

W14 V

W15 V

W16 V

W17 V

W18 V

W19 V

W20 V

DD_IO

DD

DD_DRAM

DD

DD_DRAM

DD

DD_IO

Y5 V Y6 V Y7 V Y8 V Y9 V Y10 V Y11 V Y12 V Y13 V Y14 V Y15 V Y16 V Y17 V Y18 V Y19 V Y20 V

SS

DD_IO

SS

DD_IO

SS

DD_IO

SS

DD_IO

SS

DD_IO

SS

U21 L1CLKINN V21 L1DATI3_N W21 L1CLKON Y21 L1DATO1_N U22 L1CLKINP V22 L1DATI3_P W22 L1CLKOP Y22 L1DATO1_P U2 3 L 1D ATI 1_ N V2 3 L 1D ATI 2_ N W 2 3 L 1 DATO 3_ N Y2 3 L 1D ATO 2_ N U2 4 L 1D ATI 1_ P V2 4 L1 DAT I2 _ P W 24 L 1D ATO3 _P Y 2 4 L1 DAT O2 _P

Rev. D | Page 43 of 48 | May 2012

ADSP-TS203S

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)

Ball No. Signal Name

AA1 FLAG2 AB1 V AA2 FLAG1 AB2 V AA3 IRQ3 AA4 V

SS

Ball No. Signal Name

SS

AB3 V

SS

Ball No. Signal Name

AC1 FLAG0 AD1 V AC2 V AC3 V

SS

DD_IO

AD2 ID1 AD3 V

SS

DD_IO

AB4 NC AC4 TMS AD4 TRST AA5 IRQ0 AB5 IRQ2 AC5 IOWR AD5 IORD AA6 IOEN AB6 IRQ1 AC6 DMAR2 AD6 DMAR3 AA7 DMAR0 AB7 DMAR1 AC7 CPA AD7 DPA AA8 HBR AB8 HBG AC8 BOFF AD8 BUSLOCK AA9 TM3 AB9 V

DD_IO

AC9 NC AD9 NC AA10 NC AB10 NC AC10 NC AD10 NC AA11 NC AB11 NC AC11 NC AD11 NC AA12 V AA13 V AA14 V

SS

DD_IO

AA15 NC AB15 V AA16 NC AB16 NC AC16 TM2 AD16 V

AB12 V AB13 V AB14 V

SS

DD_IO

SS

AC12 V

AC13 V

AC14 V

DD_IO

SS

DD_IO

AD12 V AD13 V AD14 V

AC15 NC AD15 V

DD_IO

SS

DD_IO

AA17 NC AB17 NC AC17 NC AD17 NC AA18 NC AB18 NC AC18 NC AD18 NC AA19 V AA20 V AA21 V

SS

DD_IO

SS

AA22 L1BCMPO AB22 V AA23 L1DATO0_N AB23 V AA24 L1DATO0_P AB24 V

1

On revision 1.x silicon, the R2 and R3 balls are NC. On revision 0.x silicon, the R2 ball is SCLK, and the R3 ball is SCLK_V

on revision 0.x silicon, see EE-179: ADSP-TS20x TigerSHARC System Design Guidelines.

AB19 V AB20 V

DD_IO

AC19 V

AC20 V

AB21 NC AC21 V

SS

DD_IO

AC22 V

AC23 V

AC24 L1ACKI AD24 V

DD_IO

SS

AD19 V AD20 V AD21 V AD22 V AD23 V

. For more information on SCLK and SCLK_V

REF

DD_IO

SS

REF

Rev. D | Page 44 of 48 | May 2012

ADSP-TS203S

TOP VIEW

191721 2315

13

11

9

57

31

20

18

1614

1210

8624 22 24

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

Y

W

V

U

T

AD

AC

AB

AA

V

DD

V

DD_IO

V

DD_DRAM

V

SS

SIGNAL

V

DD_A

V

REF

KEY:

NO CONNECT

1

For a more detailed pin summary diagram, see EE-179: ADSP-TS20x TigerSHARC System Design Guidelines.

Figure 44. 576-Ball BGA_ED Pin Configurations1 (Top View, Summary)

Rev. D | Page 45 of 48 | May 2012

ADSP-TS203S

1.00

BSC

(BALL

PITCH)

0.75

0.65

0.55

(BALL

DIAMETER)

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILL IMETERS.

2. THE ACTUAL PO SITION OF THE BALL GRID IS WITHIN 0.25 m m OF ITS IDEAL POSITIO N RELATIVE TO THE PACKAGE EDGES.

3. CENTER DIMENSIONS ARE NOMINAL.

4. THIS PACKAGE C ONFORMS TO JEDEC MS-034 SP ECIFICATION.

SEATING PLANE

1.60 MAX

0.20 MAX

DETAIL A

0.97 BSC

79531

1113

15

1721 1923

68

10121416182024 22

42

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

Y

W

V

U

T

AD

AC

AB

AA

23.00 BSC

SQ

25.20

25.00

24.80

25.20

25.00

24.80

TOP VI EW

BOTTOM VIEW

1.00

BSC

0.60

0.50

0.40

1.00 BSC

A1 BALL INDICATOR

1.25

1.00

0.75

1.25

1.00

0.75

3.10

2.94

2.78

OUTLINE DIMENSIONS

The ADSP-TS203S processor is available in a 25 mm × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576).

SURFACE MOUNT DESIGN

The following table is provided as an aide to PCB design. The numbers listed in the table are for reference purposes and should not supersede the PCB design rules. Please reference IPC-7351, Surface Mount Design and Land Pattern Standard, for PCB design recommendations.

Package Ball Attach Type

576-Ball BGA_ED (BP-576-1)

Nonsolder Mask Defined (NSMD)

Solder Mask Opening Ball Pad Size

0.69 0.56

Figure 45. 576-Ball BGA_ED (BP-576)

Rev. D | Page 46 of 48 | May 2012

ORDERING GUIDE

ADSP-TS203S

Model

1

Temperature

2

Range

Instruction

3

Rate

On-Chip DRAM Package Option

Package Description

ADSP-TS203SBBPZ050 0°C to +85°C 500 MHz 4M bit BP-576 576-Ball BGA_ED ADSP-TS203SABP-050 –40°C to +85°C 500 MHz 4M bit BP-576 576-Ball BGA_ED ADSP-TS203SABPZ050 –40°C to +85°C 500 MHz 4M bit BP-576 576-Ball BGA_ED

1

Z = RoHS complaint part.

2

Represents case temperature.

3

The instruction rate is the same as the internal processor core clock (CCLK) rate.

Rev. D | Page 47 of 48 | May 2012

ADSP-TS203S

D04326-0-5/12(D)

Rev. D | Page 48 of 48 | May 2012

Datasheet ADSP-TS203S Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

KEY FEATURES

KEY BENEFITS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

DUAL COMPUTE BLOCKS

DATA ALIGNMENT BUFFER (DAB)

DUAL INTEGER ALU (IALU)

PROGRAM SEQUENCER

Interrupt Controller

Flexible Instruction Set

MEMORY

EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

Host Interface

Multiprocessor Interface

SDRAM Controller

EPROM Interface

DMA CONTROLLER

LINK PORTS (LVDS)

TIMER AND GENERAL-PURPOSE I/O

CLOCK DOMAINS

RESET AND BOOTING

FILTERING REFERENCE VOLTAGE AND CLOCKS

POWER DOMAINS

DEVELOPMENT TOOLS

Evaluation Kit

RELATED SIGNAL CHAINS

ADDITIONAL INFORMATION

Designing an Emulator-Compatible DSP Board (Target)

PIN FUNCTION DESCRIPTIONS

STRAP PIN FUNCTION DESCRIPTIONS

SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PACKAGE INFORMATION

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

General AC Timing

Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing

Link Port—Data Out Timing

Link Port—Data In Timing

OUTPUT DRIVE CURRENTS

TEST CONDITIONS

Output Disable Time

Output Enable Time

Capacitive Loading

ENVIRONMENTAL CONDITIONS

Thermal Characteristics

576-BALL BGA_ED PIN CONFIGURATIONS

OUTLINE DIMENSIONS

SURFACE MOUNT DESIGN

ORDERING GUIDE