Datasheet ADSP-TS202S Datasheet (Analog Devices)

Page 1

TigerSHARC

Embedded Processor

ADSP-TS202S

KEY FEATURES

500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory 25 mm × 25 mm (576-ball) thermally enhanced ball grid array

package

Dual-computation blocks—each containing an ALU, a multi-

plier, a shifter, and a register file

Dual-integer ALUs, providing data addressing and pointer

manipulation

Integrated I/O includes 14-channel DMA controller, external

port, four link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

1149.1 IEEE compliant JTAG test access port for on-chip emulation

On-chip arbitration for glueless multiprocessing

DATA ADDRESS GENERATION

FILE

32 × 32

128

INTEGER

KALU

32 × 32

DAB

PROGRAM

SEQUENCER

ADDR

FETCH

BTB

IAB

INTEGER

JALU

32 × 32

J-BUS ADDR

J-BUS DATA

K-BUS ADDR

K-BUS DATA

I-BUS ADDR

I-BUS DATA

SHIFT

ALU

MUL

KEY BENEFITS

Provides high-performance Static Superscalar DSP opera-

tions, optimized for large, demanding multiprocessor DSP applications

Performs exceptionally well on DSP algorithm and I/O bench-

marks (see benchmarks in Table 1)

Supports low overhead DMA transfers between internal

memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs

Eases DSP programming through extremely flexible instruc-

tion set and high-level-language friendly DSP architecture

Enables scalable multiprocessing systems with low commu-

nications overhead

12M BITS INTERNAL MEMORY

MEMORY BLOCKS

(PAGE CACHE)

4xCROSSBAR CONNECT

ADADA

128

S-BUS ADDR

S-BUS DATA

128

FILE

32 × 32

MUL

ALU

128

SHIFT

SOC

I/F

SOC BUS

JTAG

HOST

MULTI-

PROC

SDRAM

CTRL

C-BUS

ARB

DMA

OUT

JTAG PORT

EXTERNAL

PORT

EXT DMA

REQ

LINK PORTS

4 8

4 8 4 8

4 8

ADDR

DATA

CTRL

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

COMPUTATIONAL BLOCKS

Figure 1. Functional Block Diagram

Page 2

ADSP-TS202S

General Description ................................................. 3

Dual Compute Blocks ............................................ 4

Data Alignment Buffer (DAB) .................................. 4

Dual Integer ALU (IALU) ....................................... 4

Program Sequencer ............................................... 5

Interrupt Controller ........................................... 5

Flexible Instruction Set ........................................ 5

DSP Memory ....................................................... 5

External Port (Off-Chip Memory/Peripherals Interface) . 5

Host Interface ................................................... 6

Multiprocessor Interface ...................................... 7

SDRAM Controller ............................................ 7

EPROM Interface .............................................. 7

DMA Controller ................................................... 7

Link Ports (LVDS) ................................................ 8

Timer and General-Purpose I/O ............................... 9

Reset and Booting ................................................. 9

Clock Domains .................................................... 9

Power Domains .................................................... 9

Filtering Reference Voltage and Clocks ...................... 9

Development Tools ............................................. 10

Evaluation Kit .................................................... 11

Designing an Emulator-Compatible

DSP Board (Target) .......................................... 11

Additional Information ........................................ 11

Pin Function Descriptions ....................................... 12

Strap Pin Function Descriptions ................................ 19

ADSP-TS202S—Specifications .................................. 21

Recommended Operating Conditions ...................... 21

Electrical Characteristics ....................................... 22

Absolute Maximum Ratings .................................. 23

ESD Sensitivity ................................................... 23

Timing Specifications .......................................... 24

General AC Timing .......................................... 24

Link Port Low-Voltage, Differential-Signal (LVDS)

Electrical Characteristics and Timing ................. 30

Link Port—Data Out Timing ........................... 31

Link Port—Data In Timing ............................. 34

Output Drive Currents ......................................... 35

Test Conditions .................................................. 36

Output Disable Time ......................................... 36

Output Enable Time ......................................... 37

Capacitive Loading ........................................... 37

Environmental Conditions .................................... 39

Thermal Characteristics ..................................... 39

576-Ball BGA_ED Pin Configurations ......................... 40

Outline Dimensions ................................................ 44

Ordering Guide ..................................................... 44

REVISION HISTORY

11/04—Rev. PrB to Rev. 0: Initial (Production) Version

Applies corrections and additional information (including more detail on 500 MHz parts) to:

SCLK_VREF Filtering Scheme ................................ 10

Pin Definitions—Link Ports ................................... 17

Pin Definitions—Impedance Control, Drive Strength Con-

trol, and Regulator Enable .................................. 18

Recommended Operating Conditions ...................... 21

Electrical Characteristics ....................................... 22

Power-Up Timing ............................................... 26

AC Signal Specifications ........................................ 28

Ordering Guide .................................................. 44

Provides a usable jitter specification in:

Reference Clocks—System Clock (SCLK) Cycle Time . . 25

Provides thermal information for wider temperature range in:

Thermal Characteristics for 25 mm × 25 mm Package . . 39

Rev. 0 | Page 2 of 44 | November 2004

Page 3

GENERAL DESCRIPTION

ADSP-TS202S

The ADSP-TS202S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and supporting 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing 24 fixedpoint (16-bit) operations or six floating-point operations.

Four independent 128-bit wide internal data buses, each connecting to the six 2M bit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS202S processor’s core has a 2.0 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS202S processor can perform four billion 40bit MACs or one billion 80-bit MACs per second. Table 1 shows the DSP’s performance benchmarks.

Table 1. General-Purpose Algorithm Benchmarks

at 500 MHz

Clock

Benchmark Speed

Cycles

32-bit algorithm, one billion MACs/s peak performance 1K point complex FFT 64K point complex FFT

(Radix2)

(Radix2) 2.8 ms 1397544

18.8 µs 9419

FIR filter (per real tap) 1 ns 0.5 [8 × 8][8 × 8] matrix multiply (complex,

floating-point) 2.8 µs 1399 16-bit algorithm, four billion MACs/s peak performance 256 point complex FFT

(Radix 2) 1.9 µs 928 I/O DMA transfer rate External port 1G bytes/s n/a Link ports (each) 1G bytes/s n/a

Cache preloaded

The ADSP-TS202S processor is code-compatible with the other TigerSHARC processors.

The Functional Block Diagram on Page 1 shows the ADSPTS202S processor’s architectural blocks. These blocks include:

• Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, and 32-word register file and associated data alignment buffers (DABs)

• Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing and a status register

• A program sequencer with instruction alignment buffer (IAB) and branch target buffer (BTB)

• An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts

• Four 128-bit internal data buses, each connecting to the six 2M bit memory banks

• On-chip DRAM (12M bit)

• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM

• A 14-channel DMA controller

• Four full-duplex LVDS link ports

• Two 64-bit interval timers and timer expired pin

• A 1149.1 IEEE compliant JTAG test access port for on-chip emulation

Figure 2 on Page 3 shows a typical single-processor system with

external SRAM and SDRAM. Figure 4 on Page 8 shows a typical multiprocessor system.

ADSP-TS202S

CLOCK

REFERENCE

SDRAM

MEMORY

(OPTIONAL)

CLK ADDR

RAS

DATA

CAS

DQM

CKE

A10

LINK

DEVICES

(4 MAX)

(OPTIONAL)

RST_IN RST_OUT POR_IN

SCLK SCLKRAT2–0

SCLK_V

REF

IRQ3–0

FLAG3–0 ID2–0

MSSD3–0 RAS CAS

LDQM HDQM

SDWE

SDCKE SDA10

IORD IOWR IOEN

LxDATO3–0P/N LxCLKOUTP/N LxACKI

LxBCMPO

LxDATI3–0P/N LxCLKINP/N LxACKO

LxBCMPI

CONTROLIMP1–0 TMR0E DS2–0

ADDR31–0

DATA63–0

WRH/WRL

DMAR3–0

BUSLOCK

BMS

BRST

ACK

MS1–0

MSH HBR HBG

BOFF

BR7–0

CPA DPA

JTAG

S S

A T A D

BOOT

EPROM

(OPTIONAL)

ADDR DATA

MEMORY

(OPTIONAL)

ADDR

DATA

OE WE

ACK

HOST

PROCESSOR

INTERFACE (OPTIONAL)

ADDR

DATA

DMA DEVICE

(OPTIONAL)

DATA

Figure 2. ADSP-TS202S Single-Processor System with External SDRAM

†

The TigerSHARC DSP uses a Static Superscalar

architecture. This architecture is superscalar in that the ADSP-TS202S processor’s core can execute simultaneously from one to four 32-bit instructions encoded in a very large instruction word (VLIW) instruction line using the DSP’s dual compute blocks. Because

†

Static Superscalar is a trademark of Analog Devices, Inc.

Rev. 0 | Page 3 of 44 | November 2004

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ADSP-TS202S

the DSP does not perform instruction re-ordering at run-time— the programmer selects which operations will execute in parallel prior to run-time—the order of instructions is static.

With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a ten-deep processor pipeline.

For optimal DSP program execution, programmers must follow the DSP’s set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the DSP can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. The programmer has direct control of three core components—the IALUs, the compute blocks, and the program sequencer.

The ADSP-TS202S processor, in most cases, has a two-cycle execution pipeline that is fully interlocked, so—whenever a computation result is unavailable for another operation dependent on it—the DSP automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies.

In addition, the ADSP-TS202S processor supports SIMD operations two ways—SIMD compute blocks and SIMD computations. The programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution).

DUAL COMPUTE BLOCKS

The ADSP-TS202S processor has compute blocks that can execute computations either independently or together as a singleinstruction, multiple-data (SIMD) engine. The DSP can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, or shifter to perform independent, simultaneous operations. Each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with the operation in the other block.

The compute blocks are referred to as X and Y in assembly syntax, and each block contains three computational units—an ALU, a multiplier, a 64-bit shifter—and a 32-word register file.

• Register File—each compute block has a multiported 32word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned).

• ALU—the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic and PERMUTE operations.

• Multiplier—the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate.

• Shifter—the 64-bit shifter performs logical and arithmetic shifts, bit and bitstream manipulation, and field deposit and extraction operations.

Using these features, the compute blocks can:

• Provide 8 MACs per cycle peak and 7.1 MACs per cycle sustained 16-bit performance and provide 2 MACs per cycle peak and 1.8 MACs per cycle sustained 32-bit performance (based on FIR)

• Execute six single-precision floating-point or execute 24 fixed-point (16-bit) operations per cycle, providing 3GFLOPS or 12.0GOPS performance

• Perform two complex 16-bit MACs per cycle

DATA ALIGNMENT BUFFER (DAB)

The DAB is a quad-word FIFO that enables loading of quadword data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR filters.

DUAL INTEGER ALU (IALU)

The ADSP-TS202S processor has two IALUs that provide powerful address generation capabilities and perform many generalpurpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features:

• Provide memory addresses for data and update pointers

• Support circular buffering and bit-reverse addressing

• Perform general-purpose integer operations, increasing programming flexibility

• Include a 31-word register file for each IALU

As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each IALU can specify either a single-, dual-, or quad-word access from memory.

The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location.

Because the IALU’s computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is unavailable in a given cycle.

Rev. 0 | Page 4 of 44 | November 2004

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ADSP-TS202S

PROGRAM SEQUENCER

The ADSP-TS202S processor’s program sequencer supports the following:

• A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles

• A ten-cycle instruction pipeline—four-cycle fetch pipe and six-cycle execution pipe—computation results available two cycles after operands are available

• Supply of instruction fetch memory addresses; the sequencer’s instruction alignment buffer (IAB) caches up to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution

• Management of program structures and program flow determined according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software exceptions

• Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches that are taken occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty

• Compact code without the requirement to align code in memory; the IAB handles alignment

Interrupt Controller

The DSP supports nested and nonnested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level-sensitive or edge-sensitive, except the IRQ3–0 are programmable.

The DSP distinguishes between hardware interrupts and software exceptions, handling them differently. When a software exception occurs, the DSP aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the DSP continues to execute instructions already in the instruction pipe.

Flexible Instruction Set

The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the DSP to conditionally execute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include:

• Algebraic assembly language syntax

• Direct support for all DSP, imaging, and video arithmetic types

hardware interrupts, which

• Eliminates toggling DSP hardware modes because modes are supported as options (for example, rounding, saturation, and others) within instructions

• Branch prediction encoded in instruction; enables zerooverhead loops

• Parallelism encoded in instruction line

• Conditional execution optional for all instructions

• User defined partitioning between program and data memory

DSP MEMORY

The DSP’s internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in Figure 3.

The memory map is divided into four memory areas—host space, external memory, multiprocessor space, and internal memory—and each memory space, except host memory, is subdivided into smaller memory spaces.

The ADSP-TS202S processor internal memory has 12M bits of on-chip DRAM memory, divided into six blocks of 2M bits (64K words × 32 bits). Each block—M0, M2, M4, M6, M8, and M10—can store program instructions, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the DSP to access data while performing an instruction fetch. Each memory segment contains a 128K bit cache to enable single cycle accesses to internal DRAM.

The six internal memory blocks connect to the four 128-bit wide internal buses through a crossbar connection, enabling the DSP to perform four memory transfers in the same cycle. The DSP’s internal bus architecture provides a total memory bandwidth of 28G bytes per second, enabling the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. The DSP’s flexible memory structure enables:

• DSP core and I/O accesses to different memory blocks in the same cycle

• DSP core access to three memory blocks in parallel—one instruction and two data accesses

• Programmable partitioning of program and data memory

• Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB

EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

The ADSP-TS202S processor’s external port provides the DSP’s interface to off-chip memory and peripherals. The 4G word address space is included in the DSP’s unified address space. The separate on-chip buses—four 128-bit data buses and four 32-bit address buses—are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction. The external system bus provides a single 64-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 1G bytes per second over the external bus.

Rev. 0 | Page 5 of 44 | November 2004

Page 6

ADSP-TS202S

INTERNAL SPACE

RESERV ED

SOC R EGISTE RS ( UR EGS)

RESERV ED

INTERNAL REGISTERS (UREGS)

RESERV ED

INTERNAL MEMORY BLOCK 10

RESERV ED

INTERNAL MEMORY BLOCK 8

RESERV ED

INTERNAL MEMORY BLOCK6

RESERV ED

INTERNAL MEMORY BLOCK4

RESERV ED

INTERNAL MEMORYBLOCK 2

RESERV ED

INTERNAL MEMORYBLOCK 0

0x03FFFFFF

0x001F03FF

0X 001F 0000

0x 001E0 3FF

0X001E0000

0x0014FFFF

0x 00140 000

0x0010FFFF

0x 00100 000

0x000CFFFF

0x 000C 0000

0x 0008 FFFF

0 x000 80000

0x 0004 FFFF

0 x000 40000

0x0000FFFF

0x0 0000 000

GLOBAL SPACE

HOST (MSH)

RE SER V ED

MSSD BANK 3 (MSSD3)

E C A P S

Y R O M E M L A N R E T X E

E C A P S

Y R O M E M

R O S S E C O R P

I T L U

RE SER V ED

MSSD BA NK 2 (MSSD2)

RE SER V ED

MSSD BANK 1 (MSSD1)

RE SER V ED

MSSD BANK 0 (MSSD0)

BANK 1 (MS1 )

BANK 0 (MS0 )

PROCESSORID7

PROCESSORID6

PROCESSORID5

PROCESSORID4

PROCESSORID3

PROCESSORID2

PROCESSORID1

PROCESSORID0

BROADCAST

RE SER V ED

INTER NAL MEMORY

0xFFFFFFFF

0x 8000 0000

0x 7400 0000

0x 7000 0000

0x 6400 0000

0x 6000 0000

0x 5400 0000

0x 5000 0000

0x4 4000 000

0x4 0000 000

0x 3800 0000

0x 30000 000

0x 2C00 0000

0x 28000 000

0x 24000 000

0x 20000 000

0x 1C00 0000

0x 18000 000

0x 14000 000

0x 10000 000

0X0C000000

0x03FFFFFF

0x 00000 000

EACH IS A COPY

OF INTERNAL SPACE

Figure 3. ADSP-TS202S Memory Map

The external bus can be configured for 32- or 64-bit, littleendian operations. When the system bus is configured for 64-bit operations, the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses.

The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals.

The ADSP-TS202S processor provides programmable memory, pipeline depth, and idle cycle for synchronous accesses, and external acknowledge controls to support interfacing to pipelined or slow devices, host processors, and other memorymapped peripherals with variable access, hold, and disable time requirements.

Rev. 0 | Page 6 of 44 | November 2004

Host Interface

The ADSP-TS202S processor provides an easy and configurable interface between its external bus and host processors through the external port. To accommodate a variety of host processors, the host interface supports pipelined or slow protocols for ADSP-TS202S processor accesses of the host as slave or pipelined for host accesses of the ADSP-TS202S processor as slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles.

The host interface supports burst transactions initiated by a host processor. After the host issues the starting address of the burst and asserts the BRST internally while the host continues to assert BRST

signal, the DSP increments the address

The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the DSP. The BOFF

signal provides the deadlock recovery mecha-

Page 7

ADSP-TS202S

nism. When the host asserts BOFF, the DSP backs off the current transaction and asserts HBG external bus.

The host can directly read or write the internal memory of the ADSP-TS202S processor, and it can access most of the DSP registers, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands.

and relinquishes the

Multiprocessor Interface

The ADSP-TS202S processor offers powerful features tailored to multiprocessing DSP systems through the external port and link ports. This multiprocessing capability provides highest bandwidth for interprocessor communication, including:

• Up to eight DSPs on a common bus

• On-chip arbitration for glueless multiprocessing

• Link ports for point-to-point communication

The external port and link ports provide integrated, glueless multiprocessing support.

The external port supports a unified address space (see Figure 3) that enables direct interprocessor accesses of each ADSPTS202S processor’s internal memory and registers. The DSP’s on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight ADSPTS202S processors and a host processor. Bus arbitration has a rotating priority. Bus lock supports indivisible read-modifywrite sequences for semaphores. A bus fairness feature prevents one DSP from holding the external bus too long.

The DSP’s four link ports provide a second path for interprocessor communications with throughput of 4G bytes per second. The cluster bus provides 1G bytes per second throughput—with a total of 4G bytes per second interprocessor bandwidth (limited by SOC bandwidth).

SDRAM Controller

The SDRAM controller controls the ADSP-TS202S processor’s transfers of data to and from external synchronous DRAM (SDRAM) at a throughput of 32 or 64 bits per SCLK cycle using the external port and SDRAM control pins.

The SDRAM interface provides a glueless interface with standard SDRAMs—16M bit, 64M bit, 128M bit, and 256M bit. The DSP supports directly a maximum of four banks of 64M words × 32 bits of SDRAM. The SDRAM interface is mapped in external memory in each DSP’s unified memory map.

EPROM Interface

The ADSP-TS202S processor can be configured to boot from an external 8-bit EPROM at reset through the external port. An automatic process (which follows reset) loads a program from the EPROM into internal memory. This process uses 16 wait cycles for each read access. During booting, the BMS tions as the EPROM chip select signal. The EPROM boot procedure uses DMA Channel 0, which packs the bytes into 32-bit instructions. Applications can also access the EPROM (write flash memories) during normal operation through DMA.

pin func-

The EPROM or flash memory interface is not mapped in the DSP’s unified memory map. It is a byte address space limited to a maximum of 16M bytes (24 address bits). The EPROM or flash memory interface can be used after boot via a DMA.

DMA CONTROLLER

The ADSP-TS202S processor’s on-chip DMA controller, with 14 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the DSP’s core, enabling DMA operations to occur while the DSP’s core continues to execute program instructions.

The DMA controller performs DMA transfers between internal memory and external memory and memory-mapped peripherals, the internal memory of other DSPs on a common bus, a host processor, or link port I/O; between external memory and external peripherals or link port I/O; and between an external bus master and internal memory or link port I/O. The DMA controller performs the following DMA operations:

• External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the DSP’s internal memory and any external memory or memorymapped peripheral on the external bus. These transfers support master mode and handshake mode protocols.

• Link port transfers. Eight dedicated DMA channels (four transmit and four receive) transfer quad-word data only between link ports and between a link port and internal or external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels.

• AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus mas ter to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer.

The DMA controller provides these additional features:

• Flyby transfers. Flyby operations only occur through the external port (DMA channel 0) and do not involve the DSP’s core. The DMA controller acts as a conduit to transfer data from an external I/O device and external SDRAM memory. During a transaction, the DSP relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0 RD

• DMA chaining. DMA chaining operations enable applications to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes.

• Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions.

); outputs the IORD, IOWR, IOEN, and

/WR strobes; and responds to ACK.

Rev. 0 | Page 7 of 44 | November 2004

Page 8

ADSP-TS202S

001

LINK

DEVICES

000

RESET

CLOCK

REFERENCE REFERENCE

LINK

DEVICES

(4 MAX)

(OPTIONAL)

ID2–0

RST_IN

CLKS/REFS

ID2–0

RST_IN

CLKS/REFS

RST_OUT POR_IN

SCLK

SCLK_V V

REF

SCLKRAT2–0

IRQ3–0

FLAG3–0

LINK

LxDATO3–0P/N LxCLKOUTP/N LxACKI

LxBCMPO

LxDATI3–0P/N LxCLKINP/N LxACKO

LxBCMPI

TMR0E

CONTROLIMP1–0 DS2–0

ADSP-TS202S #7 ADSP-TS202S #6 ADSP-TS202S #5 ADSP-TS202S #4 ADSP-TS202S #3 ADSP-TS202S #2

ADSP-TS202S #1

ADDR31–0

DATA63–0

LINK

JTAG

CONTROL

ADSP-TS202S #0

ADDR31–0

DATA63–0

BUSLOCK

REF

DMAR3–0

MSSD3–0

CONTROL

BR7–2,0

BR1

BR7–1

BR0

WRH/L

ACK

MS1–0

BMS

CPA

DPA

BRST

BOFF

HBR HBG

MSH

IORD

IOWR

IOEN

RAS CAS

LDQM

HDQM

SDWE

SDCKE

SDA10

S S

O R T N O C

L O R T N O C

D A

S S

D A

ADDR

GLOBAL

DATA

MEMORY

OE WE

ACK

ADDR DATA

CS RAS CAS

CKE A10 ADDR DATA

PERIPHERALS

(OPTIONAL)

PROCESSOR

(OPTIONAL)

DQM

AND

BOOT

EPROM

CLOCK

HOST

INTERFACE (OPTIONAL)

SDRAM

MEMORY

CLK

Figure 4. ADSP-TS202S Shared Memory Multiprocessing System

LINK PORTS (LVDS)

The DSP’s four full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using LowVoltage, Differential-Signal (LVDS) technology. With the ability to operate at a double data rate—latching data on both the rising and falling edges of the clock—running at 500 MHz, each link port can support up to 500M bytes per second per direction, for a combined maximum throughput of 4G bytes per second.

The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also use the link ports for booting.

Rev. 0 | Page 8 of 44 | November 2004

Each link port has its own triple-buffered quad-word input and double-buffered quad-word output registers. The DSP’s core can write directly to a link port’s transmit register and read from a receive register, or the DMA controller can perform DMA transfers through eight (four transmit and four receive) dedicated link port DMA channels.

Each link port direction has three signals that control its operation. For the transmitter, LxCLKOUT is the output transmit clock, LxACKI is the handshake input to control the data flow, and the LxBCMPO

output indicates that the block transfer is complete. For the receiver, LxCLKIN is the input receive clock, LxACKO is the handshake output to control the data flow, and

Page 9

ADSP-TS202S

the LxBCMPI input indicates that the block transfer is complete. The LxDATO3–0 pins are the data output bus for the transmitter and the LxDATI3–0 pins are the input data bus for the receiver.

Applications can program separate error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are transmitted.

TIMER AND GENERAL-PURPOSE I/O

The ADSP-TS202S processor has a timer pin (TMR0E) that generates output when a programmed timer counter has expired and four programmable general-purpose I/O pins (FLAG3–0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching.

RESET AND BOOTING

The ADSP-TS202S processor has three levels of reset:

• Power-up reset—after power-up of the system (SCLK, all static inputs, and strap pins are stable), the RST_IN must be asserted (low).

• Normal reset—for any chip reset following the power-up reset, the RST_IN

pin must be asserted (low).

• DSP-core reset—when setting the SWRST bit in EMUCTL, the DSP core is reset, but not the external port or I/O.

For normal operations, tie the RST_OUT POR_IN

pin.

pin to the

After reset, the ADSP-TS202S processor has four boot options for beginning operation:

•Boot from EPROM.

• Boot by an external master (host or another ADSP-TS202S processor).

•Boot by link port.

• No boot—start running from memory address selected with one of the IRQ3–0

interrupt signals. See Table 2.

Using the “no boot” option, the ADSP-TS202S processor must start running from memory when one of the interrupts is asserted.

For more information on boot options, see the EE-200: ADSP- TS20x TigerSHARC Processor Boot Loader Kernels Operation on the Analog Devices website (www.analog.com)

CLOCK DOMAINS

The DSP uses calculated ratios of the SCLK clock to operate as shown in Figure 5. The instruction execution rate is equal to CCLK. A PLL from SCLK generates CCLK which is phaselocked. The SCLKRATx pins define the clock multiplication of SCLK to CCLK (see Table 4 on Page 12). The link port clock is generated from CCLK via a software programmable divisor, and the SOC bus operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. SCLK also provides clock input for the external bus interface and defines the AC specification reference for the external bus signals. The external bus interface runs at the SCLK frequency. The maximum SCLK frequency is one quarter the internal DSP clock (CCLK) frequency.

EXTERNAL INTERFACE

SCLK

SCLKRATx

LCTLx REGISTER

PLL

/CR

SPD BITS,

Figure 5. Clock Domains

CCLK (INSTRUCTION RATE)

SOCCLK (PERIPHERAL BUS RATE)

LxCLKOUT (LINK OUTPUT RATE)

POWER DOMAINS

The ADSP-TS202S processor has separate power supply connections for internal logic (V buffer (V

), and internal DRAM (V

DD_IO

Note that the analog (V

), analog circuits (V

DD_DRAM

) supply powers the clock generator

DD_A

) power supply.

), I/O

PLLs. To produce a stable clock, systems must provide a clean power supply to power input V attention to bypassing the V

. Designs must pay critical

DD_A

supply.

DD_A

FILTERING REFERENCE VOLTAGE AND CLOCKS

Figure 6 and Figure 7 show possible circuits for filtering V

and SCLK_V

. These circuits provide the reference voltages

REF

for the switching voltage reference and system clock reference.

REF

Table 2. No Boot, Run from Memory Addresses

Interrupt Address

IRQ0 IRQ1 IRQ2 IRQ3

0x3000 0000 (External Memory) 0x3800 0000 (External Memory) 0x8000 0000 (External Memory) 0x0000 0000 (Internal Memory)

The ADSP-TS202S processor core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset.

Rev. 0 | Page 9 of 44 | November 2004

DD_IO

R2 C1 C2

R1: 2 k⍀ SERIES RESISTOR (±1%) R2: 2.87 k⍀ SERIE S RESISTOR (±1%) C1: 1 ␮F CAPACITOR (SMD) C2: 1 nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS

Figure 6. V

Filtering Scheme

REF

Page 10

ADSP-TS202S

CLOCK DRIVER

VOLTAGE OR

DD_IO

R2 C1 C2

R1: 2 k⍀ SERIES RESISTOR (±1%) R2: 2.87 k⍀ SERIES RESISTOR (±1%) C1: 1 ␮FCAPACITOR(SMD) C2: 1 nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS

IF CLOCK DRIVER VOLTAGE ⬎ V

Figure 7. SCLK_V

DD_IO

Filtering Scheme

REF

SCLK_V

REF

DEVELOPMENT TOOLS

The ADSP-TS202S processor is supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS202S processor.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for theses tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

†

software and hardware development tools,

‡

devel-

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

VCSE is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It also can be used for downloading components from the Web, dropping them into the application, and publishing component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data

Rev. 0 | Page 10 of 44 | November 2004

Page 11

ADSP-TS202S

to different areas of the DSP or external memory with a drag of the mouse, examine run-time stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-TS202S processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the TigerSHARC processor family. Hardware tools include TigerSHARC processor PC plug-in cards. Third party software tools include DSP libraries, realtime operating systems, and block diagram design tools.

EVALUATION KIT

Analog Devices offers a range of EZ-KIT Lite forms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

†

evaluation plat-

halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use the string “EE-68” in site search. This document is updated regularly to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSPTS202S processor’s architecture and functionality. For detailed information on the ADSP-TS202S processor’s core architecture and instruction set, see the ADSP-TS201 TigerSHARC Processor

Hardware Reference and the ADSP-TS201 TigerSHARC Processor Programming Reference. For detailed information on the development tools for this processor, see the VisualDSP++ User’s Guide for TigerSHARC Processors.

DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be

†

EZ-Kit Lite is a registered trademark of Analog Devices, Inc.

Rev. 0 | Page 11 of 44 | November 2004

Page 12

ADSP-TS202S

PIN FUNCTION DESCRIPTIONS

While most of the ADSP-TS202S processor’s input pins are normally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. Use the ac specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals.

The output pins can be three-stated during normal operation. The DSP three-states all outputs during reset, allowing these pins to get to their internal pull-up or pull-down state. Some pins have an internal pull-up or pull-down resistor (±30% tolerance) that maintains a known value during transitions between different drivers.

Table 3. Pin Definitions—Clocks and Reset

Signal Type Term Description

Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-programmable using the SCLKRATx pins to the values shown in Table 4. These pins may change only during reset; connect these pins to V

or VSS. All reset specifications

DD_IO

in Table 22, Table 23, and Table 24 must be satisfied. The core clock rate (CCLK) is the

SCLKRAT2–0 I (pd) na

instruction cycle rate. System Clock Input. The DSP’s system input clock for cluster bus.The core clock rate

is user-programmable using the SCLKRATx pins. For more information, see Clock

SCLK I na

Domains on Page 9.

Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN must be asserted a specified time according to the type of reset operation. For details,

RST_IN RST_OUT POR_IN

I/A na

see Reset and Booting on Page 9, Table 18 on Page 24, and Figure 13 on Page 27. O na Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN. I/A na Power-On Reset for internal DRAM. Connect to RST_OUT.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

; VSS = connect directly to VSS.

Table 4. SCLK Ratio

SCLKRAT2–0 Ratio

000 (default) 4 001 5 010 6 011 7 100 8 101 10 110 12 111 Reserved

Rev. 0 | Page 12 of 44 | November 2004

Page 13

Table 5. Pin Definitions—External Port Bus Controls

Signal Type Term Description

Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS202S processors. The DSP

ADDR31–0

DATA63–0

I/O/T (pu_ad) nc

inputs addresses when a host or another DSP accesses its internal memory or I/O processor registers.

External Data Bus. The DSP drives and receives data and instructions on these pins. Pull-up or pull-down resistors on unused DATA pins are unnecessary.

Memory Read. RD is asserted whenever the DSP reads from any slave in the system,

is an input and indicates read trans-

I/O/T (pu_0) epu

excluding SDRAM. When the DSP is a slave, RD

actions that access its internal memory or universal registers. In a multiprocessor system, the bus master drives RD

. RD changes concurrently with ADDR pins.

Write Low. WRL is asserted in two cases: when the ADSP-TS202S processor writes to an even address word of external memory or to another external bus agent; and when the ADSP-TS202S processor writes to a 32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP) asserts WRL to a DSP’s low word of internal memory. In a multiprocessor system, the bus master

. WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL

WRL

I/O/T (pu_0) epu

drives WRL

is an input and indicates write transactions that access its internal memory or universal registers.

Write High. WRH is asserted when the ADSP-TS202S processor writes a long word (64 bits) or writes to an odd address word of external memory or to another external bus agent on a 64-bit data bus. An external master (host or another DSP) must assert WRH for writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system, the

. WRH changes concurrently with ADDR pins. When the DSP

WRH

I/O/T (pu_0) epu

bus master drives WRH

is a slave, WRH memory or universal registers.

is an input and indicates write transactions that access its internal

Acknowledge. External slave devices can deassert ACK to add wait states to external memory accesses. ACK is used by I/O devices, memory controllers and other peripherals on the data phase. The DSP can deassert ACK to add wait states to read and write

ACK

BMS

MS1–0

MSH

I/O/T/OD (pu_od_0) epu

O/T (pu_0) na

O/T (pu_0) nc

accesses of its internal memory. The pull-up is 50 Ω on low-to-high transactions and is 500 Ω on all other transactions.

Boot Memory Select. BMS reset, the DSP uses BMS cessor system, the DSP bus master drives BMS

is the chip select for boot EPROM or flash memory. During

as a strap pin (EBOOT) for EPROM boot mode. In a multipro-

. For details, see Reset and Booting on

Page 9 and see the EBOOT signal description in Table 16 on Page 19.

Memory Select. MS0 or 1, respectively. MS1–0 with ADDR pins. When ADDR31:27 = 0b00110, MS0

or MS1 is asserted whenever the DSP accesses memory banks 0

are decoded memory address pins that change concurrently

is asserted. When ADDR31:27 =

0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0. Memory Select Host. MSH

space (ADDR31 = 0b1). MSH

is asserted whenever the DSP accesses the host address

is a decoded memory address pin that changes concur-

rently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading

or writing data associated with consecutive addresses. A slave device can ignore addresses after the first one and increment an internal address counter after each

BRST

I/O/T (pu_0) epu

transfer. For host-to-DSP burst accesses, the DSP increments the address automatically while BRST

is asserted.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

This external pull-up may be omitted for the ID = 000 TigerSHARC processor.

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

ADSP-TS202S

for writing

; VSS = connect directly to VSS.

Rev. 0 | Page 13 of 44 | November 2004

Page 14

ADSP-TS202S

Table 6. Pin Definitions—External Port Arbitration

Signal Type Term Description

Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to

arbitrate for bus mastership. Each DSP drives its own BRx

value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight

DSPs, set the unused BRx

pins high (V

DD_IO

BR7–0

I/O V

DD_IO

Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in

a multiprocessor system. These pins also indicate to the DSP which bus request

(BR0

–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,

, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a constant

ID2–0 I (pd) na

011 = BR3

value during system operation and can change during reset only.

Bus Master. The current bus master DSP asserts BM

Ona

is a strap pin. For more information, see Table 16 on Page 19.

Back Off. A deadlock situation can occur when the host and a DSP try to read from

each other’s bus at the same time. When deadlock occurs, the host can assert BOFF

BOFF

BUSLOCK

HBR

Iepu O/T

(pu_0) na

to force the DSP to relinquish the bus before completing its outstanding transaction.

Bus Lock Indication. Provides an indication that the current bus master has locked

the bus. At reset, this is a strap pin. For more information, see Table 16 on Page 19.

Host Bus Request. A host must assert HBR

When HBR Iepu

bus and asserts HBG

to request control of the DSP’s external bus.

is asserted in a multiprocessing system, the bus master relinquishes the

once the outstanding transaction is finished.

Host Bus Grant. Acknowledges HBR and indicates that the host can take control of

the external bus. When relinquishing the bus, the master DSP three-states the

ADDR31–0, DATA63–0, MSH

IOWR

, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM and HDQM pins, and the DSP puts

, MSSD3–0, MS1–0, RD, WRL, WRH, BMS, BRST, IORD,

the SDRAM in self-refresh mode. The DSP asserts HBG

HBG

I/O/T (pu_0) epu

In multiprocessor systems, the current bus master DSP drives HBG

monitor it.

Core Priority Access. Asserted while the DSP’s core accesses external memory. This

pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and

gain control of the external bus for core-initiated transactions. CPA

output, connected to all DSPs in the system. If not required in the system, leave CPA

unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7).

CPA

I/O/OD (pu_od_0) epu

DMA Priority Access. Asserted while a high priority DSP DMA channel accesses

external memory. This pin enables a high priority DMA channel on a slave DSP to

interrupt transfers of a normal priority DMA channel on a master DSP and gain control

of the external bus for DMA-initiated transactions. DPA

DPA

I/O/OD (pu_od_0) epu

connected to all DSPs in the system. If not required in the system, leave DPA

nected (external pull-ups will be required for DSP ID = 1 through ID = 7).

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V

This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

line (corresponding to the

. For debugging only. At reset this

until the host deasserts HBR.

, and all slave DSPs

is an open drain

is an open drain output,

; epu = external pull-up approx-

; VSS = connect directly to VSS.

DD_IO

uncon-

DD_IO

Rev. 0 | Page 14 of 44 | November 2004

Page 15

Table 7. Pin Definitions—External Port DMA/Flyby

Signal Type Term Description

DMA Request Pins. Enable external I/O devices to request DMA services from the DSP.

DMAR3–0

I/A epu

In response to DMARx channel’s initialization. The DSP ignores DMA requests from uninitialized channels.

, the DSP performs DMA transfers according to the DMA

I/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP

IOWR

O/T (pu_0) nc

asserts the IOWR signal during the data cycles. This assertion makes the I/O device sample the data instead of the TigerSHARC.

I/O Read. When a DSP DMA channel initiates a flyby mode write transaction, the DSP

IORD

O/T (pu_0) nc

asserts the IORD signal during the data cycle. This assertion with the IOEN makes the I/O device drive the data instead of the TigerSHARC.

I/O Device Output Enable. Enables the output buffers of an external I/O device for fly-

IOEN

O/T (pu_0) nc

by transactions between the device and external memory. Active on flyby transactions.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

Table 8. Pin Definitions—External Port SDRAM Controller

ADSP-TS202S

; VSS = connect directly to VSS.

Signal Type Term Description

Memory Select SDRAM. MSSD0 DSP accesses SDRAM memory space. MSSD3–0

, MSSD1, MSSD2, or MSSD3 is asserted whenever the

are decoded memory address pins

that are asserted whenever the DSP issues an SDRAM command cycle (access to

MSSD3–0

RAS

CAS

I/O/T (pu_0) nc

ADDR31:30 = 0b01—except reserved spaces shown in Figure 3 on Page 6). In a multi- processor system, the master DSP drives MSSD3–0

Row Address Select. When sampled low, RAS

indicates that a row address is valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to SDRAM specification.

Column Address Select. When sampled low, CAS

indicates that a column address is valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to the SDRAM specification.

Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ

LDQM

O/T (pu_0) nc

buffers. LDQM is valid on SDRAM transactions when CAS read transactions. On write transactions, LDQM is active when accessing an odd address word on a 64-bit memory bus to disable the write of the low word.

is asserted, and inactive on

High Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ buffers. HDQM is valid on SDRAM transactions when CAS

is asserted, and inactive on read transactions. On write transactions, HDQM is active when accessing an even address in word accesses or when memory is configured for a 32-bit bus to disable the write of the high word.

HDQM

O/T (pu_0) nc

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

; VSS = connect directly to VSS.

DD_IO

Rev. 0 | Page 15 of 44 | November 2004

Page 16

ADSP-TS202S

Table 8. Pin Definitions—External Port SDRAM Controller (Continued)

Signal Type Term Description

O/T

SDA10

(pu_0) nc

I/O/T (pu_m/

SDCKE

pd_m) nc

I/O/T

SDWE

(pu_0) nc

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k ID = 0; pu_od_0 = internal pull-up 500

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

on DSP bus master; pu_ad = internal pull-up 40 k Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k

imately 5 k

Ω to V

, nc = not connected; na = not applicable (always used); V

DD_IO

Table 9. Pin Definitions—JTAG Port

SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while the DSP executes non-SDRAM transactions.

SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend modes. A slave DSP in a multiprocessor system does not have the pull-up or pulldown. A master DSP (or ID = 0 in a single processor system) has a pull-up before granting the bus to the host, except when the SDRAM is put in self refresh mode. In self refresh mode, the master has a pull-down before granting the bus to the host.

SDRAM Write Enable. When sampled low while CAS SDRAM write access. When sampled high while CAS SDRAM read access. In other SDRAM accesses, SDWE

is active, SDWE indicates an

defines the type of operation to

execute according to SDRAM specification.

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

= connect directly to V

DD_IO

; VSS = connect directly to VSS.

Signal Type Term Description

EMU

O/OD nc TCK I epd or epu TDI I (pu_ad) nc TDO O/T nc TMS I (pu_ad) nc

Emulation. Connected to the DSP’s JTAG emulator target board connector only.

Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. Test Data Input (JTAG). A serial data input of the scan path. Test Data Output (JTAG). A serial data output of the scan path. Test Mode Select (JTAG). Used to control the test state machine. Test Reset (JTAG). Resets the test state machine. TRST

must be asserted or pulsed low

after power up for proper device operation. For more information, see Reset and

TRST

I/A (pu_ad) na

Booting on Page 9.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

See the reference on Page 11 to the JTAG emulation technical reference EE-68.

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

; VSS = connect directly to VSS.

Rev. 0 | Page 16 of 44 | November 2004

Page 17

Table 10. Pin Definitions—Flags, Interrupts, and Timer

Signal Type Term Description

FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin

FLAG3–0

I/O/A (pu) nc

can be configured individually for input or for output. FLAG3–0 are inputs after power-up and reset.

Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 can be independently set for edge-triggered or level-sensitive operation. After reset, these

IRQ3–0

I/A (pu) nc

pins are disabled unless the IRQ3–0 booting.

strap option and interrupt vectors are initialized for

Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.

TMR0E O na

For more information, see Table 16 on Page 19.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

Table 11. Pin Definitions—Link Ports

Signal Type Term Description

LxDATO3–0P O nc Link Ports 3–0 Data 3–0 Transmit LVDS P. LxDATO3–0N O nc Link Ports 3–0 Data 3–0 Transmit LVDS N. LxCLKOUTP O nc Link Ports 3–0 Transmit Clock LVDS P. LxCLKOUTN O nc Link Ports 3–0 Transmit Clock LVDS N.

Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the

LxACKI I (pd) nc

transmitter that it may continue the transmission. Link Ports 3–0 Block Completion. When the transmission is executed using DMA, this

signal indicates to the receiver that the transmitted block is completed. The pull-up

only. At reset, the L1BCMPO, L2BCMPO, and L3BCMPO

LxBCMPO

O (pu) nc LxDATI3–0P I V LxDATI3–0N I V LxCLKINP I/A V LxCLKINN I/A V

DD_IO

resistor is present on L0BCMPO pins are strap pins. For more information, see Table 16 on Page 19.

Link Ports 3–0 Data 3–0 Receive LVDS P. Link Ports 3–0 Data 3–0 Receive LVDS N. Link Ports 3–0 Receive Clock LVDS P. Link Ports 3–0 Receive Clock LVDS N. Link Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the

LxACKO O nc

transmitter that it may continue the transmission. Link Ports 3–0 Block Completion. When the reception is executed using DMA, this

LxBCMPI

I (pd_l) V

signal indicates to the receiver that the transmitted block is completed.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω; pd_l = internal pull-down 50 kΩ. For more pull-down and pull-up information, see

Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 kΩ to V

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

Ω to V

; epu = external pull-up approx-

DD_IO

ADSP-TS202S

pins

; VSS = connect directly to VSS.

Rev. 0 | Page 17 of 44 | November 2004

Page 18

ADSP-TS202S

Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable

Signal Type Term Description

Impedance Control. As shown in Table 13, the CONTROLIMP1–0 pins select between normal driver mode and A/D driver mode. When using normal mode (recommended), the output drive strength is set relative to maximum drive strength according to

Table 14. When using A/D mode, the resistance control operates in the analog mode,

CONTROLIMP0 CONTROLIMP1

DS2, DS1

ENEDREG I (pu) V

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

Ω to V

DD_IO

Table 13. Impedance Control Selection

I (pd) I (pu)

na na

where drive strength is continuously controlled to match a specific line impedance as

shown in Table 14.

Digital Drive Strength Selection. S elected as shown in Table 14. For drive strength calcu-

lation, see Output Drive Currents on Page 35. The drive strength for some pins is preset,

not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%)

I (pu) I (pd) na

include: CPA

x2 drive strength 7 (100%).

Connect the ENEDREG pin to VSS. Connect the V

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

DRAM power supply.

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

, nc = not connected; na = not applicable (always used); V

, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin is always

pins to a properly decoupled

DD_DRAM

Ω to V

; epu = external pull-up approx-

= connect directly to V

DD_IO

; VSS = connect directly to VSS.

CONTROLIMP1-0 Driver Mode

00 (recommended) Normal 01 Reserved 10 (default) A/D Mode 11 Reserved

Table 14. Drive Strength/Output Impedance Selection

DS2–0 Pins

Drive Strength

Output Impedance

000 Strength 0 (11.1%) 26 Ω 001 Strength 1 (23.8%) 32 Ω 010 Strength 2 (36.5%) 40 Ω 011 Strength 3 (49.2%) 50 Ω 100 Strength 4 (61.9%) 62 Ω 101 (default) Strength 5 (74.6%) 70 Ω 110 Strength 6 (87.3%) 96 Ω 111 Strength 7 (100%) 120 Ω

CONTROLIMP1 = 0, A/D mode disabled.

CONTROLIMP1 = 1, A/D mode enabled.

Rev. 0 | Page 18 of 44 | November 2004

Page 19

Table 15. Pin Definitions—Power, Ground, and Reference

Signal Type Term Description

DD_A

DD_IO

DD_DRAM

PnaV PnaV PnaV PnaV

pins for internal logic.

pins for analog circuits. Pay critical attention to bypassing this supply.

pins for I/O buffers.

pins for internal DRAM.

Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN

, IRQ3–0, FLAG3–0, DMAR3–0, ID2–0, CONTROLIMP1–0, LxDATO3–0P/N,

POR_IN LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST connected to a power supply or set by a voltage divider circuit as shown in Figure 6.

REF

Ina

For more information, see Filtering Reference Voltage and Clocks on Page 9.

System Clock Reference. Connect this pin to a reference voltage as shown in Figure 7.

SCLK_V V

REF

Ina

For more information, see Filtering Reference Voltage and Clocks on Page 9.

GnaGround pins.

No Connect. Do not connect these pins to anything (not to any supply, signal, or each

NC — nc

other). These pins are reserved and must be left unconnected.

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k imately 5 k

Ω to V

DD_IO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Ω to V

; epu = external pull-up approx-

, nc = not connected; na = not applicable (always used); V

= connect directly to V

DD_IO

ADSP-TS202S

. V

can be

REF

; VSS = connect directly to VSS.

STRAP PIN FUNCTION DESCRIPTIONS

Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value. If a strap pin is not connected to an overdriving external pull-up, pull-down, or logic load, the DSP samples the default value during reset. If strap pins are con-

Table 16. Pin Definitions—I/O Strap Pins

Type (at

Signal

Reset) On Pin … Description

EPROM Boot.

0 = boot from EPROM immediately after reset (default)

EBOOT

I (pd_0) BMS

1 = idle after reset and wait for an external device to boot DSP

through the external port or a link port

Interrupt Enable.

0 = disable and set IRQ3–0

reset (default)

1 = enable and set IRQ3–0

immediately after reset

IRQEN

I (pd) BM

Link Port Input Default Data Width.

LINK_DWIDTH

I (pd) TMR0E

0 = 1-bit (default) 1 = 4-bit

SYSCON and SDRCON Write Enable.

SYS_REG_WE

I (pd_0) BUSLOCK

0 = one-time writable after reset (default) 1 = always writable

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

nected to logic inputs, a stronger external pull-up or pull-down may be required to ensure default value depending on leakage and/or low level input current of the logic load. To set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pull-up or pull-down. Table 16 lists and describes each of the DSP’s strap pins.

interrupts to edge-sensitive after

interrupts to level-sensitive

Rev. 0 | Page 19 of 44 | November 2004

Page 20

ADSP-TS202S

Table 16. Pin Definitions—I/O Strap Pins (Continued)

Type (at

Signal

TM1

TM2

TM3

I = input; A = asynchronous; O = output; OD = open drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 k

ID = 0; pu_od_0 = internal pull-up 500 on DSP bus master; pu_ad = internal pull-up 40 k

Reset) On Pin … Description

I (pu) L1BCMPO Test Mode 1. Do not overdrive default value during reset.

I (pu) L2BCMPO

I (pu) L3BCMPO

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Test Mode 2. Do not overdrive default value during reset.

Test Mode 3. Do not overdrive default value during reset.

When default configuration is used, no external resistor is needed on the strap pins. To apply other configurations, a 500 Ω resistor connected to V external pull-downs, do not strap these pins directly to V

is required. If providing

DD_IO

; the

strap pins require 500 Ω resistor straps.

All strap pins are sampled on the rising edge of RST_IN

(deassertion edge). Each pin latches the strapped pin state (state of the strap pin at the rising edge of RST_IN sertion of RST_IN

, these pins are reconfigured to their normal

). Shortly after deas-

functionality.

These strap pins have an internal pull-down resistor, pull-up resistor, or no-resistor (three-state) on each pin. The resistor type, which is connected to the I/O pad, depends on whether RST_IN

is active (low) or if RST_IN is deasserted (high).

Table 17 shows the resistors that are enabled during active reset

and during normal operation.

Table 17. Strap Pin Internal Resistors—Active Reset (RST_IN

Pin RST_IN = 0 RST_IN = 1

BMS BM TMR0E (pd) Driven BUSLOCK L1BCMPO L2BCMPO L3BCMPO

pd = internal pull-down 5 k pd_0 = internal pull-down 5 k pu_0 = internal pull-up 5 k

= 0) vs. Normal Operation (RST_IN = 1)

(pd_0) (pu_0) (pd) Driven

(pd_0) (pu_0) (pu) Driven (pu) Driven (pu) Driven

Ω; pu = internal pull-up 5 kΩ;

Ω on DSP ID = 0;

Ω on DSP ID = 0

Rev. 0 | Page 20 of 44 | November 2004

Page 21

ADSP-TS202S—SPECIFICATIONS

Note that component specifications are subject to change without notice. For information on Link port electrical characteristics, see Link Port Low-Voltage, Differential-Signal

(LVDS) Electrical Characteristics and Timing on Page 30.

RECOMMENDED OPERATING CONDITIONS

Parameter Test Conditions Grade

ADSP-TS202S

Min Typ Max Unit

DD_A

DD_IO

DD_DRAM

CASE

IH1

IH2

DD_A

DD_IO

DD_DRAMVDD_DRAM

REF

SCLK_V

Specifications vary for different grades (for example, SABP-060, SABP-050, SWBP-050). For more information on part grades, see Ordering Guide on Page 44.

IH1

RAS

IH2

Applies to input and bidirectional pins.

For details on internal and external power calculation issues, including other operating conditions, see the EE-170, Estimating Power for the ADSP-TS202S on the Analog

Devices website.

Internal Supply Voltage @ CCLK = 500 MHz 050 1.00 1.05 1.10 V

Analog Supply Voltage @ CCLK = 500 MHz 050 1.00 1.05 1.10 V

I/O Supply Voltage (all) 2.38 2.50 2.63 V

Internal DRAM Supply Voltage @ CCLK = 500 MHz 050 1.425 1.500 1.575 V

Case Operating Temperature A –40 +85 °C

High Level Input Voltage

Low Level Input Voltage

VDD Supply Current, Typical Activity

Supply Current, Typical Activity @ CCLK = 500 MHz, VDD = 1.05 V, T

DD_A

Supply Current, Typical Activity 5@ SCLK = 62.5 MHz, V

DD_IO

Supply Current, Typical Activity5@ CCLK = 500 MHz, V

Voltage Reference (all) (V

REF

specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, WRH, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0,

, CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG.

specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.

@ VDD, V

@ CCLK = 500 MHz, VDD = 1.05 V, T

= max (all) 1.7 V

DD_IO

= max (all) 1.9 V

DD_IO

= min (all) 0.8 V

DD_IO

= 2.5 V, T

DD_IO

DD_DRAM

CASE

= 1.5 V, T

= 25ºC 050 2.06 A

= 25ºC 050 20 50 mA

= 25ºC (all) 0.15 A

= 25ºC 050 0.25 0.40 A

CASE

×0.59)±5% V

DD_IO

CLOCK_DRIVE

×0.59)±5% V

Rev. 0 | Page 21 of 44 | November 2004

Page 22

ADSP-TS202S

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Max Unit

High Level Input Current @V

IH_PU

IH_PD

IH_PD_I

Low Level Input Current @V

IL_PU

IL_PU_AD

OZH

OZH_PD

Three-State Leakage Current Low @V

OZL

OZL_PU

OZL_PU_AD

OZL_OD

High Level Output Voltage

Low Level Output Voltage

High Level Input Current @V

Low Level Input Current @V

Three-State Leakage Current High @V

Three-State Leakage Current Low @V

Input Capacitance

2, 3

Parameter name suffix conventions: no suffix = applies to pins without pull-up or pull-down resistors, _PD = applies to pin types (pd) or (pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD

Applies to output and bidirectional pins.

Applies to all signals.

Guaranteed but not tested.

=min, IOH = –2 mA 2.18 V

DD_IO

=min, IOL=4 mA 0.4 V

DD_IO

=max, VIN=VIH max 20 µA

DD_IO

=max, VIN=VIH max 50 µA

DD_IO

=max, VIN=V

DD_IO

=max, VIN=VIH max 30 76 µA

DD_IO

=max, VIN=0 V 20 µA

DD_IO

=max, VIN=0 V 0.3 0.76 mA

DD_IO

=max, VIN= 0 V 30 100 µA

DD_IO

=max, VIN=VIH max 20 µA

DD_IO

=max, VIN=V

DD_IO

=max, VIN=0 V 20 µA

DD_IO

=max, VIN=0 V 0.3 0.76 mA

DD_IO

=max, VIN= 0 V 30 100 µA

DD_IO

=max, VIN =0 V 4 7.6 mA

DD_IO

@fIN=1 MHz, T

CASE

max 0.3 0.76 mA

DD_IO

max 0.3 0.76 mA

DD_IO

=25ºC, VIN=2.5 V 3 pF

Rev. 0 | Page 22 of 44 | November 2004

Page 23

ABSOLUTE MAXIMUM RATINGS

DD_A

DD_IO

)

DD_DRAM

–0.3 V to +1.40 V –0.3 V to +1.40 V –0.3 V to +3.5 V

)1–0.3 V to +2.1 V

–0.5 V to +3.63 V

–65ºC to +150ºC

–0.5 V to V

DD_IO

+0.5 V

Internal (Core) Supply Voltage (VDD) Analog (PLL) Supply Voltage (V External (I/O) Supply Voltage (V External (DRAM) Supply Voltage (V Input Voltage Output Voltage Swing

Storage Temperature Range

Stresses greater than those listed above may cause permanent damage to the device. These

are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-TS202S features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ADSP-TS202S

Rev. 0 | Page 23 of 44 | November 2004

Page 24

ADSP-TS202S

TIMING SPECIFICATIONS

With the exception of DMAR3–0, IRQ3–0, TMR0E, and FLAG3–0 (input only) pins, all ac timing for the ADSP-TS202S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSPTS202S processor has few calculated (formula-based) values. For information on ac timing, see General AC Timing. For information on Link port transfer timing, see Link Port Low-

Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing on Page 30.

General AC Timing

Timing is measured on signals when they cross the 1.25 V level as described in Figure 14 on Page 29. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.25 V and the point that the second signal reaches

1.25 V.

The general ac timing data appears in Table 19 and Table 25. All ac specifications are measured with the load specified in

Figure 35 on Page 37, and with the output drive strength set to

strength 4. In order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to Figure 36 on Page 37 through Figure 43 on Page 38 (Rise and Fall Time vs. Load Capacitance) and Figure 44 on Page 38 (Output Valid vs. Load Capacitance and Drive Strength).

The AC asynchronous timing data for the IRQ3–0 FLAG3–0, and TMR0E pins appears in Table 18.

, DMAR3–0,

Table 18. AC Asynchronous Signal Specifications

Name Description Pulse Width Low (min) Pulse Width High (min)

IRQ3–0 DMAR3–0 FLAG3–0 TMR0E

These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.

For output specifications on FLAG3–0 pins, see Table 25.

This pin is a strap option. During reset, an internal resistor pulls the pin low.

Interrupt Request 2 × t DMA Request 2 × t FLAG3–0 Input 2 ×t Timer 0 Expired 4×t

ns 2 × t

SCLK

ns 2 × t

SCLK

ns 2 ×t

SCLK

ns –

SCLK

ns ns

Rev. 0 | Page 24 of 44 | November 2004

Page 25

Table 19. Reference Clocks—Core Clock (CCLK) Cycle Time

Grade = 050 (500MHz)

Parameter Description

CCLK

CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t

(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 44.

Core Clock Cycle Time 2.0 12.5 ns

) divided by the system clock ratio

SCLK

CCLK

Figure 8. Reference Clocks—Core Clock (CCLK) Cycle Time

Table 20. Reference Clocks—System Clock (SCLK) Cycle Time

SCLKRAT = 4, 6, 8, 10, 12 SCLKRAT = 5, 7

Parameter Description

1, 2, 3

SCLK

SCLKH

SCLKL

SCLKF

SCLKR

5, 6

SCLKJ

For more information, see Table 3 on Page 12.

For more information, see Clock Domains on Page 9.

The value of (t

System clock transition times apply to minimum SCLK cycle time (t

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

System Clock Cycle Time 8 50 8 50 ns System Clock Cycle High Time 0.40 × t System Clock Cycle Low Time 0.40 × t System Clock Transition Time—Falling Edge

–1.5–1.5ns

SCLK

0.60 × t

SCLK

0.45 × t

SCLK

System Clock Transition Time—Rising Edge – 1.5 – 1.5 ns System Clock Jitter Tolerance – 500 – 500 ps

/ SCLKRAT2-0) must not violate the specification for t

SCLK

CCLK

) only.

ADSP-TS202S

UnitMin Max

UnitMin Max Min Max

0.55 × t

SCLK

ns ns

SCLK

SCLKF

SCLKR

SCLK

SCLKH

SCLKL

SCLKJ

Figure 9. Reference Clocks—System Clock (SCLK) Cycle Time

Table 21. Reference Clocks—JTAG Test Clock (TCK) Cycle Time

Parameter Description Min Max Unit

Greater of 30

t t t

TCK

TCKH

TCKL

Test Clock (JTAG) Cycle Time

or t

× 4 – ns

CCLK

Test Clock (JTAG) Cycle High Time 12 – ns Test Clock (JTAG) Cycle Low Time 12 – ns

TCK

TCKH

Figure 10. Reference Clocks—JTAG Test Clock (TCK) Cycle Time

TCKL

Rev. 0 | Page 25 of 44 | November 2004

Page 26

ADSP-TS202S

Table 22. Power-Up Timing

Parameter Min Max Unit

Timing Requirements

VDD_DRAM

For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing.

DD_IO

DD_DRAM

DD_A

Stable After VDD, V

DD_A

VDD_DRAM

, V

Stable >0 ms

DD_IO

Figure 11. Power-Up Timing

Table 23. Power-Up Reset Timing

Parameter Min Max Unit

Timing Requirements

RST_IN_PWR

TRST_IN_PWR

RST_IN Deasserted After VDD, V

TRST Asserted During Power-Up Reset 100 × t

DD_A

, V

DD_IO

, V

DD_DRAM

, SCLK, and Static/Strap Pins Stable 2 ms

SCLK

Switching Characteristic

RST_OUT_PWR

Applies after VDD, V

RST_OUT Deasserted After RST_IN Deasserted 1.5 ms

, V

DD_A

DD_IO

, V

, and SCLK are stable and before RST_IN deasserted.

DD_DRAM

RST_IN

RST_OUT

TRST

SCLK, V

DD,VDD_A,

DD_IO,VDD_DRAM

STATIC/STRAP PINS

RST_IN_PWR

TRST_PWR

RST_OUT_PWR

Figure 12. Power-Up Reset Timing

Rev. 0 | Page 26 of 44 | November 2004

Page 27

ADSP-TS202S

Table 24. Normal Reset Timing

Parameter Min Max Unit

Timing Requirements

RST_IN

STRAP

Switching Characteristic

RST_OUT

RST_IN Asserted 2 ms RST_IN Deasserted After Strap Pins Stable 1.5 ms

RST_OUT Deasserted After RST_IN Deasserted 1.5 ms

RST_IN

RST_OUT

STRAP

STRAP PINS

Figure 13. Normal Reset Timing

Rev. 0 | Page 27 of 44 | November 2004

Page 28

ADSP-TS202S

Table 25. AC Signal Specifications

(All values in this table are in nanoseconds.)

Output Disable

(max)

Name Description

Input Setup

(min)

Input Hold

(min)

Output Valid

(max)

Output Hold

(min)

Output Enable

(min)

ADDR31–0 External Address Bus 1.5 0.5 4.0 1.0 1.15 2.0 SCLK DATA63–0 External Data Bus 1.5 0.75 4.0 1.0 1.15 2.0 SCLK MSH MSSD3–0 MS1–0 RD WRL WRH

Memory Select HOST Line — — 4.0 1.0 1.15 2.0 SCLK Memory Select SDRAM Lines 1.5 0.5 4.0 1.0 1.0 2.0 SCLK Memory Select for Static Blocks — — 4.0 1.0 1.15 2.0 SCLK Memory Read 1.5 0.5 4.0 1.0 1.15 2.0 SCLK Write Low Word 1.5 0.5 4.0 1.0 1.15 2.0 SCLK Write High Word 1.5 0.5 4.0 1.0 1.15 2.0 SCLK Acknowledge for Data High to Low 1.5 0.75 3.6 1.0 1.15 2.0 SCLK

ACK

Acknowledge for Data Low to High 1.5 0.75 4.2 2.0 1.15 2.0 SCLK SDCKE SDRAM Clock Enable 1.5 0.5 4.0 1.0 1.15 2.0 SCLK RAS CAS SDWE

Row Address Select 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

Column Address Select 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

SDRAM Write Enable 1.5 0.5 4.0 1.0 1.15 2.0 SCLK LDQM Low Word SDRAM Data Mask — — 4.0 1.0 1.15 2.0 SCLK HDQM High Word SDRAM Data Mask — — 4.0 1.0 1.15 2.0 SCLK SDA10 SDRAM ADDR10 — — 4.0 1.0 1.15 2.0 SCLK HBR HBG BOFF BUSLOCK BRST BR7–0 BM IORD IOWR IOEN

Host Bus Request 1.5 0.75 — — — — SCLK

Host Bus Grant 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

Back Off Request 1.50.75————SCLK

Bus Lock — — 4.0 1.0 1.15 2.0 SCLK

Burst Pin 1.5 0.5 4.0 1.0 1.15 2.0 SCLK

Multiprocessing Bus Request Pins 1.5 0.75 4.0 1.0 — — SCLK

Bus Master Debug Aid Only — — 4.0 1.0 — — SCLK

I/O Read Pin — — 4.0 1.0 1.0 2.0 SCLK

I/O Write Pin — — 4.0 1.0 1.15 2.0 SCLK

I/O Enable Pin — — 4.0 1.0 1.15 2.0 SCLK

Core Priority Access High to Low 1.5 0.5 4.0 1.0 0.75 2.0 SCLK CPA

Core Priority Access Low to High 1.5 0.5 29.5 2.0 0.75 2.0 SCLK

DMA Priority Access High to Low 1.5 0.5 4.0 1.0 0.75 2.0 SCLK DPA BMS FLAG3–0 RST_IN

3, 4

DMA Priority Access Low to High 1.5 0.5 29.5 2.0 0.75 2.0 SCLK

Boot Memory Select — — 4.0 1.0 1.15 2.0 SCLK

FLAG Pins — — 4.0 1.0 1.15 2.0 SCLK

Global Reset Pin 1.5 2.5 — — — — SCLK TMS Test Mode Select (JTAG) 1.5 0.5 — — — — TCK TDI Test Data Input (JTAG) 1.5 0.5 — — — — TCK TDO Test Data Output (JTAG) — — 4.0 1.0 0.75 2.0 TCK

3, 4

TRST

EMU

ID2–0 CONTROLIMP1–0

Test Reset (JTAG) 1.5 0.5 — — — — TCK

Emulation High to Low — — 5.5 2.0 1.15 4.0 TCK or SCLK

Static Pins—Must Be Constant — — — — — — —

Reference

Clock

Rev. 0 | Page 28 of 44 | November 2004

Page 29

Table 25. AC Signal Specifications (Continued)

(All values in this table are in nanoseconds.)

ADSP-TS202S

Name Description

DS2–0 SCLKRAT2–0

ENEDREG Static Pins—Must Be Connected to V STRAP SYS JTAG SYS

The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The

apparent driver overlap, due to output disables being larger than output enables, is not actual.

For input specifications on FLAG3–0 pins, see Table 18.

These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.

For additional requirement details, see Reset and Booting on Page 9.

RST_IN clock reference is the falling edge of SCLK.

TDO output clock reference is the falling edge of TCK.

Reference clock depends on function.

These pins may change only during reset; recommend connecting it to V

STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.

Specifications applicable during reset only.

JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10,

IOEN

9, 10

11, 12

, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0,

Static Pins—Must Be Constant — — — — — — — Static Pins—Must Be Constant — — — — — — —

Strap Pins 1.50.5————SCLK JTAG System Pins 2.5 10.0 12.0 –1.0 — — TCK

DD_IO/VSS

Input Setup

(min)

Input Hold

(min)

Output Valid

(max)

Output Hold

(min)

Output Enable

(min)1Output Disable

(max)

———————

L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP, L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0, L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO, ACK, CPA SCLKRAT2–0, DS2–0, ENEDREG.

JTAG system output timing clock reference is the falling edge of TCK.

, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0,

REFERENCE

CLOCK

1.25V

SCLK

OR t

TCK

Reference

Clock

INPUT

SIGNAL

OUTPUT

SIGNAL

THREE-

STATE

INPUT

SETUP

OUTPUT

VALID

OUTPUT

DISABLE

1.25V

Figure 14. General AC Parameters Timing

Rev. 0 | Page 29 of 44 | November 2004

INPUT

HOLD

OUTPUT

HOLD

OUTPUT ENABLE

Page 30

ADSP-TS202S

Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing

Table 26 and Table 27 with Figure 15 provide the electrical

characteristics for the LVDS link ports. The LVDS link port signal definitions represent all differential signals with a V level and use signal naming without N (negative) and P (positive) suffixes (see Figure 15).

Table 26. Link Port LVDS Transmit Electrical Characteristics

Parameter Test Conditions Min Max Unit

| Output Differential Voltage RL = 100 Ω 250 650 mV

OCM

Output Voltage High, V Output Voltage Low, V

O_P

or V

O_N

Short-Circuit Output Current V

Common-Mode Output Voltage 1.20 1.50 V

Table 27. Link Port LVDS Receive Electrical Characteristics

Parameter Test Conditions Min Max Unit

| Differential Input Voltage 100 700 mV

ICM

Common-Mode Input Voltage 0.6 1.57 V

=0V

RL = 100 Ω 1.85 V RL = 100 Ω 0.92 V

or V

O_P

= 0 V +5/–55 mA

O_N

= 0 V +/–10 mA

O_P

O_N

VOD=(V

OCM

Figure 15. Link Ports—Transmit Electrical Characteristics

DIF FEREN TIAL PAIR W AVEFO RMS

Lx<PIN>P

Lx<PIN>N

DIF FEREN TIAL VO LTAGE WAVEF ORM

Lx<PIN>

=0V

VOD=V

O_N

O_P

O_P–VO_N

Figure 16. Link Ports—Signals Definition

O_P–VO_N

O_P+VO_N

)

Rev. 0 | Page 30 of 44 | November 2004

Page 31

ADSP-TS202S

Link Port—Data Out Timing

Table 28 with Figure 18, Figure 17, Figure 19, Figure 20, Figure 21, and Figure 22 provide the data out timing for the

LVDS link ports.

Table 28. Link Port—Data Out Timing

Parameter Min Max Unit

Outputs

REO

FEO

LCLKOP

LCLKOH

LCLKOL

COJT

LDOS

LDOH

LACKID

BCMPOV

BCMPOH

Inputs

LACKIS

LACKIH

Timing is relative to the 0 differential voltage (VOD = 0).

LCR (link port clock ratio) = 1, 1.5, 2, or 4. t

The –/+100 value applies for LCLKOUT = 500 MHz.

The 2.5 value for t

The t

and t

LDOS

TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × t

Rising Edge (Figure 18)200ps Falling Edge (Figure 18)200ps

Greater of 2.0 or

LxCLKOUT Period (Figure 17) LxCLKOUT High (Figure 17)0.4×t LxCLKOUT Low (Figure 17)0.4×t LxCLKOUT Jitter (Figure 17)

0.9 × LCR × t

LCLKOP

Smaller of 2.5

LxDATO Output Setup, LCR = 1 and LCR = 1.5 (Figure 19)

0.25 × LCR × t Smaller of 2.5

LxDATO Output Setup, LCR = 2 and LCR = 4 (Figure 19)

0.25 × LCR × t Smaller of 2.5 or

LxDATO Output Hold, LCR = 1 and LCR = 1.5 (Figure 19)

0.25 × LCR × t Smaller of 2.5 or

LxDATO Output Hold, LCR = 2 and LCR = 4 (Figure 19)

0.25 × LCR × t

Delay from LxACKI rising edge to first transmission clock edge (Figure 20)16×LCR×t

LxBCMPO Valid (Figure 20)2×LCR×t LxBCMPO Hold (Figure 21) 3 × TSW – 0.5

1, 2

CCLK

1.1 × LCR × t

0.6 × t

LCLKOP

0.6 × t

LCLKOP

1, 2

CCLK

ns ns ns

–/+ 125 ps

CCLK

1, 6

–0.15

–0.3

–0.15

–0.3

1, 2, 5

CCLK

1, 2

ns ns ns

LxACKI low setup to guarantee that the transmitter stops transmitting (Figure 21) LxACKI high setup to guarantee that the transmitter continues its transmission without any interruption (Figure 22)16×LCR×t

LxACKI High Hold Time (Figure 22)0.5

is the core period.

CCLK

applies for LCLKOUT ≤ 100 MHz.

LDOS

values include LCLKOUT jitter.

LDOH

. For a 1-bit link, it is 8 × LCR × t

CCLK

1, 2

ns ns

ns.

VOD=0V

LxCLKOUT

LCLKOP

COJT

LCLKOH

LCLKOL

Figure 17. Link Ports—Output Clock

Rev. 0 | Page 31 of 44 | November 2004

Page 32

ADSP-TS202S

O_P

O_N

+|V

MIN

OD|

=0V

–

MIN

OD|

REO

L_P

L_N

FEO

RL=100⍀ C

=0.1pF

=5pF

L_P

=5pF

L_N

LxCLKOUT

=0V

LxDATO

VOD=0V

LDOStLDOHtLDOStLDOH

Figure 18. Link Ports—Differential Output Signals Transition Time

LxCLKOUT

=0V

LxDATO

VOD=0V

LxACKI

LxBCMPO

LACK ID

Figure 19. Link Ports—Data Output Setup and Hold

These parameters are valid for both clock edges.

BCMPOV

Figure 20. Link Ports—Transmission Start

Rev. 0 | Page 32 of 44 | November 2004

Page 33

LxCLKOUT

=0V

LxDATO

VOD=0V

ADSP-TS202S

FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD

LAST EDGE IN A QUAD WORD

LxACKI

LxBCMPO

LxCLKOUT

=0V

LACKIS

BCMPOH

Figure 21. Link Ports—Transmission End and Stops

LAST EDGE IN A QUAD WORD

LACKIH

LxDATO

VOD=0V

LxACKI

LACKIS

Figure 22. Link Ports—Back to Back Transmission

Rev. 0 | Page 33 of 44 | November 2004

LACKIH

Page 34

ADSP-TS202S

Link Port—Data In Timing

Table 29 with Figure 23 and Figure 24 provide the data in tim-

ing for the LVDS link ports.

Table 29. Link Port—Data In Timing

Parameter Min Max Unit

Inputs

LCLKIP

LDIS

LDIH

BCMPIS

BCMPIH

Timing is relative to the 0 differential voltage (VOD = 0).

LxCLKIN Period (Figure 24) LxDATI Input Setup (Figure 24)0.2 LxDATI Input Hold (Figure 24)0.2 LxBCMPI Setup (Figure 23)2×t LxBCMPI Hold (Figure 23)2×t

LxCLKIN

=0V

Greater of 1.8 or

0.9 × t

CCLK

LCLKIP

FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD

ns ns ns ns ns

LxCLKIN

=0V

LxDATI

VOD=0V

LxDATI

VOD=0V

LxBCMPI

LCLKIP

LDIStLDIHtLDIStLDIH

BCMPIS

Figure 23. Link Ports—Last Received Quad Word

BCMPIH

Figure 24. Link Ports—Data Input Setup and Hold

These parameters are valid for both clock edges.

Rev. 0 | Page 34 of 44 | November 2004

Page 35

OUTPUT DRIVE CURRENTS

Figure 25 through Figure 32 show typical I–V characteristics for

the output drivers of the ADSP-TS202S processor. The curves in these diagrams represent the current drive capability of the output drivers as a function of output voltage over the range of drive strengths. For complete output driver characteristics, refer to the DSP’s IBIS models, available on the Analog Devices website (www.analog.com).

15.0

A m – T N

E R R U C

I P

T U P T

–10.0

U O

–12.5

–15.0

12.5

10.0

7.5

5.0

2.5

–2.5

–5.0

–7.5

=2.38V,+85°C

DD_IO

=2.38V,+85°C

DD_IO

02.80.4 0.8 1.2 1.6 2.0 2.4

Figure 25. Typical Drive Currents at Strength 0

DD_IO

02.80.4

=2.38V,+85°C

DD_IO

=2.38V,+85°C

A m

– T N

E R R U C

–5

I P

–10

T U P

–15

T U O

–20

–25

–30

Figure 26. Typical Drive Currents at Strength 1

STRENGTH 0

=2.5V,+25°C

DD_IO

=2.5V,+25°C

DD_IO

OUTPUT PIN VOLTAGE – V

STRENGTH 1

=2.5V,+25°C

DD_IO

=2.5V,+25°C

DD_IO

1.2 1.6 2.0 2.4

0.8 OUTPUT PIN VOLTAGE – V

DD_IO

= 2.63V, –40°C

=2.63V,–40°C

= 2.63V, –40°C

STRENGTH 2

= 2.5V, +25°C

DD_IO

=2.38V,+85°C

= 2.5V, +25°C

DD_IO

1.2 1.6 2.0 2.4

0.8 OUTPUT PIN VOLTAGE – V

DD_IO

A m – T N

E R R U C

I P

T U P T U O

–9

–18

–27

–36

–45

02.80.4

DD_IO

=2.38V,+85°C

Figure 27. Typical Drive Currents at Strength 2

A m

– T

N E

R R U C

I P

–11

T U P

–22

T U O

–33

–44

–55

DD_IO

=2.38V,+85°C

02.80.4 0.8 1.2 1.6 2.0 2.4

STRENGTH 3

=2.5V,+25°C

DD_IO

=2.5V,+25°C

DD_IO

OUTPUT PIN VOLTAGE – V

Figure 28. Typical Drive Currents at Strength 3

70 60 50 40

m –

T N E

R R U C

–10

I P

–20

T U

–30

P T

–40

U O

–50 –60 –70

DD_IO

=2.38V,+85°C

= 2.38V, +85°C

02.80.4 0 .8 1.2 1.6 2.0 2.4

STRENGTH 4

=2.5V,+25°C

DD_IO

=2.5V,+25°C

DD_IO

OUTPUT PIN VOLTAGE – V

ADSP-TS202S

= 2.63V, –40°C

DD_IO

= 2.63V, –40°C

DD_IO

= 2.63V, –40°C

DD_IO

= 2.63V, –40°C

DD_IO

=2.63V,–40°C

DD_IO

Rev. 0 | Page 35 of 44 | November 2004

Figure 29. Typical Drive Currents at Strength 4

Page 36

ADSP-TS202S

88 77 66 55 44

A m

– T

N E

R R U C

–11

I P

–22

–33

U P T

–44

U O

–55 –66 –77 –88

DD_IO

=2.38V,+85°C

02.80.4 0.8 1.2 1.6 2.0 2.4

STRENGTH 5

=2.5V,+25°C

DD_IO

=2.5V,+25°C

DD_IO

OUTPUT PIN VOLTAGE – V

Figure 30. Typical Drive Currents at Strength 5

100

A m – T

N E R R U C

I P

T U P T U O

–10 –20 –30 –40 –50 –60 –70 –80 –90

–100

90 80 70 60 50 40 30 20 10

DD_IO

=2.38V,+85°C

DD_IO

02.80.4 0.8 1.2 1.6 2.0 2.4

STRENGTH 6

=2.5V,+25°C

DD_IO

=2.38V,+85°C

=2.5V,+25°C

DD_IO

OUTPUT PIN VOLTAGE – V

Figure 31. Typical Drive Currents at Strength 6

110

A m – T

N E R R U C

I P

T U P T U O

100

–10 –20 –30 –40 –50 –60 –70 –80

–90 –100 –110

90 80 70 60 50 40 30 20 10

DD_IO

=2.38V,+85°C

02.80.4 0.8 1.2 1.6 2.0 2.4

STRENGTH 7

=2.5V,+25°C

DD_IO

=2.5V,+25°C

DD_IO

OUTPUT PIN VOLTAGE – V

Figure 32. Typical Drive Currents at Strength 7

DD_IO

= 2.63V, –40°C

=2.63V,–40°C

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 25 on Page 28. These include output disable time, output

enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 33.

INPUT

OUTPUT

Figure 33. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, C load current, I lowing equation:

The output disable time t t

MEASURED_DIS

switches to when the output voltage decays ∆V from the measured output high or output low voltage. t with test loads C

REFERENCE

OH (MEASURED)

OL (MEASURED)

1.25V 1.25V

. This decay time can be approximated by the fol-

and t

DECAY

DIS

as shown in Figure 34. The time

DECAY

CLV∆()IL⁄=

is the difference between

is the interval from when the reference signal

is calculated

DECAY

MEASURED_ENA

ENA

– ⌬V

+ ⌬V

RAMP

OUTPUT STARTS

1.65V

0.85V

SIGNAL

and IL, and with ∆V equal to 0.4 V.

MEASURED_DIS

DIS

OH (MEASURED)

OL (MEASURED)

DECAY

OUTPUT STOPS

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.25V.

Figure 34. Output Enable/Disable

and the

DRIVING

Rev. 0 | Page 36 of 44 | November 2004

Page 37

ADSP-TS202S

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The time for the voltage on the bus to ramp by ∆V is dependent on the capacitive load, C

, and the drive current, ID.

This ramp time can be approximated by the following equation:

RAMP

The output enable time t t

MEASURED_ENA

and t

RAMP

is the interval from when the reference signal

as shown in Figure 34. The time

CLV∆()ID⁄=

is the difference between

ENA

switches to when the output voltage ramps ∆V from the measured three-stated output level. t

, drive current ID, and with ∆V equal to 0.4 V.

is calculated with test load

RAMP

Capacitive Loading

Output valid and hold are based on standard capacitive loads: 30 pF on all pins (see Figure 35). The delay and hold specifications given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. Figure 36 through Figure 43 show how output rise time varies with capacitance. Figure 44 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on

Page 36.) The graphs of Figure 36 through Figure 44 may not be

linear outside the ranges shown.

OUTPUT

Figure 35. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

s n –

S E M

I T

L L A F

D N A

E S

I R

FALL TIME

Y = 0.251X + 4.2245

10 20 30 40 50 60 70 80 90 100

Y = 0.259X + 3.0842

LOAD CAPACITANCE – pF

Figure 36. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 0

50⍀

30pF

STRENGTH 0

=2.5V)

DD_IO

RISE TIME

1.25V

DD_IO

= 2.5 V) vs.

STRENGTH 1

=2.5V)

s n

– S

E M

I T

L L A

F D

N A

I R

0 102030405060708090100

Y = 0.1527X + 0.7485

DD_IO

FALL TIME

RISE TI ME

Y = 0.1501X + 0.05

LOAD CAPACITANCE – pF

Figure 37. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 1

STRENGTH 2

=2.5V)

s n

– S

E M

I T

L L A

F D

N A

I R

0102030405060708090100

DD_IO

FALL TIME

Y = 0.0949X + 0.8112

RISE TIME

Y = 0.0861X + 0.4712

LOAD CAPACITANCE – pF

Figure 38. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 2

STRENGTH 3

=2.5V)

s n –

E M

I T

L L A

F D

N A

I R

0102030405060708090100

DD_IO

FALL TIME

Y = 0.0691X + 1.1158

RISE TIME

Y = 0.06X + 1.1362

LOAD CAPACITANCE – pF

Figure 39. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 3

DD_IO

=2.5V) vs.

Rev. 0 | Page 37 of 44 | November 2004

Page 38

ADSP-TS202S

STRENG TH 4

=2.5V)

s n

– S

E M

I T

L L

A F

D N A

I R

10 20 30 40 50 60 70 80 90 100

DD_IO

FALL TIME

Y = 0.0592X + 1.0629

RISE TIME

Y = 0.0573X + 0.9789

LOAD CAPACITANCE – pF

Figure 40. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 4

STRENGTH 5

=2.5V)

s n

–

S E M

I T

L L

A F

D N A

E S

I R

10 20 30 40 50 60 70 80 90 100

DD_IO

FALL TIME

Y = 0.0493X + 0.8389

RISE TIME

Y = 0.0481X + 0.7889

LOAD CAPACITANCE – pF

Figure 41. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 5

STREN GTH 6

=2.5V)

s n

– S

E M

I T

L L

A F

D N A

I R

FALL TIME

Y = 0.0374X + 0.851

DD_IO

RISE TIME

Y = 0.0377X + 0.7449

DD_IO

= 2.5 V) vs.

STRENGTH 7

=2.5V)

s n

– S

E M

I T

L L

A F

D N A

E S

I R

FALL TIME

Y = 0.0313X + 0.818

10 20 30 40 50 60 70 80 90 100

DD_IO

RISE TIME

Y = 0.0321X + 0.6512

LOAD CAPACITANCE – pF

Figure 43. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 7

s n

– D

I L A V

T U P T U O

0 102030405060708090100

Figure 44. Typical Output Valid (V Case Temperature and Strength 0–7

The line equations for the output valid vs. load capacitance are:

STRENGTH 0–7

=2.5V)

DD_IO

LOAD CAPACITANCE –pF

= 2.5 V) vs. Load Capacitance at Max

DD_IO

Strength 0: y = 0.0956x + 3.5662 Strength 1: y = 0.0523x + 3.2144 Strength 2: y = 0.0433x + 3.1319 Strength 3: y = 0.0391x + 2.9675 Strength 4: y = 0.0393x + 2.7653 Strength 5: y = 0.0373x + 2.6515 Strength 6: y = 0.0379x + 2.1206 Strength 7: y = 0.0399x + 1.9080

DD_IO

=2.5V) vs.

10 20 30 40 50 60 70 80 90 100

LOAD CAPACITANCE – pF

Figure 42. Typical Output Rise and Fall Time (10%–90%, V Load Capacitance at Strength 6

= 2.5 V) vs.

DD_IO

Rev. 0 | Page 38 of 44 | November 2004

Page 39

ENVIRONMENTAL CONDITIONS

The ADSP-TS202S processor is rated for performance under T

environmental conditions specified in the Recommended

CASE

Operating Conditions on Page 21.

Thermal Characteristics

The ADSP-TS202S processor is packaged in a 25 mm × 25 mm thermally enhanced ball grid array (BGA_ED). The ADSPTS202S processor is specified for a case temperature (T ensure that the T

data sheet specification is not exceeded, a

CASE

heat sink and/or an air flow source may be required.

Table 30 shows the thermal characteristics of the

25 mm × 25 mm BGA_ED package. All parameters are based on a JESD51-9 four-layer 2s2p board. All data are based on 3 W power dissipation.

Table 30. Thermal Characteristics for 25 mm × 25 mm Package

CASE

). To

ADSP-TS202S

Parameter Condition Typical Unit

Airflow = 0 m/s 12.9

°C/W

Airflow = 1 m/s 10.2 °C/W

Airflow = 2 m/s 9.0 °C/W Airflow = 3 m/s 8.0 °C/W

θJA measured per JEDEC standard JESD51-6.

θJA = 12.9°C/W for 0 m/s is for vertically mounted boards. For horizontally

mounted boards, use 17.0°C/W for 0 m/s.

θJB measured per JEDEC standard JESD51-9.

θJC measured by cold plate test method (no approved JEDEC standard).

–7.7°C/W –0.7°C/W

Rev. 0 | Page 39 of 44 | November 2004

Page 40

ADSP-TS202S

576-BALL BGA_ED PIN CONFIGURATIONS

Figure 45 shows a summary of pin configurations for the 576-

ball BGA_ED package and Table 31 lists the signal-to-ball assignments.

AB AC AD

1917 21

KEY:

SIGNAL

DD_IO

DD_DRAM

DD_A

REF

8624

J K

1210

1614

15131195731

TOP VIEW

Figure 45. 576-Ball BGA_ED Pin Configurations1 (Top View, Summary)

For a more detailed pin summary diagram, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com).

Rev. 0 | Page 40 of 44 | November 2004

Page 41

ADSP-TS202S

Table 31. 576-Ball (25 mm × 25 mm) BGA_ED Pin Assignments

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

A1 V

A2 DATA51 B2 V A3 V

A4 DATA49 B4 DATA50 C4 DATA52 D4 V A5 DATA43 B5 DATA44 C5 DATA47 D5 DATA48 A6 DATA41 B6 DATA42 C6 DATA45 D6 DATA46 A7 DATA37 B7 DATA38 C7 DATA39 D7 DATA40 A8 DATA33 B8 DATA34 C8 DATA35 D8 DATA36 A9 DATA29 B9 DATA30 C9 DATA31 D9 DATA32 A10 DATA25 B10 DATA26 C10 DATA27 D10 DATA28 A11 DATA23 B11 DATA24 C11 DATA21 D11 DATA22 A12 DATA19 B12 DATA20 C12 DATA17 D12 DATA18 A13 DATA15 B13 DATA16 C13 V A14 DATA11 B14 DATA12 C14 DATA13 D14 DATA14 A15 DATA9 B15 DATA10 C15 DATA7 D15 DATA8 A16 DATA5 B16 DATA6 C16 DATA3 D16 DATA4 A17 DATA1 B17 DATA2 C17 ACK D17 DATA0 A18 WRL A19 ADDR30 B19 ADDR31 C19 ADDR26 D19 ADDR27 A20 ADDR28 B20 ADDR29 C20 ADDR24 D20 ADDR25 A21 ADDR22 B21 ADDR23 C21 ADDR20 D21 V A22 V

A23 ADDR21 B23 V A24 V

E1 DATA61 F1 DATA63 G1 MSSD1 E2 DATA62 F2 MS1 G2 V E3 DATA57 F3 DATA59 G3 MS0 H3 MSSD3 E4 DATA58 F4 DATA60 G4 BMS H4 SCLKRAT0 E5 V E6 V E7 V E8 V E9 V E10 V E11 V E12 V E13 V E14 V E15 V E16 V E17 V E18 V E19 V E20 V

DD_IO

E21 ADDR15 F21 ADDR13 G21 ADDR7 H21 ADDR3 E22 ADDR14 F22 ADDR12 G22 ADDR6 H22 ADDR2 E23 ADDR11 F23 ADDR9 G23 ADDR5 H23 ADDR1 E24 ADDR10 F24 ADDR8 G24 ADDR4 H24 ADDR0

B1 DATA53 C1 V

C2 V C3 V

B3 V

D1 DATA55 D2 DATA56 D3 DATA54

D13 V

B18 WRH C18 RD D18 BRST

B22 V

B24 ADDR18 C24 V

F5 V F6 V F7 V F8 V F9 V F10 V F11 V F12 V F13 V F14 V F15 V F16 V F17 V F18 V F19 V F20 V

DD_IO

DD_DRAM

DD_IO

C22 V C23 V

G5 V G6 V G7 V G8 V G9 V G10 V G11 V G12 V G13 V G14 V G15 V G16 V G17 V G18 V G19 V G20 V

DD_IO

DD_DRAM

DD_IO

D22 ADDR19 D23 ADDR17 D24 ADDR16 H1 V

H2 MSH

H5 V H6 V H7 V H8 V H9 V H10 V H11 V H12 V H13 V H14 V H15 V H16 V H17 V H18 V H19 V H20 V

DD_IO

Rev. 0 | Page 41 of 44 | November 2004

Page 42

ADSP-TS202S

Table 31. 576-Ball (25 mm × 25 mm) BGA_ED Pin Assignments (Continued)

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

J1 RAS K1 SDA10 L1 SDWE M1 BR3 J2 CAS K2 SDCKE L2 BR0 M2 SCLKRAT1 J3 V J4 V J5 V J6 V J7 V J8 V J9 V J10 V J11 V J12 V J13 V J14 V J15 V J16 V J17 V J18 V J19 V J20 V

REF

J21 L0ACKO K21 L0DATI1_N L21 L0DATI3_N M21 V J22 L0BCMPI K22 L0DATI1_P L22 L0DATI3_P M22 V J23 L0DATI0_N K23 L0CLKINN L23 L0DATI2_N M23 L0DATO3_N J24 L0DATI0_P K24 L0CLKINP L24 L0DATI2_P M24 L0DATO3_P N1 ID0 P1 SCLK R1 V N2 V N3 V N4 V N5 V N6 V N7 V N8 V N9 V N10 V N11 V N12 V N13 V N14 V N15 V N16 V N17 V N18 V N19 V N20 V

DD_A

DD_IO

N21 L0DATO2_N P21 L0DATO1_N R21 NC T21 L1DATI0_N N22 L0DATO2_P P22 L0DATO1_P R22 V N23 L0CLKON P23 L0DATO0_N R23 L0BCMPO N24 L0CLKOP P24 L0DATO0_P R24 L0ACKI T24 L1BCMPI

K3 LDQM L3 BR1 M3 BR5 K4 HDQM L4 BR2 M4 BR6 K5 V K6 V K7 V K8 V K9 V K10 V K11 V K12 V K13 V K14 V K15 V K16 V K17 V K18 V K19 V K20 V

DD_IO

DD_DRAM

DD_IO

P2 SCLK_VREF R2 NC (SCLK) P3 V

L5 V L6 V L7 V L8 V L9 V L10 V L11 V L12 V L13 V L14 V L15 V L16 V L17 V L18 V L19 V L20 V

DD_IO

DD_DRAM

DD_IO

R3 NC (SCLK_VREF)

M5 V M6 V M7 V M8 V M9 V M10 V M11 V M12 V M13 V M14 V M15 V M16 V M17 V M18 V M19 V M20 V

DD_IO

T1 RST_IN T2 SCLKRAT2

T3 BR4 P4 BM R4 BR7 T4 DS0 P5 V P6 V P7 V P8 V P9 V P10 V P11 V P12 V P13 V P14 V P15 V P16 V P17 V P18 V P19 V P20 V

DD_IO

DD_DRAM

DD_IO

R5 V R6 V R7 V R8 V R9 V R10 V R11 V R12 V R13 V R14 V R15 V R16 V R17 V R18 V R19 V R20 V

DD_IO

DD_DRAM

DD_IO

T5 V

T6 V

T7 V

T8 V

T9 V

T10 V

T11 V

T12 V

T13 V

T14 V

T15 V

T16 V

T17 V

T18 V

T19 V

T20 V

T22 L1DATI0_P

T23 L1ACKO

Rev. 0 | Page 42 of 44 | November 2004

Page 43

ADSP-TS202S

Table 31. 576-Ball (25 mm × 25 mm) BGA_ED Pin Assignments (Continued)

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

U1 MSSD0 V1 MSSD2 W1 CONTROLIMP0 Y1 EMU U2 RST_OUT V2 DS2 W2 ENEDREG Y2 TCK U3 ID2 V3 POR_IN U4 DS1 V4 CONTROLIMP1 W4 TDO Y4 FLAG3 U5 V U6 V U7 V U8 V U9 V U10 V U11 V U12 V U13 V U14 V U15 V U16 V U17 V U18 V U19 V U20 V

DD_IO

DD_DRAM

DD_IO

V5 V V6 V V7 V V8 V V9 V V10 V V11 V V12 V V13 V V14 V V15 V V16 V V17 V V18 V V19 V V20 V

DD_DRAM

DD_IO

U21 L1CLKINN V21 L1DATI3_N W21 L1CLKON Y21 L1DATO1_N U22 L1CLKINP V22 L1DATI3_P W22 L1CLKOP Y22 L1DATO1_P U23 L1DATI1_N V23 L1DATI2_N W23 L1DATO3_N Y23 L1DATO2_N U24 L1DATI1_P V24 L1DATI2_P W24 L1DATO3_P Y24 L1DATO2_P AA1 FLAG2 AB1 V AA2 FLAG1 AB2 V AA3 IRQ3 AA4 V

AB3 V AB4 NC AC4 TMS AD4 TRST

AA5 IRQ0 AB5 IRQ2 AC5 IOWR AD5 IORD AA6 IOEN AB6 IRQ1 AC6 DMAR2 AD6 DMAR3 AA7 DMAR0 AB7 DMAR1 AC7 CPA AD7 DPA AA8 HBR AB8 HBG AC8 BOFF AD8 BUSLOCK AA9 L3BCMPO AB9 L3ACKI AC9 L3DATO0_N AD9 L3DATO0_P AA10 L3DATO1_N AB10 L3DATO1_P AC10 L3CLKON AD10 L3CLKOP AA11 L3DATO3_N AB11 L3DATO3_P AC11 L3DATO2_N AD11 L3DATO2_P AA12 V

AB12 V

AA13 L3DATI2_N AB13 L3DATI2_P AC13 L3CLKINN AD13 L3CLKINP AA14 L3DATI1_N AB14 L3DATI1_P AC14 L3DATI0_N AD14 L3DATI0_P AA15 NC AB15 V

AA16 L2DATO0_N AB16 L2DATO0_P AC16 L2BCMPO AD16 L2ACKI AA17 L2CLKON AB17 L2CLKOP AC17 L2DATO1_N AD17 L2DATO1_P AA18 L2DATO3_N AB18 L2DATO3_P AC18 L2DATO2_N AD18 L2DATO2_P AA19 L2CLKINN AB19 L2CLKINP AC19 L2DATI3_N AD19 L2DATI3_P AA20 L2DATI1_N AB20 L2DATI1_P AC20 L2DATI2_N AD20 L2DATI2_P AA21 V

AA22 L1BCMPO AA23 L1DATO0_N AB23 V AA24 L1DATO0_P AB24 V

On revision 1.x silicon, the R2 and R3 pins are NC. On revision 0.x silicon, the R2 pin is SCLK, and the R3 pin is SCLK_V

on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com).

AB21 L2ACKO AC21 L2DATI0_N AD21 L2DATI0_P AB22 V

DD_IO

W3 TDI Y3 TMR0E

W5 V W6 V W7 V W8 V W9 V W10 V W11 V W12 V W13 V W14 V W15 V W16 V W17 V W18 V W19 V W20 V

DD_IO

DD_DRAM

DD_IO

AC1 FLAG0 AD1 V AC2 V AC3 V

DD_IO

Y5 V Y6 V Y7 V Y8 V Y9 V Y10 V Y11 V Y12 V Y13 V Y14 V Y15 V Y16 V Y17 V Y18 V Y19 V Y20 V

AD2 ID1 AD3 V

DD_IO

AC12 L3DATI3_N AD12 L3DATI3_P

AC15 L3ACKO AD15 L3BCMPI

AC22 V AC23 V

DD_IO

AC24 L1ACKI AD24 V

AD22 V

DD_IO

AD23 L2BCMPI

. For more information on SCLK and SCLK_V

REF

Rev. 0 | Page 43 of 44 | November 2004

Page 44

ADSP-TS202S

OUTLINE DIMENSIONS

The ADSP-TS202S processor is available in a 25 mm × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576).

25.2 0

25.0 0

24.8 0

1.25

1.00

0.75

3.10 MAX

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 mm OF ITS IDEAL POSITION RELATIVETO THE PACKAGE EDGES.

3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.

4. CENTER DIMENSIONS ARE NOMINAL.

5. THIS PACKAGE CONFORMS WITH THE JEDEC MS-034 SPECIFICATION.

A1 BALL INDICATOR

25.20

25.00

24.80

1.25

1.00

0.75

TOP VIEW BOTTOM VIEW

DETAIL A

1.00 BSC

23.00 BSC

1.00

BSC

BALL

PITCH

1.00

BSC

0.97 BSC

SEATING PLANE

BALL DIAME TER

1721 1923

25.20

25.00 SQ

24.80

DETAIL A

10121416182024 22

1113

0.75

0.65

0.55

79531

B D F H K M P T V Y AB AD

1.60 MAX

0.60

0.50

0.40

0.20 MAX

A C E G J L N R U W AA AC

Figure 46. 576-Ball BGA_ED (BP-576)

ORDERING GUIDE

Case Temperature Range

Part Number

1, 2, 3, 4

ADSP-TS202SABP-050 –40°C to +85°C 500 MHz 12M bit 1.05 V

S indicates 1.x/2.5 V supplies.

A indicates –40°C to 85°C temperature.

BP indicated thermally enhanced ball grid array (BGA_ED) package.

-050 indicates 500 MHz operation.

The instruction rate is the same as the internal processor core clock (CCLK) rate.

The BP-576 package measures 25 mm × 25 mm.

C04325-0-11/04(0)

Instruction

Rate

On-Chip DRAM

Operating Voltage Package

Rev. 0 | Page 44 of 44 | November 2004

, 2.5 V

DD_IO

, 1.5 V

DD_DRAM

(BP-576)

Datasheet ADSP-TS202S Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

KEY FEATURES

KEY BENEFITS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

DUAL COMPUTE BLOCKS

DATA ALIGNMENT BUFFER (DAB)

DUAL INTEGER ALU (IALU)

PROGRAM SEQUENCER

Interrupt Controller

Flexible Instruction Set

DSP MEMORY

EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

Host Interface

Multiprocessor Interface

SDRAM Controller

EPROM Interface

DMA CONTROLLER

LINK PORTS (LVDS)

TIMER AND GENERAL-PURPOSE I/O

RESET AND BOOTING

CLOCK DOMAINS

POWER DOMAINS

FILTERING REFERENCE VOLTAGE AND CLOCKS

DEVELOPMENT TOOLS

EVALUATION KIT

ADDITIONAL INFORMATION

PIN FUNCTION DESCRIPTIONS

STRAP PIN FUNCTION DESCRIPTIONS

ADSP-TS202S—SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

General AC Timing

Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing

Link Port—Data Out Timing

Link Port—Data In Timing

OUTPUT DRIVE CURRENTS

TEST CONDITIONS

Output Disable Time

Output Enable Time

Capacitive Loading

ENVIRONMENTAL CONDITIONS

Thermal Characteristics

576-BALL BGA_ED PIN CONFIGURATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE