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ADSP-TS201S EZ-KIT Lite
®
Evaluation System Manual
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
Revision 2.0, January 2005
Part Number
82-000770-01
a
Page 2
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Limited Warranty
The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, TigerSHARC, VisualDSP++, the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog
Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
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Regulatory Compliance
The ADSP-TS201S EZ-KIT Lite evaluation system has been certified to
comply with the essential requirements of the European EMC directive
89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE”
mark.
The ADSP-TS201S EZ-KIT Lite evaluation system had been appended to
Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE
Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
Page 4
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CONTENTS
PREFACE
Purpose of This Manual ................................................................. xii
Intended Audience ......................................................................... xii
Manual Contents ........................................................................... xii
What’s New in This Manual .......................................................... xiii
Technical or Customer Support ...................................................... xiv
Supported Processors ...................................................................... xiv
Product Information ....................................................................... xv
MyAnalog.com .......................................................................... xv
Processor Product Information ................................................... xv
Related Documents .................................................................. xvi
Online Technical Documentation ............................................ xvii
Accessing Documentation From VisualDSP++ .................... xviii
Accessing Documentation From Windows .......................... xviii
Accessing Documentation From Web ................................... xix
Printed Manuals ....................................................................... xix
VisualDSP++ Documentation Set ......................................... xix
Hardware Tools Manuals ...................................................... xix
Processor Manuals ................................................................. xx
ADSP-TS201S EZ-KIT Lite Evaluation System Manual v
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CONTENTS
Data Sheets .......................................................................... xx
Notation Conventions ................................................................... xxi
USING EZ-KIT LITE
Package Contents ......................................................................... 1-2
Default Configuration .................................................................. 1-3
Installation and Session Startup ..................................................... 1-5
Evaluation License Restrictions ..................................................... 1-6
Memory Map ............................................................................... 1-6
SDRAM Interface ......................................................................... 1-7
Flash Memory .............................................................................. 1-8
Programmable FLAG Pins ............................................................ 1-9
Interrupt Pins ............................................................................. 1-10
Audio Interface ........................................................................... 1-11
Processor Link Ports ................................................................... 1-11
Example Programs ...................................................................... 1-12
Flash Programmer Utility ............................................................ 1-13
EZ-KIT LITE HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
External Port ........................................................................... 2-3
Expansion Interface ................................................................. 2-3
JTAG Emulation Port ............................................................. 2-4
Switch Settings ............................................................................. 2-5
Audio Amplification Selection (SW1) ...................................... 2-6
vi ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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CONTENTS
Processor Mode Selections (SW2) ............................................ 2-6
Processor Boot Strap Settings .............................................. 2-7
SYSCON/SDRCON Mode Settings .................................... 2-7
Interrupt Enable Settings .................................................... 2-8
Link Port Width Settings .................................................... 2-8
FLAGs and IRQs Switch Settings (SW10) ................................ 2-9
Configuration Resistors ............................................................... 2-10
Processor ID Settings ............................................................. 2-10
Clock Mode Settings ............................................................. 2-12
Control Impedance Selection ................................................. 2-14
Drive Strength Selection ........................................................ 2-15
LEDs and Push Buttons .............................................................. 2-16
Power LED (LED1) ............................................................... 2-16
Reset LEDs (LED2 and LED8) .............................................. 2-17
FLAG LEDs (LED3–6) ......................................................... 2-17
USB Monitor LED (LED9) ................................................... 2-17
Programmable FLAG Push Buttons (SW6–9) ......................... 2-18
Interrupt Push Buttons (SW4–5) ........................................... 2-18
Reset Push Button (SW3) ...................................................... 2-19
Connectors ................................................................................. 2-19
Audio (P1–2) ........................................................................ 2-20
Power (P3) ............................................................................ 2-20
JTAG (P4) ............................................................................ 2-21
USB (P5) .............................................................................. 2-21
ADSP-TS201S EZ-KIT Lite Evaluation System Manual vii
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CONTENTS
Expansion Interface (J1–3) .................................................... 2-21
Link Ports (J4–7) .................................................................. 2-22
Specifications ............................................................................. 2-22
Power Supply ........................................................................ 2-22
BILL OF MATERIALS
INDEX
viii ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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PREFACE
Thank you for purchasing the ADSP-TS201S EZ-KIT Lite®, Analog
Devices (ADI) evaluation system for TigerSHARC
embedded processors.
The TigerSHARC processor is a Static Super Scalar (SSS) architecture targeted at software-defined radio applications. In these wireless
infrastructure applications, the TigerSHARC processor is replacing
field-programmable gate arrays (FPGAs) in the Chip Rate processing
applications for third generation cellular. The performance, flexibility,
multiprocessing and IO capabilities of the TigerSHARC processor makes
it superior to FPGA implementations.
The evaluation board is designed to be used in conjunction with the VisualDSP++
ADSP-TS201S TigerSHARC processor. The VisualDSP++ development
environment gives you the ability to perform advanced application code
development and debug, such as:
®
development environment to test the capabilities of the
• Create, compile, assemble, and link application programs written
in C++, C, and ADSP-TS201S assembly
• Load, run, step-in, step-out, step-over, halt, and set breakpoints in
application program
®
floating-point
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Page 10
Access to the ADSP-TS201S processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-TS201S processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/processors/tools/.
The ADSP-TS201S EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.
L
Refer to the VisualDSP++ Installation Quick Reference Card for details.
The board features:
The ADSP-TS201S EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. Once
the initial unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-TS201S EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 128K words of internal
memory for code space with no restrictions for data space.
• Two Analog Devices ADSP-TS201S processors
D 500 MHz Core Clock Speed
D Configurable Core Clock Mode
• Analog Devices AD1871 96 kHz Analog-to-Digital Converter
D Line-In 3.5 mm Stereo Jack
x ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Preface
• Analog Devices AD1854 96 kHz Digital-to-Analog Converter
D Line-Out 3.5 mm Stereo Jack
• SDRAM Memory
D 32 MB (4 MB x 64)
• Flash Memory
D 512K Main Flash Memory
• USB Debugging Interface
• Interface Connectors
D 14-Pin Emulator Connector for JTAG Interface
D LVDS Link Ports via RJ-45 Connectors
D Expansion Interface Connectors (not populated)
• General-Purpose IO
D 4 Push Button FLAGS (two for each processor)
D 2 Push Button Interrupts (one for each processor)
D 4 LED FLAG Outputs (two for each processor)
• Analog Devices ADP3331, ADP3336, and ADP3339 for Voltage
Regulation
The EZ-KIT Lite board contains two external memories: flash memory
and SDRAM. The flash memory can be used to store user-specific boot
code. By configuring the boot mode switch (
SW2) and programming the
flash memory, the board can run as a stand-alone unit. The SDRAM is
shared by both processors and can be used to store data external to the
processors. For more information, see “Memory Map” on page 1-6.
The EZ-KIT Lite board contains an audio interface, facilitating creation
of audio signal processing applications.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual xi
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Purpose of This Manual
Additionally, the EZ-KIT Lite board provides expansion connectors,
allowing you to connect to the processor’s external port (EP).
Purpose of This Manual
The ADSP-TS201S EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes the operation and configuration of the board components and
provides guidelines for running your own code on the ADSP-TS201S
EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a
reference for future designs.
The product software installation is detailed in the
Intended Audience
The primary audience of this manual is a programmer who is familiar with
Analog Devices processors. This manual assumes that the audience has a
working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors
can use this manual but should supplement it with other texts (such as the
ADSP-TS201 TigerSHARC Processor Hardware Reference and the
ADSP-TS201 TigerSHARC Processor Programming Reference) that describe
your target architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
Manual Contents
The manual consists of:
xii ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Preface
• Chapter 1, “Using EZ-KIT Lite” on page 1-1
Provides information on the EZ-KIT Lite from a programmer’s
perspective and outlines the board’s memory map.
• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1
Provides information on the hardware aspects of the EZ-KIT Lite.
• Appendix A, “Bill Of Materials” on page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
• Appendix B, “Schematics” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
L
This appendix is not part of the online Help. The online Help
viewers should go to the PDF version of the ADSP-TS201S
EZ-KIT Lite Evaluation System Manual located in the
Docs\EZ-KIT Lite Manuals folder on the installation CD to see the
schematics. Alternatively, the schematics can be found on the Analog Devices Web site,
www.analog.com/processors.
What’s New in This Manual
This revision of the ADSP-TS201S EZ-KIT Lite Evaluation System Manual
provides an updated listing of related documents and updated licensing
information.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual xiii
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Technical or Customer Support
Technical or Customer Support
You can reach DSP Tools Support in the following ways.
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technicalSupport
• E-mail tools questions to
dsptools.support@analog.com
• E-mail processor questions to
dsp.support@analog.com
• Phone questions to 1-800-ANALOGD
• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
The ADSP-TS201S EZ-KIT Lite evaluation system supports the Analog
Devices ADSP-TS201S TigerSHARC embedded processors.
xiv ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Product Information
You can obtain product information from the Analog Devices website,
from the product CD-ROM, or from the printed publications (manuals).
Preface
Analog Devices is online at
mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and embedded processors.
www.analog.com. Our website provides infor-
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
Registration:
Visit
www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and processors, visit our Web
site at www.analog.com/processors, which provides access to technical
publications, data sheets, application notes, product overviews, and product announcements.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual xv
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Product Information
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
• E-mail questions or requests for information to
dsp.support@analog.com
• Fax questions or requests for information to
1-781-461-3010 (North America)
+49 (89) 76 903-557 (Europe)
• Access the FTP Web site at
ftp ftp.analog.com or ftp 137.71.23.21
ftp://ftp.analog.com
Related Documents
For information on product related development software, see the following publications.
Table 1. Related Processor Publications
Title Description
ADSP-TS201S Embedded Processor Datasheet General functional description, pinout, and
timing
ADSP-TS201 TigerSHARC Processor Hardware
Reference
ADSP-TS201 TigerSHARC Processor Programming Reference
Description of internal processor architecture
and all register functions
Description of all allowed processor assembly
instructions
Table 2. Related VisualDSP++ Publications
Title Description
VisualDSP++ User’s Guide Description of VisualDSP++ features and usage
VisualDSP++ Assembler and Preprocessor
Manual
Description of the assembler function and commands
xvi ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Table 2. Related VisualDSP++ Publications (Cont’d)
Title Description
Preface
VisualDSP++ C/C++ Complier and
Library Manual for TigerSHARC Processors
VisualDSP++ Linker and Utilities Manual Description of the linker function and commands
VisualDSP++ Loader Manual Description of the loader/splitter function and com-
Description of the complier function and commands for TigerSHARC processors
mands
All documentation is available online. Most documentation is available in
printed form.
If you plan to use the EZ-KIT Lite board in conjunction with a
L
JTAG emulator, also refer to the documentation that accompanies
the emulator.
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
http://www.analog.com/processors/resources/technicalLibrary
Online Technical Documentation
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary
Docs folder on the VisualDSP++ installation CD.
.PDF files of most manuals are provided in the
Each documentation file type is described as follows.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual xvii
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Product Information
File Description
.CHM Help system files and manuals in Help format
.HTM or
.HTML
.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the
Internet Explorer 4.0 (or higher).
Viewing and printing the
Reader (4.0 or higher).
.PDF files requires a PDF reader, such as Adobe Acrobat
.HTML files requires a browser, such as
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows
®
Explorer, or the Analog Devices
Web site.
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
To view ADSP-TS201S EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
Help system files (.
CHM) are located in the Help folder, and .PDF files are
located in the Docs folder of your VisualDSP++ installation CD-ROM.
The
Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.
xviii ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Your software installation kit includes online Help as part of the Win-
®
dows
interface. These help files provide information about VisualDSP++
and the ADSP-TS201S EZ-KIT Lite evaluation system.
Accessing Documentation From Web
Download manuals at the following Web site:
http://www.analog.com/processors/resources/technicalLibrary/manuals
.
Preface
Select a processor family and book title. Download archive (.
ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
Hardware Tools Manuals
To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual xix
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Product Information
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
xx ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example Description
Preface
Close command
(File menu)
{this | that} Alternative required items in syntax descriptions appear within curly
[this | that] Optional items in syntax descriptions appear within brackets and sepa-
[this,…] Optional item lists in syntax descriptions appear within brackets
.SECTION Commands, directives, keywords, and feature names are in text with
filename Non-keyword placeholders appear in text with italic style format.
L
a
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close
command appears on the File menu).
brackets and separated by vertical bars; read the example as
that. One or the other is required.
rated by vertical bars; read the example as an optional
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of
letter gothic font.
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
this.
this or
this or that.
Warn in g: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
[
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Wa rn in g
appears instead of this symbol.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual xxi
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Notation Conventions
L
Additional conventions, which apply only to specific chapters, may
appear throughout this document.
xxii ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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1 USING EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-TS201S EZ-KIT Lite evaluation system.
The information appears in the following sections.
• “Package Contents” on page 1-2
Lists the items contained in your ADSP-TS201S EZ-KIT Lite
package.
• “Default Configuration” on page 1-3
Shows the default configuration of the ADSP-TS201S EZ-KIT
Lite.
• “Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing
ADSP-TS201SEZ-KIT Lite session using VisualDSP++.
• “Evaluation License Restrictions” on page 1-6
Describes the restrictions of the VisualDSP++ demo license
shipped with the EZ-KIT Lite.
• “Memory Map” on page 1-6
Describes the ADSP-TS201S EZ-KIT Lite board’s memory map.
• “SDRAM Interface” on page 1-7
Defines the register values needed to configure the external memory for SDRAM access.
• “Flash Memory” on page 1-8
Describes how to program and use the flash memory.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-1
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Package Contents
• “Programmable FLAG Pins” on page 1-9
Describes the function and use of the programmable FLAG pins on
the EZ-KIT Lite evaluation system.
• “Interrupt Pins” on page 1-10
Describes the function and use of the interrupt pins on the
EZ-KIT Lite evaluation system.
• “Audio Interface” on page 1-11
Describes how to use and configure the audio interface.
• “Processor Link Ports” on page 1-11
Describes how to use and configure the link ports.
• “Example Programs” on page 1-12
Provides information about the example programs included in the
ADSP-TS201S EZ-KIT Lite evaluation system.
• “Flash Programmer Utility” on page 1-13
Provides information on the Flash Programmer utility included
with VisualDSP++.
For detailed information about programming the ADSP-TS201S TigerSHARC processor, see the documents referred to as “Related
Documents”.
Package Contents
Your ADSP-TS201S EZ-KIT Lite package contains the following items.
• ADSP-TS201S EZ-KIT Lite board
• VisualDSP++ Installation Quick Reference Card
• ADSP-TS201S EZ-KIT Lite Evaluation System Manual (this
document)
1-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Using EZ-KIT Lite
• CD containing:
D VisualDSP++ software
D ADSP-TS201 EZ-KIT Lite debug software
D USB driver files
D Example programs
• Universal 7.5V DC power supply
• USB 2.0 cable
• Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
The ADSP-TS201S EZ-KIT Lite board is designed to run outside your
personal computer as a stand-alone unit. You do not have to open your
computer case.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings, DIP
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-3
Page 26
Default Configuration
switches, connector locations, and LEDs used in installation. Confirm
that your board is set up in the default configuration) before using the
board.
Figure 1-1. EZ-KIT Lite Hardware Setup
1-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Installation and Session Startup
Using EZ-KIT Lite
L
To set up an EZ-KIT Lite session in VisualDSP++:
For correct operation, install the software and hardware in the
order presented in the VisualDSP++ Installation Quick Reference
Card.
1. Verify that the yellow USB monitor LED (
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. From the Start menu, navigate to the VisualDSP++ environment
via the Programs menu.
If you are running VisualDSP++ for the first time, the New Session
dialog box appears on the screen (skip the rest of the procedure and
go to step 3).
If you have run VisualDSP++ previously, the last opened session
appears on the screen.
To switch to another session, via the Session List dialog box, hold
down the Ctrl key while starting VisualDSP++ (go to step 5).
3. In Debug Target, choose TigerSHARC Emulators/EZ-KIT Lites.
In Platform, select ADSP-TS201 EZ-KIT Lite via Debug Agent.
In Session name, type a new name or accept the default.
LED9, located near the
4. Click OK to return to the Session List.
5. Highlight the session and click Activate.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-5
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Evaluation License Restrictions
Evaluation License Restrictions
The ADSP-TS201S EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-TS201S EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 128K words of internal
memory for code space with no restrictions for data space.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
Memory Map
The ADSP-TS201S processor has 24 Mbits of internal memory that can
be used for program storage or data storage. The configuration of internal
memory is detailed in the ADSP-TS201 TigerSHARC Processor Hardware
Reference.
The ADSP-TS201S EZ-KIT Lite board contains 512K x 8-bit of external
flash memory. The memory is divided into eight uniform 64 Kb sections.
This memory connects to the processor’s
memory can be accessed in boot memory space as well as the external
memory bank zero space.
The board also contains 4M x 64-bit of external SDRAM memory. This
memory connects to the processor’s SDRAM interface.
1-6 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
~BMS and ~MSO pins. The flash
Page 29
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start Address End Address Content
Internal
Memory
External
Memory
0x0000 0000 0x 0001 FFFF Internal Memory 0
0x0004 0000 0x0005 FFFF Internal Memory 2
0x0008 0000 0x0009 FFFF Internal Memory 4
0x000C 0000 0x000D FFFF Internal Memory 6
0x0010 0000 0x0011 FFFF Internal Memory 8
0x0014 0000 0x0015 FFFF Internal Memory 10
0x001E 0000 0x001E 03FF Internal Registers
0x001F 0000 0x001F 03FF SOC Registers
0x0C00 0000 0x0FFF FFFF Broadcast
0x1000 0000 0x13FF FFFF Processor ID 0
0x1400 0000 0x17FF FFFF Processor ID 1
0x3000 0000 0x37FF FFFF External Memory Space Bank 0 (MS0);
MS0 includes flash memory which ends at
0x3007 FFFF.
0x3800 0000 0x39FF FFFF External Memory Space Bank 1
0x4000 0000 0x43FF FFFF External Memory Space (MSSD0);
MSSD0 includes SDRAM which ends at
0x407F FFFF.
0x8000 0000
0xFFFF FFFF
Host
Using EZ-KIT Lite
SDRAM Interface
The SDRAM on the EZ-KIT Lite evaluation board is 32 MB. To access
SDRAM, the
The SDRAM default values are:
•
SYSCON = 0x00189067
• SDRCON = 0x00005983
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-7
SYSCON and SDRCON registers must be configured properly.
Page 30
Flash Memory
For the supplied memory, the
follows:
• SDRAM enable, CAS latency of two cycles
• pipe depth of zero, page boundary of 256 words
• refresh rate of every 3700 cycles, precharge to RAS of two cycles
• RAS to precharge of five cycles
• init sequence is MRS cycle follows refresh
[
L
The SYSCON and SDRCON registers define bus control configuration.
They can be written once only after reset and cannot be changed
during system operation.
In emulation space, the SYSCON and the SDRCON registers can be
written to as many times as needed. The USB debug monitor operates in emulation space and allows “always writable” mode for these
registers.
Flash Memory
SDRCON register should be configured as
The AT49BV040 chip provides a total of 512K x 8-bits of external flash
memory, arranged into eight uniform 64 Kb memory blocks. The block
addresses are shown in Table 1-2.
Table 1-2. Flash Memory Map
Start Address End Address Content
0x3000 0000 0x3000 FFFF Uniform Block 0
0x3001 0000 0x3001 FFFF Uniform Block 1
0x3002 0000 0x3002 FFFF Uniform Block 2
0x3003 0000 0x3003 FFFF Uniform Block 3
1-8 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Using EZ-KIT Lite
Table 1-2. Flash Memory Map (Cont’d)
Start Address End Address Content
0x3004 0000 0x3004 FFFF Uniform Block 4
0x3005 0000 0x3005 FFFF Uniform Block 5
0x3006 0000 0x3006 FFFF Uniform Block 6
0x3007 0000 0x3007 FFFF Uniform Block 7
To program the flash memory with your boot code, you must first create a
loader file from your processor code. You set up the loader in VisualDSP++ depending on how you plan to boot the flash. For information
on creating a loader file, refer to VisualDSP++ online help and the
VisualDSP++ Loader Manual.
Next, the loader file must be programmed into the flash memory. This can
be done using the VisualDSP++ Flash Programmer utility (see “Flash Pro-
grammer Utility” on page 1-13).
Programmable FLAG Pins
Each ADSP-TS201S processor has four programmable FLAG pins. Two
FLAG pins from each processor (
the running program through the use of a switch (SW6–9). The FLAG2 and
FLAG3 pins from each processor are connected to LEDs (LED3–6).
After the processor is reset, the programmable FLAGs are configured as
inputs. The direction of each programmable FLAG is configured in the
FLAGREG register. If the FLAG is configured for an output, the value to be
output is set in the
FLAGREG register. If the FLAG is configured for an
input, the value on the FLAG pin is read from the SQSTAT register. Programmable FLAGs are summarized in Table 1-3. For more information
on how to configure the programmable FLAG pins, see the ADSP-TS201S
TigerSHARC Processor Hardware Reference.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-9
FLAG0 and FLAG1) allow interaction with
Page 32
Interrupt Pins
Table 1-3. Programmable FLAG Pin Summary
FLAG Connected To Use
FLAG0_A SW9
FLAG1_A SW8
FLAG0_B SW6
FLAG1_B
FLAG2_A LED4
FLAG3_A LED6
FLAG2_B LED5
FLAG3_B LED3
SW7
The FLAG0 and FLAG1 pins are connected to the push
buttons to supply feedback for program execution. For
instance, you can write user input to trigger a routine
when the push button is pressed.
The FLAG2 and FLAG3 pins are connected to the LEDs to
supply feedback during program execution.
Interrupt Pins
The ADSP-TS201S processor includes four interrupt pins (IRQ3–0) for
interaction with the running program. One external interrupt from each
processor is directly accessible through push button switches
on the EZ-KIT Lite board. Interrupts are summarized in Table 1-4. For
more information on configuring the interrupt pins, see the
ADSP-TS201S TigerSHARC Processor Hardware Reference.
SW4 and SW5
Table 1-4. Interrupt Pin Summary
Interrupt Connected To Use
IRQ0_A SW4 The IRQ0 interrupt is connected to push buttons to supply
IRQ0_B SW5
feedback for program execution. For instance, you can write
your code to perform a different function when an interrupt is
detected.
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Using EZ-KIT Lite
Audio Interface
The audio interface of the EZ-KIT Lite board allows you to interface with
the board’s analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The audio interface consists of two main ICs: AD1871 and
AD1854.
The AD1871 is a stereo audio ADC intended for digital audio applications requiring high-performance analog-to-digital conversion. The
AD1871 provides 97 dB THD+N and 107 dB dynamic range.
The AD1854 is a high-performance, single-chip stereo, audio DAC delivering 113 dB dynamic range and 112 dB SNR at a 48 kHz sample rate.
Because the ADSP-TS201S processor does not have any SPORTs, an Xilinx field-programmable gate array (FPGA) generates the audio interface
control signals between the processor and the audio circuit. Setting the
FLAG3 signal of processor A “high” enables the audio interface inside of the
FPGA. Once the audio interface has been enabled, the audio data can be
transferred to and from the processor by generating a
audio data interfaces with the processor via the lowest 24 bits of the data
bus (
D23–0).
DMAR0 cycle. The
Refer to the audio example program included in the EZ-KIT Lite’s installation directory for more information on how to use the audio interface.
Refer to “Audio (P1–2)” on page 2-20 for information about the audio
connectors.
Processor Link Ports
The link ports on the ADSP-TS201S processor use LVDS signaling to
communicate with each another. Each processor has a TX (transmit) port
and RX (receive) port for each of its link ports. The RJ-45 connectors,
and
J5, are the TX and RX for processor A. Similarly, J6 and J7 are TX
and RX for processor B. The TX and RX of one processor’s link ports
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-11
J4
Page 34
Example Programs
should be respectively connected to RX and TX of another processor’s link
port. In this manner, the TX of one processor connects to the RX of the
other processor.
The link ports should be connected using a standard CAT 5E networking
cable. The length of the cable may affect the maximum frequency at which
the data can be transferred. Refer to the ADSP-TS201S Embedded Proces-
sor Datasheet for more information.
There are four link ports on each of the processors on the EZ-KIT Lite.
Link Port0 of both processors connects to the field-programmable gate
array (FPGA) at
U20. Link Port1 of both processors connects to J3 of the
expansion interface. Link Port2 of each of the processors connects to each
other. Finally,
The
L0CLKIN_P of both processor A and processor B are pulled up inter-
Link Port3 connects to the RJ-45 connectors (J4–J7).
nally in the FPGA. Similarly, L0CLKININ_N of both processor A and
processor B are pulled down internally in the FPGA. Finally,
R12 and R28
are not populated. All of this is done to avoid noise affecting the EZ-KIT
Lite operation.
To suppress noise from the expansion interface, a similar pull-up or
pull-down scheme has been used on
R239 are used to pull up L1CLKIN_P of both processors. Similarly, R242 and
R241 are used to pull down L1CLKIN_N of both processors. Finally, R14 and
R30 are not populated to avoid a short between 2.5V power and GND. The
Link Port1. The board’s R240 and
link ports can be reactivated by removing the pull up and pull downs and
adding a 100 Ohm resistor on
R14 and R30.
Example Programs
Example programs are provided with the ADSP-TS201S EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
1-12 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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Using EZ-KIT Lite
\…\TS\EZ-KITs\ADSP-TS201\Examples subdirectory of the VisualDSP++
installation directory. Please refer to the readme file provided with each
example program for more information.
[
When running the examples, do not change these bits:
BGEN or NMOD (bits 8 or 9) in the SQCTL register.
The change can disable communications with the host.
Flash Programmer Utility
The ADSP-TS201S EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on
the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++.
Once the utility is installed, it is accessible from the Tools pull-down
menu.
For more information on the Flash Programmer utility, refer to the online
Help.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-13
Page 36
Flash Programmer Utility
1-14 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 37
2 EZ-KIT LITE HARDWARE
REFERENCE
This chapter describes the hardware design of the ADSP-TS201S EZ-KIT
Lite board. The following topics are covered.
• “System Architecture” on page 2-2
Describes the configuration of the ADSP-TS201S processor and
explains how the board components interface with the EZ-KIT
Lite.
• “Switch Settings” on page 2-5
Shows the location and describes the function of each configuration DIP switch.
• “Configuration Resistors” on page 2-10
Shows the location and describes the function of each configuration resistor.
• “LEDs and Push Buttons” on page 2-16
Shows the location and describes the function of the LEDs and
push buttons.
• “Connectors” on page 2-19
Shows the location of and gives the part number for all of the connectors on the board. In addition, provides the manufacturer and
part number information for the mating parts.
• “Specifications” on page 2-22
Describes the power connector.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-1
Page 38
System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-TS201S TigerSHARC processor. The processor is powered by
three separate regulators for the core, the internal DRAM, and the IO.
2-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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EZ-KIT Lite Hardware Reference
The processor core voltage is set to 1.15V. The internal DRAM is powered by an external 1.5V regulator. Finally, the external interface (IO)
operates at 2.5V but can accept up to 3.3V levels.
A 20 MHz SMT oscillator in conjunction with a clock generator set to 5x
supply the input clock to the processors. The speed at which the core
operates is determined by pull-up and pull-down resistors on both the
clock generator (
U1) and the SCLKRAT[2:0] bit of each of the processors.
For more information, see “Clock Mode Settings” on page 2-12. By
default, the processor core runs at 500 MHz (20 MHz x 5 (
U1) x 5
(sclkrat) =500 MHz).
External Port
The external port (EP) connects to a 512K x 8-bit flash memory. The
flash memory connects to the boot memory select pin (
bank zero pin (
~MS0), allowing the memory to be used to boot the proces-
sor as well as to store information during normal operation. Refer to
“Flash Memory” on page 1-8 for information about the flash memory
locations.
~BMS) and memory
The EP also connects to a 4M x 64-bit SDRAM. Refer to “SDRAM Inter-
face” on page 1-7 for information on how to configure the SDRAM
registers.
Expansion Interface
The expansion interface consists of three connectors. The following table
shows the interfaces each connector provides. For the exact pinout of these
connectors, refer to Appendix B, “Schematics”.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-3
Page 40
System Architecture
Table 2-1. Expansion Interface Connectors
Connector Interfaces
J1 5V, GND, Address, Data
J2 2.5V, GND, SDRAM control signals, FLAGs, IRQs, TIMERs, Data
J3 GND, Reset, DMA, Memory Control, CLKOUT, Link Ports signals
When you use the expansion interface, limits to the current and to the
interface speed must be taken into consideration. The maximum current
limit depends on the capabilities of the regulator. Additional circuitry can
also add extra loading to signals, decreasing their maximum effective
speed.
L
Analog Devices does not support and is not responsible for the
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory, as well as the special function registers
through a 14-pin header. See “JTAG (P4)” on page 2-21 for more infor-
mation about the JTAG connector. To learn more about available
emulators, contact Analog Devices as described in “Product Information”
on page -xv.
For more information about designing JTAG into a custom board or to
learn more about the JTAG interface, please refer to EE-68 found at Analog Devices website.
2-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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EZ-KIT Lite Hardware Reference
Switch Settings
This section describes the function of the DIP switches SW1, SW2, and
SW10. The location of the switches and their respective default settings are
shown in Figure 2-2.
Figure 2-2. Switch Locations
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-5
Page 42
Switch Settings
Audio Amplification Selection (SW1)
The SW1 switch determines the amplification of right and left signals connected to the
Line-IN connector P1. A non-powered electret microphone
can be used by simply varying the switch setting to the values shown in
Table 2-2. An amplification gain of a factor of 10 can be achieved by set-
ting the switch into electret microphone use.
Table 2-2. Audio Amplification Selection (SW1)
Position 1 Position 2 Position 3 Position 4 Audio Amplification Mode
1
OFF
ON ON OFF OFF For electret microphone use
1 Default settings
OFF ON ON No amplification
Processor Mode Selections (SW2)
The SW2 switch configures several processor strap pins, which set the processor’s operating modes after power up or hard reset:
• “Processor Boot Strap Settings”
• “SYSCON/SDRCON Mode Settings”
• “Interrupt Enable Settings”
• “Link Port Width Settings”
The switch settings should not be changed while power is applied to the
board. Many of the strap pin settings may be re-configured in software
after the processor is powered up. Refer to the ADSP-TS201S Embedded
Processor Datasheet for more information.
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Processor Boot Strap Settings
EZ-KIT Lite Hardware Reference
Position 1 of the
SW2 switch determines how the processor boots.
Table 2-3 shows the available boot mode settings. Refer to the
ADSP-TS201S Embedded Processor Datasheet for more information.
Table 2-3. Processor Boot Strap Settings (SW2 Position 1)
Position 1 Boot Mode
1
OFF
ON External Boot or Link Port Boot
1 Default settings
EPROM Boot
SYSCON/SDRCON Mode Settings
Position 2 of the
SW2 switch determines how the processor handles writes
to the SYSCON and SDRCON registers. Table 2-4 shows the setting for the
type of write. Refer to the ADSP-TS201S Embedded Processor Datasheet for
more information.
Table 2-4. SYSCON/SRDCON Mode Settings (SW2 Position 2)
Position 2 SYSCON/SDRCON Mode
OFF
1
SYSCON/SDRCON one-time writable
ON SYSCON/SDRCON always writable
1 Default settings
In emulation space, the SYSCON and SDRCON registers can be written
L
to as many times as needed. The USB debug monitor operates in
emulation space and allows “always writable” mode for these
registers.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-7
Page 44
Switch Settings
Interrupt Enable Settings
Positions 3 and 5 of the
SW2 switch determine how each of the processor
handles interrupts. Table 2-5 and Table 2-6 show the settings for the
interrupt modes. Refer to the ADSP-TS201S Embedded Processor Datasheet
for more information.
Table 2-5. Interrupt Enable Settings (SW2 Position 3)
Position 3 Interrupt Enable Mode for Processor A (U11)
1
OFF
ON Enable interrupts, edge-sensitive mode
1 Default settings
Disable interrupts, level-sensitive mode
Table 2-6. Interrupt Enable Settings (SW2 Position 5)
Position 5 Interrupt Enable Mode for Processor B (U12)
1
OFF
ON Enable interrupts, edge-sensitive mode
1 Default settings
Disable interrupts, level-sensitive mode
Link Port Width Settings
Positions 4 and 6 of the
SW2 switch determine the link port data width.
Table 2-7 and Table 2-8 show the settings for the two types of link ports
data widths. Refer to the ADSP-TS201S Embedded Processor Datasheet for
more information.
Table 2-7. Link Port Width Settings (SW2 Position 4)
Position 4 Link Port Data Width for Processor A (U11)
1
OFF
ON 4-Bit link port data width
1 Default settings
1-Bit link port data width
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EZ-KIT Lite Hardware Reference
Table 2-8. Link Port Width Settings (SW2 Position 6)
Position 6 Link Port Data Width for Processor B (U12)
1
OFF
ON 4-Bit link port data width
1 Default settings
1-Bit link port data width
FLAGs and IRQs Switch Settings (SW10)
The SW10 switch determines the source of the FLAG and IRQ signals connected to each of the prospective processors. The source can be modified
so that the nets can be driven by either a push button switch or an external
source via the Expansion Header. Refer to “Programmable FLAG Push
Buttons (SW6–9)” and “Interrupt Push Buttons (SW4–5)” on page 2-18
for information on FLAGs, IRQs, and the associated push buttons.
Table 2-9 shows the setting for the interrupt modes.
Table 2-9. FLAGs and IRQs Switch Settings (SW10)
DSP A DSP B DSP A DSP B
Position 1
(FLAG0)
OFF OFF OFF OFF OFF OFF External source
1
ON
1 Default settings
Position 2
(FLAG1)
ON ON ON ON ON On-board push button
Position 3
(FLAG0)
Position 4
(FLAG1)
Position 5
(IRQ0)
Position 6
(IRQ0)
Use With
switch
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-9
Page 46
Configuration Resistors
Configuration Resistors
This section describes the function of the two TigerSHARC processors’
configuration resistors. The location of the configuration resistors and
their respective default settings are shown in Figure 2-3.
Figure 2-3. Resistor Locations (Bottom View of Board)
Processor ID Settings
The two ADSP-TS201S processors on the EZ-KIT Lite are factory-configured to set the processor A to an ID value of zero and processor B to an ID
value of one. This means that in the cluster processor A is the master.
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EZ-KIT Lite Hardware Reference
Although it is not recommended, the ID value of each processor can be
varied by placing 500 Ohm resistors in the appropriate position.
Table 2-10 and Table 2-11 show the available ID settings.
L
to zero (
0) on the board. ID0 must be present in order to allow ini-
tialization of SDRAM external memory. Internal pull-up or
pull-downs on certain pins, such as memory interface and bus arbi-
The EZ-KIT Lite must have a processor with the processor ID set
tration, are enabled only when the
ID=(000). Refer to the
ADSP-TS201S TigerSHARC Processor Hardware Reference for more
information.
Table 2-10. Processor A ID Pins Configuration
R115 (Net: ID2_A) R117 (Net: ID1_A) R120 (Net: ID0_A) ID[2:0] Value
Not populated
Not populated Not populated Populated 1
Not populated Populated Not populated 2
Not populated Populated Populated 3
Populated Not populated Not populated 4
Populated Not populated Populated 5
Populated Populated Not populated 6
Populated Populated Populated 7
1
Not populated Not populated
0
1 Default settings
Table 2-11. Processor B ID Pins Configuration
R122 (Net: ID2_B) R123 (Net: ID1_B) R124 (Net: ID0_B) ID[2:0] Value
Not populated Not populated Not populated 0
Not populated
Not populated Populated Not populated 2
1
Not populated Populated 1
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-11
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Configuration Resistors
Table 2-11. Processor B ID Pins Configuration (Cont’d)
R122 (Net: ID2_B) R123 (Net: ID1_B) R124 (Net: ID0_B) ID[2:0] Value
Not populated Populated Populated 3
Populated Not populated Not populated 4
Populated Not populated Populated 5
Populated Populated Not populated 6
Populated Populated Populated 7
1 Default settings
Clock Mode Settings
The resistors on the clock generator (U1) and the resistors on the SCLKRAT
pins[
2:0] of each of the processors determine the frequency at which the
two processor operate. The frequency supplied to CLKIN of the processor
may also be changed by replacing the 20 MHz oscillator (
with the board with a different oscillator. Ensure that the selected clock
mode and frequency do not exceed the minimum and maximum specifications of the ADSP-TS201S processor as noted in the datasheet.
U18) shipped
The final frequency at which the processors operate is determined by the
following equation:
(Freq of U18)*(Mult Factor of U1)*(Mult Factor of SCLKRAT pins) =
Final Oper Freq
The default frequency factory setting is 20 MHz*5*5 = 500 MHz.
Table 2-12 through Table 2-14 show the resistor settings for the clock
generator and the
SCLKRAT pins. For more information on the clock
modes, see the ADSP-TS201S Embedded Processor Datasheet.
The Processor A and Processor B SCLK ratios must be of the same
L
value.
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EZ-KIT Lite Hardware Reference
Table 2-12. Clock Generator (U1) Settings
R215 R224 R3 R223 Multiplication Factor
Not populated Populated Not populated Populated 2
Not populated Populated Populated Populated 3
Not populated Populated Populated Not populated 4
Populated Populated Not populated Populated 4.25
1
Populated
Populated Populated Populated Not populated 6
Populated Not populated Not populated Populated 6.25
Populated Not populated Populated Populated 8
Populated Not populated Populated Not populated Reserved (Test mode)
1 Default settings
Populated Popul ated Populated 5
Table 2-13. SCLK Ratio Settings for Processor A
R128 (SCLKRAT2) R127 (SCLKRAT1) R133 (SCLKRAT0) Multiplication Factor
Not populated Not populated Not populated 4
Not populated
Not populated Populated Not populated 6
Not populated Populated Populated 7
Populated Not populated Not populated 8
Populated Not populated Populated 10
Populated Populated Not populated 12
Populated Populated Populated Reserved
1 Default settings
1
Not populated Populated 5
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-13
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Configuration Resistors
Table 2-14. SCLK Ratio Settings for Processor B
R126 (SCLKRAT2) R125 (SCLKRAT1) R45 (SCLKRAT0) Multiplication Factor
Not populated Not populated Not populated 4
Not populated
Not populated Populated Not populated 6
Not populated Populated Populated 7
Populated Not populated Not populated 8
Populated Not populated Populated 10
Populated Populated Not populated 12
Populated Populated Populated Reserved
1 Default settings
1
Not populated Populated 5
Control Impedance Selection
The CONTROLIMP1 and CONTROLIMP0 resistors set the impedance and driver
mode of the processors, as described in Table 2-15. The resistors are used
together with the drive strength pins to determine the actual impedance
and drive strength. Refer to the ADSP-TS201S Embedded Processor
Datasheet for more information.
Table 2-15. Control Impedance Selection
R143 (CONTROLIMP1) R131 (CONTROLIMP0) Driver Mode
Populated
Populated Populated Pulse mode
Not populated Not populated A/D mode
Not populated Populated Pulse mode, A/D mode
1 Default settings
1
Not populated Normal
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EZ-KIT Lite Hardware Reference
Drive Strength Selection
The DS[2:0] pins of each processor determine the digital drive strength, as
described in Table 2-16 and Table 2-17. Refer to the ADSP-TS201S
Embedded Processor Datasheet for more information.
Table 2-16. Drive Strength Setting for Processor A
R136 (DS2) R132 (DS1) R135 (DS0) Drive Strength Output
Impedance
Populated Not populated Populated 11.1% 26Ω
Populated Not populated Not populated 23.8% 32Ω
Populated Populated Populated 36.5% 40Ω
Populated Populated Not populated 49.2% 50Ω
Not populated Not populated Populated 61.9% 62Ω
1
Not populated
Not populated Populated Populated 87.3% 96Ω
Not populated Populated Not populated 100% 120Ω
Not populated Not populated 74.6% 70Ω
1 Default settings
Table 2-17. Drive Strength Setting for Processor B
R138 (DS2) R139 (DS1) R137 (DS0) Drive Strength Output
Impedance
Populated Not populated Populated 11.1% 26Ω
Populated Not populated Not populated 23.8% 32Ω
Populated Populated Populated 36.5% 40Ω
Populated Populated Not populated 49.2% 52Ω
Not populated Not populated Populated 61.9% 62Ω
1
Not populated
Not populated Populated Populated 87.3% 96Ω
Not populated Populated Not populated 100% 120Ω
1 Default settings
Not populated Not populated 74.6% 70Ω
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-15
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LEDs and Push Buttons
LEDs and Push Buttons
This section describes the function of the LEDs and push buttons.
Figure 2-4 shows the locations of the LEDs and push buttons.
Figure 2-4. LED and Push Button Locations
Power LED (LED1)
The green LED, LED1, indicates that power is being properly supplied to
the board.
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EZ-KIT Lite Hardware Reference
Reset LEDs (LED2 and LED8)
When LED2 is lit, the USB interface is being reset. This interface is only
reset when it is not configured. Once it has been configured, you must
remove power to reset the USB interface.
When
active.
LED8 is lit, it indicates that the master reset of all the major ICs is
FLAG LEDs (LED3–6)
The FLAG LEDs connect to the processor’s FLAG pins (FLAG2 and
FLAG3). These LEDs are active “high” and are lit by an output of “1” from
the processor. Refer to “Programmable FLAG Pins” on page 1-9 for information on how to utilize the FLAGs when programming the processor.
Table 2-18 shows the FLAG signals and the corresponding LEDs.
Table 2-18. FLAG LEDs
FLAG Pin LED Reference Designator FLAG Pin LED Reference Designator
FLAG2_A LED4 FLAG2_B LED5
FLAG3_A LED6 FLAG3_B LED3
USB Monitor LED (LED9)
The USB monitor LED indicates that USB communication has been initialized successfully, allowing you to connect to the processor using
VisualDSP++. If
the USB driver (see “Installing EZ-KIT Lite USB Driver” on page 1-7).
LED9 is not lit, try resetting the board and/or reinstalling
L
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-17
When VisualDSP++ is actively communicating with the EZ-KIT
Lite target board, the LED can flicker, indicating communications
handshake.
Page 54
LEDs and Push Buttons
Programmable FLAG Push Buttons (SW6–9)
Four push buttons are provided for general-purpose user input. The SW6,
SW7, SW8, and SW9 push buttons connect to the processor’s programmable
FLAG pins. The push buttons are active “high” and when pressed, send a
high (1) to the processor. Refer to “Programmable FLAG Pins” on
page 1-9 for more information on how to use the FLAGs. Table 2-19
shows the FLAG signals and the corresponding switches.
Table 2-19. FLAG Push Buttons
FLAG Pin Push Button Reference Designator
FLAG0_A SW9
FLAG1_A SW8
FLAG0_B SW6
FLAG1_B SW7
Interrupt Push Buttons (SW4–5)
Two push buttons, SW4 and SW5, are provided for user interrupts. The
push buttons connect to the processor’s interrupt pins. The push buttons
are active “low” and, when pressed, send a
to “Interrupt Pins” on page 1-10 for more information on how to use the
interrupts. Table 2-20 shows the interrupt signals and the corresponding
switches.
Table 2-20. Interrupt Push Buttons
Interrupt Pin Push Button Reference Designator
IRQ0_A SW4
IRQ0_B SW5
2-18 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
low (0) to the processor. Refer
Page 55
EZ-KIT Lite Hardware Reference
Reset Push Button (SW3)
The RESET push button, SW3, resets all the ICs on the board, except the
USB interface after it has been configured.
Connectors
This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown
in Figure 2-5.
Figure 2-5. Connector Locations
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-19
Page 56
Connectors
Audio (P1–2)
There are two 3.5 mm stereo audio jacks.
Part Description Manufacturer Part Number
3.5 mm stereo jack Shogyo SJ-0359AM-5
Mating Connector
3.5 mm stereo plug to 3.5 mm stereo cable
Radio Shack L12-2397A
Power (P3)
The power connector provides all the power necessary to operate the
EZ-KIT Lite board.
Part Description Manufacturer Part Number
2.5 mm Power Jack (
7.5V Power Supply GlobTek TR9CC2000LCP-Y
P3) SWITCHCRAFT RAPC712
Digi-Key SC1152-ND
Mating Power Supply (shipped with the EZ-KIT Lite)
2-20 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 57
EZ-KIT Lite Hardware Reference
JTAG (P4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
pod. For more information about designing JTAG into a custom board or
to learn more about the JTAG interface, please refer to EE-68 found at
Analog Devices website.
L
[
Pin 3 is missing to provide keying. Pin 3 in the mating connector
should have a plug. When an emulator is connected to the JTAG
header, the USB debug interface is disabled.
When using an emulator with the EZ-KIT Lite board, follow the
connection instructions provided with the emulator.
USB (P5)
The USB connector is a standard Type B USB receptacle.
Part Description Manufacturer Part Number
Type B USB receptacle Mill-Max 897-30-004-90-000
Digi-Key ED90003-ND
Mating Connector
USB cable (provided with the kit) Assman AK672/2-3
Digi-Key AE1302-ND
Expansion Interface (J1–3)
Three board-to-board connectors provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the
board. For more information about the expansion interface, see “Expan-
sion Interface” on page 2-3.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-21
Page 58
Specifications
Part Description Manufacturer Part Number
90 Position 0.05" Spacing Samtec SFC-145-T2-F-D-A
Mating Connector
90 Position 0.05” Spacing
(Through Hole)
90 Position 0.05” Spacing
(Surface Mount)
90 Position 0.05” Spacing
(Low Cost)
Samtec TFM-145-x1 Series
Samtec TFM-145-x2 Series
Samtec TFC-145 Series
Link Ports (J4–7)
There are four RJ-45 connectors on the EZ-KIT Lite. Two connectors are
used for Link Port 3 of Processor A and two are used for Link Port 3 of
Processor B.
Part Description Manufacturer Part Number
8-Pin RJ-45 Connector TYCO 1-1609214-1
Mating Cables
BLK CAT 5E Cable (1 Foot) E-FILLIATE 119-5136
Gray CAT 5E Cable (1 Meter) Digi-Key AE1233-ND
Specifications
This section provides the requirements for powering the board.
Power Supply
The power connector supplies DC power to the EZ-KIT Lite board.
Table 2-21 shows the power connector pinout.
2-22 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 59
EZ-KIT Lite Hardware Reference
Table 2-21. Power Connectors
Terminal Connection
Center pin +7.5 VDC@2amps
Outer Ring GND
ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-23
Page 60
Specifications
2-24 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 61
A BILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website,
http://www.analog.com/Processors/Processors/DevelopmentTools/tec
hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals
.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-1
Page 62
ADP3331ART
DEVICES
1 1 3.3V-OCTAL-BUFFER U28 TI SN74LVT244BDW
Ref. # Description Reference Designator Manufacturer Part Number
2 2 HEX-INVER-SCHMITT-TRIGGER U14, U30 TI 74LVC14AD
3 1 3.3V-OCTAL-BUFFER U13 IDT IDT74FCT3244APY
4 1 ADJ 200MA REGULATOR VR4 ANALOG
5 3 SINGLE-2-INPUT-NAND U15, U31, U38 TI SN74AHC1G00DBVR
6 1 12.288MHz SMT OSCILLATOR U2 DIGIKEY SG-8002CA-PCC-ND
7 2 ADJUSTABLE-3A-SWITCH-REG VR1–2 LINEAR TECH LT1765ES8
8 1 P-CHANNEL-MOSFET U35 FAIRCHILD SEMI FDS6375
9 1 ADJ-7A-SWITCH-REG-CNTRLR VR5 LINEAR TECH LTC1773EMS
10 1 N-CHANNEL-MOSFET U36 VISHAY SI9804DY
11 2 4MX32-SDRAM-166MHZ U24–25 MICRON MT48LC4M32B2TG–7
12 1 3.3V CLK GENERATOR U1 IDT IDT5V928PGI
13 1 3.3V 1:5 CLK DRIVER U37 IDT IDT49FCT3805AQ
14 1 512K-X-8-BIT-FLASH-3.3V U10 ATMEL AT49BV040-90JC
A-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 63
Bill Of Materials
AVX 12065A222JAT050
C56–57
ADM708SAR
ADP3339AKC-3.3-RL
DEVICES
DEVICES
AD1854JRS
AD1871YRS
DEVICES
ADP3336ARM-REEL
DEVICES
ADSP-TS201SABP-ENG
DEVICES
U11–12 ANALOG
DEVICES
sor
15 2 1000pF 50V 5% C47–48 AVX 12065A102JAT2A
Ref. # Description Reference Designator Manufacturer Part Number
16 4 2200pF 50V 5% C22, C24,
17 1 0.1uF 50V 20% C5 AVX 12065E104MAT2A
18 1 VOLTAGE-SUPERVISOR U5 ANALOG
19 1 3.3V 1.5A REGULATOR VR3 ANALOG
20 4 DUAL AUDIO OP AMP U6–8, U26 NATIONAL LMV722M
21 1 STERO-DAC U3 ANALOG
22 1 STERO-DAC U9 ANALOG
23 1 ADJ 500MA REGULATOR VR6 ANALOG
24 2 TigerSHARC ADSP-TS201S Proces-
25 4 RUBBER FEET BLACK MH1–2, MH4–5 MOUSER 517-SJ-5018BK
26 1 PWR 2.5MM_JACK P3 SWITCH-CRAFT SC1152-ND12
ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-3
Page 64
YAGEO 0.0ECT-ND
R109–110, R113,
R118, R178–179,
R189, R202
27 7 SPST-MOMENTARY 6MM SW3–9 PANASONIC EVQ-PAD04M
28 3 0.05 45X2 SMT J1–3 SAMTEC SFC-145-T2-F-D-A
29 2 DIP6 SW2, SW10 DIGIKEY CKN1364-ND
30 4 RJ45 8PIN RIGHT ANGLE J4–7 TYCO 1-1609214-1
31 1 4 PIN SMT SWITCH SW1 DIGIKEY CKN1363-ND
Ref. # Description Reference Designator Manufacturer Part Number
32 12 0.00 1/8W 5% R76, R91, R104, R107,
33 4 AMBER-SMT LED3–6, PANASONIC LN1461C-TR
34 2 330pF 50V 5% NPO C25, C30 AVX 08055A331JAT
35 4 0.01uF 100V 10% CERM C1–2, C7–8 AVX 08051C103KAT2A
AVX 08055C104KAT
C142–143, C145–149,
C247–249
36 15 0.1uF 50V 10% CERM C4, C51, C63, C66,
37 4 0.001uF 50V 5% NPO C10–11, C13–14 AVX 08055A102JAT2A
38 2 10uF 16V 10% TANT CT22–23 SPRAGUE 293D106X9016C2T
A-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 65
Bill Of Materials
Ref. # Description Reference Designator Manufacturer Part Number
AVX CR21-103J-T
R39–42, R77,
R86–87, R89,
39 39 10K 100MW 5% R3, R26,
R92, R94, R100,
R102, R108, R112,
R116, R153, R158–
160,
R182–183, R187,
R194, R195, R203,
R213–215, R223–224,
R235–236, R238–242
40 4 4.7K 100MW 5% R5, R93, R186, R188 AVX CR21-4701F-T
41 1 10.7K 1/8W 1% R217 DALE CRCW1206-1072FRT1
42 1 10.5K 1/8W 1% R227 BECKMAN BCR1/81052FT
DALE CR32-2001F-T
R156–157
43 6 2.00K 1/8W 1% R37–38,R88, R121,
AVX 12061A101JAT2A
C20–21, C23, C27,
44 2 49.9K 1/8W 1% R60, R63 AVX CR32-4992F-T
45 12 100pF 100V 5% NPO C3, C6, C9, C12, C15,
C31, C52–53
46 3 10uF 16V 10% TANT CT1–3 AVX TAJB106K016R
47 1 3A SCHOT_RECT D2 MICRO-SEMI HSM350J
ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-5
Page 66
AVX CR21-101J-T
PHYCOMP 9C12063A5761FKHFT
R101, R103
48 6 100 100MW 5% R78, R85, R95, R99,
Ref. # Description Reference Designator Manufacturer Part Number
49 3 220pf 50V 10% NPO C28, C32, C62 AVX 12061A221JAT2A
50 1 2A SILICON RECTIFIER D1 GENERALSEMI S2A
FER1–3, FER6–7 DIGIKEY 240-1019-1-ND
BEAD
51 5 600 100MHZ 500MA FERRITE
52 4 237 1/8W 1% R46, R48, R50, R52 AVX CR32-2370F-T
53 2 750K 1/8W 1% R47, R49 DALE-VISHAY CRCW12067503FRT1
54 8 5.76K 1/8W 1% R44,R53–57, R150,
R152
55 2 11.0K 1/8W 1% R61–62 DALE CRCW12061102FRT1
56 4 120PF 50V 5% NPO C16–19 PHILLIPS 1206CG121J9B200
57 4 1UF 16V 10% X7R C54, C70–72 MURATA GRM40X7R105K016AL
58 1 47PF 100V 10% C64 KEMET C1206C470K1GACTU
60 1 340K 1/8W 1% R192 DALE CRCW0805-3403FT
61 1 698K 1/8W 1% R201 DALE CRCW0805-6983FT
62 2 680PF 50V 1% NPO C26, C29 AVX 08055A681FAT2A
A-6 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 67
SL22
Bill Of Materials
SEMI
63 2 2.74K 1/8W 1% R68, R73 DALE CRCW12062741FRT1
64 4 5.49K 1/8W 1% R64–65, R69–70 PANASONIC ERJ-8ENF5491V
65 2 3.32K 1/8W 1% R66, R71 DALE CRCW12063321FRT1
66 2 1.65K 1/8W 1% R67, R72 PANASONIC ERJ-8ENF1651V
67 2 10UF 16V 20% ELEC CT4–5 DIG01 PCE3062TR-ND
68 2 68UF 25V 20% ELEC CT6–7 PANASONIC EEV-FC1E680P
Ref. # Description Reference Designator Manufacturer Part Number
69 2 2A SL22 SCHOTTKY D4, D5 GENERAL
70 1 332K 1/10W 1% R234 PHILIPS 9C08052A3323FKRT/R
VISHAY CRCW0805 0.0 RT1
R155, R161, R181,
71 18 0.00 100MW 5% R1–2, R7–10, R130,
R184–185, R208–212,
R226
72 1 190 100MHZ 5A FERRITE BEAD FER5 MURATA DLW5BSN191SQ2
73 1 35.7K 1/10W 1% R220 YAGEO 9C08052A3572FKHFT
74 2 10UH X 10% L1–2 PANASONIC ELJ-FC100KF
ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-7
Page 68
VISHAY/DALE CRCW0805220JRT1
R32,
R34–35,R129,
R205–207
YAGEO 1206CG229C9B200
C42–43, C45
AVX 0402ZD104KAT2A
C155–162,
C108,C110–115,C118,
C120–122, C141,
C144,C165–166,
C182,C184–185,
C187,C197–201,
C221–225,
C228–231,
C237–239, C241
75 11 22 1/10W 5% R4, R6, R11, R24,
Ref. # Description Reference Designator Manufacturer Part Number
76 2 0.47UF 16V 10% C73–74 AVX 0805YC474KAT2A
77 4 1UF 10V 10% C37, C41, C44, C46 AVX 0805ZC105KAT2A
78 6 1000PF 10V 20% C38–40,
79 3 4.7UF 6.3V 10% C61, C65, C76 AVX 08056D475KAT2A
80 53 0.1UF 10V 10% C69, C75,C79–84,
A-8 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 69
Bill Of Materials
CMDSH-3
AVX 0402YC103KAT2A
C103–104, 107, C109,
81 46 0.01UF 16V 10% C68,C85–90,C92–99,
Ref. # Description Reference Designator Manufacturer Part Number
C129–140,C167,
C181,C183,C202–205,
C216,C218–220,C227,
C232,C240, C242
82 2 4.7K 31MW 5% RN3–4 CTS 746X101472J
VISHAY CRCW08054990FRT1
R51,R111, R114,R124,
R133,R140–146,R154
83 16 499 1/10W 1% R23, R25,R45,
84 1 1UH 5.9MOHMS 30% L6 DIGIKEY 919AS-1RON=P3-ND
85 2 1.5UH 45MOHM 20% L4–5 TYCO DS6630-1R5M
86 1 0.01 1.5W 5% R219 IRC LR2512-01-R010-F
87 1 2.55K 1/10W 1% R105 VISHAY CRCW08052251FRT1
88 1 30K 1/10W 5% R218 VISHAY CRCW0805303JRT1
89 1 80.6K 1/10W 1% R221 VISHAY CRCW08058062FRT1
SEMI
90 2 SUPERMINI SCHOTTKY D6–7 CENTRAL
91 1 3A MBRS340T3 D3 ON SEMI MBRS340T3
ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-9
Page 70
Ref. # Description Reference Designator Manufacturer Part Number
92 1 680uF 6.3V 10% TANT-LOW-ESR CT15 AVX TPSE687K006R0045
93 2 0.18uF 25V 10% CERM C55, C58 AVX 08053C184KAT2A
94 2 100uF 10V 10% TANT-LOW-ESR CT16–17 AVX TPSC107K010R0075
95 1 150uF 10V 10% TANT-LOW-ESR CT14 KEMET T494D157K010AS
96 2 2.2uF 10V 10% CERM C59–60 AVX 0805ZD225KAT2A
AVX 04025C102JAT2A
C186,C188–196,
C206–215, C217,
C226,C233–236,
97 44 1000PF 50V 5% CERM C67, C168–180,
C243–246
98 1 64.9K 1/10W 1% R191 VISHAY CRCW08056492FRT1
99 2 57.6K 1/4W 1% R147–148 VISHAY CRCW12065762FRT1
100 1 210K 1/4W 1% R190 VISHAY CRCW08052103FRT1
VISHAY CRCW08051000FRT1
R29, R31, R33, R36,
101 22 100 1/10W 1% R13, R15–22, R27,
R43, R83, R96,R98,
R230–233
102 3 100K 1/8W 5% R58–59, R228 AVX CR1206-1003FRT1
A-10 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 71
Bill Of Materials
ADG774ABRQ
AVX CR32-271J-T
R151
103 7 270 1/8W 5% R79–82, R84, R90,
Ref. # Description Reference Designator Manufacturer Part Number
104 1 20MHZ 1/2 U18 ECLIPTEK EC1100HS-20.000M
105 2 10.0K 1/8W 1% R216, R222 DALE CRCW1206-1002FRT1
106 1 13.0K 1/8W 1% R225 PANASONIC ERJ-8ENF1302V
107 2 RED-SMT GULL-WING LED2,LED8 PANASONIC LN1261C
108 1 GREEN-SMT GULL-WING LED1 PANASONIC LN1361C
109 2 604 1/8W 1% R74–75 DALE CRCW12066040FRT1
110 6 1uF 25V 20% TANT CT8–13 PANASONIC ECS-T1EY105R
111 2 QUICKSWITCH-257 U22–23 ANALOG
DEVICES
112 1 IDC 7X2 P4 BERG 54102-T08-07
113 1 2.5A RESETABLE F1 RAYCHEM SMD250-2
AVX 08056D106KAT2A
114 2 3.5MM STEREO_JACK P1–2 A/D ELEC. ST-323-5
115 5 10uF 6.3V 10% TANT C91, C100, C154,
C163, C164
ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-11
Page 72
A-12 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 73
A B C D
1
1
2
2
ADSP-TS201S EZ-KIT Lite
3
ANALOG
4
DEVICES
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
3
4
Approvals
Date
Title
ADSP-TS201S EZ-KIT LITE - TITLE
Drawn
Checked
Engineering
A B C D
Size Board No.
C
Date Sheet of
A0178-2002
Rev
1.1C
1513-1-2004_10:59
Page 74
A B C D
DSP A
A[0:31]
A0
A1
R1
0.00
805
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
1
2
EMU
3
PLACE CLOSE TO DSP PINS
SCLK_DSP_A
R2
0.00
805
C33
10PF
805
DNP
TCK_DSP_A
R7
0.00
805
C34
10PF
805
DNP
DSP_RESET
TDI
TDO_A
TMS
TRST
4
U11
H24
ADDR0
H23
ADDR1
H22
ADDR2
H21
ADDR3
G24
ADDR4
G23
ADDR5
G22
ADDR6
G21
ADDR7
F24
ADDR8
F23
ADDR9
E24
ADDR10
E23
ADDR11
F22
ADDR12
F21
ADDR13
E22
ADDR14
E21
ADDR15
D24
ADDR16
D23
ADDR17
B24
ADDR18
D22
ADDR19
C21
ADDR20
A23
ADDR21
A21
ADDR22
B21
ADDR23
C20
ADDR24
D20
ADDR25
C19
ADDR26
D19
ADDR27
A20
ADDR28
B20
ADDR29
A19
ADDR30
B19
ADDR31
AA15
NC1
AB4
NC2
R21
NC3
Y1
EMU
Y2
TCK
W3
TDI
W4
TDO
AC4
TMS
AD4
TRST
P1
SCLK1
R2
SCLK2
T1
RST_IN
U2
RST_OUT
V3
POR_IN
ADSP-TS201S
BP576
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
DATA32
DATA33
DATA34
DATA35
DATA36
DATA37
DATA38
DATA39
DATA40
DATA41
DATA42
DATA43
DATA44
DATA45
DATA46
DATA47
DATA48
DATA49
DATA50
DATA51
DATA52
DATA53
DATA54
DATA55
DATA56
DATA57
DATA58
DATA59
DATA60
DATA61
DATA62
DATA63
D17
A17
B17
C16
D16
A16
B16
C15
D15
A15
B15
A14
B14
C14
D14
A13
B13
C12
D12
A12
B12
C11
D11
A11
B11
A10
B10
C10
D10
A9
B9
C9
D9
A8
B8
C8
D8
A7
B7
C7
D7
A6
B6
A5
B5
C6
D6
C5
D5
A4
B4
A2
C4
B1
D3
D1
D2
E3
E4
F3
F4
E1
E2
F1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D[0:63]
BR[0:7]
MSSD[0:3]
RD
WRL
WRH
ACK
BRST
MS0
MS1
MSH
BMS
BM_A
BOFF
BUSLOCK
HBR
HBG
RAS
CAS
LDQM
HDQM
SDA10
SDCKE
SDWE
BR0
BR1
BR2
BR3
BR4
BR5
BR6
BR7
MSSD0
MSSD1
MSSD2
MSSD3
U11
C18
RD
A18
WRL
B18
WRH
C17
ACK
D18
BRST
G3
MS0
F2
MS1
H2
MSH
G4
BMS
L2
BR0
L3
BR1
L4
BR2
M1
BR3
T3
BR4
M3
BR5
M4
BR6
R4
BR7
P4
BM
AC8
BOFF
AD8
BUSLOCK
AA8
HBR
AB8
HBG
J1
RAS
J2
CAS
K3
LDQM
K4
HDQM
K1
SDA10
K2
SDCKE
L1
SDWE
U1
MSSD0
G1
MSSD1
V1
MSSD2
H3
MSSD3
ADSP-TS201S
BP576
LABEL "DSP A" near this DSP
AC7
CPA
AD7
DPA
AA7
DMAR0
AB7
DMAR1
AC6
DMAR2
AD6
DMAR3
AC5
IOWR
AD5
IORD
AA6
IOEN
N1
ID0
AD2
ID1
U3
ID2
DS0
DS1
DS2
TMR0E
FLAG0
FLAG1
FLAG2
FLAG3
IRQ0
IRQ1
IRQ2
IRQ3
H4
M2
T2
W1
V4
T4
U4
V2
W2
Y3
AC1
AA2
AA1
Y4
AA5
AB6
AB5
AA3
FLAG0_A
FLAG1_A
FLAG2_A
FLAG3_A
IRQ0_A
IRQ1_A
IRQ2_A
IRQ3_A
SCLKRAT0
SCLKRAT1
SCLKRAT2
CONTROLIMP0
CONTROLIMP1
ENEDREG
CPA
DPA
DMAR0
DMAR1_A
DMAR2_A
DMAR3_A
IOWR
IORD
IOEN
ID0_A
ID1_A
ID2_A
SCLKRAT0_A
SCLKRAT1_A
SCLKRAT2_A
CONTROLIMP0
CONTROLIMP1
DS0_A
DS1_A
DS2_A
ENEDREG_A
TMR0E_A
FLAG[3:0]_A
IRQ[3:0]_A
3.3V
R26
10K
805
1 5
Approvals
U18
OE OUT
20MHZ
OSC001
R215
805
R224 R223
10K
805
Date
R3
10K10K
805
10K
805
R11
22
805
Title
PLACE CLOSE TO IDT5v929 PINS
3.3V
U1
4
VDD
5
VDDQ1
12
VDDQ2
13
VDDQ3
20
VDDQ4
2
X1_I
3
X2_O
22
OE
24
S0
23
S1
1
REF
IDT5V928PGI
TSSOP24
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND1
GND2
GND3
GND4
GND5
6
7
10
11
14
15
18
19
8
9
16
17
21
PLACE CLOSE TO EACH OTHER
C108
0.1UF
402
ANALOG
DEVICES
KEEP THESE NETS THE SAME LENGTH
R4
22
805
TP1
SCLK_DSP_A
SCLK_DSP_B
SDRAM_CLK0
SDRAM_CLK1
CLKOUT_EXP
TP6
R6
22
805
R24
22
805
R32
22
805
R34
22
805
R35
22
805
PLACE TEST POINTS NEXT TO EACH OTHER
3.3V3.3V
C107
0.01UF 0.01UF
402
IDT5V928PGI 20MHz
C103
0.01UF
402
C104
402
C141
0.1UF
402
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
1
2
3
4
ADSP-TS201S EZ-KIT LITE - DSP A
Drawn
Checked
Engineering
Size Board No.
C
Date Sheet of
3-1-2004_10:59 2 15
A0178-2002
Rev
1.1C
A B C D
Page 75
A B C D
DSP B
LABEL "DSP B" near this DSP
U12
C18
RD
A18
WRL
B18
WRH
C17
ACK
D18
BRST
G3
MS0
F2
MS1
H2
MSH
G4
BMS
L2
BR0
L3
BR1
L4
BR2
M1
BR3
T3
BR4
M3
BR5
M4
BR6
R4
BR7
P4
BM
AC8
BOFF
AD8
BUSLOCK
AA8
HBR
AB8
HBG
J1
RAS
J2
CAS
K3
LDQM
K4
HDQM
K1
SDA10
K2
SDCKE
L1
SDWE
U1
MSSD0
G1
MSSD1
V1
MSSD2
H3
MSSD3
ADSP-TS201S
BP576
BR[0:7]
BUSLOCK
RD
WRL
WRH
ACK
BRST
MS0
MS1
MSH
BMS
BR0
BR1
BR2
BR3
BR4
BR5
BR6
BR7
BM_B
BOFF
HBR
HBG
RAS
CAS
LDQM
HDQM
SDA10
SDCKE
SDWE
MSSD0
MSSD1
MSSD2
MSSD3
CPA
DPA
DMAR0
DMAR1
DMAR2
DMAR3
IOWR
IORD
IOEN
ID0
ID1
ID2
SCLKRAT0
SCLKRAT1
SCLKRAT2
CONTROLIMP0
CONTROLIMP1
DS0
DS1
DS2
ENEDREG
TMR0E
FLAG0
FLAG1
FLAG2
FLAG3
IRQ0
IRQ1
IRQ2
IRQ3
AC7
AD7
AA7
AB7
AC6
AD6
AC5
AD5
AA6
N1
AD2
U3
H4
M2
T2
W1
V4
T4
U4
V2
W2
Y3
AC1
AA2
AA1
Y4
AA5
AB6
AB5
AA3
FLAG0_B
FLAG1_B
FLAG2_B
FLAG3_B
IRQ0_B
IRQ1_B
IRQ2_B
IRQ3_B
Approvals
CPA
DPA
DMAR0
DMAR1_B
DMAR2_B
DMAR3_B
IOWR
IORD
IOEN
ID0_B
ID1_B
ID2_B
SCLKRAT0_B
SCLKRAT1_B
SCLKRAT2_B
CONTROLIMP0
CONTROLIMP1
DS0_B
DS1_B
DS2_B
ENEDREG_B
TMR0E_B
FLAG[3:0]_B
IRQ[3:0]_B
Date
Title
BR3
BR2
BR1
SDCKE
DMAR2_A
DMAR3_A
BOFF
DMAR1_B
DMAR0
DMAR1_A
DMAR3_B
DMAR2_B
BR5
BR6
BR7
BR4
ANALOG
DEVICES
R5
4.7K
805
BR0
R93
4.7K
805
HBR
RN4
1
R1
2
R2
3
R3
4
R4
6
R5
7
R6
8
R7
9
R8
4.7K
RNET8
RN3
1
R1
2
R2
3
R3
4
R4
6
R5
7
R6
8
R7
9
R8
4.7K
RNET8
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
COM1
COM2
COM1
COM2
1
2.5V
2.5V
2.5V
5
10
2
5
10
3
4
H24
H23
H22
H21
G24
G23
G22
G21
F24
F23
E24
E23
F22
F21
E22
E21
D24
D23
B24
D22
C21
A23
A21
B21
C20
D20
C19
D19
A20
B20
A19
B19
AA15
AB4
R21
W3
W4
AC4
AD4
U12
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
ADDR24
ADDR25
ADDR26
ADDR27
ADDR28
ADDR29
ADDR30
ADDR31
NC1
NC2
NC3
Y1
EMU
Y2
TCK
TDI
TDO
TMS
TRST
P1
SCLK1
R2
SCLK2
T1
RST_IN
U2
RST_OUT
V3
POR_IN
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
DATA32
DATA33
DATA34
DATA35
DATA36
DATA37
DATA38
DATA39
DATA40
DATA41
DATA42
DATA43
DATA44
DATA45
DATA46
DATA47
DATA48
DATA49
DATA50
DATA51
DATA52
DATA53
DATA54
DATA55
DATA56
DATA57
DATA58
DATA59
DATA60
DATA61
DATA62
DATA63
D17
A17
B17
C16
D16
A16
B16
C15
D15
A15
B15
A14
B14
C14
D14
A13
B13
C12
D12
A12
B12
C11
D11
A11
B11
A10
B10
C10
D10
A9
B9
C9
D9
A8
B8
C8
D8
A7
B7
C7
D7
A6
B6
A5
B5
C6
D6
C5
D5
A4
B4
A2
C4
B1
D3
D1
D2
E3
E4
F3
F4
E1
E2
F1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D[0:63]
MSSD[0:3]
A[0:31]
A0
A1
R10
0.00
805
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
1
2
EMU
3
PLACE CLOSE TO DSP PINS
SCLK_DSP_B
R8
0.00
805
C36
10PF
805
DNP
TCK_DSP_B
R9
0.00
805
C35
10PF
805
DNP
DSP_RESET
TDI_B
TDO_B
TMS
TRST
4
ADSP-TS201S
BP576
ADSP-TS201S EZ-KIT LITE - DSP B
Drawn
Checked
Engineering
Size Board No.
C
Date Sheet of
3-1-2004_10:59 153
A0178-2002
Rev
1.1C
A B C D
Page 76
A B C D
ALL NETS ON THIS PAGE EXCEPT L?ACK?_? and L?BCMP?_? ARE DIFFERETIAL PAIRS
THESE SIGNAL SHOULD BE ROUTING ACCORDING THE GUIDELINES SET IN EE-179
Link Port 0
Link Port 1
Link Port 2
Link Port 3
DSP A DSP B
FPGA
EXP INT
DSP B
FPGA
EXP INT
DSP A
RJ45 RJ45
1
2
L0DATI0_P_A
L0CLKIN_P_A
2_5V_DSP_A
R240
10K
805
PLACE CLOSE TO DSP A PINS (CRITICAL)
R27
100
805
L0DATI0_N_A
R12
100
805
DNP
L0CLKIN_N_A
R13
100
805
L1DATI0_N_AL1DATI0_P_A
R14
100
805
DNP
L1CLKIN_N_AL1CLKIN_P_A
L0DATI0_P_A
L0DATI0_N_A
L0CLKIN_P_A
L0CLKIN_N_A
L0ACKO_A
L0BCMPI_A
L1DATI0_P_A
L1DATI0_N_A
L1CLKIN_P_A
L1CLKIN_N_A
L1ACKO_A
L1BCMPI_A
2_5V_DSP_A
U11
J24
L0DATI0_P
J23
L0DATI0_N
K22
L0DATI1_P
K21
L0DATI1_N
L24
L0DATI2_P
L23
L0DATI2_N
L22
L0DATI3_P
L21
L0DATI3_N
K24
L0CLKIN_P
K23
L0CLKIN_N
J21
L0ACKO
J22
L0BCMPI
T22
L1DATI0_P
T21
L1DATI0_N
U24
L1DATI1_P
U23
L1DATI1_N
V24
L1DATI2_P
V23
L1DATI2_N
V22
L1DATI3_P
V21
L1DATI3_N
U22
L1CLKIN_P
U21
L1CLKIN_N
T23
L1ACKO
T24
L1BCMPI
DSP A
L0DATO0_P
L0DATO0_N
L0DATO1_P
L0DATO1_N
L0DATO2_P
L0DATO2_N
L0DATO3_P
L0DATO3_N
L0CLKO_P
L0CLKO_N
L0BCMPO
L1DATO0_P
L1DATO0_N
L1DATO1_P
L1DATO1_N
L1DATO2_P
L1DATO2_N
L1DATO3_P
L1DATO3_N
L1CLKO_P
L1CLKO_N
L1BCMPO
L0ACKI
L1ACKI
P24
P23
P22
P21
N22
N21
M24
M23
N24
N23
R24
R23
AA24
AA23
Y22
Y21
Y24
Y23
W24
W23
W22
W21
AC24
AA22
L0DATO0_N_A
L0CLKOUT_P_A
L0CLKOUT_N_A
L0ACKI_A
L0BCMPO_A
L1DATO0_P_A
L1DATO0_N_A
L1CLKOUT_P_A
L1CLKOUT_N_A
L1ACKI_A
L1BCMPO_A
2_5V_DSP_B
R239
10K
805
PLACE CLOSE TO DSP B PINS (CRITICAL)
L0DATI0_P_B
L0CLKIN_P_B
L1DATI0_P_B
L1CLKIN_P_B
R29
100
805
R30
100
805
DNP
R22
100
805
R28
100
805
DNP
L0DATI0_N_B
L0CLKIN_N_B
L1DATI0_N_B
L1CLKIN_N_B
L0DATI0_P_BL0DATO0_P_A
L0DATI0_N_B
L0CLKIN_P_B
L0CLKIN_N_B
L0ACKO_B
L0BCMPI_B
L1DATI0_P_B
L1DATI0_N_B
L1CLKIN_P_B
L1CLKIN_N_B
L1ACKO_B
L1BCMPI_B
2_5V_DSP_B
DSP B
U12
J24
L0DATI0_P
J23
L0DATI0_N
K22
L0DATI1_P
K21
L0DATI1_N
L24
L0DATI2_P
L23
L0DATI2_N
L22
L0DATI3_P
L21
L0DATI3_N
K24
L0CLKIN_P
K23
L0CLKIN_N
J21
L0ACKO
J22
L0BCMPI
T22
L1DATI0_P
T21
L1DATI0_N
U24
L1DATI1_P
U23
L1DATI1_N
V24
L1DATI2_P
V23
L1DATI2_N
V22
L1DATI3_P
V21
L1DATI3_N
U22
L1CLKIN_P
U21
L1CLKIN_N
T23
L1ACKO
T24
L1BCMPI
L0DATO0_P
L0DATO0_N
L0DATO1_P
L0DATO1_N
L0DATO2_P
L0DATO2_N
L0DATO3_P
L0DATO3_N
L0CLKO_P
L0CLKO_N
L0ACKI
L0BCMPO
L1DATO0_P
L1DATO0_N
L1DATO1_P
L1DATO1_N
L1DATO2_P
L1DATO2_N
L1DATO3_P
L1DATO3_N
L1CLKO_P
L1CLKO_N
L1ACKI
L1BCMPO
P24
P23
P22
P21
N22
N21
M24
M23
N24
N23
R24
R23
AA24
AA23
Y22
Y21
Y24
Y23
W24
W23
W22
W21
AC24
AA22
1
L0DATO0_P_B
L0DATO0_N_B
L0CLKOUT_P_B
L0CLKOUT_N_B
L0ACKI_B
L0BCMPO_B
L1DATO0_P_B
L1DATO0_N_B
2
L1CLKOUT_P_B
L1CLKOUT_N_B
L1ACKI_B
L1BCMPO_B
R15
100
805
L2DATI0_P_A
L2DATI1_P_A
L2DATI2_P_A
L2DATI3_P_A
R16
100
805
R17
100
805
R18
100
805
L2DATI0_N_A
L2DATI1_N_A
L2DATI2_N_A
L2DATI3_N_A
R242
10K
805
3
R19
100
805
L2CLKIN_P_A L2CLKIN_N_A
R20
100
805
L3DATI0_P_A
L3CLKIN_P_A
R21
100
805
L3DATI0_N_A
L3CLKIN_N_A
L2DATI0_P_A
L2DATI0_N_A
L2DATI1_P_A
L2DATI1_N_A
L2DATI2_P_A
L2DATI2_N_A
L2DATI3_P_A
L2DATI3_N_A
L2CLKIN_P_A
L2CLKIN_N_A
L2ACKO_A
L2BCMPI_A
L3DATI0_P_A
L3DATI0_N_A
L3CLKIN_P_A
L3CLKIN_N_A
L3ACKO_A
L3BCMPI_A
AD21
AC21
AB20
AA20
AD20
AC20
AD19
AC19
AB19
AA19
AB21
AD23
AD14
AC14
AB14
AA14
AB13
AA13
AD12
AC12
AD13
AC13
AC15
AD15
L2DATI0_P
L2DATI0_N
L2DATI1_P
L2DATI1_N
L2DATI2_P
L2DATI2_N
L2DATI3_P
L2DATI3_N
L2CLKIN_P
L2CLKIN_N
L2ACKO
L2BCMPI
L3DATI0_P
L3DATI0_N
L3DATI1_P
L3DATI1_N
L3DATI2_P
L3DATI2_N
L3DATI3_P
L3DATI3_N
L3CLKIN_P
L3CLKIN_N
L3ACKO
L3BCMPI
L2DATO0_P
L2DATO0_N
L2DATO1_P
L2DATO1_N
L2DATO2_P
L2DATO2_N
L2DATO3_P
L2DATO3_N
L2CLKO_P
L2CLKO_N
L2ACKI
L2BCMPO
L3DATO0_P
L3DATO0_N
L3DATO1_P
L3DATO1_N
L3DATO2_P
L3DATO2_N
L3DATO3_P
L3DATO3_N
L3CLKO_P
L3CLKO_N
L3ACKI
L3BCMPO
AB16
AA16
AD17
AC17
AD18
AC18
AB18
AA18
AB17
AA17
AD16
AC16
AD9
AC9
AB10
AA10
AD11
AC11
AB11
AA11
AD10
AC10
AB9
AA9
L2DATO0_P_A
L2DATO0_N_A
L2DATO1_P_A
L2DATO1_N_A
L2DATO2_P_A
L2DATO2_N_A
L2DATO3_P_A
L2DATO3_N_A
L2CLKOUT_P_A
L2CLKOUT_N_A
L2ACKI_A
L2BCMPO_A
L3DATO0_P_A
L3DATO0_N_A
L3CLKOUT_P_A
L3CLKOUT_N_A
L3ACKI_A
L3BCMPO_A
L2DATO0_P_A L2DATO0_N_A
L2DATO2_P_A L2DATO2_N_A
L2CLKOUT_P_A L2CLKOUT_N_A
R36
100
805
R43
100
805
R83
100
805
R96
100
805
R98
100
805
R31
100
805
R33
100
805
L2ACKI
L3ACKI
AB16
AA16
AD17
AC17
AD18
AC18
AB18
AA18
AB17
AA17
AD16
AC16
AD9
AC9
AB10
AA10
AD11
AC11
AB11
AA11
AD10
AC10
AB9
AA9
L2DATI0_P_A
L2DATI0_N_A
L2DATI1_P_A
L2DATI1_N_A
L2DATI2_P_A
L2DATI2_N_A
L2DATI3_P_A
L2DATI3_N_A
L2CLKIN_P_A
L2CLKIN_N_A
L2ACKO_A
L2BCMPI_A
L3DATO0_P_B
L3DATO0_N_BL3DATI0_N_B
L3CLKOUT_P_B
L3CLKOUT_N_B
L3ACKI_B
L3BCMPO_B
3
AD21
L2DATO0_P_A
L2DATO0_N_A
R241
10K
L2DATO1_P_A
805
L2DATO1_N_A
L2DATO1_N_AL2DATO1_P_A
L2DATO3_N_AL2DATO3_P_A
L3DATI0_N_BL3DATI0_P_B
L3CLKIN_N_BL3CLKIN_P_B
L2DATO2_P_A
L2DATO2_N_A
L2DATO3_P_A
L2DATO3_N_A
L2CLKOUT_P_A
L2CLKOUT_N_A
L2ACKI_A
L2BCMPO_A
L3DATI0_P_B
L3CLKIN_P_B
L3CLKIN_N_B
L3ACKO_B
L3BCMPI_B
AC21
AB20
AA20
AD20
AC20
AD19
AC19
AB19
AA19
AB21
AD23
AD14
AC14
AB14
AA14
AB13
AA13
AD12
AC12
AD13
AC13
AC15
AD15
L2DATI0_P
L2DATI0_N
L2DATI1_P
L2DATI1_N
L2DATI2_P
L2DATI2_N
L2DATI3_P
L2DATI3_N
L2CLKIN_P
L2CLKIN_N
L2ACKO
L2BCMPI
L3DATI0_P
L3DATI0_N
L3DATI1_P
L3DATI1_N
L3DATI2_P
L3DATI2_N
L3DATI3_P
L3DATI3_N
L3CLKIN_P
L3CLKIN_N
L3ACKO
L3BCMPI
L2DATO0_P
L2DATO0_N
L2DATO1_P
L2DATO1_N
L2DATO2_P
L2DATO2_N
L2DATO3_P
L2DATO3_N
L2CLKO_P
L2CLKO_N
L2BCMPO
L3DATO0_P
L3DATO0_N
L3DATO1_P
L3DATO1_N
L3DATO2_P
L3DATO2_N
L3DATO3_P
L3DATO3_N
L3CLKO_P
L3CLKO_N
L3BCMPO
2_5V_DSP_A
4
L0BCMPI_A
L1BCMPI_A
L2BCMPI_A
L3BCMPI_A
R108
10K
805
R116
10K
805
R119
10K
805
DNP
ADSP-TS201S
BP576
R153
10K
805
L0BCMPI_B
L1BCMPI_B
L2BCMPO_A
L3BCMPI_B
10K
805
2_5V_DSP_B
R236
10K
805
R237
10K
805
DNP
R238R235
10K
805
Approvals
Drawn
Checked
Engineering
Date
Title
ADSP-TS201S EZ-KIT LITE - DSP LINK PORTS
Size Board No.
C
Date Sheet of
ADSP-TS201S
BP576
ANALOG
20 Cotton Road
Nashua, NH 03063
DEVICES
PH: 1-800-ANALOGD
A0178-2002
3-1-2004_10:59 154
4
Rev
1.1C
A B C D
Page 77
A B C D
3.3V 2.5V
R121
2.00K
1206
DSP_SCLK_VREF DSP_VREF
1
R37
2.00K
1206
C41
1UF
805
R38
2.00K
1206
R88
2.00K
1206
C37
1UF
805
1V_DSP_A
L1
10UH
1008
C44
1UF
805
A1V_DSP_A
1V_DSP_B
L2
10UH
1008
C46
1UF
805
A1V_DSP_B
1
PLACE CLOSE TOGETHER
USE at least 3 vias per connection
DSP B
PLACE CLOSE TOGETHER
USE at least 3 vias per connection
DSP A
1.0V
1V_DSP_B
1_5V_DSP_B
1.5V
2
3
DSP_SCLK_VREF
4
A1V_DSP_A
R76
0.00
1206
R91
0.00
1206
P8
1 2
IDC2X1
2X1
DNP
1V_DSP_A
C40
1000PF
805
U11
F10
VDD1
F13
VDD2
F14
VDD3
F17
VDD4
F18
VDD5
F19
VDD6
F6
VDD7
F7
VDD8
F8
VDD9
F9
VDD10
G10
VDD11
G13
VDD12
G14
VDD13
G17
VDD14
G18
VDD15
G19
VDD16
G6
VDD17
G7
VDD18
G8
VDD19
G9
VDD20
H18
VDD21
H19
VDD22
H6
VDD23
H7
VDD24
J18
VDD25
J19
VDD26
J6
VDD27
J7
VDD28
K6
VDD29
K7
VDD30
L6
VDD31
L7
VDD32
M18
VDD33
M19
VDD34
M6
VDD35
M7
VDD36
N18
VDD37
N19
VDD38
N6
VDD39
N7
VDD40
P6
VDD41
P7
VDD42
R6
VDD43
R7
VDD44
T18
VDD45
T19
VDD46
T6
VDD47
T7
VDD48
U10
VDD49
U18
VDD50
U19
VDD51
U6
VDD52
U7
VDD53
V10
VDD54
V13
VDD55
V14
VDD56
V17
VDD57
V18
VDD58
V19
VDD59
V6
VDD60
V7
VDD61
V8
VDD62
V9
VDD63
W10
VDD64
W13
VDD65
W14
VDD66
W17
VDD67
W18
VDD68
W19
VDD69
W6
VDD70
W7
VDD71
W8
VDD72
W9
VDD73
N3
VDD_A1
N4
VDD_A2
P2
SCLK_VREF1
R3
SCLK_VREF2
ADSP-TS201S
BP576
1000PF
805
VDD_DRAM1
VDD_DRAM2
VDD_DRAM3
VDD_DRAM4
VDD_DRAM5
VDD_DRAM6
VDD_DRAM7
VDD_DRAM8
VDD_DRAM9
VDD_DRAM10
VDD_DRAM11
VDD_DRAM12
VDD_DRAM13
VDD_DRAM14
VDD_DRAM15
VDD_DRAM16
VDD_DRAM17
VDD_DRAM18
VDD_DRAM19
VDD_DRAM20
VDD_DRAM21
VDD_DRAM22
VDD_DRAM23
VDD_DRAM24
VDD_DRAM25
VDD_IO1
VDD_IO2
VDD_IO3
VDD_IO4
VDD_IO5
VDD_IO6
VDD_IO7
VDD_IO8
VDD_IO9
VDD_IO10
VDD_IO11
VDD_IO12
VDD_IO13
VDD_IO14
VDD_IO15
VDD_IO16
VDD_IO17
VDD_IO18
VDD_IO19
VDD_IO20
VDD_IO21
VDD_IO22
VDD_IO23
VDD_IO24
VDD_IO25
VDD_IO26
VDD_IO27
VDD_IO28
VDD_IO29
VDD_IO30
VDD_IO31
VDD_IO32
VDD_IO33
VDD_IO34
VDD_IO35
VDD_IO36
VDD_IO37
VDD_IO38
VDD_IO39
VDD_IO40
VDD_IO41
VDD_IO42
VDD_IO43
VDD_IO44
VDD_IO45
VDD_IO46
VDD_IO47
VDD_IO48
VDD_IO49
VDD_IO50
VREF
F11
F12
F15
F16
G11
G12
G15
G16
K18
K19
L18
L19
P18
P19
R18
R19
U11
V11
V12
V15
V16
W11
W12
W15
W16
AB23
AB24
AC22
AC3
AD22
AD3
C23
C24
E10
E11
E12
E13
E14
E15
E17
E19
E6
E8
F20
F5
G20
H20
H5
K20
K5
L20
L5
M20
M5
N20
N5
P20
P5
R20
R5
U20
U5
V20
W20
W5
Y10
Y11
Y12
Y13
Y14
Y15
Y17
Y19
Y6
Y8
J4
1_5V_DSP_A1.0V
R104
0.00
1206
P10
IDC2X1
2X1
DNP
2_5V_DSP_A
R107
0.00
1206
P11
1 2
IDC2X1
2X1
DNP
DSP_VREF
C38C42
1000PF
805
1.5V
21
2.5V
PLACE CLOSE TO DSP A PINS
U11
A1
VSS1
A22
VSS2
A24
VSS3
A3
VSS4
AA12
VSS5
AA21
VSS6
AA4
VSS7
AB1
VSS8
AB12
VSS9
AB15
VSS10
AB2
VSS11
AB22
VSS12
AB3
VSS13
AC2
VSS14
AC23
VSS15
AD1
VSS16
AD24
VSS17
B2
VSS18
B22
VSS19
B23
VSS20
B3
VSS21
C1
VSS22
C13
VSS23
C2
VSS24
C22
VSS25
C3
VSS26
D13
VSS27
D21
VSS28
D4
VSS29
E16
VSS30
E18
VSS31
E20
VSS32
E5
VSS33
E7
VSS34
E9
VSS35
G2
VSS36
G5
VSS37
H1
VSS38
H10
VSS39
H11
VSS40
H12
VSS41
H13
VSS42
H14
VSS43
H15
VSS44
H16
VSS45
H17
VSS46
H8
VSS47
H9
VSS48
J10
VSS49
J11
VSS50
J12
VSS51
J13
VSS52
J14
VSS53
J15
VSS54
J16
VSS55
J17
VSS56
J20
VSS57
J3
VSS58
J5
VSS59
J8
VSS60
J9
VSS61
K10
VSS62
K11
VSS63
K12
VSS64
K13
VSS65
K14
VSS66
K15
VSS67
K16
VSS68
K17
VSS69
K8
VSS70
K9
VSS71
L10
VSS72
L11
VSS73
L12
VSS74
L13
VSS75
L14
VSS76
L15
VSS77
ADSP-TS201S
BP576
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
L16
L17
L8
L9
M10
M11
M12
M13
M14
M15
M16
M17
M21
M22
M8
M9
N10
N11
N12
N13
N14
N15
N16
N17
N2
N8
N9
P10
P11
P12
P13
P14
P15
P16
P17
P3
P8
P9
R1
R10
R11
R12
R13
R14
R15
R16
R17
R22
R8
R9
T10
T11
T12
T13
T14
T15
T16
T17
T20
T5
T8
T9
U12
U13
U14
U15
U16
U17
U8
U9
V5
Y16
Y18
Y20
Y5
Y7
Y9
R110
0.00
1206
R109
0.00
1206
P9
21
IDC2X1
2X1
DNP
A1V_DSP_B
DSP_SCLK_VREF
PLACE CLOSE TO DSP B PINS
G10
G13
G14
G17
G18
G19
M18
M19
W10
W13
W14
W17
W18
W19
C45 C39
1000PF
805
1000PF 1000PF
805
U12
F10
VDD1
F13
VDD2
F14
VDD3
F17
VDD4
F18
VDD5
F19
VDD6
F6
VDD7
F7
VDD8
F8
VDD9
F9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
G6
VDD17
G7
VDD18
G8
VDD19
G9
VDD20
H18
VDD21
H19
VDD22
H6
VDD23
H7
VDD24
J18
VDD25
J19
VDD26
J6
VDD27
J7
VDD28
K6
VDD29
K7
VDD30
L6
VDD31
L7
VDD32
VDD33
VDD34
M6
VDD35
M7
VDD36
N18
VDD37
N19
VDD38
N6
VDD39
N7
VDD40
P6
VDD41
P7
VDD42
R6
VDD43
R7
VDD44
T18
VDD45
T19
VDD46
T6
VDD47
T7
VDD48
U10
VDD49
U18
VDD50
U19
VDD51
U6
VDD52
U7
VDD53
V10
VDD54
V13
VDD55
V14
VDD56
V17
VDD57
V18
VDD58
V19
VDD59
V6
VDD60
V7
VDD61
V8
VDD62
V9
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
W6
VDD70
W7
VDD71
W8
VDD72
W9
VDD73
N3
VDD_A1
N4
VDD_A2
P2
SCLK_VREF1
R3
SCLK_VREF2
ADSP-TS201S
BP576
VDD_DRAM1
VDD_DRAM2
VDD_DRAM3
VDD_DRAM4
VDD_DRAM5
VDD_DRAM6
VDD_DRAM7
VDD_DRAM8
VDD_DRAM9
VDD_DRAM10
VDD_DRAM11
VDD_DRAM12
VDD_DRAM13
VDD_DRAM14
VDD_DRAM15
VDD_DRAM16
VDD_DRAM17
VDD_DRAM18
VDD_DRAM19
VDD_DRAM20
VDD_DRAM21
VDD_DRAM22
VDD_DRAM23
VDD_DRAM24
VDD_DRAM25
VDD_IO1
VDD_IO2
VDD_IO3
VDD_IO4
VDD_IO5
VDD_IO6
VDD_IO7
VDD_IO8
VDD_IO9
VDD_IO10
VDD_IO11
VDD_IO12
VDD_IO13
VDD_IO14
VDD_IO15
VDD_IO16
VDD_IO17
VDD_IO18
VDD_IO19
VDD_IO20
VDD_IO21
VDD_IO22
VDD_IO23
VDD_IO24
VDD_IO25
VDD_IO26
VDD_IO27
VDD_IO28
VDD_IO29
VDD_IO30
VDD_IO31
VDD_IO32
VDD_IO33
VDD_IO34
VDD_IO35
VDD_IO36
VDD_IO37
VDD_IO38
VDD_IO39
VDD_IO40
VDD_IO41
VDD_IO42
VDD_IO43
VDD_IO44
VDD_IO45
VDD_IO46
VDD_IO47
VDD_IO48
VDD_IO49
VDD_IO50
VREF
C43
805
F11
F12
F15
F16
G11
G12
G15
G16
K18
K19
L18
L19
P18
P19
R18
R19
U11
V11
V12
V15
V16
W11
W12
W15
W16
AB23
AB24
AC22
AC3
AD22
AD3
C23
C24
E10
E11
E12
E13
E14
E15
E17
E19
E6
E8
F20
F5
G20
H20
H5
K20
K5
L20
L5
M20
M5
N20
N5
P20
P5
R20
R5
U20
U5
V20
W20
W5
Y10
Y11
Y12
Y13
Y14
Y15
Y17
Y19
Y6
Y8
J4
R113
0.00
1206
P12
1 2
IDC2X1
2X1
DNP
2_5V_DSP_B
R118
0.00
1206
P13
IDC2X1
2X1
DNP
DSP_VREF
2.5V
21
ANALOG
DEVICES
U12
A1
VSS1
A22
VSS2
A24
VSS3
A3
VSS4
AA12
VSS5
AA21
VSS6
AA4
VSS7
AB1
VSS8
AB12
VSS9
AB15
VSS10
AB2
VSS11
AB22
VSS12
AB3
VSS13
AC2
VSS14
AC23
VSS15
AD1
VSS16
AD24
VSS17
B2
VSS18
B22
VSS19
B23
VSS20
B3
VSS21
C1
VSS22
C13
VSS23
C2
VSS24
C22
VSS25
C3
VSS26
D13
VSS27
D21
VSS28
D4
VSS29
E16
VSS30
E18
VSS31
E20
VSS32
E5
VSS33
E7
VSS34
E9
VSS35
G2
VSS36
G5
VSS37
H1
VSS38
H10
VSS39
H11
VSS40
H12
VSS41
H13
VSS42
H14
VSS43
H15
VSS44
H16
VSS45
H17
VSS46
H8
VSS47
H9
VSS48
J10
VSS49
J11
VSS50
J12
VSS51
J13
VSS52
J14
VSS53
J15
VSS54
J16
VSS55
J17
VSS56
J20
VSS57
J3
VSS58
J5
VSS59
J8
VSS60
J9
VSS61
K10
VSS62
K11
VSS63
K12
VSS64
K13
VSS65
K14
VSS66
K15
VSS67
K16
VSS68
K17
VSS69
K8
VSS70
K9
VSS71
L10
VSS72
L11
VSS73
L12
VSS74
L13
VSS75
L14
VSS76
L15
VSS77
ADSP-TS201S
BP576
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
L16
L17
L8
L9
M10
M11
M12
M13
M14
M15
M16
M17
M21
M22
M8
M9
N10
N11
N12
N13
N14
N15
N16
N17
N2
N8
N9
P10
P11
P12
P13
P14
P15
P16
P17
P3
P8
P9
R1
R10
R11
R12
R13
R14
R15
R16
R17
R22
R8
R9
T10
T11
T12
T13
T14
T15
T16
T17
T20
T5
T8
T9
U12
U13
U14
U15
U16
U17
U8
U9
V5
Y16
Y18
Y20
Y5
Y7
Y9
2
3
4
Approvals
Date
Title
ADSP-TS201S EZ-KIT LITE - DSP POWER
Drawn
Checked
Engineering
A B C D
Size Board No.
C
A0178-2002
Date Sheet of
Rev
1.1C
1553-1-2004_10:59
Page 78
A B C D
2.5V 2.5V
ID[2-0] have internal 5Kohm pull-down resistors
ID(2-0) Proc ID
R115
499
805
1
ID2_A
ID1_A
ID0_A
R117
499
805
DNP DNP
R120
499
805
ID2_B
ID1_B
ID0_B
DSP A
Default ID = 0
R122
499
805
DNPDNP
DSP B
Default ID = 1
R123
499
805
DNP
R124
499
805
THESE RESISTORS DO NOT NEED TO BE VERY CLOSE TO THE DSP
000
001
010
011
100
101
110
IF POSSIBLE I WOULD LIKE THEM ALL ON THE BOTTOM OF THE BOARD
ORGANIZED IN GROUPS SIMILAR TO SHOW HERE
DEPENDING ON HOW MUCH ROOM YOU CAN LEAVE NEAR THEM
I WOULD LIKE TO LABEL SOME OF THEM
2.5V2.5V
0
1
2
3
4
5
6
7111
PLACE A LABEL "HIGH" NEAR SW2.12
PLACE A LABEL FOR THE SIGNAL NAME NEXT TO SW2 PINS 1-6
SW2
ON
BMS
BUSLOCK
BM_A
TMR0E_A
BM_B
TMR0E_B
1
1 2 3 4 5 6
2
3
4
5
6 7
SWT017
DIP6
12
11
10
9
8
R140
499
805
R141
499
805 805
2.5V
R142 R144
499
499
805 805
R145 R146
499
499
805
1
R128
499
DNP
SCLKRAT2_A
SCLKRAT1_A
SCLKRAT0_A
2
DSP A
R127
499
805805
Default PLL Ratio = 5X
CCLK = 500MHz
R133
499
805
SCLKRAT2_B
SCLKRAT1_B
SCLKRAT0_B
Default PLL Ratio = 5X
CCLK = 500MHz
R126
499
805
DNPDNP
DSP B
R125
499
805
DNP
R45
499
805
SCLKRAT[2-0] have internal 5Kohm pull-down resistors
SCLKRAT(2-0)
000
001
010
011
100
101
110
111
PLL Ratio
4
5
6
7
8
10
12
RESERVED
All strap pins have internal 5Kohm pull-down resistors during DSP reset
Switch OFF (Signal Pulled Low) Switch ON (Signal Pulled High)
BMS
BM
TMR0E
BUSLOCK
*
EPROM Boot
Disable interupts, level sensitive*
1-bit Link Port Data Width*
*
SYSCON/SDRCON one-time writable
External or link port boot
Enable interupts, edge sensitive
4-bit Link Port Data Width
SYSCON/SDRCON always writable
* indicates DEFAULT
2
KEEP STUB TO THE SIGNAL AS SMALL AS POSSIBLE
2.5V
CONTROLIMP0
CONTROLIMP1
R131
499
805
DNP
DEFAULT = NORMAL
CONTROLIMP0 has an internal 5Kohm pull-down resistor
CONTROLIMP1 has an internal 5Kohm pull-up resistor
CONTROLIMP(1:0)
00
01
10
11
Driver Mode
Normal
Pulse Mode
A/D Mode
Pulse Mode, A/D Mode
L1BCMPO_A
L2BCMPO_A
L3BCMPO_A L3BCMPO_B
R134
499
DNP
R23
805805
R51
499499
805
REALLY (L1BCMP0_B)
L1BCMPO_B
L2BCMPI_A
R106
499
805
DNP
R111
499
805
R114
499
805
R143
499
805
3
DS2_A
DS1_A
DS0_A
R132
499
805
DNP
R135
499
805 805
DNP
R136
499
DNP DNP
DS2_B
DS1_B
DS0_B
2.5V2.5V
R139
499
805
DNP
R137
499
805 805
R138
499
DNP
DS1 has internal 5Kohm pull-down resistor
DS2 and DS0 have internal 5Kohm pull-up resistors
DS(2-0) Drive Strength OUTPUT IMP
000
001
010
011
100
101
110
111
11.1%
23.8%
36.5%
49.2%
61.9%
74.6%
87.3%
100%
26
32
40
50
62
70
96
120
DEFAULT
ENEDREG_A
R25
499
805
ANALOG
ENEDREG_B
20 Cotton Road
R154
499
805
3
Nashua, NH 03063
4
DEVICES
PH: 1-800-ANALOGD
4
Approvals
Date
Title
ADSP-TS201S EZ-KIT LITE - CONFIG
Drawn
Checked
Engineering
A B C D
Size Board No.
C
Date Sheet of
3-4-2004_10:58 6 15
A0178-2002
Rev
1.1C
Page 79
A B C D
SDRAM 256Mb
(32MB - 4M x 64bits)
FLASH (512Kbx8)
LABEL "SDRAM(LOW)" LABEL "SDRAM(HIGH)"
1
2
D[0:63]
A[0:18]
U24
A1
25
A0
A2
26
A1
A3
27
A2
A4
60
A3
A5
61
A4
A6
62
A5
A7
63
A6
A8
64
A7
A9
65
66
24
21
22
23
20
67
68
17
18
19
16
71
28
59
14
30
57
69
70
73
A8
A9
A10
A11
BA0
BA1
CS
CKE
CLK
WE
CAS
RAS
DQM0
DQM1
DQM2
DQM3
NC1
NC2
NC3
NC4
NC5
NC6
A10
SDA10
A12
A13
A14
SDRAM_CS
SDCKE
SDRAM_CLK0 SDRAM_CLK1
SDWE
CAS
RAS
LDQM
3.3V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D0
2
D1
4
D2
5
D3
7
D4
8
D5
10
D6
11
D7
13
D8
74
D9
76
D10
77
D11
79
D12
80
D13
82
D14
83
D15
85
D16
31
D17
33
D18
34
D19
36
D20
37
D21
39
D22
40
D23
42
D24
45
D25
47
D26
48
D27
50
D28
51
D29
53
D30
54
D31
56
SDA10
SDRAM_CS
SDCKE
SDWE
CAS
RAS
HDQM
3.3V
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A12
A13
A14
25
26
27
60
61
62
63
64
65
66
24
21
22
23
20
67
68
17
18
19
16
71
28
59
14
30
57
69
70
73
U25
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
CS
CKE
CLK
WE
CAS
RAS
DQM0
DQM1
DQM2
DQM3
NC1
NC2
NC3
NC4
NC5
NC6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U10
12
D32
2
D33
4
D34
5
D35
7
D36
8
D37
10
D38
11
D39
13
D40
74
D41
76
D42
77
D43
79
D44
80
D45
82
D46
83
D47
85
D48
31
D49
33
D50
34
D51
36
D52
37
D53
39
D54
40
D55
42
D56
45
D57
47
D58
48
D59
50
D60
51
D61
53
D62
54
D63
56
MS0
BMS
U31
1
2
SN74AHC1G00
SOT23-5
4
U38
1
2
SN74AHC1G00
SOT23-5
4
RD
WRL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
29
A14
3
A15
2
A16
30
A17
1
A18
22
CE
24
OE
31
WE
AT49BV040
PLCC32RS
D0
D1
D2
D3
D4
D5
D6
D7
13
D0
14
D1
15
D2
17
D3
18
D4
19
D5
20
D6
21
D7
1
2
1
VDD1
15
3
VDD2
29
VDD3
43
VDD4
3
VDDQ1
9
VDDQ2
35
VDDQ3
41
VDDQ4
49
VDDQ5
55
VDDQ6
75
VDDQ7
81
VDDQ8
MT48LC4M32B2
TSOP86
3.3V
VSS1
VSS2
VSS3
VSS4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
44
58
72
86
6
12
32
38
46
52
78
84
1
VDD1
15
VDD2
29
VDD3
43
VDD4
3
VDDQ1
9
VDDQ2
35
VDDQ3
41
VDDQ4
49
VDDQ5
55
VDDQ6
75
VDDQ7
81
VDDQ8
MT48LC4M32B2
TSOP86
3.3V
VSS1
VSS2
VSS3
VSS4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
44
58
72
86
R155
0.00
6
12
32
38
46
52
78
84
MSSD[0:1]
PLACE CLOSE TO DSP (not so critical)
MSSD0
MSSD1
805
R149
0.00
805
DNP
SDRAM_CS
ANALOG
C129 C136
4
0.01UF
402
C130
402
C132
0.01UF
402
C131
0.01UF0.01UF
402
0.01UF
402
C135
0.01UF 0.01UF
402
C133
0.01UF
402
C134
402
C140
0.01UF
402
C139 C137
0.01UF
402
0.01UF
402
C138
0.01UF
402
DEVICES
3.3V 3.3V
C113
402
SN74AHC1G00 SN74AHC1G00
C112
0.1UF0.1UF
402
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
3.3V
C109
0.01UF
402
AT49BV040
3
4
Approvals
Date
Title
ADSP-TS201S EZ-KIT LITE - MEMORY
Drawn
SDRAM
SDRAM
Checked
Engineering
A B C D
Size Board No.
C
A0178-2002
Date Sheet of
Rev
1.1C
1573-4-2004_11:06
Page 80
A B C D
KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE
PLACE NEAR CONNECTOR
FER2
1
600
1206
CT5
10UF
CAP002
R44
5.76K
1206
INL-_AMPIN
R148
57.6K
1206
1
TRY TO KEEP ALL TRACES AS SHORT AS POSSIBLE
C16
120PF
1206
U6
LMV722M
SOIC8
R54
5.76K
1206
C17
120PF
1206
U6
LMV722M
SOIC8
R147
57.6K
1206
C18
120PF
1206
U7
LMV722M
SOIC8
R56
5.76K
1206
C19
120PF
1206
U7
LMV722M
SOIC8
R52
237
1
7
1
7
INL-_AMPOUT
INR-_AMPOUT INR-
1206
R50
237
1206
R48
237
1206
R46
237
1206
AGND
AGND
C14
0.001UF
805
C11
0.001UF
805
C13
0.001UF
805
C10
0.001UF
805
INL-
C12
100PF
1206
INL+
INR+
C9
100PF
1206
ADC LEFT
ADC RIGHT
MCLK
RESET
C3
100PF
1206
C8
0.01UF
805 805
C7
0.01UF
AGND
ADC
U9
13
CAPLN
12
CAPLP
11
C6
100PF
1206
C2
0.01UF
805
VINLP
10
VINLN
18
VINRP
19
VINRN
16
CAPRN
17
CAPRP
1
MCLK
24
RESET
AD1871YRS
SSOP28
C1
0.01UF
805
CCLK/{256~/512}
CLATCH/{M~/S}
KEEP THESE CLOSE TO AD1871
CASC
XCTRL
COUT/{DF0}
CIN/{DF1}
LRCLK
BCLK
DOUT
DIN
VREF
21
8
2
3
4
5
28
27
26
25
14
3.3V
10K
805
R39R42
10K
805
LRCLK
BCLK
DR
C4
0.1UF
805
AGND
SLAVE MODE
MCLK IS 256 x Fs
48 kHZ SAMPLE RATE
I S I/F MODE
VREF_AUDIO
CT2
10UF
B
2
3
LABEL "LINE IN"
P1
CON001
STEREO_JACK
R58
100K
1206
1
5
4
3
2
AUDIO_IN_LEFT
LOOPBACK_LEFT
LOOPBACK_RIGHT
AUDIO_IN_RIGHT
AGND
C20
100PF
1206
VREF_AUDIO
R55
5.76K
1206
R49
750K
1206
2
3
6
5
2
AGND
AGND
CT4
10UF
CAP002
R53
5.76K
1206
INR-_AMPIN
2
3
R59
100K
1206
FER1
600
1206
AGND
C15
100PF
1206
PLACE NEAR CONNECTOR
R57
5.76K
1206
3
2
3
U26
LMV722M
SOIC8
1
R47
750K
1206
6
5
AGND
AGND
C249
0.1UF
805
5V
C149
0.1UF
AD1871AD1871
Approvals
Drawn
Checked
A5V
U26
LMV722M
SOIC8
7
VREF_AUDIO
6
5
4
INL-_AMPIN
R157
2.00K
1206
R156
2.00K
1206
R150
5.76K
1206
R152
5.76K
1206
WHEN USING AN ELECTRET MICROPHONE
PLACE SW1.1 AND SW1.2 IN ON POSITION
PLACE SW1.3 AND SW1.4 IN OFF POSITION
SW1
1 2 3 4
SWT018
DIP4
ON
8
7
6
AUDIO_IN_RIGHT
AUDIO_IN_LEFT
INR-_AMPOUTINR-_AMPIN
INL-_AMPOUT
1
2
3
4 5
AGND
A5V
C147
0.1UF
805 805
AGND
NEAR U7 NEAR U26NEAR U6
A5V
C146 C145
0.1UF
AGND
A5V 3.3V
C148
AGND
AD1871
0.1UF
805
0.1UF
805 805
Engineering
THE GND AND AGND PLANES SHOULD GO FROM PIN 8 to PIN 21 of U9
R179
0.00
1206
AGND
PLACE RESISTOR BETWEEN AD1871 and AD1854
ANALOG
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
Date
DEVICES
Title
ADSP-TS201S EZ-KIT LITE - AUDIO IN
Size Board No.
C
Date Sheet of
A0178-2002
4
Rev
1.1C
1583-4-2004_10:58
A B C D
Page 81
A B C D
1
1
KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE
R62
11.0K
1206
R65
5.49K
1206
R66
3.32K
1206
C27
100PF
1206
THE GND AND AGND PLANES SHOULD GO FROM PIN 10 to PIN 20 of U3
DAC LEFT
C23
100PF
DAC
U3
10
96/48~
6
384/256~
7
X2MCLK
2
MCLK
26
BCLK
25
LRCLK
27
SDATA
4
CCLK
3
CLATCH
5
CDATA
24
RESET
9
DEEMP
23
MUTE
3.3V
R40
10K
805
MCLK
BCLK
LRCLK
DT
RESET
2
OUTL-
OUTL+
OUTR-
OUTR+
FILTR
FILTB
ZEROL
ZEROR
OUTL-
16
17
OUTL+
OUTR-
13
OUTR+
12
14
19
22
8
CT3
10UF
B B
C5
0.1UF
1206
CT1
10UF
1206
VREF_AUDIO
R64
5.49K
1206
C25
330PF
805
C26
680PF
805
R68
2.74K
1206
R70
5.49K
1206
R67
1.65K
1206
AGND
2
3
C28
220PF
1206
C31
100PF
1206
U8
LMV722M
SOIC8
CT7
68UF
CAP003
1
R74
604
1206
C24
2200PF
1206
R63
49.9K
1206
2
LABEL "LINE OUT"
AGND
P2
1
5
LOOPBACK_LEFT
LOOPBACK_RIGHT
4
3
2
CON001
STEREO_JACK
R71
3.32K
1206
R72
1.65K
1206
6
5
U8
LMV722M
SOIC8
7
CT6
68UF
CAP003
R75
604
1206
C22
2200PF
1206
R60
49.9K
1206
3
C21
100PF
1206
R61
11.0K
1206
5.49K
1206
C30
330PF
805
C29
680PF
805R69
21
IDPM0
20
IDPM1
AD1854JRS
SSOP28
AGND
DAC RIGHT
3
SLAVE MODE
MCLK IS 256 x Fs
48 kHZ SAMPLE RATE
I S I/F MODE
5V A5V A5V
C143C142
0.1UF
805
0.1UF
805
C153
0.1UF
805
R73
2.74K
1206
AGND
C32
220PF
1206
AGND
AGND
NEAR U8
ANALOG
20 Cotton Road
AD1854
AGND
AD1854
Nashua, NH 03063
4
Approvals
Date
Title
DEVICES
PH: 1-800-ANALOGD
4
ADSP-TS201S EZ-KIT LITE - AUDIO OUT
Drawn
Checked
Engineering
Size Board No.
C
A0178-2002
Date Sheet of
A B C D
Rev
1.1C
1593-1-2004_10:59
Page 82
A B C D
3.3V
3.3V
R89
10K
LABEL "FLAG0_A"
1
R95
100
805
SW9
SWT013
SPST-MOMENTARY
R94
10K
805
CT8
1UF
A
U14
74LVC14A
SOIC14
1011
LABEL "IRQ_A"
SW4
SWT013
SPST-MOMENTARY
R99
100
805
805
CT9
1UF
A
U14
74LVC14A
SOIC14
3.3V
U30
21
1 2
74LVC14A
SOIC14
IRQ0_A_S
3.3V
R92
10K
805
1
LABEL "RESET"
3.3V
3.3V
SW3
SWT013
SPST-MOMENTARY
R100
R77
3.3V
10K
805
13 12
CT13
1UF
A
U14
74LVC14A
SOIC14
LABEL "FLAG1_A"
R78
100
805
2
SW8
SWT013
SPST-MOMENTARY
LABEL "IRQ_B"
SW5
SWT013
SPST-MOMENTARY
R85
100
805
10K
805
CT10
1UF
A
U14
3 4
74LVC14A
SOIC14
3.3V
U30
74LVC14A
SOIC14
43
IRQ0_B_S
SOFT_RESET
R86
10K
805
USB_CONFIGURED
U5
81
4
RESETMR
PFI
RESET
ADM708SAR
SOIC8
PFO
7
5
LABEL "USB RESET"
1
2
USB RESET
LED2
RED-SMT
LED001
U15
4
SN74AHC1G00
SOT23-5
R130
0.00
805
3.3V
RESET
LED8
RED-SMT
LED001
USB_RESET
RESET
DSP_RESET
2
LABEL "RESET"
R112
10K
805
R87
10K
3.3V
805
CT12
1UF
A
R102
10K
805
CT11
1UF
A
U14
74LVC14A
SOIC14
U14
9 8
74LVC14A
SOIC14
65
SW10
ON
IRQ0_A_S
IRQ0_B_S
1
1 2 3 4 5 6
2
3
4
5
6 7
SWT017
DIP6
12
11
10
9
8
FLAG0_A
FLAG1_A
FLAG0_B
FLAG1_B
IRQ0_A
IRQ0_B
LABEL "FLAG0_B"
R103
100
805
SW6
SWT013
SPST-MOMENTARY
3
LABEL "FLAG1_B"
R101
100
805
SW7
SWT013
SPST-MOMENTARY
R160
10K
805
R159
R158
10K
10K
805
805
U30
5 6
74LVC14A
SOIC14
U30
89
74LVC14A
SOIC14
U30
11 10
74LVC14A
SOIC14
U30
1213
74LVC14A
SOIC14
3.3V 3.3V 3.3V
3.3V3.3V
USB_RESET
RESET
FLAG2_A
FLAG2_B
FLAG3_A
FLAG3_B
U13
2
1A1
4
1A2
6
1A3
8
1A4
11
2A1
13
2A2
15
2A3
17
2A4
1
OE1
19
OE2
IDT74FCT3244APY
SSOP20
18
1Y1
16
1Y2
14
1Y3
12
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
AMBER-SMT
LED001
270
1206
LABEL "FLAG3_B" LABEL "FLAG2_B"
LABEL "FLAG3_A/AUDIO"
R84
270
1206
FLAG3_A/AUDIO
LED6 LED5
AMBER-SMT
LED001
R80R79
1206
R90
270
1206
AMBER-SMT AMBER-SMT
LED001
270270
1206
LABEL "FLAG2_A"
LED4LED3
LED001
R82R81
270
1206
LABEL "POWER"
3.3V
R151
270
1206
POWERFLAG3_B FLAG2_B FLAG2_A
LED1
GREEN-SMT
LED001
3
Switch ON = Pushbutton will drive DSP net.
Switch OFF = DSP net can come from an external source
4
DEFAULT = All Switches ON
C114
0.1UF
402
0.1UF
402
C111C118
402
C120
0.1UF0.1UF
402
C144
0.1UF
402
Approvals
Date
ANALOG
DEVICES
Title
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
4
ADSP-TS201S EZ-KIT LITE - RESET/PB/LED
Drawn
74LVC14SN74AHC1G00
A B C D
ADM70874LVC14 IDT74FCT3244APY
Checked
Engineering
Size Board No.
C
Date Sheet of
3-1-2004_10:59 10 15
A0178-2002
Rev
1.1C
Page 83
A B C D
Expansion Interface (TYPE A)
PLACE LABEL "EXPANSION INTERFACE (TYPE A)" NEAR MIDDLE CONNECTOR
5V 5V
2.5V2.5V 3.3V
WARNING: WHEN CONNECTING TO ANOTHER BOARD
MAKE SURE TX CONNECTOR GOES TO A RX CONNECTOR
DO NOT USE CROSSOVER CABLE
1
2
3
D[0:63]
A[0:31]
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
D1
D3
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D25
D27
D29
D31
D33
D35
D37
D39
D41
D43
D45
D47
J1
45X2
CON019
1
3
5
78
9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
2
4
6
10
20
30
40
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90 89
A0
A2
A4
A6
A8
A10
A12
A14
A16
A18
A20
A22
A24
A26
A28
A30
D0
D2
D4
D6
D8
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
D36
D38
D40
D42
D44
D46
J2
2
4
CLKOUT_EXP
HDQM
D51
D53
D55
D57
D59
D61
D63
FLAG1_A FLAG0_A
FLAG3_A FLAG2_A
FLAG1_B FLAG0_B
FLAG3_B
IRQ1_A
IRQ3_A
IRQ1_B
IRQ3_B
6
8 7
10
12 11
14 13
16 15
18 17
20
22 21
24 23
26 25
28 27
30
32 31
34 33
36 35
38 37
40
42 41
44 43
46 45
48 47
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
45X2
CON019
1
3
5
9
D48D49
19
29
39
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
8990
D50
D52
D54
D56
D58
D60
D62
SDWE
SDA10CAS
RASSDCKE
LDQM
FLAG2_B
TMR0E_A
IRQ0_A BMS
IRQ2_A
IRQ0_B
IRQ2_B
DMAR3_B DMAR2_B
IOWR
MSSD1MSSD0
MSSD3
RESET
L1DATO0_N_A
L1CLKOUT_N_A
L1BCMPO_A
L1DATI0_N_A
L1CLKIN_N_A
L1BCMPI_A
L1DATO0_N_B
L1CLKOUT_N_B
L1BCMPO_B
L1DATI0_N_B
L1CLKIN_N_B
L1BCMPI_B L1ACKO_B
IOEN
BUSLOCK
HBG
MS0
MS1
ACK
BM_A
J3
2
4
6
10
20
30
40
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90 89
45X2
CON019
J4
1
3
5
78
9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
DMAR0DPA
DMAR1_A
MSH
IORD
MSSD2
BM_B
L1DATO0_P_A
L1CLKOUT_P_A
L1ACKI_A
L1DATI0_P_A
L1CLKIN_P_A
L1ACKO_A
L1DATO0_P_B
L1CLKOUT_P_B
L1ACKI_B
L1DATI0_P_B
L1CLKIN_P_B
BOFF
HBR
CPA
RD
WRL
WRH
BRST
L3CLKOUT_P_A
L3CLKOUT_N_A
L3DATO0_P_A
L3ACKI_A
L3DATO0_N_A
L3BCMPO_A
L3CLKIN_P_A
L3CLKIN_N_A
L3DATI0_P_A
L3ACKO_A
L3DATI0_N_A
L3BCMPI_A
L3CLKOUT_P_B
L3CLKOUT_N_B
L3DATO0_P_B
L3ACKI_B
L3DATO0_N_B
L3BCMPO_B
L3CLKIN_P_B
L3CLKIN_N_B
L3DATI0_P_B
L3ACKO_B
L3DATI0_N_B
L3BCMPI_B
1
2
3
4
5
6
7
8
CON_RJ45
J5
1
2
3
4
5
6
7
8
CON_RJ45
J6
1
2
3
4
5
6
7
8
CON_RJ45
J7
1
2
3
4
5
6
7
8
LABEL "DSP A TX"
DSP A TX
LABEL "DSP A RX"
DSP A RX
LABEL "DSP B TX"
DSP B TX
LABEL "DSP B RX"
DSP B RX
1
2
3
CON_RJ45
ANALOG
20 Cotton Road
Nashua, NH 03063
4
Approvals
Date
Title
DEVICES
PH: 1-800-ANALOGD
4
ADSP-TS201S EZ-KIT LITE - EXPANSION INT
Drawn
Checked
Engineering
Size Board No.
C
Date Sheet of
3-1-2004_10:59 11 15
A0178-2002
A B C D
Rev
1.1C
Page 84
A B C D
3.3V
R41
PLACE CLOSE TO OSC
10K
805
U2
1 3
OE OUT
12.288MHZ
1
12.288MHZ
OSC003
R129
22
805
AUDIOCLK
All USB interface circuitry is considered proprietary and has
been omitted from this schematic.
When designing your JTAG interface please refer to the
Engineer to Engineer Note EE-68 which can be found at
http://www.analog.com
R182
10K
805
3.3V
R213
805
R214
10K10K
805
R186
4.7K
805
1
PLACE CLOSE TO FPGA
R205
22
805
MCLK
R206
22
805
BCLK
R207
22
805
LRCLK LRCLK_S
U20
M15
RD
WRL
FLAG3_A
2
PLACE CLOSE TO FPGA PINS (CRITICAL)
DSP_RESET
3
R230
100
805
L0DATO0_P_A L0DATO0_N_A
R231
100
805
L0CLKOUT_P_A
L0DATO0_P_B
L0CLKOUT_P_B
R233
100
805
R232
100
805
L0CLKOUT_N_A
L0DATO0_N_B
L0CLKOUT_N_B
DMAR0
MS1
DT
DR
BCLK_S
LRCLK_S
MCLK_S
AUDIOCLK
L0DATO0_P_A
L0DATO0_N_A
L0CLKOUT_P_A
L0CLKOUT_N_A
L0ACKI_A
L0BCMPO_A
L0DATO0_P_B
L0DATO0_N_B
L0CLKOUT_P_B
L0CLKOUT_N_B
L0ACKI_B
L0BCMPO_B
R97
0.00
805
DNP
AUDIO_RD
M16
AUDIO_WRL
D6
AUDIO_EN
E14
ADUIO_DMAR
N11
AUDIO_SELECT
L15
AUDIO_DOUT
L14
AUDIO_DIN
T5
AUDIO_BCLK
C1
AUDIO_LRCLK
N14
AUDIO_MCLK
T9
AUDIO_CLK
H2
DSP_RESET
L4
LA_DATI0_P
L5
LA_DATI0_N
M1
LA_CLKIN_P
N1
LA_CLKIN_N
M2 N3
LA_BCOMPI LA_BCOMPO
J2
LB_DATI0_P
J3
LB_DATI0_N
K2
LB_CLKIN_P
K3
LB_CLKIN_N
J4 K1
LB_BCOMPI LB_BCOMPO
AUDIO_D0
AUDIO_D1
AUDIO_D2
AUDIO_D3
AUDIO_D4
AUDIO_D5
AUDIO_D6
AUDIO_D7
AUDIO_D8
AUDIO_D9
AUDIO_D10
AUDIO_D11
AUDIO_D12
AUDIO_D13
AUDIO_D14
AUDIO_D15
AUDIO_D16
AUDIO_D17
AUDIO_D18
AUDIO_D19
AUDIO_D20
AUDIO_D21
AUDIO_D22
AUDIO_D23
LA_DATO0_P
LA_DATO0_N
LA_CLKO_P
LA_CLKO_N
LA_ACKILA_ACKO
LB_DATO0_P
LB_DATO0_N
LB_CLKO_P
LB_CLKO_N
LB_ACKILB_ACKO
P6
F2
C6
D8
E16
F15
G12
G13
K13
K14
R4
F1
A3
A6
A7
B3
B5
B7
C4
C5
C15
C16
D2
D7
M3
M4
P1
P2
N2L3
K4
K5
L1
L2
J1H1
MCLK_S
BCLK_S
D[0:23]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
L0DATI0_P_A
L0DATI0_N_A
L0CLKIN_P_A
L0CLKIN_N_A
L0ACKO_A
L0BCMPI_A
L0DATI0_P_B
L0DATI0_N_B
L0CLKIN_P_B
L0CLKIN_N_B
L0ACKO_B
L0BCMPI_B
3.3V
R203
10K 10K
805
P4
1
3
5
7
9
11
13
IDC7X2
7X2
R187
805
2
4
6
8
10
12
14
DSP JTAG HEADER
USB_TMS
USB_TCK
USB_TRST
USB_TDI
USB_EMU
USB_TDO
3.3V 3.3V3.3V
C115
0.1UF
402
C110
0.1UF
402
U22
2
I0A
3
I1A
5
I0B
6
I1B
11
I0C
10
I1C
14
I0D
13
I1D
1
S
15
E
ADG774A
QSOP16
U23
2
I0A
3
I1A
5
I0B
6
I1B
11
I0C
10
I1C
14
I0D
13
I1D
1
S
15
E
ADG774A
QSOP16
3.3V
C121 C122
0.1UF
402
YA
YB
YC
YD
YA
YB
YC
YD
4
7
9
12
4
7
9
12
0.1UF
402
R188
4.7K
805
U28
2
1A1
4
1A2
6
1A3
8
1A4
11
TDO
EMU
U37
10
IN_A
3.3V
9
OE_A
R183
10K
805
TDO_A TDI_B
TDO
R180
0.00
805
DNP
11
IN_B
12
OE_B
IDT49FCT3805
QSOP20
2A1
13
2A2
15
2A3
17
2A4
1
OE1
19
OE2
SN74LVT244DW
SOIC20
R208
0.00
805
R209
0.00
805
OUT_A1
OUT_A2
OUT_A3
OUT_A4
OUT_A5
OUT_B1
OUT_B2
OUT_B3
OUT_B4
OUT_B5
MON
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
2
3
4
6
7
19
18
17
15
14
13
18
16
14
12
9
7
5
3
TDO_B
R184
0.00
805
R185
0.00
805
R181
0.00
805
R210
0.00
805
R161
0.00
805
R211
0.00
805
R212
0.00
805
TMS
TRST
TDI
2
TCK_DSP_A
TCK_DSP_B
3
IDT74FCT3244 QS325712.288MHz
QS3257
ANALOG
20 Cotton Road
Nashua, NH 03063
4
Title
Size Board No.
XC2S150E
FT256
Approvals
Drawn
Checked
Date
DEVICES
ADSP-TS201S EZ-KIT LITE - JTAG/FPGA
C
Engineering
Date Sheet of
PH: 1-800-ANALOGD
A0178-2002
Rev
1.1C
15123-4-2004_11:17
4
A B C D
Page 85
A B C D
D2
SCHOT_RECT
3A
DO214AB
UNREG_IN
SHGND
FER7
600
1206
FER6
600
1206
TP2 TP3 TP4
TP5
MH1
MH3MH2 MH4
1
SHGND
P3
1
7_5V_POWER
CON005
2.5MM_JACK
F1
2.5A
FUS001
C48
2
3
1000PF
1206
D1
S2A_RECT
2A
DO-214AA
FER5
CHOKE_COIL
4
1
3
2
1
C47
1000PF
1206
SHGND
1.8V
UNREG_IN
R178
C70
1UF
805
0.00
1206
VR6
7
IN1
8
IN2
GND
2
C71
1UF
805
4
1
OUT1
2
OUT2
3
OUT3
56
FBSD
ADP3336ARM
MSOP8
R190
210K
805
R191
64.9K
805
5V
C54
1UF
FER3
600
1206
A5V
AGND
C72
1UF
805805
3.3V
VR4
2
INPUT
6 1
SD
C73
0.47UF
805
OUTPUT
GND
4
ADP3331ART
SOT23-6
ERR
FB
R234
332K
805
3
5
R202
0.00
1206
C74
0.47UF
805
R192
340K
805
R201
698K
805
UNREG_IN
R228
100K
1206
CT22
10UF
C247
0.1UF
805
VR3
3
INPUT OUTPUT
GND
1
ADP3339AKC-33
SOT-223
2
CT23
10UF
CC
3.3V
C248
0.1UF
805
2
2.5V
UNREG_IN
R227
10.5K
1206
3
C66
0.1UF
805
4
R225
13.0K
1206
UNREG_IN
C59
2.2UF
805
R226
0.00
805
C60
2.2UF
805
VR2
2
VIN
5
SHDN
8
SYNC
4
GND
LT1765
SO-8
VR1
2
VIN
5
SHDN
8
SYNC
4
GND
LT1765
SO-8
BOOST
SW
FB
VC
BOOST
SW
FB
VC
C58
1
3
6
7
C57
2200PF
1206
1
3
6
7
C56
2200PF
1206
0.18UF
805
D4
SL22
2A
DO-214AA
D6
CMDSH-3
100MA
SOD-323
C55
0.18UF
805
D5
SL22
2A
DO-214AA
L5
1.5UH
IND003
R105
2.55K
805
R222
10.0K
1206
D7
CMDSH-3
100MA
SOD-323
L4
1.5UH
IND003
R216
10.0K
1206
R217
10.7K
1206
C61
4.7UF
805
R189
0.00
1206
C76
4.7UF
805
1.5V
2.5V
CT16
100UF
C
CT17
100UF
C
UNREG_IN
C51
0.1UF
805
CT14
150UF
D
C62
220PF
1206
C64
47PF
1206
R218
30K
805
C63
0.1UF
805
R219
0.01
2512
VR5
8
VIN
3
SYNC/FCB
1
ITH
2
RUN/SS
5
GND
LTC1773
MSOP10
Approvals
SW
SENSE
TG
BG
VFB
10
9
7
6
4
C53
100PF
1206
Date
R221
80.6K
805
Title
U35
51
2
3
4
FDS6375
SOIC8
U36
2
3
4
SI9804DY
SOIC8
R220
35.7K
805
C52
100PF
1206
6
7
8
51
6
7
8
ANALOG
DEVICES
L6
1UH
IND004
D3
MBRS340T3
3A
DIO002
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
CT15
680UF
E
1.0V
C65
4.7UF
805
3
4
ADSP-TS201S EZ-KIT LITE - POWER
Drawn
Checked
Engineering
Size Board No.
C
A0178-2002
Date Sheet of
Rev
1.1C
15133-1-2004_10:59
A B C D
Page 86
A B C D
1V_DSP_A
VDD (1.0V) Bypass Caps (per DSP)
1
(8) 1nF
(4) 0.01uF
(5) 0.1uF
(1) 100uF
C173
1000PF
402
1000PF
402
C175 C176
1000PF
402
1000PF 1000PF
402
C177 C178
402
1000PF
402
C179C174
1000PF
402
C180
1000PF
402
C219 C218
0.01UF
402
0.01UF
402
C216
0.01UF
402
C220
402
0.1UF0.01UF
402
C222C221
402
C223
0.1UF0.1UF
402
0.1UF
402
C225C224
0.1UF
402
1
1V_DSP_B
ALL BYPASS CAPS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE CORISPONDING IC
TRACES FROM COMPONENT TO CAPACITOR AND FROM THE CAPACITOR TO GND SHOULD BE AS SHORT AS POSSIBLE
THE PRIORITY FOR THE PLACEMENT:
C206
1000PF 0.01UF
402
C196 C195
402
1000PF
402
C208C207
402
1000PF1000PF
402
C210C209
1000PF
402
1000PF
402
C211
1000PF
402
0.01UF
402
C204C203
0.01UF
402
C205
402
C202
0.01UF 0.1UF
402
C201 C200
402
0.1UF 0.1UF
402
C199
402
C198 C197
0.1UF
402
0.1UF1000PF
402
1V_DSP_X
1_5V_DSP_X
2_5V_DSP_X
2
1_5V_DSP_A
1_5V_DSP_B
VDD_DRAM (1.5V) Bypass Caps (per DSP)
(6) 1nF
(2) 0.01uF
(4) 0.1uF
(1) 100uF
C67
1000PF
402
1000PF
402
C169C168
402
1000PF1000PF
402
C171C170
402
C172
1000PF1000PF
402
2_5V_DSP_A
C68
402
C167
0.01UF
402
C165
0.1UF 0.1UF
402
C166
0.1UF
402
C75 C69
402
0.1UF0.01UF
402
1000PF
402
C226 C217
1000PF
402
1000PF 1000PF
402
C215 C214
402
1000PF 1000PF
402
C213C212
402
2_5V_DSP_B
C232
0.01UF 0.1UF
402
C227
0.01UF
402
C229
402
C228
0.1UF
402
0.1UF0.1UF
402
C231C230
402
2
3
VDD_IO (2.5V) Bypass Caps (per DSP)
(8) 1nF
(2) 0.01uF
(4) 0.1uF
(1) 100uF
4
C194 C186
1000PF
402
C193
1000PF
402
C192
402
C191
1000PF
402
C190
1000PF
402
1000PF
402
C188C189
1000PF
402
1000PF1000PF
402
C181
402
0.01UF
402
C182
0.1UF0.01UF
402
C187 C185
0.1UF
402
0.1UF 0.1UF
402
C184C183
402
1000PF
402
C246
1000PF
402
C236
1000PF 1000PF
402
C245
1000PF
402
C233
1000PF
402
C244 C243
1000PF
402
1000PF
402
C235C234
402
ANALOG
DEVICES
C242
0.01UF 0.1UF
402
C240 C239
0.01UF
402
C241
402
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
0.1UF
402
C238C237
402
0.1UF0.1UF
402
3
4
Approvals
Date
Title
ADSP-TS201S EZ-KIT LITE - DSP BYPASS
Drawn
Checked
Engineering
A B C D
Size Board No.
C
Date Sheet of
3-1-2004_10:59 14 15
A0178-2002
Rev
1.1C
Page 87
A B C D
1
3.3V
C155
402
0.1UF0.1UF
402
C157C156
0.1UF
402
C162
0.1UF
402
C158
402
0.1UF0.1UF
402
C160C159
402
C161
0.1UF0.1UF
402
SPARTANIIe FPGA
C154 C99
10UF
805
0.01UF
402
C92
402
0.01UF0.01UF
402
C94C93
402
C95
0.01UF0.01UF
402
C91
10UF
805
C100
10UF
805
2
C96
402
2.5V
0.01UF0.01UF
402
C98C97
0.01UF
402
0.01UF
402
C86C85
402
1.8V
0.01UF0.01UF
402
SPARTANIIe FPGASPARTANIIe FPGA
C88C87
402
0.01UF0.01UF
402
C90C89
0.01UF
402
C164
10UF
805
C79
402
0.1UF0.1UF
402
C81C80
402
0.1UF0.1UF
402
C83C82
402
C84
0.1UF0.1UF
402
C163
10UF
805
3
3.3V
10K
805
R195R194
10K
805
3.3V
2.5V
1.8V
U20
R16
PROGRAM
A15
PROGRAM_CCLK
A14
PROGRAM_CS
A13
PROGRAM_WR
T2
FPGA_M0
R1
FPGA_M1
R3
FPGA_M2
E8
VCCO1_B0
F7
VCCO2_B0
F8
VCCO3_B0
E9
VCCO4_B1
F9
VCCO5_B1
F10
VCCO6_B1
G11
VCCO7_B2
H11
VCCO8_B2
H12
VCCO9_B2
J11
VCCO10_B3
J12
VCCO11_B3
K11
VCCO12_B3
L9
VCCO13_B4
L10
VCCO14_B4
M9
VCCO15_B4
L7
VCCO16_B5
L8
VCCO17_B5
M8
VCCO18_B5
J5
VCCO19_B6
J6
VCCO20_B6
K6
VCCO21_B6
G6
VCCO22_B7
H5
VCCO23_B7
H6
VCCO24_B7
C3
VCCINT1
C14
VCCINT2
D4
VCCINT3
D13
VCCINT4
E5
VCCINT5
E12
VCCINT6
M5
VCCINT7
M12
VCCINT8
N4
VCCINT9
N13
VCCINT10
P3
VCCINT11
P14
VCCINT12
PROGRAM_D0
PROGRAM_D1
PROGRAM_D2
PROGRAM_D3
PROGRAM_D4
PROGRAM_D5
PROGRAM_D6
PROGRAM_D7
PROGRAM_INIT
PROGRAM_DONE
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
B16
E15
F14
G15
J14
L13
L16
P16
P15
T15
A2
C13
B14
B1
A1
A16
B15
B2
F11
F6
G10
G7
G8
G9
H10
H7
H8
H9
J10
J7
J8
J9
K10
K7
K8
K9
L11
L6
R15
R2
T1
T16
1
2
3
XC2S150E
FT256
ANALOG
20 Cotton Road
Nashua, NH 03063
4
Approvals
Date
Title
DEVICES
PH: 1-800-ANALOGD
4
ADSP-TS201S EZ-KIT LITE - CONTROLLER
Drawn
Checked
Engineering
Size Board No.
C
Date Sheet of
3-1-2004_10:59 15 15
A0178-2002
A B C D
Rev
1.1C
Page 88
IINDEX
A
AD1854 digital-to-analog converter, -xi, 1-11
AD1871 analog-to-digital converter, -x, 1-11
ADSP-TS201S processor
clock frequency, 2-12
core speed, 2-3
core voltage, 2-3
driver modes, 2-14
drive strength, 2-15
external Flash memory, 1-6
impedance selection, 2-14
input clock, 2-3
internal memory, 1-6
memory map, 1-6
SDRAM interface, 1-6
amplification, 2-6
audio
amplification, 2-6
connectors (P1, P2), 2-20
data transfer, 1-11
interface, -xi, 1-11
see also AD1854 and AD1871
B
bill of materials, A-1
~BMS, boot memory select pin, 1-6, 2-3
board peripherals, -x
boot
code, 1-9
memory select pin (~MS0), 2-3
memory space, 1-6
strap settings, 2-7
broadcast, 1-7
bus control configuration, 1-8
C
clock
frequency, 2-12
generator (U1), 2-3, 2-12
modes, 2-12
ratios, 2-12
configuration resistors, 2-10
connectors
diagram of, 1-4, 2-19
J1-J3 (expansion interface), 2-4, 2-21
J4-J7 (link ports), 2-22
P1 (audio), 2-6, 2-20
P2 (audio), 2-20
P4 (JTAG), 2-4, 2-21
P5 (USB), 2-21
contents, EZ-KIT Lite package, 1-2
control impedance, 2-14
CONTROLIMP resistors, 2-14
converters (ADC/DAC), 1-11
core power regulator, 2-2
current limit, 2-4
customer support, -xiv
ADSP-TS201S EZ-KIT Lite Evaluation System Manual I-1
Page 89
INDEX
D
data
bus (D23-0), 1-11
memory, 1-6
transfer, 1-12
DIP switches, see SW
DMAR0 cycle, 1-11
DRAM, 2-3
drive strength, 2-15
DSP A
drive strength setting, 2-15
processor ID setting, 2-10
processor link ports, 1-11
DSP B
drive strength setting, 2-15
processor ID setting, 2-10
processor link ports, 1-11
E
electrostatic discharge, 1-3
emulation
port, 2-4
space, 2-7
SYSCON and SDRCON registers, 1-8
EPROM boot, 2-7
example programs, 1-12
expansion
header, 2-9
interface, 2-3, 2-21
external
interface regulator, 2-3
interrupts, 1-10
memory, -xi, 1-6, 2-4
ports, -xii, 2-3
regulator, 2-3
EZ-KIT Lite board
architecture, 2-2
features, -x
F
features, EZ-KIT Lite board, -x
field-programmable gate arrays (FPGAs), -ix,
1-11, 1-12
FLAG
LEDs (LED3-6), 2-17
pins, 1-9, 2-17, 2-18
push buttons (SW6-9), 2-18
source switch (SW10), 2-9
FLAG0 signal, 1-9, 1-10, 2-18
FLAG1 signal, 1-9, 1-10, 2-18
FLAG2 signal, 1-9, 1-10, 2-17
FLAG3 signal, 1-9, 1-10, 1-11, 2-17
FLAGREG register, 1-9
flash memory
boot memory select pin, 2-3
flash chip described, 1-8
specifications listed, -xi
G
general-purpose IO, -xi
H
Help, online, -xix, 1-13
host, external memory addresses, 1-7
I
interface connectors, -xi
internal
DRAM power regulator, 2-2
memory, 1-6, 1-7, 2-4
interrupt
enable settings, 2-8
modes, 2-8
mode switch (SW10), 2-9
pins, 1-10, 2-18
push buttons (SW4, SW5), 2-18
I-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 90
INDEX
IO
general purpose specifications, -xi
power regulator, 2-2
push buttons, 2-18
IRQ0_A (SW4) interrupt pin, 1-10, 2-18
IRQ0_B (SW5) interrupt pin, 1-10, 2-18
J
JTAG
emulation port, 2-4
emulator, -x
header, 2-21
jumper settings, 1-3
L
L0CLKIN pins, 1-12
LEDs
diagram of, 1-4
LED1 (power), 2-16
LED2 (USB reset), 2-17
LED3 (FLAG3_B), 1-9, 1-10, 2-17
LED4 (FLAG2_A), 1-9, 1-10, 2-17
LED5 (FLAG2_B), 1-9, 1-10, 2-17
LED6 (FLAG3_A), 1-9, 1-10, 2-17
LED8 (processor reset), 2-17
LED9 (USB monitor), 1-5, 2-17
license restrictions, 1-6
link ports, 1-11, 2-8
loader file, 1-9
LVDS signaling, 1-11
M
master processor, 2-10
memory
map, see ADSP-TS201S processor
memory blocks, see flash memory, flash chip
described
microphone, 2-6
~MS0, memory bank zero pin, 1-6, 2-3
N
networking cable, 1-12
noise, 1-12
notation conventions, -xxi
O
oscillator (U18), 2-3, 2-12
P
package contents, 1-2
peripheral interfaces, 2-21
power
connector (P3), 2-20
LED (LED1), 2-16
supply, 2-22
processor ID, 1-7, 2-10
programmable FLAG pins
see FLAG pins
program memory, 1-6
push buttons
SW3 (reset), 2-19
SW4-5 (interrupt), 1-10, 2-18
SW6 (FLAG0_B), 1-10, 2-18
SW7 (FLAG1_B), 1-10, 2-18
SW8 (FLAG1_A), 1-10, 2-18
SW9 (FLAG0_A), 1-10, 2-18
R
registering this product, 1-3
registers
SDRAM, 2-3
SDRCON, 1-7, 2-7
SOC, 1-7
SQSTAT, 1-9
SYSCON, 1-7, 2-7
ADSP-TS201S EZ-KIT Lite Evaluation System Manual I-3
Page 91
INDEX
reset
LEDs (LED2, LED8), 2-17
push button (SW3), 2-19
resistors
clock mode settings, 2-12
control impedance, 2-14
diagram of, 2-10
locations of, 2-10
RJ-45 connectors
interface connectors, -xi
part numbers and manufacturers, 2-22
TX and RX for DSP A, 1-11
S
SCLKRAT bit, 2-3, 2-12
SDRAM
default values, 1-7
memory, 1-6
registers, 2-3
specification listed, -xi
uses for, -xi
SDRCON registers, 1-7, 2-7
SOC registers, 1-7
specifications, power connector, 2-22
SQSTAT register, 1-9
switches
location and default settings, 2-5
SW1, 2-6
SW10, 2-9
SW2, -xi, 2-7, 2-8
SW6-9, 1-9, 1-10
SYSCON registers, 1-7, 2-7
system architecture, EZ-KIT Lite board, 2-2
U
USB
cable, 1-3
connector (P7), 2-21
debug monitor, 1-8, 2-7
interface, 2-17
monitor LED (LED9), 2-17
port, -x
V
VisualDSP++
documentation, -xix
Flash Programmer utility, 1-9
online Help, -xix
voltage regulators, -xi
I-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Page 92
INDEX
ADSP-TS201S EZ-KIT Lite Evaluation System Manual I-5
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