Datasheet ADSP-TS201 Datasheet (ANALOG DEVICES)

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ADSP-TS201 TigerSHARC® Processor

Hardware Reference

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 1.1, December 2004

Part Number

82-000815-01

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-ICE, SHARC, TigerSHARC, the TigerSHARC logo, and VisualDSP++, and are registered trademarks of Analog Devices, Inc.

Static Superscalar is a trademark of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ................................................................. xxi

Intended Audience ......................................................................... xxi

Manual Contents .......................................................................... xxii

What’s New in This Manual ......................................................... xxiv

Technical or Customer Support ..................................................... xxv

Supported Processors .................................................................... xxvi

Product Information ................................................................... xxvii

MyAnalog.com ...................................................................... xxvii

Processor Product Information ............................................... xxvii

Related Documents .............................................................. xxviii

Online Technical Documentation ........................................... xxix

Accessing Documentation From VisualDSP++ ..................... xxx

Accessing Documentation From Windows ........................... xxx

Accessing Documentation From the Web ............................ xxxi

Printed Manuals ..................................................................... xxxi

ADSP-TS201 TigerSHARC Processor Hardware Reference iii

CONTENTS

VisualDSP++ Documentation Set ...................................... xxxi

Hardware Tools Manuals .................................................. xxxii

Processor Manuals ............................................................ xxxii

Data Sheets ...................................................................... xxxii

Conventions .............................................................................. xxxiii

PROCESSOR ARCHITECTURE

Processor Core .............................................................................. 1-8

Compute Blocks ................................................................... 1-10

Arithmetic Logic Unit (ALU) ............................................ 1-12

Communications Logic Unit (CLU) .................................. 1-12

Multiply Accumulator (Multiplier) .................................... 1-12

Bit Wise Barrel Shifter (Shifter) ........................................ 1-13

Integer Arithmetic Logic Unit (IALU) ................................... 1-13

Program Sequencer ............................................................... 1-15

Processor Core Controls ........................................................ 1-17

Clock Domains ................................................................ 1-17

Operation Modes ............................................................. 1-18

User Mode ................................................................... 1-19

Supervisor Mode ........................................................... 1-20

Emulator Mode ............................................................ 1-20

Boot Modes ...................................................................... 1-22

Memory, Registers, and Buses ..................................................... 1-22

Internal Buses ....................................................................... 1-23

Internal Registers .................................................................. 1-23

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CONTENTS

SOC Interface ............................................................................. 1-24

Timers ........................................................................................ 1-24

Flags ........................................................................................... 1-25

Interrupts ................................................................................... 1-26

Direct Memory Access ................................................................. 1-26

External (Address and Data) Port ................................................. 1-28

External Bus and Host Interface ............................................. 1-28

External Memory .............................................................. 1-29

Multiprocessing ................................................................ 1-30

Host Interface ................................................................... 1-31

Link Ports ................................................................................... 1-32

JTAG Port and Debug Interface .................................................. 1-32

Programming Information ........................................................... 1-33

MEMORY AND REGISTERS

Host Address Space ....................................................................... 2-4

External Memory Bank Space ........................................................ 2-4

Multiprocessor Space ..................................................................... 2-6

Internal Address Space .................................................................. 2-7

Universal (Ureg) Register Space ..................................................... 2-8

Compute Block Register Groups ............................................ 2-14

Unmapped Compute Block Registers ................................. 2-19

IALU Register Groups ........................................................... 2-22

IALU Status (J31/JSTAT and K31/KSTAT) Registers ......... 2-26

Sequencer Register Groups .................................................... 2-27

ADSP-TS201 TigerSHARC Processor Hardware Reference v

CONTENTS

Flag Control (FLAGREG) Register ................................... 2-28

Sequencer Control (SQCTL) Register ............................... 2-29

Static Flags (SFREG) Register ........................................... 2-30

Sequencer Control Set Bits (SQCTLST) Register .............. 2-31

Sequencer Control Clear Bits (SQCTLCL) Register ........... 2-31

Sequencer Status (SQSTAT) Register ................................ 2-31

Cache Register Groups .......................................................... 2-34

Cache/Memory System Command/Status

(CACMDx, CCAIRx, and CASTATx) Registers ............. 2-36

Interrupt Register Groups ..................................................... 2-41

Interrupt Vector Table Register Groups ............................. 2-41

Interrupt Control (INTCTL) Register ............................... 2-45

Interrupt Latch (ILATL/ILATH) Registers ........................ 2-46

Interrupt Pointer Mask (PMASKL/PMASKH) Registers .... 2-47

Interrupt Mask (IMASKL/IMASKH) Registers .................. 2-47

Timer Interrupt (TIMERxH/L) Registers .......................... 2-50

Timer Initial Value (TMRINxH/L) Registers ..................... 2-50

DMA Control and Status Register Group .............................. 2-51

DMA Control (DCNT) Register ....................................... 2-51

DMA Status (DSTAT) Register ......................................... 2-53

External Port DMA TCB Register Group ............................... 2-56

Link Port Transmit DMA TCB Register Group ...................... 2-57

Link Port Receive DMA TCB Register Group ........................ 2-58

AutoDMA Register Group .................................................... 2-60

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CONTENTS

DMA Index (DI), X-Dimension (DX),

Y-Dimension (DY), and Pointer (DP) TCB Registers ........... 2-61

Link Port Register Groups ..................................................... 2-65

Link Receive Control (LRCTLx) Registers ......................... 2-68

Link Transmit Control (LTCTLx) Registers ....................... 2-69

Link Receive Status (LRSTATx) Registers .......................... 2-70

Link Transmit Status (LTSTATx) Registers ........................ 2-71

External Bus Interface Register Groups .................................. 2-72

System Configuration (SYSCON) Register ........................ 2-73

Bus Lock (BUSLOCK) System Control Register ................ 2-76

SDRAM Configuration (SDRCON) Register .................... 2-76

System Status (SYSTAT) Register ...................................... 2-77

Bus Master Maximum (BMAX) Register ............................ 2-80

Bus Master Maximum Current Count (BMAXC) Register .. 2-80

JTAG Test and Emulation Register Groups ............................ 2-81

Emulation Control (EMUCTL) Register ........................... 2-82

Emulation Status (EMUSTAT) Register ............................. 2-83

Silicon Version and ID Code (IDCODE) Register ............. 2-83

Debug Register Groups .......................................................... 2-84

Watchpoint Control (WPxCTL) Registers ......................... 2-86

Watchpoint Status (WPxSTAT) Registers ........................... 2-89

Watchpoint Address Pointer (WPxL/WPxH) Registers ....... 2-89

Performance Monitor Mask (PRFM) Register .................... 2-89

Performance Monitor Counter (PRFCNT) Register ........... 2-92

Cycle Counter (CCNTx) Registers .................................... 2-92

ADSP-TS201 TigerSHARC Processor Hardware Reference vii

CONTENTS

Trace Buffers and Pointer (TRCBx/TRCBPTR) Registers .. 2-93

SOC INTERFACE

SOC Interface Operations ............................................................ 3-5

SOC OFIFO Transactions ....................................................... 3-5

SOC IFIFO/OBUF Transactions ............................................. 3-7

SOC Interface Programming ......................................................... 3-8

TIMERS

Timer Operations ......................................................................... 4-2

Timer Programming ..................................................................... 4-4

Timer Expired (TMR0E) Pin and Signal Timing ........................... 4-8

FLAGS

Flag Operations ............................................................................ 5-1

Flag Programming ........................................................................ 5-3

Flag (FLAG3-0) Pin and Signal Timing ....................................... 5-10

INTERRUPTS

Interrupt Operations .................................................................... 6-5

Interrupt Service Routines ....................................................... 6-8

Handling Interrupts .......................................................... 6-13

Returning From an Interrupt ............................................ 6-14

Handling Exceptions ........................................................ 6-15

Interrupt Vector Table ........................................................... 6-17

Timer Expired Interrupts .................................................. 6-19

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CONTENTS

Link Port Service Request Interrupts .................................. 6-20

DMA Complete Interrupts ................................................ 6-20

External (IRQ3–0) Input Interrupts .................................. 6-20

Vector Interrupt ................................................................ 6-21

Bus Lock Interrupt Register ............................................... 6-21

Hardware Error Interrupt .................................................. 6-22

Software Exception Interrupts ........................................... 6-23

Emulation Exception Interrupt .......................................... 6-24

Interrupt Programming ............................................................... 6-25

Interrupt (IRQ3-0) Pin and Signal Timing .................................. 6-32

DIRECT MEMORY ACCESS

DMA Controller Features .............................................................. 7-8

Cluster Bus Transfers ............................................................... 7-8

AutoDMA Transfers .............................................................. 7-10

Link Port Transfers ................................................................ 7-10

Two-Dimensional DMA ........................................................ 7-11

Chained DMA ...................................................................... 7-11

DMA Architecture ...................................................................... 7-12

DMA Request (DMAR3-0) Pins ............................................ 7-13

Terminology .......................................................................... 7-14

Setting Up DMA Transfers .......................................................... 7-15

DMA Transfer Control Block Registers ........................................ 7-15

DMA Channel Control ......................................................... 7-16

Transfer Control Block (TCB) Registers ............................ 7-16

ADSP-TS201 TigerSHARC Processor Hardware Reference ix

CONTENTS

DIx Register ................................................................. 7-18

DXx Register ................................................................ 7-18

DYx Register ................................................................ 7-19

DPx Register ................................................................ 7-19

DMA Control and Status Registers ............................................. 7-23

DMA Status Register (DSTAT/DSTATC) .............................. 7-23

DMA Control Registers ........................................................ 7-26

DCNT Register ................................................................ 7-26

DCNTST Register ........................................................... 7-27

DCNTCL Register ........................................................... 7-27

DMA Control Register Restrictions ................................... 7-27

DMA Controller Operations ....................................................... 7-31

Link Port DMA Control ....................................................... 7-31

External Port DMA Control .................................................. 7-32

AutoDMA Register Control .................................................. 7-32

DMA Transfers ..................................................................... 7-33

Internal Memory Buses ..................................................... 7-33

DMA Channels ................................................................ 7-34

DMA Memory Addressing .................................................... 7-34

DMA Channel Prioritization ................................................. 7-36

Internal Memory Bus Priority ........................................... 7-36

DMA Channel Priority ..................................................... 7-36

Rotating Priority .............................................................. 7-38

DMA Chaining ..................................................................... 7-40

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CONTENTS

Enabling and Disabling Chaining ...................................... 7-42

Generating a DMA Complete Interrupt While Chaining .... 7-42

Transfer Control Blocks and Chain Loading ...................... 7-42

Setting Up and Starting the Chain ..................................... 7-43

Chain Insertion ................................................................. 7-43

Two-Dimensional DMA ........................................................ 7-44

Two-Dimensional DMA Channel Organization ................. 7-45

Two-Dimensional DMA Operation ................................... 7-46

Examples of Two Dimensional DMA Transfers .................. 7-48

DMA Interrupts .................................................................... 7-49

Starting and Stopping DMA Sequences .................................. 7-51

Starting a DMA Sequence ................................................. 7-51

Ending a DMA Sequence .................................................. 7-52

Suspending a DMA Sequence ............................................ 7-52

Resuming a DMA Sequence .............................................. 7-52

External Port DMA ..................................................................... 7-52

Internal and External Address Generation .............................. 7-53

External Port DMA Transfer Types ........................................ 7-54

External to Internal Memory ............................................. 7-54

Internal to External Memory ............................................. 7-57

External I/O Device to External Memory (Flyby) ............... 7-60

External Memory to External I/O Device (Flyby) ............... 7-62

DMA Semaphores ............................................................. 7-63

Handshake Mode .............................................................. 7-64

ADSP-TS201 TigerSHARC Processor Hardware Reference xi

CONTENTS

Flyby Mode ...................................................................... 7-65

Link Port DMA .......................................................................... 7-66

Link Ports DMA Transfer Types ............................................ 7-66

Link Port to Internal/External Memory ............................. 7-66

Internal/External Memory to Link .................................... 7-68

Receiving Link Port to Link Port ....................................... 7-69

DMA Throughput ...................................................................... 7-71

Internal Memory DMA ......................................................... 7-71

External Memory DMA ........................................................ 7-71

DMA Operation on Boot ............................................................ 7-72

DMA Examples .......................................................................... 7-73

EXTERNAL PORT AND SDRAM INTERFACE

External Bus Features .................................................................... 8-2

Bus Interface I/O Pins .................................................................. 8-3

Processor Microarchitecture .......................................................... 8-5

SYSCON Register Programming ................................................. 8-13

Bus Width ............................................................................ 8-13

Slow Device Protocol for Bus ................................................ 8-14

Pipelined Protocol for Bus ..................................................... 8-14

Initial Value for Bus Operation .............................................. 8-15

Pipelined Protocol Interface ........................................................ 8-15

Control Signals for Pipelined Transactions ............................. 8-16

Using Basic Pipelined Transactions ........................................ 8-16

Using Burst Pipelined Transactions ........................................ 8-18

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CONTENTS

Wait Cycles ........................................................................... 8-23

Slow Device Protocol Interface .................................................... 8-26

EPROM Interface ....................................................................... 8-32

Multiprocessing Interface ............................................................ 8-34

Bus Arbitration Protocol ........................................................ 8-38

Core Priority Access (CPA) Pin ......................................... 8-40

DMA Priority Access (DPA) Pin ........................................ 8-42

Bus Fairness (BMAX) Register ........................................... 8-44

Bus Lock (BUSLOCK) Register ......................................... 8-44

Software (Processor Core) Reset Operation ........................ 8-45

Host Processor Interface .............................................................. 8-46

Back Off (BOFF) Pin ............................................................ 8-48

SDRAM Interface ....................................................................... 8-50

SDRAM Interface I/O Pins .................................................... 8-55

SDRAM Physical Connection ................................................ 8-56

Bank Select Pins ................................................................ 8-59

Internal Address and SDRAM Physical Connection ........... 8-60

SDRAM Programming .......................................................... 8-67

Enabling SDRAM ............................................................. 8-68

Selecting the CAS Latency Value – CAS ............................ 8-69

Setting the SDRAM Buffering Option – Pipeline Depth .... 8-69

Selecting the SDRAM Page Size – Page Boundary .............. 8-70

Setting the Refresh Counter Value – Refresh Rate .............. 8-70

Selecting the Precharge to RAS Delay ................................ 8-72

ADSP-TS201 TigerSHARC Processor Hardware Reference xiii

CONTENTS

Selecting the RAS to Precharge Delay ................................ 8-72

Setting the SDRAM Power-Up Mode

– Initialization Sequence ................................................ 8-73

Enabling the Extended Mode (EMR) Register ................... 8-73

Flyby Transactions ................................................................ 8-74

SDRAM Interface Throughput .............................................. 8-77

Multiprocessing Operation .................................................... 8-78

Understanding DQM Operation ........................................... 8-79

Powering Up After Reset ....................................................... 8-79

SDRAM Controller Commands ............................................ 8-80

Mode Register Set (MRS) Command ................................ 8-81

Precharge (PRE) Command .............................................. 8-83

Terminating Read/Write Cycles ..................................... 8-83

Precharging .................................................................. 8-83

Bank Active (ACT) Command .......................................... 8-84

Read Command ............................................................... 8-85

Bus Width = 64 ............................................................ 8-87

Bus Width = 32 ............................................................ 8-88

Write Command ............................................................... 8-89

Bus Width = 64 ............................................................ 8-91

Bus Width = 32 ............................................................ 8-92

Refresh (REF) Command ................................................. 8-93

Self-Refresh (SREF) Command ......................................... 8-93

Programming Example .......................................................... 8-94

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CONTENTS

LINK PORTS

Link Architecture .......................................................................... 9-2

Link I/O Pins .......................................................................... 9-4

Link Transmit and Receive Data .............................................. 9-7

Link DMA .............................................................................. 9-9

Link Block Completion ........................................................... 9-9

Link Interrupts ...................................................................... 9-10

Link Reset Initialization and Boot .......................................... 9-10

Link Alternate (Software) Initialization .................................. 9-11

Link Port Communication Protocol ............................................. 9-12

Link Port Transmission Delays .................................................... 9-17

Link Port Error Detection Mechanisms ........................................ 9-19

Link Transmitter Timeout ..................................................... 9-20

Link Receiver Timeout .......................................................... 9-20

Link Verification Error .......................................................... 9-20

Link Transmit/Receive Write Error ........................................ 9-21

Link Port Control Registers ......................................................... 9-21

Link Port Status Registers ............................................................ 9-26

JTAG PORT AND

TEST/DEBUG INTERFACE

Operating Modes ........................................................................ 10-4

Debug Resources ......................................................................... 10-5

Special Instructions ............................................................... 10-5

Watchpoints .......................................................................... 10-5

ADSP-TS201 TigerSHARC Processor Hardware Reference xv

CONTENTS

Programming – Control and Address Pointer Registers ...... 10-5

Watchpoint Operation ...................................................... 10-6

Watchpoint Status (WPiSTAT) ......................................... 10-7

Instruction Address Trace Buffer (TBUF) .............................. 10-8

Performance Monitors ................................................................ 10-8

Cycle Counter (CCNT1–0) .................................................. 10-9

Performance Monitor Mask – PRFM ..................................... 10-9

Performance Monitor Counter ............................................ 10-10

JTAG Functionality .................................................................. 10-11

JTAG Port I/O Pins ............................................................ 10-11

JTAG Instruction Register ................................................... 10-13

Data Registers ..................................................................... 10-13

SYSTEM DESIGN

Processor Booting Methods ......................................................... 11-2

Using Boot Modes and Boot Loader Kernels .......................... 11-3

Executing a Processor Boot Operation ................................... 11-3

EPROM Boot ................................................................... 11-4

Host Boot ........................................................................ 11-5

Link Port Boot ................................................................. 11-6

No Boot ........................................................................... 11-6

Booting References ................................................................ 11-8

Hardware System Design Guidelines ........................................... 11-8

Power Supplies ...................................................................... 11-9

System Clock (SCLK) Pin ................................................... 11-10

xvi ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

Considerations for SCLK Design ..................................... 11-10

Considerations for SCLK Distribution ............................ 11-11

Boundary Scan and Emulator Pins ....................................... 11-15

External Ports Pins .............................................................. 11-15

Link Ports Pins .................................................................... 11-17

Hardware Design References ................................................ 11-17

Processor Thermal Relief Methods ............................................. 11-18

Thermal Overview ............................................................... 11-19

Thermal Calculations .......................................................... 11-21

Heat Sink Basics .................................................................. 11-23

Pin Fins versus Rectangular Fins .......................................... 11-23

PCB Design for Thermal Dissipation ................................... 11-24

Thermal Simulations ........................................................... 11-25

Thermal Design Terminology .............................................. 11-26

Thermal Design References .................................................. 11-27

Other Design and Test References ............................................. 11-28

ADSP-TS201 Processor EZ-KIT Lite ................................... 11-28

ADSP-TS201S MP System Simulation and Analysis

Cluster Bus Topology – Signal Integrity and PCB Design

Considerations ................................................................. 11-29

IBIS Models ........................................................................ 11-29

FPGA Link Port Support ..................................................... 11-30

Recommended Reading References ............................................ 11-31

INDEX

ADSP-TS201 TigerSHARC Processor Hardware Reference xvii

CONTENTS

xviii ADSP-TS201 TigerSHARC Processor Hardware Reference

ADSP-TS201 TigerSHARC Processor Hardware Reference xix

xx ADSP-TS201 TigerSHARC Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using TigerSHARC® processors from Analog Devices.

Purpose of This Manual

The ADSP-TS201 TigerSHARC Processor Hardware Reference contains information about the DSP architecture and DSP system design for TigerSHARC processors. These are 32-bit, fixed- and floating-point digital signal processors from Analog Devices for use in computing, communications, and consumer applications.

The manual provides information on how the processor core and I/O peripherals operate in the TigerSHARC processor’s architecture along with reference information about I/O peripheral features.

Intended Audience

The primary audience for this manual is a system developer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and microprocessor system design. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate programming reference manuals and data sheets) that describe your target architecture.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxi

Manual Contents

The manual consists of:

• Chapter 1, Processor Architecture This chapter provides an architectural overview of the TigerSHARC processor.

• Chapter 2, Memory and Registers This chapter defines the memory map of the ADSP-TS201 TigerSHARC processor. The memory space defines the location of each element on the TigerSHARC processor.

• Chapter 3, SOC Interface This chapter discusses clocking inputs, including the three different types of operating modes in which the ADSP-TS201 TigerSHARC processor can operate and the boot modes from which the TigerSHARC processor initiates.

• Chapter 4, Timers This chapter discusses clocking inputs, including the three different types of operating modes in which the ADSP-TS201 TigerSHARC processor can operate and the boot modes from which the TigerSHARC processor initiates.

• Chapter 5, Flags This chapter discusses clocking inputs, including the three different types of operating modes in which the ADSP-TS201 TigerSHARC processor can operate and the boot modes from which the TigerSHARC processor initiates.

• Chapter 6, Interrupts This chapter discusses the various types of interrupts supported by the ADSP-TS201 TigerSHARC processor. Some of the interrupts are generated internally or externally.

xxii ADSP-TS201 TigerSHARC Processor Hardware Reference

Preface

• Chapter 7, Direct Memory Access This chapter describes how the ADSP-TS201 TigerSHARC processor’s on-chip DMA controller acts as a machine for transferring data without core interruption.

• Chapter 8, External Port and SDRAM Interface This chapter focuses on the external bus interface of the ADSP-TS201 TigerSHARC processor, which includes the bus arbitration logic and the external address, data and control buses, and interface to SDRAM devices.

• Chapter 9, Link Ports This chapter describes how link ports provide point-to-point communications between ADSP-TS201 TigerSHARC processors in a system. The Link ports can also be used to interface with any other device that is designed to work in the same protocol.

• Chapter 10, JTAG Port and Test/Debug Interface This chapter describes features of the ADSP-TS201 TigerSHARC processor that are useful for performing software debugging and services usually found in Operating System (OS) kernels.

• Chapter 11, System Design This chapter describes system features of the ADSP-TS201 TigerSHARC processor. These include Power, Reset, Clock, JTAG, and Booting, as well as pin descriptions and other system level information.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxiii

This hardware reference is a companion document to the ADSP-TS201 TigerSHARC Processor Programming Reference.

What’s New in This Manual

Revision 1.0 of the ADSP-TS201 TigerSHARC Processor Hardware Reference differs in a number of ways from the revision 0.2 book. In

revision 1.0, the following additions and corrections have been made:

• The Processor Architecture chapter has replaced the previous Introduction chapter. This new chapter provides a more detailed road map to the processor architecture and processor core mode controls.

• The SOC Interface, Timers, and Flags chapters have been added. A description of the operation of all I/O peripherals as bus masters or slaves on the SOC bus has been added in all chapters.

• The Interrupts chapter has been re-ordered to provide more guidance on using interrupts, and a consolidated interrupt vector table has been added.

• The System Design chapter has been expanded. Many of the Engineer-to-Engineer (EE) Notes to which the revision 0.2 book referred have been added to the revision 1.0 book. The topics added include booting, system design guidelines, and thermal design guidelines.

• The index has been enhanced.

• Errata reports against the revision 0.2 book have been corrected.

xxiv ADSP-TS201 TigerSHARC Processor Hardware Reference

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

dsptools.support@analog.com

• E-mail processor questions to

dsp.support@analog.com

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized distributor

Preface

• Send questions by mail to:

Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

ADSP-TS201 TigerSHARC Processor Hardware Reference xxv

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®.

TigerSHARC (ADSP-TSxxx) Processors

The name “TigerSHARC” refers to a family of floating-point and fixed-point [8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently supports the following TigerSHARC processors:

ADSP-TS101, ADSP-TS201, ADSP-TS202, and ADSP-TS203

SHARC® (ADSP-21xxx) Processors

The name “SHARC” refers to a family of high-performance, 32-bit, floating-point processors that can be used in speech, sound, graphics, and imaging applications. VisualDSP++ currently supports the following SHARC processors:

ADSP-21020, ADSP-21060, ADSP-21061, ADSP-21062, ADSP-21065L, ADSP-21160, ADSP-21161, ADSP-21261, ADSP-21262, ADSP-21266, ADSP-21267, ADSP-21363, ADSP-21364, and ADSP-21365

Blackfin® (ADSP-BFxxx) Processors

The name “Blackfin” refers to a family of 16-bit, embedded processors. VisualDSP++ currently supports the following Blackfin processors:

ADSP-BF531, ADSP-BF532 (formerly ADSP-21532), ADSP-BF533, ADSP-BF535 (formerly ADSP-21535), ADSP-BF561, AD6532, and AD90747

xxvi ADSP-TS201 TigerSHARC Processor Hardware Reference

Preface

Product Information

You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows

customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.

Registration

Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as a means to select the information you want to receive.

If you are already a registered user, just log on. Your user name is your e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product announcements.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxvii

Product Information

You may also obtain additional information about Analog Devices and its products in any of the following ways.

• E-mail questions or requests for information to

dsp.support@analog.com

• Fax questions or requests for information to

1-781-461-3010 (North America) 089/76 903-557 (Europe)

• Access the FTP Web site at

ftp ftp.analog.com or ftp 137.71.23.21 ftp://ftp.analog.com

Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary .PDF files of most manuals are also provided.

Each documentation file type is described as follows.

File Description

.CHM Help system files and manuals in Help format

.HTM or .HTML

.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .HTML files requires a browser, such as Internet Explorer 4.0 (or higher).

Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

ADSP-TS201 TigerSHARC Processor Hardware Reference xxix

Product Information

If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD-ROM at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site.

Accessing Documentation From VisualDSP++

From the VisualDSP++ environment:

• Access VisualDSP++ online Help from the Help menu’s Contents, Search, and Index commands.

• Open online Help from context-sensitive user interface items (toolbar buttons, menu commands, and windows).

Accessing Documentation From Windows

In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documentation from Windows.

Help system files (.

CHM) are located in the Help folder, and .PDF files are

located in the Docs folder of your VisualDSP++ installation CD-ROM. The Docs folder also contains the Dinkum Abridged C++ library and the FlexLM network license manager software documentation.

Using Windows Explorer

• Double-click the

vdsp-help.chm file, which is the master Help sys-

tem, to access all the other .CHM files.

• Double-click any file that is part of the VisualDSP++ documentation set.

xxx ADSP-TS201 TigerSHARC Processor Hardware Reference

Preface

Using the Windows Start Button

• Access VisualDSP++ online Help by clicking the Start button and choosing Programs, Analog Devices, VisualDSP++, and VisualDSP++ Documentation.

• Access the

.PDF files by clicking the Start button and choosing

Programs, Analog Devices, VisualDSP++, Documentation for Printing, and the name of the book.

Accessing Documentation From the Web

Download manuals at the following Web site:

http://www.analog.com/processors/resources/technicalLibrary/ manuals

Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files.

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For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.

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To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit.

If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto

http://www.analog.com/salesdir/continent.asp.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxxi

Product Information

Hardware Tools Manuals

To purchase EZ-KIT Lite™ and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual.

Processor Manuals

Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual.

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To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.

xxxii ADSP-TS201 TigerSHARC Processor Hardware Reference

Conventions

Text conventions used in this manual are identified and described as follows.

Example Description

Close command (File menu)

{this | that} Alternative items in syntax descriptions appear within curly brackets

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

[this,…] Optional item lists in syntax descriptions appear within brackets

.SECTION Commands, directives, keywords, and feature names are in text with

filename Non-keyword placeholders appear in text with italic style format.

Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).

and separated by vertical bars; read the example as this or that. One or the other is required.

rated by vertical bars; read the example as an optional

delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of

letter gothic font.

Note: For correct operation, ... A Note: provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol.

this.

this or that.

Preface

Caution: Incorrect device operation may result if ... Caution: Device damage may result if ...

[

A Caution: identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.

Warn in g: Injury to device users may result if ... A Warning: identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for devices users. In the online version of this book, the word Wa rnin g appears instead of this symbol.

Additional conventions, which apply only to specific chapters, may

appear throughout this document.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxxiii

Conventions

xxxiv ADSP-TS201 TigerSHARC Processor Hardware Reference

1 PROCESSOR ARCHITECTURE

The ADSP-TS201 TigerSHARC Processor Hardware Reference describes the ADSP-TS201 TigerSHARC processor architecture and hardware system support features. These descriptions provide the information required for designing and configuring TigerSHARC processor systems.

As shown in Figure 1-1 and Figure 1-2, the processor architecture consists of two divisions: the processor core (where instructions execute) and the I/O peripherals (where data is stored and off-chip I/O is processed).

This chapter provides a high level description of the processor core and peripherals architecture. More detailed descriptions appear in related chapters.This chapter introduces the following section on processor architecture:

• “Processor Core” on page 1-8

• “Memory, Registers, and Buses” on page 1-22

• “SOC Interface” on page 1-24

• “Timers” on page 1-24

• “Flags” on page 1-25

• “Interrupts” on page 1-26

• “Direct Memory Access” on page 1-26

• “External (Address and Data) Port” on page 1-28

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-1

PROGR AM

SEQUENCER

ADDR

FETCH

BTB

IAB

U L

L C

U L

L C

DATA ADDRESS GENERATION

INTEGER

J-IALU

32X32 32X32

J-BUS ADDR

J-BUS DATA

K-BUS ADDR

K-BUS DATA

I-BUS ADDR

I-BUS DATA

R E

E T

T F

I H

H S

COMPUTATIONAL BLOCKS

R E

E T

T F

I H

H S

I L

L U

U M

R E

I L

L U

U M

128

FILE

32x32

FILE

32x32

128

INTEGER

K-IALU

DAB

Figure 1-1. ADSP-TS201 TigerSHARC Processor Core Diagram

1-2 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

J-BUS ADDR

J-BUS DATA

K-BUS ADDR

K-BUS DATA

I-BUS ADDR

I-BUS DATA

24M BITS INTERNAL MEMORY

INTERNAL MEMORY BLOCKS

(BUFFER/CACHE)

4xCROSSBAR CONNECT

ADADA

128

S-BUS ADDR

S-BUS DATA

128

JTAG

HOST

MULTI PROC

SDRAM

CTRL

C-BUS

ARB

DMA

OUT

JTAG PORT

EXTERNAL

PORT

EXT DMA

REQ

LINK PORTS

4 8

4 8 4 8

4 8

ADDR

DATA

CTRL

SOC BUS

E C A F R E T N

I C

O S

Figure 1-2. ADSP-TS201 TigerSHARC Processor Peripherals Diagram

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-3

• “Link Ports” on page 1-32

• “JTAG Port and Debug Interface” on page 1-32

• “Programming Information” on page 1-33

The ADSP-TS201 processor is a 128-bit, high performance TigerSHARC processor. The ADSP-TS201 processor sets a new standard of performance for digital signal processors, combining multiple computation units for floating-point and fixed-point processing as well as very wide word widths. The ADSP-TS201 processor maintains a ‘system-on-chip’ scalable computing design philosophy, including 24M bit of on-chip DRAM, six 4K word caches (one per memory block), integrated I/O peripherals, a host processor interface, DMA controllers, LVDS link ports, and shared bus connectivity for glueless multiprocessing.

In addition to providing unprecedented performance in DSP applications in raw MFLOPS and MIPS, the ADSP-TS201 processor boosts performance measures such as MFLOPS/Watt and MFLOPS/square inch in multiprocessing applications.

As shown in Figure 1-1 and Figure 1-2, the processor has the following architectural features:

• Dual computation blocks: X and Y – each consisting of a multiplier, ALU, CLU, shifter, and a 32-word register file

• Dual integer ALUs: J and K – each containing a 32-bit IALU and 32-word register file

• Program sequencer – Controls the program flow and contains an instruction alignment buffer (IAB) and a branch target buffer (BTB)

• Three 128-bit buses providing high bandwidth connectivity between internal memory and the rest of the processor core (compute blocks, IALUs, program sequencer, and SOC interface)

1-4 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

• A 128-bit bus providing high bandwidth connectivity between internal memory and external I/O peripherals (DMA, external port, and link ports)

• External port interface including the host interface, SDRAM controller, static pipelined interface, four DMA channels, four LVDS link ports (each with two DMA channels), and multiprocessing support

• 24M bits of internal memory organized as six 4M bit blocks—each block containing 128K words x 32 bits; each block connects to the crossbar through its own buffers and a 128K bit, 4-way set associative cache

• Debug features

• JTAG Test Access Port

Figure 1-3 illustrates a typical single processor system. A multiprocessor

system is illustrated in Figure 1-4 and is discussed later in “Multiprocess-

ing” on page 1-30.

The TigerSHARC processor includes several features that simplify system development. The features lie in three key areas:

• Support of IEEE floating-point formats

• IEEE Standard 1149.1 Joint Test Action Group (JTAG) serial scan path and on-chip emulation features

• Architectural features supporting high level languages and operating systems

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-5

CLOCK

REFERENCE

SDRAM

MEMORY

(OPTIONAL)

CLK ADDR

RAS CAS

DATA

DQM

CKE

A10

LINK

DEVICES

(4 MAX)

(OPTIONAL)

ADSP-TS201S

RST_IN RST_OUT POR_IN

SCLK SCLKRAT2–0

SCLK_V

REF

IRQ3–0

FLAG3–0 ID2–0

MSSD3–0 RAS CAS

LDQM HDQM

SDWE

SDCKE SDA10

IORD IOWR IOEN

LxDATO3–0P/N LxCLKOUTP/N LxACKI

LxBCMPO

LxDATI3–0P/N LxCLKINP/N LxACKO

LxBCMPI

CONTROLIMP1–0 TMR0E DS2–0

ADDR31–0

DATA63–0

WRH/WRL

DMAR3–0

BUSLOCK

BMS

BRST

ACK

MS1–0

MSH

HBR

HBG

BOFF

BR7–0

CPA DPA

JTAG

BOOT

EPROM

(OPTIONAL)

ADDR DATA

MEMORY

(OPTIONAL)

ADDR

DATA

OE WE

ACK

HOST

PROCESSOR

INTERFACE (OPTIONAL)

ADDR

DATA

DMA DEVICE

(OPTIONAL)

DATA

O R T N O C

D D D A

Figure 1-3. Single Processor Configuration

The features of the TigerSHARC processor architecture that directly support high level language compilers and operating systems include:

• Simple, orthogonal instruction allowing the compiler to efficiently use the multi-instruction slots

• General-purpose data and IALU register files

• 32-bit (IEEE Standard 754/854) and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point native data types

1-6 ADSP-TS201 TigerSHARC Processor Hardware Reference

LVDS LINKS

Processor Architecture

SDRAM

MEMORY

TigerSHARC

MSSD3–0

MS0

LVDS LINKS

TigerSHARC

TigerSHARCTigerSHARC

DEV

Figure 1-4. Multiprocessing Cluster Configuration

• Large address space

• Immediate address modify fields

HOST IF

MSH

MS1

BRIDGE

DEV

• Easily supported relocatable code and data

• Fast save and restore of processor registers onto internal memory stacks

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-7

Processor Core

The processor core is the part of the processor that executes instructions. The following discussion provides a some details on the processor core architecture. For more information on the processor core, see related chapters in the ADSP-TS201 TigerSHARC Processor Programming Refer- ence. This section describes:

• “Compute Blocks” on page 1-10

• “Arithmetic Logic Unit (ALU)” on page 1-12

• “Communications Logic Unit (CLU)” on page 1-12

• “Multiply Accumulator (Multiplier)” on page 1-12

• “Bit Wise Barrel Shifter (Shifter)” on page 1-13

• “Integer Arithmetic Logic Unit (IALU)” on page 1-13

• “Program Sequencer” on page 1-15

• “Processor Core Controls” on page 1-17

High performance is facilitated by the ability to execute up to four 32-bit wide instructions per cycle. The TigerSHARC processor uses a variation of a Static Superscalar™ architecture to allow the programmer to specify which instructions are executed in parallel in each cycle. The instructions do not have to be aligned in memory so that program memory is not wasted.

The 24M bit internal memory is divided into six 128K word memory blocks. Each of the four internal address/data bus pairs connect to all of the six memory blocks via a crossbar interface. The six memory blocks support up to four accesses every cycle where each memory block can perform a 128-bit access in a cycle. Each block’s cache and prefetch mechanism improve access performance of internal memory (embedded DRAM).

1-8 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

The external port cluster bus is 64 bits wide. The high I/O bandwidth complements the high processing speeds of the core. To facilitate the high clock rate, the ADSP-TS201 processor uses a pipelined external bus with programmable pipeline depth for interprocessor communications and for Synchronous Flow-through SRAM (SSRAM) and SDRAM.

The four LVDS link ports support point-to-point high bandwidth data transfers. Each link port supports full-duplex communication.

The processor operates with a two cycle arithmetic pipeline. The branch pipeline is four to ten cycles. A branch target buffer (BTB) is implemented to reduce branch delay.

During compute intensive operations, one or both integer ALUs compute or generate addresses for fetching up to two quad operands from two memory blocks, while the program sequencer simultaneously fetches the next quad instruction from a third memory block. In parallel, the computation units can operate on previously fetched operands while the sequencer prepares for a branch.

While the core processor is doing the above, the DMA channels can be replenishing the internal memories in the background with quad data from either the external port or the link ports.

The processing core of the ADSP-TS201 processor reaches exceptionally high DSP performance through using these features:

• Computation pipeline

• Dual computation units

• Execution of up to four instructions per cycle

• Access of up to eight words per cycle from memory

The two identical computation units support floating-point as well as fixed-point arithmetic. These units (compute blocks) perform up to 6 floating-point or 24 fixed-point operations per cycle.

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-9

Processor Core

Each multiplier and ALU unit can execute four 16-bit fixed-point operations per cycle, using Single-Instruction, Multiple-Data (SIMD) operation. This operation boosts performance of critical imaging and signal processing applications that use fixed-point data.

Compute Blocks

The TigerSHARC processor core contains two computation units called compute blocks. Each compute block contains a register file and four independent computation units—an ALU, a CLU, a multiplier, and a shifter. For meeting a wide variety of processing needs, the computation units process data in several fixed- and floating-point formats.

These formats are listed here and shown in Figure 1-5:

• Fixed-point format

These include 64-bit long word, 32-bit normal word, 32-bit complex (16-bit real and 16-bit imaginary), 16-bit short word, and 8-bit byte word. For short word fixed-point arithmetic, quad parallel operations on quad-aligned data allow fast processing of array data. Byte operations are also supported for octal-aligned data.

• Floating-point format

These include 32-bit normal word and 40-bit extended word. Floating-point operations are single or extended precision. The normal word floating-point format is the standard IEEE format, and the 40-bit extended-precision format occupies a double word (64 bits) with eight additional least significant bits (LSBs) of mantissa for greater accuracy.

Each compute block has a general-purpose, multiport, 32-word data register file for transferring data between the computation units and the data buses and storing intermediate results. All of these registers can be accessed as single-, double-, or quad-aligned registers. For more information on the register file, see Chapter 2, “Compute Block Registers” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

1-10 ADSP-TS201 TigerSHARC Processor Hardware Reference

Data Bus (128-bit)

Processor Architecture

Data

(32-bit)

31 031 0 31 0 31 0

32-bit

Single Register

16-

bit

Single Register

bit8-bit8-bit8-bit

Single Register

16-

bit

(32-bit)

30 23

bit

Data

64-bit

Dual Register

Data

Data Types

Long Word

(64-bit)

Extended Word

(40-bit)

(floating-point)

Normal Word

(32-bit)

Short Word

(16-bit)

Byte Word

(8-bit)

(32-bit)

Figure 1-5. Word Format Definitions

1 The TigerSHARC processor internal data buses are 128 bits (one quad word) wide. In a quad word,

the processor can move 16 byte words, 8 short words, 4 normal words, or 2 long words over the bus at the same time.

Data

(32-bit)

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-11

Processor Core

Arithmetic Logic Unit (ALU)

The ALU performs arithmetic operations on fixed-point and floating-point data and logical operations on fixed-point data. The source and destination of most ALU operations is the compute block register file. For more information on ALU features, see Chapter 3, “ALU” in the

ADSP-TS201 TigerSHARC Processor Programming Reference

Communications Logic Unit (CLU)

On the ADSP-TS201 processor, there is a special purpose compute unit called the communications logic unit (CLU). The CLU instructions are designed to support different algorithms used for communications applications. The algorithms that are supported by the CLU instructions are:

• Viterbi Decoding

• Turbo code Decoding

• Despreading for code division multiple access (CDMA) systems

• Cross correlations used for path search

For more information on CLU features, see Chapter 4, “CLU” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Multiply Accumulator (Multiplier)

The multiplier performs fixed-point or floating-point multiplication and fixed-point multiply/accumulate operations. The multiplier supports several data types in fixed- and floating-point formats. The floating-point formats are float and float-extended, as in the ALU. The source and destination of most operations is the compute block register file.

The ADSP-TS201 processor’s multiplier supports complex multiply-accumulate operations. Complex numbers are represented by a pair of 16-bit short words within a 32-bit word. The LSBs of the input operand repre-

1-12 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

sent the real part, and the most significant bits (MSBs) of the input operand represent the imaginary part. For more information on multiplier features, see Chapter 5, “Multiplier” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Bit Wise Barrel Shifter (Shifter)

The shifter performs logical and arithmetic shifts, bit manipulation, field deposit, and field extraction. The shifter operates on one 64-bit, one or two 32-bit, two or four 16-bit, and four or eight 8-bit fixed-point operands. Shifter operations include:

• Shifts and rotates from off-scale left to off-scale right

• Bit manipulation operations, including bit set, clear, toggle and test

• Bit field manipulation operations, including field extract and deposit, using register

BFOTMP (which is internal to the shifter)

• Bit FIFO operations to support bit streams with fields of varying length

• Support for ADSP-21000 DSP family compatible fixed-point/floating-point conversion operations (such as exponent extract, number of leading ones or zeros)

For more information on shifter features, see Chapter 6, “Shifter” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Integer Arithmetic Logic Unit (IALU)

The IALUs can execute standard standalone ALU operations on IALU register files. The IALUs also execute register load, store, and transfer operations, providing memory addresses when data is transferred between memory and registers. The processor has dual IALUs (the J-IALU and the K-IALU) that enable simultaneous addresses for two transactions of up to

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-13

Processor Core

128 bits in parallel. The IALUs allow compute operations to execute with maximum efficiency because the computation units can be devoted exclusively to processing data.

Each IALU has a multiport, 32-word register file. All IALU calculations are executed in a single cycle. The IALUs support pre-modify with no update and post-modify with update address generation. Circular data buffers are implemented in hardware. The IALUs support the following types of instructions:

• Regular IALU instructions

• Move Data instructions

• Load Data instructions

• Load/Store instructions with register update

• Load/Store instructions with immediate update

For indirect addressing (instructions with update), one of the registers in the register file can be modified by another register in the file or by an immediate 8- or 32-bit value, either before (pre-modify) or after (post-modify) the access. For circular buffer addressing, a length value can be associated with the first four registers to perform automatic modulo addressing for circular data buffers; the circular buffers can be located at arbitrary boundaries in memory. Circular buffers allow efficient implementation of delay lines and other data structures, which are commonly used in digital filters and Fourier transformations. The ADSP-TS201 processor circular buffers automatically handle address pointer wraparounds, reducing overhead and simplifying implementation.

The IALUs also support bit reverse addressing, which is useful for the FFT algorithm. Bit reverse addressing is implemented using a reverse carry addition that is similar to regular additions, but the carry is taken from the upper bits and is driven into lower bits.

1-14 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

The IALU provides flexibility in moving data as single, dual, or quad words. Every instruction can execute with a throughput of one per cycle. IALU instructions execute with a single cycle of latency. Normally, there are no dependency delays between IALU instructions, but if there are, four cycles of latency can occur.

For more information on IALU features, see Chapter 7, “IALU” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Program Sequencer

The program sequencer supplies instruction addresses to memory and, together with the IALUs, allows compute operations to execute with maximum efficiency. The sequencer supports efficient branching using the branch target buffer (BTB), which reduces branch delays for conditional and unconditional instructions. The two responsibilities of the sequencer are to decode fetched instructions—separating the instruction slots of the instruction line and sending each instruction to its execution unit (compute blocks, IALUs, or sequencer)—and to control the program flow. The sequencer’s control flow instructions divide into two types:

• Control flow instructions. These instructions are used to direct pro- gram execution by means of jumps and to execute individual instructions conditionally.

• Immediate extension instructions. These instructions are used to extend the numeric fields used in immediate operands for the sequencer and the IALU.

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-15

Processor Core

Control flow instructions divide into two types:

• Direct jumps and calls based on an immediate address operand specified in the instruction encoding. For example, ‘

jump 100;

true.

• Indirect jumps based on an address supplied by a register. The instructions used for specifying conditional execution of a line are a subcategory of indirect jumps. For example, ‘if <cond> cjmp;’ is a jump to the address pointed to by the CJMP register.

’ always jumps to address 100, if the <cond> evaluates as

if <cond>

Immediate extensions are associated with IALU or sequencer (control flow) instructions. These instructions are not specified by the programmer, but are implied by the size of the immediate data used in the instructions. The programmer must place the instruction that requires an immediate extension in the first instruction slot and leave an empty instruction slot in the line (use only three slots), so the assembler can place the immediate extension in the second instruction slot of the instruction line.

The ADSP-TS201 processor achieves its fast execution rate by means of a ten-cycle pipeline.

Two stages of the sequencer’s pipeline actually execute in the computation units. The computation units perform single cycle operations with a two-cycle computation pipeline, meaning that results are available for use two cycles after the operation is begun. Hardware causes a stall if a result is not available in a given cycle (register dependency check). Up to two com-

The control flow instruction must use the first instruction slot in the instruction line.

Note that only one immediate extension may be in a single instruction line.

1-16 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

putation instructions per compute block can be issued in each cycle, instructing the ALU, multiplier, or shifter to perform independent, simultaneous operations.

The branch penalty in a deeply pipelined processor, such as the ADSP-TS201 processor, can be compensated for by using a branch target buffer (BTB) and branch prediction. The branch target address is stored in the BTB. When the address of a jump instruction, which is predicted by the user to be taken in most cases, is recognized (the tag address), the corresponding jump address is read from the BTB and is used as the jump address on the next cycle. Thus, the latency of a jump is reduced from five to nine wasted cycles to zero wasted cycles. If this address is not stored in the BTB, the instruction must be fetched from memory.

Other instructions also use the BTB to speed up these types of branches. These instructions are interrupt return, call return, and computed jump instructions.

For more information on the sequencer, BTB, and immediate extensions, see Chapter 8, “Program Sequencer” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Processor Core Controls

There are few modes and controls required for ADSP-TS201 TigerSHARC processor operation because most operational features are specified as part of instruction syntax. This section describes operational modes for the processor that are not controlled as part of instruction syntax. These controls include clock domain controls, operating mode controls, and boot mode controls.

Clock Domains

The processor uses calculated ratios of the input system clock (SCLK) clock to operate as shown in Figure 1-6. The instruction execution rate is equal to the processor core clock (CCLK). A PLL from SCLK generates

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-17

Processor Core

CCLK which is phase locked. The link port clocks (

LxCLKOUT pins) are

generated from CCLK from a software programmable divisor, and the SOC bus clock (SOCCLK) operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. The SCLK also provides the clock input for the external bus interface and defines the AC specification reference for the external bus signals. The external bus interface runs at the SCLK frequency.

EXTERNAL INTERFACE

SCLK

SCLKRATx

LCTLx REGISTER

PLL

/CR

SPD BITS,

CCLK (INSTRUCTION RATE)

SOCCLK (PERIPHERAL BUS RATE)

LxCLKOUT (LINK OUTPUT RATE)

Figure 1-6. Clock Domains

The SCLKRATx pins define the clock multiplication of SCLK to CCLK. For information on the SCLKRATx pins settings and the maximum SCLK frequency, see the ADSP-TS201 TigerSHARC Embedded Processor Data Sheet.

The clock domains particularly influence the performance of operations that move data between domains over the processor’s SOC bus. For more information, see “SOC Interface” on page 1-24 and “SOC Interface” on

page 3-1.

Operation Modes

The TigerSHARC processor operates in one of three modes—user, supervisor, and emulator. In user and supervisor modes, all instructions are executed normally. In user mode, however, the register access is limited. Regardless of the operation mode (emulation, supervisor, or user), all instructions are executed normally.

1-18 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

The current operating mode of the TigerSHARC processor affects which components of the processor are active and can be accessed. The mode also affects which exceptions are taken and how they are handled. The mode priorities from lowest priority to highest priority are: User Mode,

Supervisor Mode, and Emulator Mode.

User Mode

The user mode operation is used for algorithms and control code that does not require the manipulation of system resources. Many system resources are not accessible in user mode. If the TigerSHARC processor attempts to access these resources, an exception occurs.

User mode is often used when running code out of an operating system. The operating system kernel runs in supervisor mode, but the user code is restricted to user mode.

The registers that may be accessed by core program in user mode are:

• Register groups 0x00 to 0x09 – compute block registers

• Register groups 0x0C to 0x0F – IALU registers

• Sequencer registers –

CJMP, loop counter registers LC0 and LC1, and

the static flag register (SFREG)

All other registers cannot be written by the core program in user mode. An attempt to write to a protected register causes an exception. These registers can still be accessed by another master (DMA, external host, and others).

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-19

Processor Core

Supervisor Mode

Most code that is not intended to run under an operating system should be designed to run in supervisor mode. Supervisor mode allows the program to access all processor resources. The TigerSHARC processor is in supervisor mode when one of these two conditions is true:

• The

NMOD bit in SQCTL is set. For more information, see “Sequencer

Control (SQCTL) Register” on page 2-29.

• An interrupt routine is executed—indicated by non-zero PMASK. For more information, see “PMASK Register” on page 6-6.)

Normally when the TigerSHARC processor is reset (via hardware or software), it goes into idle state. It exits the idle state to a running state when an interrupt is issued. The interrupt puts the TigerSHARC processor into supervisor mode.

If the NMOD bit in SQCTL is cleared, the processor enters user mode after leaving an interrupt routine (unless it is nested inside another interrupt routine).

Emulator Mode

Emulator mode is used when controlling the processor with an emulator tool via the JTAG port. The TigerSHARC processor enters emulation mode when an emulation exception is generated. An emulation exception is generated after any one of these events:

EMUTRAP instruction

•

• Watchpoint when programmed to cause emulation trap

• JTAG private instruction

• TMS rising while TEME bit in EMUCTL is set

Emulation exceptions are the highest priority exceptions or interrupts.

1-20 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

While the TigerSHARC processor is in emulator mode, the only source of instructions is the

EMUIR register. The EMUIR register is loaded via the

JTAG Test Access Port (TAP). When entering this mode, the external JTAG controller (Analog EZ-ICE or other customer hardware) must be enabled. For more information, see “Sequencer Control (SQCTL) Regis-

ter” on page 2-29.

When the emulation features are enabled and an emulation exception is encountered, the TigerSHARC processor enters emulation mode. When the TigerSHARC processor is operating in emulator mode, the only way it can exit emulator mode is by executing a return from interrupt (RTI).

In emulator mode, the debug registers (register group 0x1B) can be accessed only by move register-to-register or immediate data load instructions. These registers cannot be loaded from or stored to memory directly.

In emulation mode, the program access to the debug registers (register groups 0x1B and 0x3D) may be executed only using the instruction:

Ureg = Ureg ;

The BTB, cycle count, performance monitors, and trace buffer are inactive in emulation mode. Except for if true—RTI (np), all control flow instructions (jump, call, RDS, conditional, and so on.) and the IDLE instruction cannot be used in emulator mode. The RTI instruction can only be used without condition.

If the external reset pin is being asserted, and an external emulation exception is generated, the TigerSHARC processor core exits reset internally, enters emulator mode, and waits to fetch the value of EMUIR, which is loaded from the JTAG. In this case, only the core processor operates. The external interfaces (external port, link ports, DMA, and others) are still held in reset, although their internal registers can be accessed by the instructions inserted via JTAG and

EMUIR. This feature enables an EZ-ICE

to initialize the TigerSHARC processor internal registers and memory while it is still in reset and start its run from a known state.

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-21

Memory, Registers, and Buses

Boot Modes

The internal memory of the TigerSHARC processor can be boot loaded from an 8-bit EPROM, a host processor, or a link port using a boot mechanism at system power up. The TigerSHARC processor can also be run (no boot) from a memory location at startup. Selection of the boot source is controlled by the boot modes, see “Processor Booting Methods” on page 11-2.

BMS strap (external) pins. For more information on

Memory, Registers, and Buses

The on-chip memory consists of six blocks of 4M bits each. Each block is 128K words, thus providing high bandwidth sufficient to support both computation units, the instruction stream and external I/O, even in very intensive operations. The ADSP-TS201 processor provides access to program, two data operands, and a system access (over the SOC bus) to different memory blocks without memory or bus constraints. The memory blocks can store instructions and data interchangeably.

Each memory block is organized as 128K words of 32 bits each. The accesses are pipelined to meet one clock cycle access time needed by the core, DMA, or by the external bus. Each access can be up to four words. The six memory blocks are a resource that must be shared between the compute blocks, the IALUs, the sequencer, the external port, and the link ports. In general, if during a particular cycle more than one unit in the processor attempts to access the same memory, one of the competing units is granted access, while the other is held off for further arbitration until the following cycle—see “Bus Arbitration Protocol” on page 8-38. This type of conflict only has a small impact on performance due to the very high bandwidth afforded by the internal buses.

1-22 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

An important benefit of large on-chip memory is that by managing the movement of data on and off chip with DMA, a system designer can realize high levels of determinism in execution time. Predictable and deterministic execution time is a central requirement in DSP and real-time systems.

Internal Buses

The processor core has three buses (I-bus, J-bus, and K-bus), each connected to all of the internal memory blocks via a crossbar interface. These buses are 128 bits wide to allow up to four instructions, or four aligned data words, to be transferred in each cycle on each bus. On-chip system elements use the SOC bus and S-bus to access memory. Only one access to each memory block is allowed in each cycle, so if the application accesses a different memory segment for each purpose (instruction fetch, load/store J-IALU and K-IALU instructions and external accesses), all transactions can be executed with no stalls.

Most registers of the ADSP-TS201 processor are classified as universal registers (Ureg ). Instructions are provided for transferring data between any two Ureg registers, between a Ureg and memory, or for the immediate load of a Ureg .This includes control registers and status registers, as well as the data registers in the register files. These transfers occur with the same timing as internal memory load/store. All registers can be accessed by register-move instructions or by external master access (another ADSP-TS201 on the same cluster bus or host), but only the core registers can be accessed by load/store instructions or load-immediate instructions.

Internal Registers

Most registers of the ADSP-TS201 processor are classified as universal registers ( any two

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-23

Ureg). Instructions are provided for transferring data between

Ureg registers, between a Ureg and memory, or for the immediate

SOC Interface

load of a as the data registers in the register files. These transfers occur with the same timing as internal memory load/store.

Ureg. This includes control registers and status registers, as well

SOC Interface

A separate system on chip (SOC) bus connects the external interfaces (external port, DMA, link ports, JTAG port, and others) to the memory system via the SOC interface and S-bus. This bus has a 128-bit wide data bus and a 32-bit wide address bus. It works at half the processor core clock rate. All data transferred between internal memory or core, and external port (cluster bus, link port, and others) passes through this bus.

As shown in Figure 1-7, the SOC bus and other buses operate at the speed of the clock in their clock domain. Data that moves from one clock domain to another (for example, a DMA to or from internal memory) must pass through arbitration and synchronization at the border of each domain. If multiple masters are requesting a bus, this arbitration can become an important factor in system performance. For more information, see “Clock Domains” on page 1-17 and “SOC Interface” on

page 3-1.

Timers

The TigerSHARC processor has two general-purpose 64-bit timers— Timer 0 and Timer 1. The timers are free-running counters that are loaded with an initial value and give an indication when expiring. The indication is normally an interrupt, but could also be an external pin (TMR0E) for Timer 0. For more information, see “Timers” on page 4-1.

1-24 ADSP-TS201 TigerSHARC Processor Hardware Reference

Cluster

Bus

64 Bits Wide

Operates at

SCLK rate

Operate at

LxCLKIN/OUT

rate

Operates at

TCK rate

Processor Architecture

Operate at SCLK rate

FLAGx

IRQx

TMR0E

DMARx

SOC

Bus

J-Bus

K-Bus

I-Bus

S-Bus

External

Port (EBIU)

Operates at SOCCLK rate

SOC

Interface

Memory

128 Bits Wide

Link

Ports

JTAG

Port

Processor Core

Compute Blocks

Integer ALUs

Sequencer

Non-Ureg Registers

Flags

Interrupts

Each 128 BitsWide

Operate at CCLK rate

Timer

DMA

Extended Core

Operates at

CCLK rate

Figure 1-7. Buses, Bus Masters, and Clock Domains

Flags

There are four input/output flag pins. Each pin can be individually configured to be an input or output. When they are configured as input flag pins, they can be used either as a condition or as a value in the

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-25

SQSTAT reg-

Interrupts

ister. (See “Flag Control (FLAGREG) Register” on page 2-28.) After powerup reset, them at logic high value. For more information, see “Flags” on page 5-1.

FLAG3–0 are inputs where static 5 kΩ pull-up resistors hold

Interrupts

The ADSP-TS201 processor has four general-purpose external interrupts,

IRQ3-0. The processor also has internally generated interrupts for the two

timers, DMA channels, link ports, arithmetic exceptions, multiprocessor vector interrupts, and user-defined software interrupts. Interrupts can be nested through instruction commands. Interrupts have a short latency and do not abort currently executing instructions. Interrupts vector directly to a user-supplied address in the interrupt table register file, removing the overhead of a second branch. For more information, see “Interrupts” on

page 6-1.

Direct Memory Access

The TigerSHARC processor on-chip DMA controller allows zero-overhead data transfers without processor intervention. The TigerSHARC processor can simultaneously fetch instructions and access two memories for data without relying on data or instruction caches. The DMA controller operates independently of the processor core, supplying addresses for internal and external memory access. The DMA channels, therefore, are not part of the core processor from a programming point of view.

The processor core has four buses, each one connected to one of the internal bus masters (J-IALU, K-IALU, program sequencer, and SOC interface). Each bus can connect to any memory block. These buses are 128 bits wide to allow up to four instructions, or four aligned data words, to be transferred in each cycle on each bus. On-chip system elements also use these buses to access memory. Only one access to each memory block is allowed in each cycle, so DMA or external port transfers must compete

1-26 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

with core accesses on the same block. Because of the large bandwidth available from each memory block, not all the memory bandwidth can be used by the core units, which leaves some memory bandwidth available for use by the processor’s DMA processes or by the bus interface to serve other DSPs’ external cluster bus master transfers to the TigerSHARC processor’s memory.

Both code and data can be downloaded to the TigerSHARC processor using DMA transfers, which can occur between the following.

• TigerSHARC processor internal memory and external memory, external peripherals or a host processor

• External memory and external peripheral devices

• External memory and link ports or between two link ports

Six DMA channels (four external port DMA channels and two autoDMA channels) are available on the TigerSHARC processor for data transfers through the external port. Eight DMA channels are available for link data transfers (two per link).

Asynchronous off-chip peripherals can control any one of four DMA channels using DMA request lines (

DMAR3–0). Other DMA features

include flyby (for channel 0 only), interrupt generation upon completion of DMA transfers, and DMA chaining for automatically linked DMA transfers.

For more information on DMA, see “Direct Memory Access” on page 7-1.

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-27

External (Address and Data) Port

The TigerSHARC processor external port provides an interface to external memory, to memory-mapped I/O, to host processor, and to additional TigerSHARC processors. The external port performs external bus arbitration and supplies control signals to shared, global memory, SDRAM, and I/O devices.

The external port cluster bus can be configured to be either 32 or 64 bits wide. The high I/O bandwidth complements the high processing speeds of the core. To facilitate the high clock rate, the TigerSHARC processor uses a pipelined external bus protocol with programmable pipeline depth for external memory access and host communication. For more information on the external port, see “External Port and SDRAM Interface” on

page 8-1.

External Bus and Host Interface

The TigerSHARC processor external port (EP) provides an interface between the core processor and the 32/64-bit parallel external bus. The external port contains FIFOs that maintain the throughput of an external bus that is shared with multiple processors and peripherals—each of which may operate at speeds other than that of the core.

The most effective way to access external data in the TigerSHARC processor is through the DMA. This runs in the background, allowing the core to continue processing while new data is read in or processed data is written out. Multiple DMA data streams can occur simultaneously, and the use of FIFOs helps to maintain throughput in the system.

Burst accesses are provided through the device on the bus to accept the first address and then automatically increment that address as successive data words arrive.

1-28 ADSP-TS201 TigerSHARC Processor Hardware Reference

BRST pin, which allows a slave

Processor Architecture

External Memory

The TigerSHARC processor external port provides the processor interface to off-chip memory and peripherals. The off-chip memory and peripherals are included in the TigerSHARC processor unified address space. The separate on-chip buses are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. External memory and devices can be either 32 or 64 bits wide. The TigerSHARC processor automatically packs external data into either 32-, 64-, or 128-bit word widths, the latter being more efficient for reducing memory access conflicts.

On-chip decoding of high order address lines (to generate memory block select signals) facilitates addressing of external memory devices. Separate control lines are also generated for simplified addressing of page mode DRAM.

The TigerSHARC processor uses the address on the external port bus to pipeline the data. This allows interfacing to synchronous DRAM and speeds up interprocessor accesses. An option allows asynchronous operation for slower devices.

External data can be accessed by DMA channels or by the core. For core accesses, the read latency can be significant—eight or more cycles. The core provides I/O buffering by stalling if the data is accessed before the data is loaded in a universal register (Ureg).

Programmable memory wait states permit peripherals with different access, hold, and disable time requirements.

External shared memory resources are assigned between processors by using semaphore operations.

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-29

External (Address and Data) Port

Multiprocessing

The ADSP-TS201 processor, like the ADSP-TS101 processor, is designed for multiprocessing applications. The primary multiprocessing architecture supported is a cluster of up to eight TigerSHARC processors that share a common bus, a global memory, and an interface to either a host processor or to other clusters. In large multiprocessing systems, this cluster can be considered an element and connected in configurations such as torroid, mesh, tree, crossbar, or others. The user can provide a personal interconnect method or use the on-chip communication ports.

The ADSP-TS201 processor includes the following multiprocessing capabilities:

• On-chip bus arbitration for glueless multiprocessing

• Globally accessible internal memory and registers

• Semaphore support

• Powerful, in-circuit multiprocessing emulation

The TigerSHARC processor offers features tailored to multiprocessing systems:

• The unified address space allows direct interprocessor accesses of each TigerSHARC processor internal memory and resources.

• Distributed bus arbitration logic is included on chip for glueless connection of systems containing up to eight TigerSHARC processors and a host processor.

• Bus arbitration rotates, except for host requests that always hold the highest priority.

• Processor bus lock allows indivisible read-modify-write sequences for semaphores.

1-30 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

• A vector interrupt capability is provided for interprocessor commands.

• Broadcast writes allow simultaneous transmissions of data to all TigerSHARC processors.

Host Interface

Connecting a host processor to a cluster of TigerSHARC processors is simplified by the memory-mapped nature of the interface bus and the availability of special host bus request signals.

A host that is able to access a pipelined memory interface can be easily connected to the parallel TigerSHARC processor bus. All the internal memory, Uregs, and resources within the TigerSHARC processor, such as the DMA control registers and the internal memory, are accessible to the host.

The host interface is through the TigerSHARC processor external address and data bus, with additional lines being provided for host control. The protocol is similar to the standard TigerSHARC processor pipelined bus protocol.

The host becomes bus master of the cluster by asserting the Host Bus Request (

HBR) signal. Host Bus Grant (HBG) is returned by the

TigerSHARC processors when the current master grants bus by asserting

HBR. The host interface is synchronous, and can be delayed a number of

cycles to allow slow host access. The host can also access external memory directly.

All DMA channels are accessible to the host interface, allowing code and data transfers to be accomplished with low software overhead. The host can directly read and write the internal memory of the TigerSHARC processor and can access the DMA channel setup. Vector interrupt support is provided for efficient execution of host commands and burst-mode transfers.

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-31

Link Ports

The TigerSHARC processor has four link ports that provide four-bit receive and four-bit transmit I/O capabilities in multiprocessing systems. The link ports have the following characteristics.

• Link clock speed is selectable as either x1/4, x1/2, x2/3, or x1 of internal clock frequency.

• Link port data is packed into 128-bit words for DMA transfer to on- or off-chip memory.

• Each link port has its own buffer registers.

• Link port transfers are controlled by acknowledge handshaking.

• Link ports support full-duplex transfer and transfers to/from the external port or other links.

For more information on the link ports, see “Link Ports” on page 9-1.

JTAG Port and Debug Interface

The ADSP-TS201 processor supports the IEEE Standard 1149.1 Joint Test Action Group (JTAG) port for system test. This standard defines a method for serially scanning the I/O status of each component in a system. The JTAG serial port is also used by the TigerSHARC processor emulator to gain access to the processor’s on-chip emulation features.

For more information, see “JTAG Port and Test/Debug Interface” on

page 10-1.

1-32 ADSP-TS201 TigerSHARC Processor Hardware Reference

Processor Architecture

Programming Information

Refer to the ADSP-TS201 TigerSHARC Processor Programming Reference for more programming information. Information available in the programming reference includes:

• Detailed chapters on each computation unit (ALU, CLU, multiplier, and shifter), IALU, program sequencer, and embedded DRAM (internal memory) operation

• Complete reference information on all processor instructions

• Complete reference information on instruction parallelism rules

• All available reference information on other programming topics

ADSP-TS201 TigerSHARC Processor Hardware Reference 1-33

Programming Information

1-34 ADSP-TS201 TigerSHARC Processor Hardware Reference

2 MEMORY AND REGISTERS

This chapter describes the ADSP-TS201 TigerSHARC processor memory and register map. For information on using registers for computations and memory for register loads and stores, see the ADSP-TS201 TigerSHARC Processor Programming Reference. For information on using registers for configuring the TigerSHARC processor’s peripherals, use the applicable chapters in this book.

The ADSP-TS201 TigerSHARC processor has six internal memory blocks as shown in the memory map (Figure 2-1). Each memory block consists of 4M bits of memory space, and is configured as 128K words, each 32 bits in width. There are four separate internal 128-bit data buses, each can access any of the memory blocks. Memory blocks can store instructions and data interchangeably, with one access per memory block per cycle. If the programmer ensures that program and data are in different memory blocks, then data access can occur at the same time as program fetch. The I/O processor has its own internal bus, so the I/O processor does not compete with the core for use of an internal bus. Thus in one cycle, up to four 128-bit transfers can occur within the core (two data transfers, one program instruction transfer, and one I/O processor interface transfer).

The TigerSHARC processor’s 32-bit address bus provides an address space of four gigawords. This address space is common to a cluster of TigerSHARC processors that share the same cluster bus. This chapter defines the memory map of each TigerSHARC processor in the system

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-1

GLOBAL SPACE

0xFFFFFFFF

INTERNAL SPACE

RESERVED

SOC REGISTERS(UREGS)

RESERVED

INTERNAL REGISTERS (UREGS)

RESERVED

INTERNAL MEMORY BL OCK 10

RESERVED

INTERNAL MEMO RY BLOCK 8

RESERVED

INTERNAL MEMO RY BLOCK 6

RESERVED

INTERNAL MEMO RY BLOCK 4

RESERVED

INTERNAL MEMORY BLOCK 2

RESERVED

INTERNAL MEMORY BLOCK 0

0x03FFFFFF

0 x001F0 3FF

0X0 01F00 00

0x001E03FF

0X 001E0 000

0x 0015 FF FF

0 x0014 0000

0x 0011 FF FF

0 x0010 0000

0x000DFFFF

0x0 00C 0000

0x0 009FF FF

0x 0008 0000

0x0 005FF FF

0x 0004 0000

0 x0001 FFFF

0 x0000 0000

EACH IS A COPY

OF INTERNAL SPACE

HOST (MS H)

RESERVED

MS SD B ANK 3 ( MS SD3 )

E C A P S Y R O M E M L A N R E T X E

E C A P S

Y R O M E M

R O S S E C O R P

I T L U

RESERVED

MSSD BANK 2 (MS SD 2)

RESERVED

MS SD B ANK 1 ( MS SD1 )

RESERVED

MS SD B ANK 0 (MS SD 0)

BANK 1(MS1)

BANK 0(MS0)

PROCESSOR ID 7

PROCESSOR ID 6

PROCESSOR ID 5

PROCESSOR ID 4

PROCESSOR ID 3

PROCESSOR ID 2

PROCESSOR ID 1

PROCESSOR ID 0

BROADCAST

RESERVED

INTERNAL MEMORY

0x8 0000 000

0x7 4000 000

0x7 0000 000

0x6 4000 000

0x6 0000 000

0x5 4000 000

0x5 0000 000

0 x4400 0000

0 x4000 0000

0x3 8000 000

0 x3000 0000

0x2C000000

0 x2800 0000

0 x2400 0000

0 x2000 0000

0x1C000000

0 x1800 0000

0 x1400 0000

0 x1000 0000

0X 0C00 0000

0x03FFFFFF

0 x0000 0000

Figure 2-1. ADSP-TS201 Memory Map

2-2 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

and indicates where the memory space defines the location of each element. The zones in the memory space are made up of the following regions.

• External memory bank space—the region for standard addressing of off-chip memory, including SDRAM, bank 0 (

MS0), bank 1

(MS1), and Host (MSH)

• External multiprocessor space—the on-chip memory of all other TigerSHARC processors connected in a multiprocessor system

• Internal address space—the region for standard internal addressing

The global memory map is shown in Figure 2-1.

In addition to the direct accesses (normal - one 32-bit word, long - two 32-bit words, and quad - four 32-bit words), several other efficient methods are available. These include Broadcast Write, Merged Distribution, and Broadcast Distribution. Broadcast Write is an external write to other DSPs in a multiprocessor cluster. Merged and Broadcast Distribution are internal access methods. For additional information on memory access methods, see “IALU” in the ADSP-TS201 TigerSHARC Processor Program- ming Reference.

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-3

Host Address Space

The host address space is the space defined for the host when it is accessed as a slave. When referring to this space, the pipelined or asynchronous protocol is used according to the host bits in the SYSCON register—for additional information on the SYSCON register see Figure 2-35 on

page 2-74 and Figure 2-36 on page 2-75. The backoff signal is also effec-

tive on this zone—see “Back Off (BOFF) Pin” on page 8-48. The host address is two gigawords and is divided into fields, as illustrated in

Table 2-1.

Table 2-1. Host Address Space

Bits Name Definition

ADDR30–0 Address Address in host range

ADDR31 Host Select Determines the type of address.

If ADDR31=1, the address is in host address space

External Memory Bank Space

This memory space corresponds to off-chip memory and memory-mapped I/O devices (SDRAM, I/O peripherals, and other standard memory devices).

Normal external accesses are split into banks. One set of banks is for SDRAM and is accessed using external memory select pins MSSD0, MSSD1,

MSSD2, and MSSD3; the access is executed in SDRAM protocol. Another set

of banks is identified by external memory select pins the access protocol is user-configurable as pipelined or slow device protocol, and the parameters are defined by the

SYSCON register value—see

section “External Bus Interface Register Groups” on page 2-72.

2-4 ADSP-TS201 TigerSHARC Processor Hardware Reference

MS0 and MS1, where

Memory and Registers

The external memory address is divided into fields, as illustrated in

Table 2-2.

Table 2-2. External Memory Bank Space

Bits Name Definition

ADDR25–0 Address Internal address space, as described in “Internal Address Space”

on page 2-7

ADDR30–26 MS/PRID Memory Select—select an external/multiprocessor memory

space:

01100 – Bank 0 (MS0 01110 – Bank 1 (MS1 10000 – SDRAM Bank 0 (MSSD0) 10001 – Reserved 10100 – SDRAM Bank 1 (MSSD1 10101 – Reserved 11000 – SDRAM Bank 2 (MSSD2) 11001 – Reserved 11100 – SDRAM Bank 3 (MSSD3 11101 – Reserved

ADDR31 Host Select Determine the type of address.

If ADDR31=0, the address can be in external, internal, or multiprocessor address space.

) )

)

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-5

Multiprocessor Space

The multiprocessing space maps the internal memory space of each TigerSHARC processor in the cluster into any other TigerSHARC processor. This allows one processor to easily write to and read from other processors in a multiprocessor system. Broadcast space allows write access to all TigerSHARC processors in the cluster. Each TigerSHARC processor in the cluster is identified by its ID. Valid processor ID values are 0 through 7.

The external multiprocessor address is divided into fields, as illustrated in

Table 2-3.

Table 2-3. Multiprocessor Space

Bits Name Definition

ADDR25–0 Address Internal address space, as described in “Internal Address Space”

on page 2-7

ADDR30–26 MS/PRID Memory Select—select an external/multiprocessor memory

space:

00011 – Multiprocessor Broadcast 00100 – Multiprocessor ID0 00101 – Multiprocessor ID1 00110 – Multiprocessor ID2 00111 – Multiprocessor ID3 01000 – Multiprocessor ID4 01001 – Multiprocessor ID5 01010 – Multiprocessor ID6 01011 – Multiprocessor ID7

ADDR31 Host Select Determine the type of address.

If ADDR31=0, the address can be in external, internal, or multiprocessor address space.

2-6 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

The TigerSHARC processor’s own internal space (including ters) can be accessed via the multiprocessing space (including broadcast space) for write transactions only.There are no interlocks. Because this is performed through the external bus it should only be used in special cases where data must pass through the TigerSHARC processor bus interface.

Ureg regis-

Internal Address Space

The internal address space corresponds to that processor’s own internal address space, Ureg registers. The internal address space is illustrated in

Figure 2-1 on page 2-2.

Internal space is the space for transactions within the TigerSHARC processor and access to this memory space is not reflected on the cluster bus. Internal address space is used to access the internal memory blocks, or any of the Universal registers (Ureg). Universal registers are internal registers that are mapped to the TigerSHARC processor memory map. Most software accessible registers are Ureg registers.

Access to Ureg registers as memory locations is only available through multiprocessing space. Internal access to registers cannot be memory mapped—in load/store instructions, for example, the address cannot point to a register through the internal space. The DMA also cannot access a register directly, although there is an exception—link receive DMA channels may write to other link transmit registers.

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-7

Universal (Ureg) Register Space

Frequently, this text refers to universal register groups and access techniques or restrictions that apply to particular groups. The processor’s memory-mapped, universal registers are grouped according to their relationship to the processor’s architecture. For example, data registers (XR31–0, YR31–0, or XYR31–0) for the compute blocks are in one register group, while data registers (J30–0 or K30–0) for the integer ALUs (J-IALU or K-IALU) are in another register group. Each register group corresponds to a range of memory addresses because all registers in these groups are memory mapped, universal registers.

The term universal (Ureg) register indicates several important features about the register. First, the register is memory-mapped, indicating that the register can be accessed by other processors in a multiprocessor system through the register’s address. Second, the register contents can be loaded, from memory, stored to memory, or transferred to or from other Ureg registers in the processor. Third, the register can be accessed as a single-, dual-, or quad-register.

Multiprocessor accesses to another processor’s Ureg registers use the memory addresses that appear in the register group tables as part of the address, but must also add the offset for a particular processor. (See the memory map in Figure 2-1 on page 2-2.) The The following code examples show multiprocessor accesses of another processor’s Ureg registers.

/* In the following multiprocessor register access example, one processor in a multiprocessor system transfers the contents of its XR1 register to processor P1’s XR0 register */

Some universal system registers (for example, sequencer register group 0x1A, DMA control/status register group 0x23, external bus interface register group 0x24, and JTAG register group 0x3D) are not accessible as dual- or quad-registers.

2-8 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

J0 = P1_OFFSET_LOC ;;

/* P1_OFFSET_LOC is 0x1400 0000; the location of processor P1 */ J1 = XR0_LOC ;;

/* XR0_LOC is 0x001E 0000; the location of register XR0 */ [J0 + J1] = XR1 ;;

/* transfers register XR1 data to register XR0 on proc. P1 */

For information on memory read and write instruction syntax, see the “IALU Load, Store, and Transfer (Data Addressing) Operations” section in Chapter 7, IALU, in the ADSP-TS201 TigerSHARC Processor Program- ming Reference.

using a multiprocessor access. Such an read access causes an illegal access exception. A processor may make a multiprocessor write access (such as a multiprocessor broadcast write) to its own Ureg registers. For more information on exceptions, see “Handling

Exceptions” on page 6-15.

Load, store, or transfer Ureg register accesses within a processor use the register’s name, not its memory-mapped address. The register names appear in the register group tables. A register load access copies data from the processor’s memory and places the data into the register. A register store access copies data from the register and places the data into the processor’s memory. A register transfer (or move) access copies data from one register to another. The following code examples show single-register load, store, and transfer accesses.

/* In the following single-register load, store, and transfer access examples, data is copied to and from single, 32-bit registers */ XR0 = 0x76543210 ;; /* loads XR0 with immediate 32-bit data */ XR4 = [J31 + 0x43] ;; /* loads XR0 from memory */ [J0 + J4] = YR0 ;; /* stores YR0 to memory */ XR7 = SQSTAT ;; /* transfers SQSTAT contents to XR7 */

A processor may not make a read access of its own Ureg registers

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-9

Universal (Ureg) Register Space

store, or transfer accesses on an instruction line—greatly increasing performance of routines that require loading values into many registers. For information on instruction parallelism, see the “Instruction Parallelism Rules” section in Chapter 1, Introduction, in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Unlike the single-register accesses in the previous example that use the registers name to access a single register, dual- and quad-register accesses within a processor use a modified form of the register’s name to access mul- tiple, adjacent registers that are located on dual- or quad-word address boundaries. The modification to the register’s name indicates a range of registers, rather than a single register. For example the dual-register name

If using legal instruction parallelism, there can be up to two load,

XR1:0 indicates register R1 and R0 in the X compute block, and the

quad-register name J31:28 indicates registers J31, J30, J29, and J28 in the J-IALU. Alignment to a dual- or quad-word address boundary refers to the register number (and address) of the lowest register in the group; dual-register boundaries end in multiples of two (for example, R1:0, R3:2, R27:26); quad-register boundaries end in multiples of four (for example, R3:0,

R7:4, R31:28). The following code examples show dual- and quad-register

load, store, and transfer accesses.

/* In the following dual- and quad-register load, store, and transfer access examples data is copied to and from dual (64-bit) and quad (128-bit) registers */ YR5:4 = L [J31 + 0x1ff0] ;; /* loads YR5:4 from memory */ XR3:0 = Q [K4 += K5] ;; /* loads XR3:0 from memory */ L [J0 + J2] = YR31:30 ;; /* stores YR31:30 to memory */ Q [K31 + K28] = YR7:4 ;; /* stores Y7:4 to memory */

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Memory and Registers

CACMADR0 = J1:0 ;; /* transfers J1:0 to CCAIR0:CACMD0 */ DCS0 = YR11:8 ;; /* transfers YR11:8 to DCS0 (DP, DY, DX, DI) */

For information on single-, dual-, and quad-register name instruction syntax, see the “Register File Registers” section in Chapter 2, Compute Block

Registers, in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Normally, a register load from memory or a register store to memory access occurs between one register and a memory word of the same size—a single-register load/store of a normal (32-bit) word, a dual-register load/store of a long (64-bit) word, or a quad-register load/store of a quad (128-bit) word. When one register is loaded/stored using a memory word of the same size, the operation is called a normal read or write access. To take advantage of single-instruction, multiple-data (SIMD) processing, the processor’s bus architecture also supports types of accesses in which the contents of one memory word can be loaded into two registers (broad- cast read access) and supports types of accesses in which multiple registers can be loaded/stored with different data using one memory word (merged read or write access). For information on access types and data placement, see the “Normal, Merged, and Broadcast Memory Accesses” section in Chapter 7, IALU, in the ADSP-TS201 TigerSHARC Processor Program- ming Reference.

Register groups and register quad relationships can have important influence on instruction parallelism. For information on instruction parallelism, see the “Instruction Parallelism Rules” section in Chapter 1, Introduction, in the ADSP-TS201 TigerSHARC Proces- sor Programming Reference.

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-11

Note that broadcast read accesses only occur between memory and registers within a processor, while multiprocessor broadcast write accesses only occur simultaneously across all processors in a multiprocessor system.

Universal (Ureg) Register Space

The register space is composed of 64 register groups with up to 32 registers in each group. Register groups are defined in the range 0x3F–0 (63–0), where groups 0x1F–0 are accessible by all transfer instructions (load immediate, move register, load and store), and groups 0x3F–0x20 are accessible only by move register instructions and direct accesses of other masters.

The register groups are:

• Compute block register file – groups 0x00–0x09

• IALU registers – groups 0x0C–0x0F

• Debug feature registers – groups 0x0A, 0x1B

• Program sequencer – group 0x1A

• Memory controller – groups 0x1E–0x1F

• DMA registers – groups 0x20 – 0x23

• External port control/status registers – group 0x24

• Link port registers – groups 0x25 – 0x27

• Interrupt controller – groups 0x38, 0x39, and 0x3A

• JTAG registers – group 0x3D

• AutoDMA registers – group 0x3F

• Others – Reserved. These registers must not be accessed by applica-

tions since they could cause unexpected behavior by the TigerSHARC processor.

There is a direct relationship between a Ureg register’s memory-mapped address and the register group in which the register resides. (See

Figure 2-2.) Because register groups have different access restrictions, it is

2-12 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

always important to know the group to which a register belongs. When in doubt, use the information in Figure 2-2 to determine the register group number.

Figure 2-2. Register Group Number Versus Register Address

It is also important to note from a whether the register resides in the processor core (internal Ureg registers) or in the SOC interface (SOC Ureg registers). (See Figure 2-1 on

page 2-2.) Because register groups in the SOC interface have different

access restrictions than core registers, it is important to know the where the register resides.

Some of the registers do not use all 32 bits. The unused bits are reserved. When writing to register with reserved bits, these bits must be written with to zero. When reading a register with reserved bits, the reserved bits may be of any value.

Ureg register’s memory-mapped address

4 3 2 1 05

9 8 7 6 516

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-13

Universal (Ureg) Register Space

Compute Block Register Groups

Each compute block register file is a 32-word register. There are two such register files, one in each of the compute blocks (X and Y). The register file is aliased in several groups, some of which are applicable for data transfer instructions only. Some groups point to compute block X and some to block Y; those that point to both compute blocks in parallel actually point to the same register. The X and Y registers are memory mapped Universal (Ureg) registers.

The Compute Block register types of accesses are listed with their memory mapped addresses in Table 2-4, Table 2-5, Table 2-6, Table 2-7, and

Table 2-8. Note that Ureg register file groups for alternative access are

only for load/store instruction—DAB, circular buffer. For more information about alternate access, see the ADSP-TS201 TigerSHARC Processor Programming Reference.

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Memory and Registers

Table 2-4. Compute Block X Register Group

Name Address Default Name Address Default

XR0 0x1E 0000 Undefined XR16 0x1E 0010 Undefined

XR1 0x1E 0001 Undefined XR17 0x1E 0011 Undefined

XR2 0x1E 0002 Undefined XR18 0x1E 0012 Undefined

XR3 0x1E 0003 Undefined XR19 0x1E 0013 Undefined

XR4 0x1E 0004 Undefined XR20 0x1E 0014 Undefined

XR5 0x1E 0005 Undefined XR21 0x1E 0015 Undefined

XR6 0x1E 0006 Undefined XR22 0x1E 0016 Undefined

XR7 0x1E 0007 Undefined XR23 0x1E 0017 Undefined

XR8 0x1E 0008 Undefined XR24 0x1E 0018 Undefined

XR9 0x1E 0009 Undefined XR25 0x1E 0019 Undefined

XR10 0x1E 000A Undefined XR26 0x1E 001A Undefined

XR11 0x1E 000B Undefined XR27 0x1E 001B Undefined

XR12 0x1E 000C Undefined XR28 0x1E 001C Undefined

XR13 0x1E 000D Undefined XR29 0x1E 001D Undefined

XR14 0x1E 000E Undefined XR30 0x1E 001E Undefined

XR15 0x1E 000F Undefined XR31 0x1E 001F Undefined

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-15

Universal (Ureg) Register Space

Table 2-5. Compute Block Y Register Group

Name Address Default Name Address Default

YR0 0x1E 0040 Undefined YR16 0x1E 0050 Undefined

YR1 0x1E 0041 Undefined YR17 0x1E 0051 Undefined

YR2 0x1E 0042 Undefined YR18 0x1E 0052 Undefined

YR3 0x1E 0043 Undefined YR19 0x1E 0053 Undefined

YR4 0x1E 0044 Undefined YR20 0x1E 0054 Undefined

YR5 0x1E 0045 Undefined YR21 0x1E 0055 Undefined

YR6 0x1E 0046 Undefined YR22 0x1E 0056 Undefined

YR7 0x1E 0047 Undefined YR23 0x1E 0057 Undefined

YR8 0x1E 0048 Undefined YR24 0x1E 0058 Undefined

YR9 0x1E 0049 Undefined YR25 0x1E 0059 Undefined

YR10 0x1E 004A Undefined YR26 0x1E 005A Undefined

YR11 0x1E 004B Undefined YR27 0x1E 005B Undefined

YR12 0x1E 004C Undefined YR28 0x1E 005C Undefined

YR13 0x1E 004D Undefined YR29 0x1E 005D Undefined

YR14 0x1E 004E Undefined YR30 0x1E 005E Undefined

YR15 0x1E 004F Undefined YR31 0x1E 005F Undefined

2-16 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

Table 2-6. Compute Block XY Merged Register Group

Name Address Default Name Address Default

XYR0 0x1E 0080 Undefined XYR16 0x1E 0090 Undefined

XYR1 0x1E 0081 Undefined XYR17 0x1E 0091 Undefined

XYR2 0x1E 0082 Undefined XYR18 0x1E 0092 Undefined

XYR3 0x1E 0083 Undefined XYR19 0x1E 0093 Undefined

XYR4 0x1E 0084 Undefined XYR20 0x1E 0094 Undefined

XYR5 0x1E 0085 Undefined XYR21 0x1E 0095 Undefined

XYR6 0x1E 0086 Undefined XYR22 0x1E 0096 Undefined

XYR7 0x1E 0087 Undefined XYR23 0x1E 0097 Undefined

XYR8 0x1E 0088 Undefined XYR24 0x1E 0098 Undefined

XYR9 0x1E 0089 Undefined XYR25 0x1E 0099 Undefined

XYR10 0x1E 008A Undefined XYR26 0x1E 009A Undefined

XYR11 0x1E 008B Undefined XYR27 0x1E 009B Undefined

XYR12 0x1E 008C Undefined XYR28 0x1E 009C Undefined

XYR13 0x1E 008D Undefined XYR29 0x1E 009D Undefined

XYR14 0x1E 008E Undefined XYR30 0x1E 009E Undefined

XYR15 0x1E 008F Undefined XYR31 0x1E 009F Undefined

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-17

Universal (Ureg) Register Space

Table 2-7. Compute Block YX Merged Register Group

Name Address Default Name Address Default

YXR0 0x1E 00C0 Undefined YXR16 0x1E 00D0 Undefined

YXR1 0x1E 00C1 Undefined YXR17 0x1E 00D1 Undefined

YXR2 0x1E 00C2 Undefined YXR18 0x1E 00D2 Undefined

YXR3 0x1E 00C3 Undefined YXR19 0x1E 00D3 Undefined

YXR4 0x1E 00C4 Undefined YXR20 0x1E 00D4 Undefined

YXR5 0x1E 00C5 Undefined YXR21 0x1E 00D5 Undefined

YXR6 0x1E 00C6 Undefined YXR22 0x1E 00D6 Undefined

YXR7 0x1E 00C7 Undefined YXR23 0x1E 00D7 Undefined

YXR8 0x1E 00C8 Undefined YXR24 0x1E 00D8 Undefined

YXR9 0x1E 00C9 Undefined YXR25 0x1E 00D9 Undefined

YXR10 0x1E 00CA Undefined YXR26 0x1E 00DA Undefined

YXR11 0x1E 00CB Undefined YXR27 0x1E 00DB Undefined

YXR12 0x1E 00CC Undefined YXR28 0x1E 00DC Undefined

YXR13 0x1E 00CD Undefined YXR29 0x1E 00DD Undefined

YXR14 0x1E 00CE Undefined YXR30 0x1E 00DE Undefined

YXR15 0x1E 00CF Undefined YXR31 0x1E 00DF Undefined

2-18 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

Table 2-8. Compute Block XY Broadcast Register Group

Name Address Default Name Address Default

XYR0 0x1E 0100 Undefined XYR16 0x1E 0110 Undefined

XYR1 0x1E 0101 Undefined XYR17 0x1E 0111 Undefined

XYR2 0x1E 0102 Undefined XYR18 0x1E 0112 Undefined

XYR3 0x1E 0103 Undefined XYR19 0x1E 0113 Undefined

XYR4 0x1E 0104 Undefined XYR20 0x1E 0114 Undefined

XYR5 0x1E 0105 Undefined XYR21 0x1E 0115 Undefined

XYR6 0x1E 0106 Undefined XYR22 0x1E 0116 Undefined

XYR7 0x1E 0107 Undefined XYR23 0x1E 0117 Undefined

XYR8 0x1E 0108 Undefined XYR24 0x1E 0118 Undefined

XYR9 0x1E 0109 Undefined XYR25 0x1E 0119 Undefined

XYR10 0x1E 010A Undefined XYR26 0x1E 011A Undefined

XYR11 0x1E 010B Undefined XYR27 0x1E 011B Undefined

XYR12 0x1E 010C Undefined XYR28 0x1E 011C Undefined

XYR13 0x1E 010D Undefined XYR29 0x1E 011D Undefined

XYR14 0x1E 010E Undefined XYR30 0x1E 011E Undefined

XYR15 0x1E 010F Undefined XYR31 0x1E 011F Undefined

Unmapped Compute Block Registers

There are several registers in the compute block units that are not Universal registers (

Ureg registers are accessed. These registers are accessed by regular

that

Ureg registers), in that they are not accessed in the same way

compute block instructions that transfer the data between the unmapped registers and the general-purpose compute block

Ureg registers.

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-19

Universal (Ureg) Register Space

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00000000

MIS—Multiplier floating-pt. invalid op., sticky MOS—Multiplier fixed-pt. overflow, sticky MVS—Multiplier floating-pt. overflow, sticky MUS—Multiplier floating-pt, underflow, sticky AIS—ALU floating-pt. invalid op., sticky AOS—ALU fixed-pt. overflow, sticky AVS—ALU floating-pt. overflow, sticky AUS—ALU floating-pt. underflow,sticky

Reserved

IVEN—Exception enable on invalid floating-pt. OEN—Exception enable on overflow status UEN—Exception enable on underflow status

Reserved

00000 0 0 0

Figure 2-3. XSTAT/YSTAT (Upper) Register Bit Descriptions

Compute Block Status (XSTAT/YSTAT) Registers

The

XSTAT and YSTAT registers are 32-bit compute block status registers

that record the state of the compute block status flags. Every flag is updated when an instruction belonging to its computation unit is completed. The X/YSTAT registers (reset value = 0x0000 0000) appear in

Figure 2-3 and Figure 2-4. For more information on using the X/YSTAT

registers, see the “Compute Block Registers” chapter in the ADSP-TS201 TigerSHARC Processor Programming Reference.

ALU Registers

The Parallel Results registers (

PR0 and PR1) are two 32-bit registers used

for sideways sum instructions. For more information regarding the PRx registers, see “ALU” in the ADSP-TS201 TigerSHARC Processor Program- ming Reference.

2-20 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

1514131211109876543210

0000000000000000

AZ—ALU zero AN—ALU negative AV—ALU overflow AC—ALU carry MZ—Multiplier zero MN—Multiplier negative MV—Multiplier overflow MU—Multiplier underflow SZ—Shifter zero SN—Shifter negative BF—Shifter Block floating-point flags AI—ALU floating-point invalid operation MI—Multiplier floating-point invalid operation TROV—CLU trellis overflow TRSOV—CLU trellis overflow, sticky

Figure 2-4. XSTAT/YSTAT (Lower) Register Bit Descriptions

Multiplier Registers

The Multiplier Results registers (

MR3–0 and MR4) are used as accumulators

for the different types of fixed-point Multiply-Accumulate instructions. For more information regarding the MRx registers, see “Multiplier” in the ADSP-TS201 TigerSHARC Processor Programming Reference. These registers are accessed by different multiplier instructions.

Shifter Registers

The Bit FIFO Overflow register (BFOTMP) is a 64-bit register used in the

PUTBITS instruction. For more information regarding the BFOTMP register,

see the PUTBITS instruction in the ADSP-TS201 TigerSHARC Processor Programming Reference.

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-21

Universal (Ureg) Register Space

Communications Logic Unit (CLU) Registers

The CLU instructions use Trellis (

TR31–0) data registers, Trellis history

(THR3–0) registers, and/or the Communication Control (CMCTL) register. Each register is 32 bits wide. For more information regarding these registers, see the “CLU” chapter in the ADSP-TS201 TigerSHARC Processor Programming Reference.

IALU Register Groups

Each IALU has two Ureg groups. The first group is the general-purpose register file, which includes 32 normal-word registers each. The second group is the circular buffer register file which is used to specify parameters for circular buffering. The IALU register groups are listed in Table 2-9,

Table 2-10, Table 2-11, and Table 2-12.

The circular buffer register files contain these registers:

• 3–0 circular buffer base registers JB3–0 and KB3–0

• 7–4 circular buffer length registers JL3–0 and KL3–0

• 31–8 Reserved

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Memory and Registers

Table 2-9. J-IALU Register Group

Name Address Default Name Address Default

J0 0x1E 0180 Undefined J16 0x1E 0190 Undefined

J1 0x1E 0181 Undefined J17 0x1E 0191 Undefined

J2 0x1E 0182 Undefined J18 0x1E 0192 Undefined

J3 0x1E 0183 Undefined J19 0x1E 0193 Undefined

J4 0x1E 0184 Undefined J20 0x1E 0194 Undefined

J5 0x1E 0185 Undefined J21 0x1E 0195 Undefined

J6 0x1E 0186 Undefined J22 0x1E 0196 Undefined

J7 0x1E 0187 Undefined J23 0x1E 0197 Undefined

J8 0x1E 0188 Undefined J24 0x1E 0198 Undefined

J9 0x1E 0189 Undefined J25 0x1E 0199 Undefined

J10 0x1E 018A Undefined J26 0x1E 019A Undefined

J11 0x1E 018B Undefined J27 0x1E 019B Undefined

J12 0x1E 018C Undefined J28 0x1E 019C Undefined

J13 0x1E 018D Undefined J29 0x1E 019D Undefined

J14 0x1E 018E Undefined J30 0x1E 019E Undefined

J15 0x1E 018F Undefined J31 0x1E 019F Undefined

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-23

Universal (Ureg) Register Space

Table 2-10. K-IALU Register Group

Name Address Default Name Address Default

K0 0x1E 01A0 Undefined K16 0x1E 01B0 Undefined

K1 0x1E 01A1 Undefined K17 0x1E 01B1 Undefined

K2 0x1E 01A2 Undefined K18 0x1E 01B2 Undefined

K3 0x1E 01A3 Undefined K19 0x1E 01B3 Undefined

K4 0x1E 01A4 Undefined K20 0x1E 01B4 Undefined

K5 0x1E 01A5 Undefined K21 0x1E 01B5 Undefined

K6 0x1E 01A6 Undefined K22 0x1E 01B6 Undefined

K7 0x1E 01A7 Undefined K23 0x1E 01B7 Undefined

K8 0x1E 01A8 Undefined K24 0x1E 01B8 Undefined

K9 0x1E 01A9 Undefined K25 0x1E 01B9 Undefined

K10 0x1E 01AA Undefined K26 0x1E 01BA Undefined

K11 0x1E 01AB Undefined K27 0x1E 01BB Undefined

K12 0x1E 01AC Undefined K28 0x1E 01BC Undefined

K13 0x1E 01AD Undefined K29 0x1E 01BD Undefined

K14 0x1E 01AE Undefined K30 0x1E 01BE Undefined

K15 0x1E 01AF Undefined K31 0x1E 01BF Undefined

2-24 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

Table 2-11. J-IALU Circular Buffer Register Group

Name Address Default

JB0 0x1E 01C0 Undefined

JB1 0x1E 01C1 Undefined

JB2 0x1E 01C2 Undefined

JB3 0x1E 01C3 Undefined

JL0 0x1E 01C4 Undefined

JL1 0x1E 01C5 Undefined

JL2 0x1E 01C6 Undefined

JL3 0x1E 01C7 Undefined

Reserved 0x1E 01C8–

0x1E 01DF

N/A

Table 2-12. K-IALU Circular Buffer Register Group

Name Address Default

KB0 0x1E 01E0 Undefined

KB1 0x1E 01E1 Undefined

KB2 0x1E 01E2 Undefined

KB3 0x1E 01E3 Undefined

KL0 0x1E 01E4 Undefined

KL1 0x1E 01E5 Undefined

KL2 0x1E 01E6 Undefined

KL3 0x1E 01E7 Undefined

Reserved 0x1E 01E8–

0x1E 01FF

N/A

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-25

Universal (Ureg) Register Space

IALU Status (J31/JSTAT and K31/KSTAT) Registers

The

JSTAT (for the J-IALU) and KSTAT (for the K-IALU) status registers

records the state of the carry flags and is updated as a result of various IALU instructions. When being written to, the JSTAT register can be referred to as J31. When used as an operand in an IALU arithmetic, logical, or function operation—J31 is treated as zero. The J31/JSTAT (K31/KSTAT ) registers (reset value = 0x0000 0000) appear in Figure 2-5. For information on using the J31/JSTAT (K31/KSTAT ) registers, see the “IALU” chapter of the ADSP-TS201 TigerSHARC Processor Programming Reference.

1514131211109876543210

0 0 0 0 0 0 0 0 0 0 0 00000

JZ J-IALU zero JN J-IALU negative JV J-IALU overflow JC J-IALU carry

Reserved

Figure 2-5. JSTAT/KSTAT (Lower Half) Register Bit Descriptions

1 Bits 31–16 (not shown) are reserved (=0).

2-26 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

Sequencer Register Groups

This 32-bit register group is dedicated to sequencer registers, interrupt control, and status registers. See Table 2-13. All sequencer registers are accessible by single-word access only. For more information regarding the sequencer registers, see “Program Sequencer” in the ADSP-TS201 TigerSHARC Processor Programming Reference.

Table 2-13. Sequencer Register Group

Name Description Address Default

CJMP Computed jump address

Reserved N/A 0x1E 0341 N/A

RETI Return from interrupt address 0x1E 0342 Undefined

RETIB RETI alias, for interrupt nesting

RETS Return from subroutine address

DBGE Return from emulation address

0x1E 0340 Undefined

0x1E 0343 Undefined

0x1E 0344 Undefined

0x1E 0345 Undefined

Reserved N/A 0x1E 0346–0x1E 0347 N/A

LC0 Loop counter #0 0x1E 0348 Undefined

LC1 Loop counter #1 0x1E 0349 Undefined

Reserved N/A 0x1E 034A–0x1E 034F N/A

IVSW Software exception 0x1E 0350 Undefined

Reserved N/A 0x1E 0351–0x1E 0353 N/A

FLAGREG Flag control register 0x1E 0354 0x0000 0000

FLAGREGST Flag register set 0x1E 0355 Undefined

FLAGREGCL Flag register clear 0x1E 0356 Undefined

Reserved N/A 0x1E 0357 N/A

SQCTL Sequencer control register 0x1E 0358 0x0000 0004

SQCTLST Sequencer control register set bits 0x1E 0359 Undefined

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-27

Universal (Ureg) Register Space

Table 2-13. Sequencer Register Group (Cont’d)

Name Description Address Default

SQCTLCL Sequencer control register clear bits 0x1E 035A Undefined

SQSTAT Sequencer status register; read only 0x1E 035B 0x0000 FF04

SFREG Static condition flag register 0x1E 035C 0x0000 0000

Reserved N/A 0x1E 035D–0x1E 035F N/A

CJUMP Instruction in the ADSP-TS201 TigerSHARC Processor Programming Reference.

1 See 2 See “Interrupts” on page 6-1 3 See “Handling Exceptions” on page 6-15.

Flag Control (FLAGREG) Register

The

FLAGREG register is a 32-bit register that controls flag pin direction

(input or output) and provides output value controls (1 or 0) for output flag pins. The FLAGREG register (reset value = 0x0000 0000) appears in

Figure 2-6. For information on using the FLAGREG register, see the “Pro-

gram Sequencer” chapter of the ADSP-TS201 TigerSHARC Processor Programming Reference.

1514131211109876543210

0 0 0 0 0 0 0 000000000

FLAGx_EN – Enables a flag pin as either

1=output or 0=input; bit 0-FLAG0, bit 1FLAG1, bit 2-FLAG2, bit 3-FLAG3

FLAGx_OUT – Selects output value of flag

pins if pin is enabled as an output by its FLAGx_EN bit; bit 4-FLAG0, bit 5-FLAG1, bit 6- FLAG2, bit 7-FLAG3

Reserved

Figure 2-6. FLAGREG (Lower) Register Bit Descriptions

1 Bits 31–16 (not shown) are reserved (=0).

2-28 ADSP-TS201 TigerSHARC Processor Hardware Reference

Sequencer Control (SQCTL) Register

Memory and Registers

The sequencer is controlled and configured by writing to the

SQCTL regis-

ter. The SQCTL register (reset value = 0x0000 0004) appears in Figure 2-7. For information on using the SQCTL register, see the “Program Sequencer” chapter of the ADSP-TS201 TigerSHARC Processor Programming Reference.

1514131211109876543210

0 0 0 000000 0 0 0010 0

Reserved GIE – Global interrupt enable, mask;

1=unmask, 0=mask

SW – Exception (software interrupt), mask;

1=unmask, 0=mask

Reserved

DBGEN – Debug enable; 1=disable, 0=enable NMOD – Normal mode; 0=User, 1=Supervisor TRCBEN – Trace buffer enable;

0=TRCBPTR and TRCBx retain value, 1=TRCBPTR cleared and TRCBx starts monitoring jumps (normal operation)

TRCBEXEN – Trace buffer exception enable;

0=disable, 1=enable

Reserved

Figure 2-7. SQCTL (Lower) Register Bit Descriptions

1 Bits 31–16 (not shown) are reserved (=0). 2 There is a five cycle stall after any write to the SQCTL register.

1,2

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-29

Universal (Ureg) Register Space

Static Flags (SFREG) Register

Static flags are used as static copies of conditions. When the programmer wishes to keep a condition value after another instruction changes its value, it can be copied into the

SFREG and used later as a condition. All

static condition flags are grouped into the SFREG register. The SFREG register (reset value = 0x0000 0000) appears in Figure 2-8. For information on using the SFREG register, see the “Program Sequencer” chapter of the ADSP-TS201 TigerSHARC Processor Programming Reference.

1514131211109876543210

0 0 0 0 0 0 0 0 0 0000000

GSCF0 – IALU/global static flag 0 GSCF1 – IALU/global static flag 1 XSCF0 – X compute block static

flag 0

XSCF1 – X compute block static

flag 1

YSCF0 – Y compute block static

flag 0

YSCF1 – Y compute block static

flag 1

Reserved

Figure 2-8. SFREG (Lower) Register Bit Descriptions

1 Bits 31–16 (not shown) are reserved (=0).

2-30 ADSP-TS201 TigerSHARC Processor Hardware Reference

Memory and Registers

Sequencer Control Set Bits (SQCTLST) Register

The

SQCTLST bit is an alias used to write to SQCTL. When writing to this

address, the data written into SQCTL is the OR of the old register value and the new data written into SQCTLST. A ‘1’ in any bit of the written data sets the corresponding bit in SQCTL, while a ‘0’ in written data does not change the bit value.

Sequencer Control Clear Bits (SQCTLCL) Register

The SQCTLCL bit is an alias used to write to SQCTL. When writing to this address, the data written into SQCTL is the AND of the old register value and the new data written into SQCTLCL. This way a ‘0’ in any bit of the written data clears the corresponding bit in SQCTL, while a ‘1’ in written data does not change the bit value.

Sequencer Status (SQSTAT) Register

This is a read-only register that holds information about the current status of the sequencer. The SQSTAT register (reset value = 0x0000 FF04) appears in Figure 2-9 and Figure 2-10. For information on using the SQSTAT register, see the “Program Sequencer” chapter of the ADSP-TS201 TigerSHARC Processor Programming Reference.

ADSP-TS201 TigerSHARC Processor Hardware Reference 2-31

Universal (Ureg) Register Space

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 0000 00000000000

Reserved BTBLK – BTB lock; 1=lock (every new entry

written to BTB is locked), 0=unlocked

BTBEN – BTB enable; 1=enable, 0=disable Reserved BTBMOD – Indicates BTB mode;

00=BTB disabled 01=BTB enabled 10=reserved 11=BTB enabled, locking on

Reserved

EMUL – Emulation interrupt, status SW – Exception (software interrupt), status GIE – Global Interrupt Enable, nest FLGx – Indicates input value of flag pins if pin

is enabled as an input by its FLAGx_EN bit; bit 16-FLAG0, bit 17-FLAG1, bit 18-FLAG2, bit 19-FLAG3

Figure 2-9. SQSTAT (Upper) Register Bit Descriptions

2-32 ADSP-TS201 TigerSHARC Processor Hardware Reference

Datasheet ADSP-TS201 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

PREFACE

PROCESSOR ARCHITECTURE

MEMORY AND REGISTERS

SOC INTERFACE

TIMERS

FLAGS

INTERRUPTS

DIRECT MEMORY ACCESS

LINK PORTS

SYSTEM DESIGN

INDEX

PREFACE

Purpose of This Manual

Intended Audience

Manual Contents

What’s New in This Manual

Technical or Customer Support

Supported Processors

Product Information

MyAnalog.com

Processor Product Information

Related Documents

Online Technical Documentation

Accessing Documentation From VisualDSP++

Accessing Documentation From Windows

Accessing Documentation From the Web

Printed Manuals

VisualDSP++ Documentation Set

Hardware Tools Manuals

Processor Manuals

Data Sheets

Conventions

1 PROCESSOR ARCHITECTURE

Processor Core

Compute Blocks

Arithmetic Logic Unit (ALU)

Communications Logic Unit (CLU)

Multiply Accumulator (Multiplier)

Bit Wise Barrel Shifter (Shifter)

Integer Arithmetic Logic Unit (IALU)

Program Sequencer

Processor Core Controls

Clock Domains

Operation Modes

User Mode

Supervisor Mode

Emulator Mode

Memory, Registers, and Buses

Boot Modes

Internal Buses

Internal Registers

SOC Interface

Timers

Flags

Interrupts

Direct Memory Access

External (Address and Data) Port

External Bus and Host Interface

External Memory

Multiprocessing

Host Interface

Link Ports

JTAG Port and Debug Interface

Programming Information

2 MEMORY AND REGISTERS

Host Address Space

External Memory Bank Space

Multiprocessor Space

Internal Address Space

Universal (Ureg) Register Space

Compute Block Register Groups

Unmapped Compute Block Registers

IALU Register Groups

IALU Status (J31/JSTAT and K31/KSTAT) Registers

Sequencer Register Groups