Datasheet ADSP-BF561 Datasheet (ANALOG DEVICES)

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ADSP-BF561 EZ-KIT Lite

Evaluation System Manual

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 2.0, January 2005

Part Number

82-000811-01

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Printed in the USA.

Limited Warranty

The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, VisualDSP++, the VisualDSP++ logo, Blackfin, CROSSCORE, the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

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Regulatory Compliance

The ADSP-BF561 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark.

The ADSP-BF561 EZ-KIT Lite evaluation system has been appended to

Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file.

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.

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PREFACE

Purpose of This Manual ................................................................. xii

Intended Audience ........................................................................ xiii

Manual Contents .......................................................................... xiii

What’s New in This Manual ........................................................... xiv

Technical or Customer Support ...................................................... xiv

Supported Processors ....................................................................... xv

Product Information ....................................................................... xv

MyAnalog.com .......................................................................... xv

Processor Product Information .................................................. xvi

Related Documents .................................................................. xvi

Online Technical Documentation ........................................... xviii

Accessing Documentation From VisualDSP++ .................... xviii

Accessing Documentation From Windows ............................ xix

Accessing Documentation From Web ................................... xix

Printed Manuals ....................................................................... xix

VisualDSP++ Documentation Set .......................................... xx

Hardware Tools Manuals ....................................................... xx

Processor Manuals ................................................................. xx

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CONTENTS

Data Sheets .......................................................................... xx

Notation Conventions ................................................................... xxi

USING EZ-KIT LITE

Package Contents ......................................................................... 1-2

Default Configuration .................................................................. 1-3

Installation and Session Startup ..................................................... 1-5

Evaluation License Restrictions ..................................................... 1-6

External Memory .......................................................................... 1-6

LEDs and Push Buttons ................................................................ 1-9

Audio Interface ........................................................................... 1-10

Video Interface ........................................................................... 1-11

Example Programs ...................................................................... 1-12

Flash Programmer Utility ............................................................ 1-12

Background Telemetry Channel .................................................. 1-13

VisualDSP++ Interface ................................................................ 1-13

Target Options ...................................................................... 1-14

Reset Options ................................................................... 1-14

On Emulator Exit ............................................................. 1-14

XML File ......................................................................... 1-15

Other Options .................................................................. 1-15

Restricted Software Breakpoints ............................................. 1-17

EZ-KIT LITE HARDWARE REFERENCE

System Architecture ...................................................................... 2-2

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CONTENTS

External Bus Interface Unit ...................................................... 2-3

SPORT0 Audio Interface ......................................................... 2-3

SPI Interface ........................................................................... 2-3

Programmable Flags ................................................................. 2-4

PPI Interfaces .......................................................................... 2-6

Video Output (PPI1) .......................................................... 2-7

Video Input (PPI0) ............................................................. 2-8

UART Port .............................................................................. 2-8

Expansion Interface ................................................................. 2-8

JTAG Emulation Port .............................................................. 2-9

Jumper and DIP Switch Settings .................................................. 2-10

Video Configuration Switch (SW2) ....................................... 2-10

Boot Mode Switch (SW3) ...................................................... 2-11

Push Button Enable Switch (SW4) ......................................... 2-12

PPI Clock Select Switch (SW5) .............................................. 2-13

Test DIP Switches (SW10 and SW11) .................................... 2-13

LEDs and Push Buttons .............................................................. 2-14

Reset Push Button (SW1) ...................................................... 2-14

Programmable Flag Push Buttons (SW9–6) ............................ 2-15

Power LED (J7) ..................................................................... 2-15

Reset LEDs (LED2 and LED3) .............................................. 2-15

USB Monitor LED (LED4) ................................................... 2-16

User LEDs (LED12–5, LED20–13) ....................................... 2-16

Connectors ................................................................................. 2-17

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CONTENTS

Expansion Interface (J3–1) .................................................... 2-17

Audio (J4 and J5) .................................................................. 2-18

Video (J6) ............................................................................. 2-18

Power (J7) ............................................................................ 2-18

USB (J8) .............................................................................. 2-19

RS232 (P2) ........................................................................... 2-20

SPORT0 (P3) ....................................................................... 2-20

JTAG (P4) ............................................................................ 2-20

BILL OF MATERIALS

INDEX

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PREFACE

Thank you for purchasing the ADSP-BF561 EZ-KIT Lite®, Analog Devices, Inc. evaluation system for Blackfin

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics towards delivering signal processing performance in a microprocessor-like environment.

The evaluation board is designed to be used in conjunction with the VisualDSP++ ADSP-BF561 Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code development and debug, such as:

development environment to test the capabilities of the

• Create, compile, assemble, and link application programs written in C++, C and ADSP-BF561 assembly

• Load, run, step, halt, and set breakpoints in application program

• Read and write data and program memory

• Read and write core and peripheral registers

processors.

• Plot memory

Access to the ADSP-BF561 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF561 processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster

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communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to

http://www.analog.com/dsp/tools/.

ADSP-BF561 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.

The board features:

The ADSP-BF561 EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires:

• VisualDSP++ allows a connection to the ADSP-BF561

EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.

• The linker restricts a users program to 41 KB of internal

memory for code space with no restrictions for data space.

• Analog Devices ADSP-BF561 processor

D 256-pin Mini-BGA package D 30 MHz CLKIN oscillator

• Synchronous Dynamic Random Access Memory (SDRAM)

D 64 MB (16M x 16 bits x 2 chips)

• Flash Memory

D 8 MB (4M x 16 bits)

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• Analog Audio Interface

D AD1836 A – Analog Devices 96 kHz audio codec D 4 input RCA phono jacks (2 Stereo Channels) D 6 output RCA phono jacks (3 Stereo Channels)

• Analog Video Interface

D ADV7183A video decoder w/ 3 input RCA phono jacks D ADV7179 video encoder w/ 3 output RCA phono jacks

• Universal Asynchronous Receiver/Transmitter (UART)

D ADM3202 RS-232 line driver/receiver D DB9 male connector

•LEDs

D 20 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),

16 general purpose (amber), and 1 USB monitor (amber)

Preface

• Push Buttons

D 5 push buttons with debounce logic: 1 reset,

4 programmable flags

• Expansion Interface

D PPI0, PPI1, SPI, EBIU, Timers11-0, UART,

Programmable Flags,

SPORT0, SPORT1

• Other Features

D JTAG ICE 14-pin header

The EZ-KIT Lite board holds 8 MB of flash memory, which can be used to store user-specific boot code, allowing the board to run as a stand-alone unit. The board also holds 512-Mb SDRAM, which can be used at runtime. For more information see “External Memory” on page 1-6.

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Purpose of This Manual

SPORT0 interfaces with the AD1836A audio codec, allowing you to create

audio signal processing applications.

SPORT0 also attaches to an off-board

connector to allow communication with other serial devices. For information about

SPORT0, see “SPORT0 Audio Interface” on page 2-3.

The Parallel Peripheral Interfaces (PPIs) of the processor connect to both a video encoder and video decoder, allowing you to create video signal processing applications. For information on how the board utilizes the processor’s PPIs, see “PPI Interfaces” on page 2-6.

The UART of the processor connects to an RS232 Line Driver and a male connector, allowing you to interface with a PC or other serial device. For information about the UART, see “UART Port” on page 2-8.

Additionally, the EZ-KIT Lite board provides access to most of the processor’s peripheral ports. Access is provided in the form of a three-connector expansion interface. For information about the expansion interface, see “Expansion Interface” on page 2-8.

Purpose of This Manual

The ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes the operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF561 EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs.

The product software installation is detailed in the VisualDSP++ Installa- tion Quick Reference Card.

DB9

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Intended Audience

The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts (such as the ADSP-BF561 Blackfin Processor Hardware Reference and Blackfin Processor Instruction Set Reference) that describe your target architecture.

Programmers who are unfamiliar with VisualDSP++ should refer to the VisualDSP++ online Help and user’s or getting started guides. For the locations of these documents, see “Related Documents”.

Manual Contents

Preface

The manual consists of:

• Chapter 1, “Using EZ-KIT Lite” on page 1-1 Describes the EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map

• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1 Provides information on the EZ-KIT Lite hardware components.

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What’s New in This Manual

• Appendix A, “Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board.

• Appendix B, “Schematics” on page B-1 Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design.

This appendix is not part of the online Help. The online Help viewers should go to the PDF version of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual located in the

Manuals

natively, the schematics can be found on the Analog Devices Web site,

folder on the installation CD to see the schematics. Alter-

www.analog.com/processors.

Docs\EZ-KIT Lite

What’s New in This Manual

This revision of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides an updated listing of related documents and updated licensing information.

Technical or Customer Support

You can reach DSP Tools Support in the following ways.

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

dsptools.support@analog.com

• E-mail processor questions to

dsp.support@analog.com

• Phone questions to 1-800-ANALOGD

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• Contact your Analog Devices, Inc. local sales office or authorized distributor

• Send questions by mail to:

Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

Supported Processors

This EZ-KIT Lite evaluation system supports the Analog Devices ADSP-BF561 Blackfin embedded processors.

Preface

Product Information

You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at mation about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual xv

www.analog.com. Our Web site provides infor-

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Product Information

Registration:

Visit

www.myanalog.com to sign up. Click Register to use MyAnalog.com.

Registration takes about five minutes and serves as means for you to select the information you want to receive.

If you are already a registered user, just log on. Your user name is your e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product announcements.

You may also obtain additional information about Analog Devices and its products in any of the following ways.

• E-mail questions or requests for information to

dsp.support@analog.com

• Fax questions or requests for information to

1-781-461-3010 (North America) +49 (89) 76 903-557 (Europe)

• Access the FTP Web site at

ftp ftp.analog.com or ftp 137.71.23.21 ftp://ftp.analog.com

Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary

Docs folder on the VisualDSP++ installation CD.

Each documentation file type is described as follows.

File Description

.CHM Help system files and manuals in Help format

.PDF files of most manuals are provided in the

.HTM or .HTML

.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the Internet Explorer 4.0 (or higher).

Viewing and printing the Reader (4.0 or higher).

.PDF files requires a PDF reader, such as Adobe Acrobat

.HTML files requires a browser, such as

If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows

Explorer, or the Analog Devices

Web site.

Accessing Documentation From VisualDSP++

To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP++ documentation via the Start menu.

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Preface

To view ADSP-BF561 EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help window.

Accessing Documentation From Windows

In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documentation from Windows.

Help system files (.

CHM) are located in the Help folder, and .PDF files are

located in the Docs folder of your VisualDSP++ installation CD-ROM. The

Docs folder also contains the Dinkum Abridged C++ library and the

FlexLM network license manager software documentation.

Your software installation kit includes online Help as part of the Win-

dows

interface. These help files provide information about VisualDSP++

and the ADSP-BF561 EZ-KIT Lite evaluation system.

Accessing Documentation From Web

Download manuals at the following Web site:

http://www.analog.com/processors/resources/technicalLibrary/manuals

Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files.

Printed Manuals

For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.

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Product Information

VisualDSP++ Documentation Set

To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit.

If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto

http://www.analog.com/salesdir/continent.asp.

Hardware Tools Manuals

To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual.

Processor Manuals

Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual.

Data Sheets

All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site.

To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.

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Notation Conventions

Text conventions used in this manual are identified and described as follows.

Example Description

Preface

Close command (File menu)

{this | that} Alternative required items in syntax descriptions appear within curly

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

[this,…] Optional item lists in syntax descriptions appear within brackets

.SECTION Commands, directives, keywords, and feature names are in text with

filename Non-keyword placeholders appear in text with italic style format.

Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).

brackets and separated by vertical bars; read the example as

that. One or the other is required.

rated by vertical bars; read the example as an optional

delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of

letter gothic font.

Note: For correct operation, ... A Note provides supplementary information on a related topic. In the

online version of this book, the word Note appears instead of this

symbol.

Caution: Incorrect device operation may result if ... Caution: Device damage may result if ...

A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.

this.

this or

this or that.

Warn in g: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product

[

that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Wa rn in g appears instead of this symbol.

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Notation Conventions

Additional conventions, which apply only to specific chapters, may appear throughout this document.

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1 USING EZ-KIT LITE

This chapter provides specific information to assist you with development of programs for the ADSP-BF561 EZ-KIT Lite evaluation system.

The information appears in the following sections.

• “Package Contents” on page 1-2 Lists the items contained in your ADSP-BF561 EZ-KIT Lite package.

• “Default Configuration” on page 1-3 Shows the default configuration of the ADSP-BF561 EZ-KIT Lite.

• “Installation and Session Startup” on page 1-5 Instructs how to start a new or open an existing ADSP-BF561EZ-KIT Lite session using VisualDSP++.

• “Evaluation License Restrictions” on page 1-6 Describes the restrictions of the VisualDSP++ demo license shipped with the EZ-KIT Lite.

• “External Memory” on page 1-6 Defines the ADSP-BF561 EZ-KIT Lite’s external memory map.

• “LEDs and Push Buttons” on page 1-9· Describes the board’s LEDs and push buttons.

• “Audio Interface” on page 1-10 Describes the board’s audio interface.

• “Video Interface” on page 1-11 Describes the board’s video interface.

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Package Contents

• “Example Programs” on page 1-12 Provides information about the example programs included in the ADSP-BF561 EZ-KIT Lite evaluation system.

• “Flash Programmer Utility” on page 1-12 Highlights the advantages of the Flash Programmer utility of VisualDSP++.

• “Background Telemetry Channel” on page 1-13 Highlights the advantages of the Background Telemetry Channel feature of VisualDSP++.

• “VisualDSP++ Interface” on page 1-13 Describes the target options facilities of the EZ-KIT Lite system.

For more detailed information about programming the ADSP-BF561 Blackfin processor, see the documents referred to as “Related

Documents”.

Package Contents

Your ADSP-BF561 EZ-KIT Lite evaluation system package contains the following items.

• ADSP-BF561 EZ-KIT Lite board

• VisualDSP++ Installation Quick Reference Card

• CD containing:

D VisualDSP++ software D ADSP-BF561 EZ-KIT Lite software D USB driver files D Example programs D ADSP-BF561 EZ-KIT Lite Evaluation System Manual (this

document)

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Using EZ-KIT Lite

• Universal 7.5V DC power supply

• USB 2.0 cable

• Registration card (please fill out and return)

If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc.

Default Configuration

The ADSP-BF561 EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your computer case.

When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings, DIP switch, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before using the board.

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Default Configuration

Figure 1-1. EZ-KIT Lite Hardware Setup

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Installation and Session Startup

Using EZ-KIT Lite

For correct operation, install the software and hardware in the order presented in the VisualDSP++ Installation Quick Reference Card.

1. Verify that the yellow USB monitor LED ( USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.

2. From the Start menu, navigate to the VisualDSP++ environment via the Programs menu. If you are running VisualDSP++ for the first time, the New Session dialog box appears on the screen (skip the rest of the procedure and go to step 3). If you have run VisualDSP++ previously, the last opened session appears on the screen. To switch to another session, via the Session List dialog box, hold down the Ctrl key while starting VisualDSP++ (go to step 5).

3. In Debug target, select Blackfin Emulators/EZ-KIT Lites. In Platform, select the appropriate EZ-KIT Lite via a debug agent (ADSP-BF561 EZ-KIT Lite via Debug Agent). In Session name, type a new name or accept the default.

LED4, located near the

4. Click OK to return to the Session List.

5. Highlight the session and click Activate.

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Evaluation License Restrictions

• VisualDSP++ allows a connection to the ADSP-BF561 EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.

• The linker restricts a users program to 41 KB of internal memory for code space with no restrictions for data space.

Refer to the VisualDSP++ Installation Quick Reference Card for details.

The EZ-KIT Lite hardware must be connected and powered up to use VisualDSP++ with a valid evaluation or permanent license.

External Memory

EZ-KIT Lite board includes two types of external memory, 64-MB SDRAM and 8-MB flash. Table 1-1 shows the memory map of these devices. The complete configuration of the ADSP-BF561 processor internal SRAM is detailed in Figure 1-2.

Table 1-1. EZ-KIT Lite External Memory Map

Start Address End Address Description

0x00000000 0x3FFFFFF SDRAM Bank 0; see “External Memory” on page 1-6

0x20000000 0x207FFFFF ASYNC Memory Bank 0; see “External Memory” on page 1-6.

All other locations Not used

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Using EZ-KIT Lite

0XFFFF FFFF 0XFFE0 0000

0XFFC0 0000 0XFFB0 1000

0XFFB0 0000 0XFFA1 4000

0XFFA1 0000 0XFFA0 4000 0XFFA0 0000

0XFF90 8000 0XFF90 4000

0XFF90 0000 0XFF80 8000

0XFF80 4000 0XFF80 0000 0XFF70 1000 0XFF70 0000 0XFF61 4000 0XFF61 0000 0XFF60 4000 0XFF60 0000 0XFF50 8000 0XFF50 4000 0XFF50 0000 0XFF40 8000 0XFF40 4000 0XFF40 0000 0XFEB2 0000 0XFEB0 0000 0XEF00 0800

CORE A ME MORY MAP CORE B ME MORY MAP

CORE MMR REGISTERS

RESERVED L1 SCRATCHPAD SR AM (4K)

RESERVED L1 INSTRUCTIONSRAM/CACHE (16K) RESERVED L1 INSTRUCTIONSRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

RESERVED

SYSTEM MMR REGISTERS

CORE MMR REGISTERS

RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED

L1 INSTRUCTION SRAM/CACHE (16K) RESERVED L1 INSTRUCTION SRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

RESERVED

L2 SRAM (128K)

RESERVED

Figure 1-2. ADSP-BF561 Processor Internal Memory Map

The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a ADSP-BF561 processor’s ASYNC Memory Bank 0 (

~AMS0, memory select

signal connects to the flash memory’s output enable pin).

The 64 MB of SDRAM is organized as 16M x 32 bits wide. The processor’s memory select pin

~SMS0 is configured for the SDRAM. Three

SDRAM control registers must be initialized in order to access the SDRAM memory.

When in a VisualDSP++ EZ-KIT Lite session, you can automatically configure the SDRAM registers by selecting the Use XML reset values box on the Target Options dialog box, which is accessible through the Settings

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External Memory

pull-down menu. The values for the

EBIU_SDRRC registers have been set in the ADSP-BF561.xml file found in

your

VisualDSP\SYSTEM folder under the RegReset tag. These values can

EBIU_SDGCTL, EBIU_SDBCTL, and

be changed to be more optimal depending on the SCLK frequency.

The values in Table 1-2 are programmed by default whenever Bank 0 is accessed through the debugger (for example, when viewing memory windows or loading a program). The numbers are derived for maximum flexibility and work for a system clock frequency between 60 MHz and 133 MHz.

Table 1-2. EZ-KIT Lite Session SDRAM Default Settings

EBIU_SDGCTL 0x0091998D Calculated with SCLK = 133 MHz

EBIU_SDBCTL 0x00000013

EBIU_SDRRC 0x000001CF

The

EBIU_SDGCTL register can only be written once after the processor

Calculated with SCLK = 120 MHz

comes out of reset. Therefore, the user code should not reinitialize this register. Clearing the Use XML reset values checkbox allows manual configuration of the

EBIU registers. For more information, see “Target

Options” on page 1-14.

Automatic configuration of the SDRAM is not optimized for a specific SCLK frequency. Table 1-3 shows the optimized configuration for the SDRAM registers using a 120 MHz SCLK. The frequency of 120 MHz is the maximum SCLK frequency when using a 600 MHz core frequency, the maximum frequency for the EZ-KIT Lite. Only the

SDRRC register

needs to be modified in the user code to achieve maximum performance.

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Using EZ-KIT Lite

Table 1-3. SDRAM Optimum Settings

EBIU_SDGCTL 0x0091998D

EBIU_SDBCTL 0x00000013

EBIU_SDRRC 0x000003A0

1 Calculated with SCLK = 120 MHz

For more information about the memory connection on the EZ-KIT Lite, see “External Bus Interface Unit” on page 2-3.

An example program is included in the EZ-KIT installation direc-

tory to demonstrate how to set up the SDRAM interface.

LEDs and Push Buttons

The EZ-KIT Lite provides four push buttons and sixteen LEDs for general-purpose IO.

Sixteen LEDs labeled programmable flags

PPI1 D15–8). These LEDs are accessed through the Flag 2 registers. First,

the direction must be configured to output by setting the bits of the

FIO2_DIR register to “1”. Then the value of the LEDs can be modified

using one the FIO2_FLAG_D, FIO2_FLAG_C, FIO2_FLAG_S, or FIO2_FLAG_T registers.

LED5 through LED20 are controlled by the processor’s

PF32 through PF47 (equivalent to PPI0 D15–8 and

The four general-purpose push buttons are labeled connect to the programmable flags ton can be read through the

FIO0_FLAG_D register. When the

corresponding bit of the register reads “ When the switch is released, the bit reads “

PF8–5. A status of each individual but-

1”, a switch is being pressed-on.

0”. A connection between the

SW6 through SW9. These

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Audio Interface

push button and PF input is established through the information on how to disconnect the switch from the programmable flag and use it for another objective, see “Push Button Enable Switch (SW4)”.

An example program is included in the EZ-KIT installation directory to demonstrate the functionality of the LEDs and push buttons.

SW4 DIP switch. For

Audio Interface

The AD1836A audio codec provides three channels of stereo audio output and two channels of multichannel 96 kHz input. The the processor links with the stereo audio data input and output pins of the AD1836A codec. The processor is capable of transferring data to the audio codec in Time-Division Multiplexed (TDM) or Two-Wire Interface (TWI) mode.

The TWI mode allows the codec to operate with a 96 kHz sample rate but restricts the output to two channels. TDM mode can operate at a maximum of 48 kHz sample rate but allows simultaneous use of all input and

output channels. When using TWI mode, the

well as the externally to the processor. This is accomplished with the SW4 DIP switch. See “Push Button Enable Switch (SW4)” on page 2-12 for more information.

TFS0 and RFS0 pins of the processor, must be tied together

TSCLK0 and RSCLK0 pins, as

SPORT0 interface of

The AD1836A audio codec’s internal configuration registers are configured using the processor’s for this device. For more information on how to configure the multichannel codec, download the datasheet from Analog Devices website,

www.analog.com.

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PF4 programmable flag pin is used as the select

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Using EZ-KIT Lite

The AD1836A codec reset is controlled by the processor’s programmable flag

PF15. When PF15 is “0”, the reset is asserted. When PF15 is “1”, the

reset is de-asserted. Note, when PF15 is not driven (configured as input), the AD1836A reset is asserted due to the pull-down resistor. See “Pro-

grammable Flags” on page 2-4 for more information.

Example programs are included in the EZ-KIT installation directory to demonstrate the AD1836A codec operation.

Video Interface

The board supports video input and output applications. The ADV7179 video encoder provides up to three output channels of analog video, while the ADV7183A video decoder provides up to three input channels of analog video. The video encoder connects to the Parallel Peripheral Interface 1 (PPI1), while the video decoder connects to the Parallel Peripheral Interface 0, (PPI0). Each PPI interface has an individual clock that is configured by the SW5 switch settings. See “PPI Clock Select Switch

(SW5)” on page 2-13 for more information.

Both the encoder and the decoder connect to the Parallel Peripheral Interfaces (PPI input clock) of the ADSP-BF561 processor. For additional information on the video interface hardware, refer to “PPI Interfaces” on

page 2-6.

For the video interface to be operational, the following basic steps must be performed.

1. Configure the SW2 DIP switch as required by the application. Refer to “Video Configuration Switch (SW2)” on page 2-10 for details.

2. De-assert the video device’s reset by setting a corresponding programmable flag “High”. Note that PF14 controls the ADV7179 encoder’s reset, while reset.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-11

PF13 controls the ADV7183A decoder’s

Page 34

Example Programs

3. If using the decoder:

D Enable device by driving programmable flag output PF2 to “0”. D Select PPI0 clock; for details, refer to “PPI Clock Select Switch

(SW5)” on page 2-13.

4. Program internal registers of the video device in use. Both video encoder and decoder use a 2-wire serial interface to access internal registers. The PF0 programmable flag functions as a serial clock (SCL), and PF1 functions as a serial data (SDAT).

5. Program the ADSP-BF561 processor’s PPI interfaces (configuration registers, DMA, and so on).

Example programs are included in the EZ-KIT installation directory to demonstrate the capabilities of the video interface.

Example Programs

Example programs are provided with the ADSP-BF561 EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in the

\…\Blackfin\EZ-KITs\ADSP-BF561\Examples subdirectory of the Visu-

alDSP++ installation directory. Please refer to the readme file provided with each example for more information.

Flash Programmer Utility

The ADSP-BF561 EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++. Once the utility is installed, it is accessible from the Tools pull-down menu.

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Using EZ-KIT Lite

The Flash Programmer driver is core-specific (core A) and must be loaded to the core A in order to operate correctly. The Flash Programmer relies on the user to set the correct core focus. To set up the correct core, select the core A in the multiprocessor window before opening the Flash Programmer interface.

For more information on the Flash Programmer utility, refer to the online Help.

Background Telemetry Channel

The ADSP-BF561 USB debug agent supports the Background Telemetry Channel (BTC), which facilitates data exchange between VisualDSP++ and the processor without interrupting processor execution.

The BTC allows to view a variable as it is updated or changed, all while the processor continues to execute. For increased performance of the BTC, including faster reading and writing, please check out our latest line of processor emulators at

www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULATORS,00.html

Channel, see the VisualDSP++ User’s Guide or online Help.

. For more information about the Background Telemetry

VisualDSP++ Interface

This section provides information on the following parts of the VisualDSP++ graphical user interface:

• “Target Options” on page 1-14

• “Restricted Software Breakpoints” on page 1-17

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VisualDSP++ Interface

Target Options

Choosing Target Options from the Settings menu opens the Target Options dialog box (Figure 1-3). Use target options to control certain

aspects of the processor on the ADSP-BF561 EZ-KIT Lite evaluation system.

Figure 1-3. Target Options Dialog Box

Reset Options

Reset options control how the processor behaves when a reset occurs. The reset options are described in Table 1-4.

Table 1-4. Reset Options

Option Description

Core reset Resets the core when the debugger executes a reset. Note that a core reset of

either core effects both cores as does a system reset.

System reset Resets the peripherals when the debugger executes a reset.

On Emulator Exit

This target option controls processor behavior when VisualDSP++ relinquishes processor control (for example, when exiting VisualDSP++). The option is described in Table 1-5.

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Using EZ-KIT Lite

Table 1-5. On Emulator Exit Target Options

Option Description

On Emulator Exit Determines the state the processor is left in when the board relinquishes

control of the processor: Reset DSP and Run causes the processor to reset and begin execution from its reset vector location. Run from current PC causes the processor to begin running from its current location. Stall the DSP resets the processor and then writes a tion in internal memory so the processor is stuck in a tight loop after exiting.

JUMP 0 to the first loca-

XML File

These read-only fields show the version information for the processor-specific XML file, in the

\…\SYSTEM\ADSP-BF561.xml subdirectory of the

VisualDSP++ installation directory, as well as the parser program (Table 1-6).

Table 1-6. XML File Information

Option Description

XML File Version The version of the processor’s XML file.

XML Parser Version The version of the program that parses the XML file.

Other Options

Table 1-7 describes other available target options.

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VisualDSP++ Interface

Table 1-7. Miscellaneous Target Options

Option Description

Verify all writes to target memory

Reset cycle counters on run

Use opcode scan method Enables the debugger to use a highly optimized JTAG scan method.

Use XML reset values Uses a section in the processor-specific

Mask interrupts during step

Validates all memory writes to the processor. After each write, a read is performed and the values are checked for a matching condition. Enable this option during initial program development to locate and fix initial build problems (such as attempting to load data into non-existent memory). Clear this option to increase performance while loading executable files, since VisualDSP++ does not perform the extra reads that are required to verify each write.

Resets the cycle count registers to zero before a Run command is issued. Select this option to count the number of cycles executed between breakpoints in a program.

This provides extremely fast communication between the EZ-KIT Lite and the processor. In certain circumstances, this causes JTAG scan failures. Typically, JTAG scan failures occur when using this method combined with debugging situations that hold off or stall the core (such as debugging, loading, or viewing external memory). Clearing this option uses a less optimized JTAG scan method.

.XML file located in the

installation’s system folder. The file defines registers that are reset to certain values; the values are read at startup and subsequently used to set the registers when a reset is performed through VisualDSP++. Applies to both processors.

Disables interrupts while single stepping through code. Applies to both processors.

Disable breakpoints in shared memory messages

Suppress a warning message caused by setting a breakpoint in shared memory. Applies to both processors.

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Using EZ-KIT Lite

Restricted Software Breakpoints

The EZ-KIT Lite development system restricts breakpoint placement when certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus architecture, pipeline depth, and ordering of the EZ-KIT Lite and its target processor.

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VisualDSP++ Interface

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2 EZ-KIT LITE HARDWARE

REFERENCE

This chapter describes the hardware design of the ADSP-BF561 EZ-KIT Lite board. The following topics are covered.

• “System Architecture” on page 2-2 Describes the configuration of the ADSP-BF561EZ-KIT Lite and explains how the board components interface with the processor.

• “Jumper and DIP Switch Settings” on page 2-10 Shows the location and describes the function of the configuration jumpers and switches.

• “LEDs and Push Buttons” on page 2-14 Shows the location and describes the function of the LEDs and push buttons.

• “Connectors” on page 2-17 Shows the location and gives the part number for all of the connectors on the board. Also, the manufacturer and part number information is given for the mating parts.

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System Architecture

This section describes the processor’s configuration on the EZ-KIT Lite board.

Figure 2-1. System Architecture

The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF561 Blackfin processor. The processor has IO voltage of 3.3V. The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 30 MHz.

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EZ-KIT Lite Hardware Reference

External Bus Interface Unit

The External Bus Interface Unit (EBIU) connects an external memory to the ADSP-BF561 processor. It includes a 32-bit wide data bus, an address bus (A25–A2), and a control bus. All 8-bit, 16-bit, and 32-bit accesses are supported. On the EZ-KIT Lite board, the EBI unit is connected to SDRAM and flash memory. For more information on using the external memory see “External Memory” on page 1-6.

All of the address, data, and control signals are available externally via the extender connectors (J3–J1). The pinout of these connectors can be found in Appendix B, “Schematics” on page B-1.

SPORT0 Audio Interface

The SPORT0 interface connects to the AD1836A audio codec, the SPORT connector (P3), and the expansion interface. The AD1836A codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio input and outputs.

The pinout of the SPORT connector and the expansion interface connectors can be found in Appendix B, “Schematics” on page B-1.

SPI Interface

The processor’s Serial Peripheral Interconnect (SPI) interface connects to the AD1836A audio codec and the expansion interface. The SPI connection to the AD1836A is used to access the control registers of the device. The PF4 flag of the processor acts as the devices select for the SPI port.

The SPI signals are available on the expansion interface. The pinout for the expansion interface can be found in Appendix B, “Schematics” on

page B-1.

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System Architecture

Programmable Flags

The processor has 48 programmable flag pins (PFs). Many of the flags have a multiple functionality, depending on the processor’s setup.

Table 2-1 shows how the programmable flag pins are used on the EZ-KIT

Lite.

Table 2-1. Programmable Flag Connections

Processor PF Pin

PF0 SPI Select S, Timer 0 Serial clock for programming ADV7179 video encoder

PF1 SPI Select 1, Timer 1 Serial data for programming ADV7179 video encoder and

PF2 SPI Select 2, Timer 2 ADV7183A video decoder’s ~OE.

PF3 SPI Select 3, Timer 3 ADV7183A Field pin. See “Video Configuration Switch

PF4 SPI Select 4, Timer 4 AD1836A audio codec’s SPI Select.

PF5 SPI Select 5, Timer 5 Push Button (SW6). See “LEDs and Push Buttons” on

PF6 SPI Select 6, Timer 6 Push Button (SW7). See “LEDs and Push Buttons” on

PF7 SPI Select 7, Timer 7 Push Button (SW8). See “LEDs and Push Buttons” on

Processor Function EZ-KIT Function

and ADV7183A video decoder.

ADV7183A video decoder.

(SW2)” on page 2-10.

page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push

button.

page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push

button.

page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push

button.

PF8 Push Button (SW9). See “LEDs and Push Buttons” on

page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push

button.

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EZ-KIT Lite Hardware Reference

Table 2-1. Programmable Flag Connections (Cont’d)

Processor

Processor Function EZ-KIT Function

PF Pin

PF9–PF12 Not used

PF13 ADV7183A video decoder’s reset

PF14 ADV7179 video encoder’s reset

PF15 AD1836 codec’s reset

PF16 Sport 0 Transmit Frame Sync

PF17 Sport 0 Transmit Data Secondary

PF18 Sport 0 Transmit Data Primary

PF19 Sport 0 Receive Frame Sync

PF20 Sport 0 Receive Data Secondary

PF21 Sport 1 Transmit Frame

PF2 2 Sport 1 Transmit Data Secondary

PF23 Sport 1 Transmit Data Primary

PF24 Sport 1 Receive Frame Sync

PF25 Sport 1 Receive Data Secondary

PF26 UART Transmit

PF27 UART Receive

PF28 Sport 0 Receive Serial Clock

PF29 Sport 0 Transmit Serial Clock

PF30 Sport 1 Receive Serial Clock

PF31 Sport 1 Transmit Serial Clock

PF39–32 PPI1 data 15–8 LED20–13

PF47–40 PPI0 data 15–8 LED12–5

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System Architecture

PPI Interfaces

The ADSP-BF561 processor employs two independent Parallel Peripheral Interfaces (PPIs), PPI0 and PPI1. Each PPI interface is a half-duplex, bi-directional bus consisting of 16 bits of data, a dedicated input clock, and synchronization signals. The ADSP-BF561 EZ-KIT Lite board utilizes the PPI interfaces for video input and video output.

The PPI0 interface is configured to input video data from the ADV7183A video decoder device: bits 7–0 connect to the video decoder’s data outputs. The PPI1 interface is configured to output video data to the ADV7179 video encoder device: bits 7–0 connect to the video encoder’s data inputs.

Each PPI interface has a dedicated clock input configured independently by the SW5 switch. The clock source can be one of the following: 27 MHz crystal oscillator, ADV7183A video decoder’s clock output, or external clock from the expansion interface. See “PPI Clock Select Switch (SW5)”

on page 2-13 for more information about the switch.

The SW2 switch allows flexible connectivity between dedicated synchronization IOs (SYNC1 and SYNC2 of each PPI interface) and the encoder’s and decoder’s horizontal and vertical synchronization pins. See “Video Con-

figuration Switch (SW2)” on page 2-10 for more information about the

switch. For a detailed description of the ADSP-BF561 processor’s PPI interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference.

Table 2-2 describes the PPI pins and their use on the EZ-KIT Lite board.

Table 2-2. PPI Connections

Processor PPI Pin

PPI0 bits 7–0 ADV7183A data outputs P15–8

PPI1 bits 7–0 ADV7179 data inputs P7–0

PPI0 SYNC1 Timer 8 ADV7179 HSYNC. For more information, see “Video

Other PRocessor Function

EZ-KIT Function

Configuration Switch (SW2)” on page 2-10.

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Table 2-2. PPI Connections (Cont’d)

EZ-KIT Lite Hardware Reference

Processor PPI Pin

PPI0 SYNC2 Timer 9 ADV7179 VSYNC. For more information, see “Video

PPI0 Clock A choice of ADV7183A output clock, a local 27 MHz

PPI1 SYNC1 Timer 10 ADV7183A HSYNC. For more information, see

PPI1 SYNC2 Timer 11 ADV7183A VSYNC. For more information, see “Video

PPI1 Clock A choice of ADV7183A output clock, a local 27 MHz

Other PRocessor Function

EZ-KIT Function

Configuration Switch (SW2)” on page 2-10.

oscillator, or an external clock from ADSP-BF533/BF561 EZ-KIT Extender 1 board.

“Video Configuration Switch (SW2)” on page 2-10.

Configuration Switch (SW2)” on page 2-10.

o s c i l l at o r , o r an e x t e r n a l c l o ck f r o m ADSP-BF53x/BF561 EZ-Extender 1.

Video Output (PPI1)

The

PPI1 interface is configured as output and connects to the on-board

video encoder device, ADV7179. The ADV7179 encoder generates three analog video channels on DAC A, DAC B, and DAC C. The PPI1 bits 7–0 connect to P7–0 of the encoder’s pixel inputs. The encoder’s input clock is fixed and comes from an on-board 27 MHz oscillator.

The encoder’s synchronization signals,

HSYNC and VSYNC, can be config-

ured as inputs or outputs. Video Blanking control signal is at level “1”. The

HSYNC and VSYNC signals can connect to the ADSP-BF561 processor’s

PPI1 interface SYNC1 and SYNC2 via the SW2 switch, as described in “Video

Configuration Switch (SW2)” on page 2-10.

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System Architecture

Video Input (PPI0)

The

PPI0 interface is configured as input and connect to the on-board

video decoder device, ADV7183A. The ADV7183A decoder receives three analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel data outputs P15–8 drive the PPI0 inputs 8–0. The decoder’s 27 MHz pixel clock output can be selected to drive any of the PPI clocks, as shown in

Table 2-7 on page 2-13.

Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and

FIELD can connect to the processor’s PPI1 SYNC1, SYNC2, and PF3 flag via

the SW2 DIP switch, as described in “Video Configuration Switch (SW2)”

on page 2-10.

UART Port

The processor’s Universal Asynchronous Receiver/Transmitter (UART) port connects to the ADM3202 RS232 line driver as well as to the expansion interface. The RS232 line driver is attached to the DB9 male connector, allowing you to interface with a PC or other serial device.

Expansion Interface

The expansion interface consists of the three 90-pin connectors, J3–1.

Table 2-3 shows the interfaces each connector provides. For the exact

pinout of these connectors, refer to Appendix B, “Schematics” on page

B-1. The mechanical dimensions of the connectors can be obtained from Technical or Customer Support.

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EZ-KIT Lite Hardware Reference

Table 2-3. Connector Interfaces

Connector Interfaces

J1 5V, G ND, Address, Data, PPI0 3–0, PF15–6, PF4

J2 3.3V, GND, SPI, NMI, PPI0 SYNC3–1, SPORT0, SPORT1, PF15–0, EBUI control

signals

J3 5V, 3.3V, GND, UART, PPI1 15–0, Reset, Video control signals

Limits to the current and to the interface speed must be taken into consideration when you use the expansion interface. The maximum current limit is dependent on the capabilities of the used regulator. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed.

[

effects of additional circuitry.

JTAG Emulation Port

The JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emulation port of the processor also connects to the USB debugging interface. When an emulator connects to the board at P4, the USB debugging interface is disabled. See “JTAG (P4)” on page 2-20 for more information about the JTAG connector.

To learn more about available emulators, contact Analog Devices (see

“Product Information”).

Analog Devices does not support and is not responsible for the

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Jumper and DIP Switch Settings

This section describes the operation of the jumpers and DIP switches. The jumper and DIP switch locations are shown in Figure 2-2.

Figure 2-2. DIP Switch Locations

Video Configuration Switch (SW2)

The video configuration switch (SW2) controls how some video signals from the ADV7183A video decoder and ADV7179 video encoder are routed to the processor’s PPIs. The switch also determines if the controls the

~OE signal of the ADV7183A video decoder outputs.

Table 2-4 shows which processor’s signals are connected to the encoder

and decoder when in the “

ON” position.

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EZ-KIT Lite Hardware Reference

Table 2-4. Video Configuration Switch (SW2)

Switch Position (Default) Processor Signal Video Signal

1 (OFF) PPI1 SYNC1 ADV7179

2 (OFF) PPI0 SYNC1 ADV7183A

3 (OFF) PPI1 SYNC2 ADV7183A

4 (OFF) PPI1 SYNC2 ADV7179

5 (OFF) PF3 (FIELD) ADV7183A

6 (ON) PF2 ADV7183A

Positions 1 thorough 5 of

FIELD control signals of the PPI0 and PPI1 interfaces are routed to the pro-

SW2 determine how and if the SYNC1, SYNC2, and

cessor’s PPIs. In standard configuration of the encoder and decoder, this is not necessary because the processor is capable of reading the embedded control information, which is in the data stream.

Position 6 of SW2 determines whether PF2 connects to the ~OE signal of the ADV7183A. When the switch is “OFF”, PF2 can be used for other operations, and the decoder output enable is held “HIGH” with a pull-up resistor.

Boot Mode Switch (SW3)

The SW3 switch positions 1 and 2 set the ADSP-BF561 processor’s boot mode as described in Table 2-5. Position 3 sets the processor’s PLL on boot. When

Table 2-5. Boot Mode Select Switch (SW3)

Position 1 BMODE0 Position 2 BMODE1 Boot Mode

ON ON Reserved

ON OFF Flash memory

SW3 position 3 is “ON”, the PLL is in bypass.

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Jumper and DIP Switch Settings

Table 2-5. Boot Mode Select Switch (SW3) (Cont’d)

Position 1 BMODE0 Position 2 BMODE1 Boot Mode

OFF ON 8-bit SPI PROM

OFF OFF 16-bit SPI PROM

Push Button Enable Switch (SW4)

The push button enable switch (SW4) positions 1 through 4 allow to disconnect the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6 connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836A video decoder and the processor are communicating in Two-Wire Interface (TWI) mode. Table 2-6 shows which PF is driven when the switch is in the “ON” position.

Table 2-6. Push Button Enable Switch (SW4)

Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2)

2 ON 2 SW7 11 PF6

3 ON 3 SW8 10 PF7

4 ON 4 SW9 9 PF8

5 OFF 5 TFS0 8 RFS0

6 OFF 6 RSCLK0 7 TSCLK0

ON 1 SW6 12 PF5

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PPI Clock Select Switch (SW5)

The SW5 switch controls a clock selection of PPI interfaces, as described in

Table 2-7 and Table 2-8.

Table 2-7. PPICLK1 Clock Source Setup

SW5 Position 1 PPI0_CKSEL0

ON ON 27 MHz Oscillator (default)

OFF ON ADV7183 Clock Out

XOFFExpansion Interface

SW5 Position 2 PPI0_CKSEL1

PPICLK1 Source

Table 2-8. PPICLK2 Clock Source Setup

SW5 Position 3 PPI1_CKSEL0

ON ON 27 MHz Oscillator (default)

OFF ON ADV7183 Clock Out

XOFFExpansion Interface

SW5 Position 4 PPI1_CKSEL1

PPICLK2 Source

Test DIP Switches (SW10 and SW11)

Two DIP switches (SW10 and SW11) are located on the bottom of the board. The switches are used only for testing and should be in the “ position.

OFF”

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LEDs and Push Buttons

This section describes the functionality of the LEDs and push buttons.

Figure 2-3 shows the locations of the LEDs and push buttons on the

board.

Figure 2-3. LED and Push Button Locations

Reset Push Button (SW1)

The RESET push button resets all of the ICs on the board. One exception is the USB interface chip (U34). The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communication with the PC has been initialized correctly. Once communication is initialized, the only way to reset the USB is by powering down the board.

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EZ-KIT Lite Hardware Reference

Programmable Flag Push Buttons (SW9–6)

Four push buttons, SW9–6, are provided for general-purpose user input. The buttons connect to the processor’s programmable flag pins PF8–5. The push buttons are active “HIGH” and, when pressed, send a High (1) to the processor. Refer to “LEDs and Push Buttons” on page 1-9 for more information on how to use the PFs when programming the processor. The push button enable switch (SW4) is capable of disconnecting the push buttons from the PF (refer to “Push Button Enable Switch (SW4)” on

page 2-12). The programmable flag signals and their corresponding

switches are shown in Table 2-9.

Table 2-9. Programmable Flag Switches

Processor Programmable Flag Pin Push Button Reference Designator

PF5 SW6

PF6 SW7

PF7 SW8

PF8 SW9

Power LED (J7)

When J7 is lit (green), it indicates that power is being properly supplied to the board.

Reset LEDs (LED2 and LED3)

When LED2 is lit, it indicates that the master reset of all the major ICs is active. When LED3 is lit, the USB interface chip (U34) is being reset. The USB chips only reset on power-up, or if USB communication has not been initialized.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-15

Page 56

LEDs and Push Buttons

USB Monitor LED (LED4)

The USB monitor LED (LED4) indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP++ EZ-KIT Lite session. This should take approximately 15 seconds. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver.

Lite target board, the LED can flicker, indicating communications handshake.

User LEDs (LED12–5, LED20–13)

Sixteen LEDs are connected to the ADSP-BF561 processor’s programmable flags. Eight LEDs labeled LED5 through LED12 are controlled by programmable flags PF40 through PF47 (equivalent to PPI0 D15–8). Eight LEDs labeled LED13 through LED20 are controlled by programmable flags

PF32 through PF39 (equivalent to PPI1 D15–8). To learn how to use the

flash memory when programming the LEDs, refer to “LEDs and Push

Buttons” on page 1-9.

Table 2-10. User LEDs

LED Reference Designator Flash Port Name LED Reference Designator Flash Port Name

LED5 PB40 LED13 PB32

LED6 PB41 LED14 PB33

LED7 PB42 LED15 PB34

When VisualDSP++ is actively communicating with the EZ-KIT

LED8 PB43 LED16 PB35

LED9 PB44 LED17 PB36

LED10 PB45 LED18 PB37

LED11 PB46 LED19 PB38

LED12 PB47 LED20 PB39

2-16 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 57

EZ-KIT Lite Hardware Reference

Connectors

This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown in Figure 2-4.

Figure 2-4. Connector Locations

Expansion Interface (J3–1)

Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information about the expansion interface, see

on page 2-8. For the availability and pricing of the J1, J2, and J3 connec-

tors, contact Samtec.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-17

Page 58

Connectors

Part Description Manufacturer Part Number

90 Position 0.05" Spacing, SMT

J1, J2, J3)

(

90 Position 0.05” Spacing (Through Hole)

90 Position 0.05” Spacing (Surface Mount)

90 Position 0.05” Spacing (Low Cost)

Samtec SFC-145-T2-F-D-A

Mating Connector

Samtec TFM-145-x1 Series

Samtec TFM-145-x2 Series

Samtec TFC-145 Series

Audio (J4 and J5)

Part Description Manufacturer Part Number

2x2 RCA Jacks (

3x2 RCA Jacks (J5) SWITCHCRAFT PJRAS3X2S01

Two channel RCA interconnect cable Monster Cable BI100-1M

J4) SWITCHCRAFT PJRAS2X2S01

Mating Connector

Video (J6)

Part Description Manufacturer Part Number

3x2 RCA Jacks (

J6) SWITCHCRAFT PJRAS3X2S01

Power (J7)

The power connector provides all of the power necessary to operate the EZ-KIT Lite board. The power connector supplies DC power to the board. The following table shows the power connector pinout.

2-18 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 59

EZ-KIT Lite Hardware Reference

Part Description Manufacturer Part Number

2.5 mm Power Jack (J7)SWITCHCRAFTRAPC712

Digi-Key SC1152-ND

Mating Power Supply (shipped with EZ-KIT Lite)

7.5V Power Supply GlobTek TR9CC2000LCP-Y

The power connector supplies DC power to the EZ-KIT Lite board.

Table 2-11 shows the power supply specifications.

Table 2-11. Power Supply Specification

Terminal Connection

Center pin +7.5 VDC@3Amps

Outer Ring GND

USB (J8)

The USB connector is a standard Type B USB receptacle.

Part Description Manufacturer Part Number

Type B USB receptacle (

USB cable (provided with kit) Assmann AK672-5

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-19

J8) Mill-Max 897-30-004-90-000

Digi-Key ED90003-ND

Mating Assembly

Digi-Key AK672-5ND

Page 60

Connectors

RS232 (P2)

The RS232-compatible connector is described in Table 2-12.

Table 2-12. RS232 Connector

Part Description Manufacturer Part Number

DB9, Male, Right Angle (P2) Digi-Key A2096-ND

Mating Assembly

2m Female to Female cable Digi-Key AE1016-ND

SPORT0 (P3)

The SPORT0 connector is linked to a 20-pin connector. The connector’s pinout can be found in “Schematics” on page B-1. For pricing and availability of the connectors, contact AMP.

Part Description Manufacturer Part Number

20-position AMPMODU system 50 receptacle (P3)

20-position ribbon cable connector AMP 111196-4

20-position AMPMODU system 20 connector

20-position AMPMODU system 20 connector (w/o lock)

Flexible film contacts (20 per connector)

AMP 104069-1

Mating Connectors

AMP 2-487937-0

AMP 2-487938-0

AMP 487547-1

JTAG (P4)

The JTAG header is the connecting point for a JTAG in-circuit emulator

2-20 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 61

EZ-KIT Lite Hardware Reference

pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled.

L L

Pin 3 is missing to provide keying. Pin 3 in the mating connector should have a plug.

When using an emulator with the EZ-KIT Lite board, follow the connection instructions provided with the emulator.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-21

Page 62

Connectors

2-22 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 63

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1. Please check the latest schematics on the Analog Devices website,

http://www.analog.com/Processors/Processors/DevelopmentTools/tec hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-1

Page 64

ADP3331ART

DEVICES

U47 TI 74LVC14AD

Ref.# Description Reference Designator Manufacturer Part Number

1 10MHZ SMT OSC003 3V U35 RALTRON C04310-10.00

2 74LVC14A SOIC14

U13,U30 IDT IDT74FCT3244APY

HEX-INVER-SCHMITT-TRIGGER

3 IDT74FCT3244APY SSOP20

U45 CYPRESS CY7C64603-128NC

3.3V-OCTAL-BUFFER

4 CY7C64603-128 PQFP128

Q1 FAIRCHILD MMBT4401

USB-TX/RX MICROCONTROLLER

5 MMBT4401 SOT-23

VR7 ANALOG

NPN TRANSISTOR 200MA

6 ADP3331ART SOT23-6

U38 CYPRESS CY7C1019BV33-12VC

ADJ 200MA REGULATOR

7 CY7C1019BV33-15VC SOJ32 128K

Y1 DIG01 300-6027-ND

X 8 SRAM

8 12.0MHZ THR OSC006

U44 ST MICRO DSM2150F5V

CRYSTAL

9 DSM2150F5V TQFP80

U28,U34,U39,U42 TI SN74AHC1G00DBVR

FLASH-ICP

SINGLE-2-INPUT-NAND

10 SN74AHC1G00 SOT23-5

A-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 65

GS74116ATP-10

Bill Of Materials

OGY

64MBIT 8/16-BIT FLASH MEM

U14 EPSON SG-8002CA30.000M

OSCILLATOR

21 30.0000MHZ SMT OSC003

U16 DIG01 SG-8002CA-PCC-ND

TS201/21262

Ref.# Description Reference Designator Manufacturer Part Number

11 12.288MHZ SMT OSC003

VR5 LINEAR TECH LT1765ES8

ADJUSTABLE-3A-SWITCH-REG

12 LT1765 SO-8

U40,U43 GSI TECHNOL-

256Kx16 SRAM

13 GS74116 TSOP44

14 NDS8434A SO-P-MOSFET U29 FAIRCHILD SEMI NDS8434A

U32-33 MICRON MT48LC16M16A2TG-75

256MB-SDRAM

15 MT48LC16M16A2TG-75 TSOP54

U41 XILINX XC2S150E-7FT256C

16 27MHZ SMT OSC003 U17 EPSON SG-8002CA MP

17 XC2S150E FT256

U19-20 INTEGRATED SYS ICS9112AM-16

XILINX-SPARTANIIE-FPGA

18 IDT2305-1DC SOIC8

U10 TI SN74LVC1G32DBVR

1 TO 5 ZERO DELAY CLK BUF

19 SN74LVC1G32 SOT23-5

U27 ST MICRO M29W640DT 90N1

SINGLE-2 INPUT OR GATE

20 M29W64OD TSOP48

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-3

Page 66

ADM708SAR

ADP3338AKC-3.3

ADP3339AKC-5-REEL

ADP3339AKC-3.3-RL

ADP3336ARM-REEL

AD1580BRT

ADG752BRT

AD8061ART-REEL

U31 MICROCHIP 24LC32A-I/SN “U31”

SEE 1000220

Ref.# Description Reference Designator Manufacturer Part Number

22 BF561 24LC32 “U31”

23 1000pF 50V 5% 1206 CERM C153,C160 AVX 12065A102JAT2A

24 2200pF 50V 5% 1206 NPO C46,C76-81 AVX 12065A222JAT050

DEVICES

U46 ANALOG

VOLTAGE-SUPERVISOR

25 ADM708SAR SOIC8

DEVICES

VR3 ANALOG

3.3V-1.0AMP REGULATOR

26 ADP3338AKC-33 SOT-223

DEVICES

VR1 ANALOG

5V-1.5A REGULATOR

27 ADP3339AKC-5 SOT-223

DEVICES

VR6 ANALOG

3.3V 1.5A REGULATOR

28 ADP3339AKC-33 SOT-223

DEVICES

VR2,VR4 ANALOG

ADJ 500MA REGULATOR

29 ADP3336ARM MSOP8

DEVICES

D1 ANALOG

1.2V-SHUNT-REF

30 10MA AD1580BRT SOT23D

DEVICES

U22-23,U25-26 ANALOG

CMOS-SPDT-SWITCH

31 ADG752BRT SOT23-6

DEVICES

U1-3 ANALOG

300MHZ-AMP

32 AD8061ART SOT23-5

A-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 67

Bill Of Materials

ADM3202ARN

DEVICES

U21 ANALOG

AD8606AR

AD1836AAS

DEVICES

U15 ANALOG

ADSP-BF561SKBC-600

DEVICES

U48 ANALOG

ADV7179KCP

DEVICES

U8 ANALOG

DEVICES

ADV7183AKST

DEVICES

MULTI-CHAN-

RS232-TXRX

Ref.# Description Reference Designator Manufacturer Part Number

33 ADM3202ARN SOIC16

34 AD8606AR SOIC8 OPAMP U5-7,U9,U11-12,U1,U24 ANALOG

NEL-96KHZ-CODEC

35 AD1836AAS MQFP52

DUEL BLACKFIN DSP

36 ADSP-BF561SKBC-600 256

VIDEO ENCODER

37 ADV7179 LFCSP40

38 ADV7183AKST LQFP80 U4 ANALOG

39 RUBBER FEET BLACK MH1-5 MOUSER 517-SJ-5018BK

40 PWR 2.5MM_JACK CON005 RA J7 SWITCHCRAFT SC1152-ND12

41 USB 4PIN CON009 USB J8 MILL-MAX 897-30-004-90-000000

42 RCA 2X2 CON013 J4 SWITCHCRAFT PJRAS2X2S01

43 .05 10X2 CON014 RA P3 AMP 104069-1

44 SPST-MOMENTA RY SWT013 6MM SW1,SW6-9 PANASONIC EVQ-PAD04M

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-5

Page 68

YAGEO 0.0ECT-ND

R223-225, R228, R247

LED4-20 PANASONIC LN1461C-TR

GULL-WING

51 AMBER-SMT LED001

52 330pF 50V 5% 805 NPO C82,C84,C86,C92-100 AVX 08055A331JAT

R43-44, R55, R71-73, R80,

J7 DIGI-KEY CKN3063-ND

Ref.# Description Reference Designator Manufacturer Part Number

45 DIP12 SWT014

J1-3 SAMTEC SFC-145-T2-F-D-A

46 0.05 45X2 CON019

SW2,SW4,SW10 DIG01 CKN1364-ND

SMT SOCKET

47 DIP6 SWT017

SW3,SW5,SW11 DIG01 CKN1363-ND

4PIN-SMT-SWT

48 RCA 3X2 CON024 RA J5-6 SWITCHCRAFT PJRAS3X2S01

49 DIP4 SWT018

R90, R133,R159, R163,

50 0.00 1/8W 5% 1206

A-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 69

Bill Of Materials

C129, C143, C162

CERM

AVX 08055C104KAT

C1-2, C4, C12, C19-20, C22,

C27,

C29-30, C35, C37, C48,

CERM

55 0.1uF 50V 10% 805

C51-60, C65-66, C71, C73,

C83, C85, C87-91, C102,

C109-111, C115, C122-124,

C126, C131-132, C135,

C139, C145, C147-148,

C151-152, C155, C158-159,

C164,C167,C171-172,C175,

C177-179, C183-184, C189,

AVX 08051C103KAT2A

C69-70, C74-75,

C101,C112-114,C127,C134,

C136-138, C140-141, C146,

C149-150, C154, C156-157,

C165-166, C168, C173-174,

C176, C180-182, C185-188,

Ref.# Description Reference Designator Manufacturer Part Number

53 0.01uF 100V 10% 805 CERM C3, C5, C28, C41, C49,

AVX 08053C224FAT

C104, C106-108, C125,

C190, C200-203, C249, C256

54 0.22uF 25V 10% 805

AVX 08055A102JAT2A

C191, C233, C236, C241

C38-40,C67-68,

56 0.001uF 50V 5% 805 NPO C23,C25,C33,C36,

57 10uF 16V 10% C TANT CT17-18,CT20-21, CT23-24 SPRAGUE 293D106X9016C2T

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-7

Page 70

AVX CR21-103J-T

R2, R7, R11-12, R14, R24,

R42, R45-47, R52, R57, R78,

R85, R91, R96-98, R131,

R143, R158, R160-162,

R167-170, R174-177, R179,

R181-183, R185, R189-190,

R196, R198-203, R205-206,

R208, R212, R221-222, R229,

R239-241, R246, R248-251

AVX CR21-330JTR

R39,R41,R59-61,

R165-166,R172

Ref.# Description Reference Designator Manufacturer Part Number

58 10K 100MW 5% 805

60 4.7K 100MW 5% 805 R86 AVX CR21-4701F-T

61 1M 100MW 5% 805 R76,R209 AVX CR21-1004F-T

62 1.5K 100MW 5% 805 R1,R94 AVX CR21-1501F-T

63 1.2K 1/8W 5% 1206 R23 DALE CRCW1206-122JRT1

64 49.9K 1/8W 1% 1206 R108-113 AVX CR32-4992F-T

65 2.21K 1/8W 1% 1206 R88-89 AVX CR32-2211F-T

66 100pF 100V 5% 1206 NPO C6-11,C26,C34, C61-63,C72 AVX 12061A101JAT2A

67 10uF 16V 10% B TANT CT1-4,CT15-16 AVX TAJB106K016R

59 33 100MW 5% 805

68 100 100MW 5% 805 R242-245 AVX CR21-101J-T

A-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 71

Bill Of Materials

PHILLIPS 1206CG121J9B200

R8,R15-16,R40, R49-50,R58, PHYCOMP 9C12063A5761FKHFT

75 5.76K 1/8W 1% 1206

74 750K 1/8W 1% 1206 R132,R156,R164,R173 DALE/VISHAY CRCW12067503FRT1

76 11.0K 1/8W 1% 1206 R144-149 DALE CRCW12061102FRT1

77 120PF 50V 5% 1206 NPO C103,C105,C128,

SILICON RECTIFIER

FER2-4,FER6-12,FER14-16 DIGI-KEY 240-1019-1-ND

0.70 BEAD

72 600 100MHZ 500MA 1206

73 237 1/8W 1% 1206 R25-26,R53-54 AVX CR32-2370F-T

FER18-21 MURATA BLM11A601SPT

Ref.# Description Reference Designator Manufacturer Part Number

69 220pf 50V 10% 1206 NPO C13-18 AVX 12061A221JAT2A

70 600 100MHZ 200MA 603

D2-3,D7 GENERALSEMI S2A

0.50 BEAD

71 2A S2A_RECT DO-214AA

PHILIPS 9C12063A75R0JLHFT

R4-6,R100-102,R104-105,R1

C130,C142,C144, C161,C163

07,R114, R134-135

78 75 1/8W 5% 1206

79 30PF 100V 5% 1206 C221-222 AVX 12061A300JAT2A

80 68UF 6.3V 20% D TANT CT22 PANASONIC ECS-TOJD686R

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-9

Page 72

PANASONIC ERJ-8ENF5491V

R75 PHILIPS 9C08052A5362FKRT/R

SCHOTTKY

92 332K 1/10W 1% 805 R207 PHILIPS 9C08052A3323FKRT/R

91 53.6K 1/10W 1% 805

93 10UH 47 +/-20 IND001 L11 DIG01 445-1202-2-ND

Ref.# Description Reference Designator Manufacturer Part Number

81 340K 1/8W 1% 805 R211 DALE CRCW0805-3403FT

82 698K 1/8W 1% 805 R210 DALE CRCW0805-6983FT

83 680PF 50V 1% 805 NPO C116-121 AVX 08055A681FAT2A

C31,C47,C50 MURATA GRM235Y.5V106Z025

Y5V

84 10UF 25V +80-20% 1210

85 2.74K 1/8W 1% 1206 R150-155 DALE CRCW12062741FRT1

R17-22,R27,R30-31,

R34-35,R38

86 5.49K 1/8W 1% 1206

87 3.32K 1/8W 1% 1206 R137-142 DALE CRCW12063321FRT1

88 1.65K 1/8W 1% 1206 R28-29,R32-33,R36-37 PANASONIC ERJ-8ENF1651V

CT5-14 DIG01 PCE3062TR-ND

ELEC

89 10UF 16V 20% CAP002

D6 GENERAL SEMI SL22

90 2A SL22 DO-214AA

A-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 73

Bill Of Materials

VISHAY CRCW0805 0.0 RT1

98 3.32K 100MW 1% 805 R194-195, R227 DIG01 P3.32KCCTR-ND

R67-68,R187-188, R204,R226 VISHAY/DALE CRCW0805220JRT1

99 22 1/10W 5% 805

100 0.68UH 0.72 10% 805 L1-4,L6,L8 MURATA LQG21NR68K10T1

R66,R74,R77,R79,R81,R83-8

4,R87,R99, R103,R106,R178,

R192, R252

Ref.# Description Reference Designator Manufacturer Part Number

94 10K 31MW 5% RNET8 RN3 CTS 746X101103J

95 10K 50MW 5% BGA36 RN2 CTS RT130B7

96 0.00 100MW 5% 805

97 190 100MHZ 5A FER002 FER5 MURATA DLW5BSN191SQ2

101 82NF 50V 5% 805 X7R C64 AVX 08055C823JAT2A

D5 ZETEX ZHCS1000

SCHOTTKY

102 1A ZHCS1000 SOT23D

103 2.2UH 0.63 10% 805 L5,L7,L9 MURATA LQG21N2R2K10

104 0.47UF 16V 10% 805 C218,C230 AVX 0805YC474KAT2A

105 1UF 10V 10% 805 C21,C24,C32,C44-45 AVX 0805ZC105KAT2A

106 10UF 6.3V 10% 805 C208,C217,C219, C243,C255 AVX 080560106KAT2A

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-11

Page 74

AVX 0402ZD104KAT2A

AVX 0402YC103KAT2A

C43 AVX 0805ZD225KAT2A

TANT-LOW-ESR

CERM

114 2.2uF 10V 10% 805

115 76.8K 100MW 1% 1206 R48 DALE CRCW1206-7682FRT1

112 0.18uF 25V 10% 805 CERM C170 AVX 08053C184KAT2A

CT19 AVX TPSC107K010R0075

113 100uF 10V 10% C

C204-205,C207,C214,C216,

C223,C227-229,C231-232,C2

39-240,

C246-247,C251-252,C254,C2

C192-199,C206,

C209-213,C215,

C220,C224-226, C234-235,

C237-238,C242,

C244-245,C248, C250,C253,

C258-259

Ref.# Description Reference Designator Manufacturer Part Number

107 4.7UF 6.3V 10% 805 C169 AVX 08056D475KAT2A

108 0.1UF 10V 10% 402

109 0.01UF 16V 10% 402

D4 CENTRAL SEMI CMDSH-3

SUPERMINI SCHOTTKY

110 1.5UH 45MOHM 20% IND003 2.8A L10 TYCO DS6630-1R5M

111 100MA CMDSH-3 SOD-323

A-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 75

Bill Of Materials

123 22 1/8W 5% 1206 R92-93 DALE CRCW1206220JRT1

AVX CR32-271J-T

R120,R193,R197,R213-220,

R230-237

124 270 1/8W 5% 1206

125 680 1/8W 5% 1206 R119 AVX CR32-681J-T

126 10.0K 1/8W 1% 1206 R186 DALE CRCW1206-1002FRT1

127 150 1/8W 1% 1206 R3 PANASONIC ERJ-8ENF1500V

DEVICES

RN1,RN4-12 PANASONIC EXB-38V100JV

RESISTOR ARRAY

Ref.# Description Reference Designator Manufacturer Part Number

116 147K 100MW 1% 1206 R56 DALE CRCW1206-1473FRT1

117 10 62.5MW/R 5% RA8/38V

118 17.4K 1/10W 1% 805 R180 PANASONIC ERJ-6ENF1742V

119 ADSP-BF561-EZLITE PCB ANALOD

P2 3M 787203-2

120 DB9 9PIN DB9M

R10,R95,R115-118,R136 AVX CR32-102J-T

RIGHT ANGLE MALE

121 1K 1/8W 5% 1206

122 100K 1/8W 5% 1206 R9,R13,R157 DALE CR1206-1003FRT1

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-13

Page 76

ADG774ABRQ

DEVICES

Ref.# Description Reference Designator Manufacturer Part Number

LED2-3 PANASONIC LN1261C

GULL-WING

128 RED-SMT LED001

LED1 PANASONIC LN1361C

GULL-WING

129 GREEN-SMT LED001

CT25-28 PANASONIC ECS-T1EY105R

130 604 1/8W 1% 1206 R125-130 DALE CRCW12066040FRT1

131 1uF 25V 20% A

U36-37 ANALOG

TANT -55+125

QUICKSWITCH-257

132 ADG774A QSOP16

133 IDC 2X1 IDC2X1 GO LD P1

134 IDC 7X2 IDC7X2 HEADER P4 BERG 54102-T08-07

F1 RAYCHEM CORP. SMD250-2

135 2.5A RESETABLE FUS001

A-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 77

A B C D

ADSP-BF561 EZ-KIT Lite

Schematic

ANALOG

DEVICES

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

Approvals Date

Drawn Checked Engineering

A B C D

JSZ

10/10/03

Title

ADSP-BF561 EZ-KIT LITE:

Size

Board No.

Date

12-16-2003_11:50 1 18

TITLE

A0185-2003

Rev

1.3A

Sheet of

Page 78

A B C D

U48

B16

D[31:0]

3.3V

R42 10K 805

1 3

EXT_DSP_CLK

U14

OE OUT

30.0000MHZ OSC003

OSC_30MHZ

3.3V

R60 33 805

R51 DNP 805

R196 10K 805

R160 10K 805

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31

C15 E12 C16 E14 D15 D16 E15

F13 F15 F12 F16

F14 G15 G13 G12

H12 H15 H13 H16 H14

J15 J13

J16 K14 K15 K13

L15

K12

L16

J12

M15

B12

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31

SDQM0/ SDQM1/ SDQM2/ SDQM3/

A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25

ABE0 ABE1 ABE2 ABE3

BGH

D13 G11 B15 G10 B14 C14 F11 D7 A6 C6 B5 E6 A5 E5 B4 F6 B3 C4 A3 F5 B2 D4 A2 C3

E11 B13 A14 A15

A13 C12

A2_S A3_S A4_S A5_S A6_S A7_S A8_S A9_S A10_S A11_S A12_S A13_S A14_S A15_S A16_S A17_S A18_S A19_S A20_S A21_S A22_S A23_S A24_S A25_S

A[25:2]_S

BGH

ABE0_S ABE1_S ABE2_S ABE3_S

A2_S A3_S A4_S A5_S

A6_S A7_S A8_S A9_S

A10_S A11_S A12_S A13_S

RN4

R2A

R3A

R4A 10

RA8/38V RN5

R2A

R3A

R4A 10

RA8/38V RN7

R2A

R3A

R4A 10

RA8/38V

RN11

R2A

R3A

R4A 10

RA8/38V

R1BR1A R2B R3B R4B

A10

A11

A12

A13

81 7 6 5

A14_S A15_S A16_S A17_S

A18_S A19_S A20_S A21_S

A22_S A23_S A24_S A25_S

ABE0 ABE1 ABE2 ABE3

RN12

R2A

R3A

R4A 10

RA8/38V RN6

R2A

R3A

R4A 10

RA8/38V RN8

R2A

R3A

R4A 10

RA8/38V

R1BR1A R2B R3B R4B

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A[25:2]

ARDY

RESET

3.3V

R167 10K 805

R168 10K 805

R170 10K 805

NMI0

SW3: BOOT MODE/BYPASS Select (Default = OFF, ON, ON, OFF)

1 2

BMODE0

BMODE1

ONON

OFF ON

OFF

OFF OFF

BOOT MODE RESERVED 8-BIT FLASH SPI SROM 8-BIT SPI SROM 16-BIT

DEFAULT

SW3

1 2 3 4

SWT018 DIP4

1 2 3 4 5

8 7 6

DSPCK_30MHZ

DSP_BYPASS

BMODE0 BMODE1

R169 10K 805

C42

0.1UF 805

DNP

NMI1

R176 10K 805

RESET

CLKIN

XTAL

BYPASS

M10

BMODE0

N10

BMODE1

P11

NMI0

NMI1

ADSP-BF561SKBC-600 MBGA256

AOE

ARE

AWE

AMS0 AMS1 AMS2 AMS3

SRAS SCAS

SWE

SA10 SMS0 SMS1 SMS2 SMS3 SCKE

SCLK0 SCLK1

B8 A8

C8 B7 E7 A7

C10 D10 E10 D11 E9 B9 C9 A10 B10 A11 A12

SCLK0_S SCLK1_S

R188 22 805

AOE AREARDY AWE

AMS0 AMS1 AMS2 AMS3

SCKE

SCLK1

SRAS_S SCAS_S SWE_S SA10_S SMS0_S SMS1_S SMS2_S SMS3_S

3.3V

U20

GND IDT2305-1DC

SOIC8

RN10

R2A

R3A

R4A 10

RA8/38V RN9

R2A

R3A

R4A 10

RA8/38V

CLKOUTREF

CLK1 CLK2 CLK3VDD CLK4

R1BR1A

R2B

R3B

R4B

R1BR1A

R2B

R3B

R4B

R187 22 805

8 3 2 56 7

Approvals Date

Drawn Checked Engineering

R68 22 805

R67 22 805

R65 22 805

DNP

JSZ

SRAS SCAS SWE SA10

SMS0 SMS1 SMS2 SMS3

SCLK0

10/10/03

CLK_OUT_EXP1

CLK_OUT_EXP2

Title

ADSP-BF561 EZ-KIT LITE:

Size

Date

ANALOG DEVICES

Board No.

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

DSP - EXT MEM INTERFACE

A0185-2003

Sheet of

Rev

1.3A

1825-12-2004_16:35

A B C D

Page 79

A B C D

U48

PF14 PF13 PF12 PF11 PF10

PF9 PF8

P8 R8 N8 T7 P7 R7 N6 R6 M7 T5 P6 R5 M6 T4 N5 P4

T11

PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

TDO

EMU

PF15 PF14 PF13

RN1

R2A

R3A

R4A 10

RA8/38V

R1BR1A R2B R3B R4B

PF[15:0]

81 7 6 5

AD1836_RESET VENC_RESET VDEC_RESET

PROGR. FLAG

PF15 PF14

AD1836 CODEC RESET ADV7179 VIDEO ENCODER RESET

FUNCTION

ADV7183A VIDEO DECODER RESETPF13 PF12 GENERAL PURPOSE PF11

GENERAL PURPOSE PF10 GENERAL PURPOSE PF9

GENERAL PURPOSE PF8 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT PF7

GENERAL PURPOSE / PUSH BUTTON STATUS INPUT PF6 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL PF5

GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL

P15

RSCLK0

DR0PRI

DR0SEC

TSCLK0

DT0PRI

DT0SEC

RSCLK1

DR1PRI

DR1SEC

TSCLK1

DT1PRI

DT1SEC

3.3V

RFS0

TFS0

RFS1

TFS1

MOSI MISO

SCK

R85 10K 10K 805

R200 10K 805

R179 805

RSCLK0/PF28

R16

RFS0/PF19

L12

DR0PRI

P16

DR0SEC/PF20

N16

TSCLK0/PF29

L13

TFS0/PF16

M16

DT0PRI/PF18

N15

DT0SEC/PF17

P13

RSCLK1/PF30

N13

RFS1/PF24

M12

DR1PRI

T14

DR1SEC/PF25

R14

TSCLK1/PF31

P14

TFS1/PF21

R15

DTIPRI/PF23

T15

DT1SEC/PF22

T13

RX/PF27

R13

TX/PF26

N11

MOSI

R12

MISO

M11

SCK

R10 N9

TDI TDO

T10

TMS

TCK

P10 R11

TRST EMU

PF15/TMRXCLK

PF7/SPIS7/TMR7 PF6/SPIS6/TMR6 PF5/SPIS5/TMR5 PF4/SPIS4/TMR4 PF3/SPIS3/TMR3 PF2/SPIS2/TMR2 PF1/SPIS1/TMR1

PF0/SPISS/TMR0

SLEEP

PF4 GENERAL PURPOSE / AD1836 LATCH SIGNAL

TDI TMS TCK TRST

ADSP-BF561SKBC-600 MBGA256

PF3 GENERAL PURPOSE / VIDEO DECODER FIELD PF2 GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE PF1 GENERAL PURPOSE / I2C SERIAL DATA PF0 GENERAL PURPOSE / I2C SERIAL CLOCK

R86

4.7K 805

DSP_VDD_INTDSP_VDD_EXT

U48

VDDEXT1

A16

VDDEXT2

VDDEXT3

VDDEXT4

B11

VDDEXT5

VDDEXT6

D12

VDDEXT7

E16

VDDEXT8

VDDEXT9

G16

VDDEXT10

VDDEXT11

VDDEXT12

K16

VDDEXT13

VDDEXT14

L10

VDDEXT15

VDDEXT16

M14

VDDEXT17

VDDEXT18

T12

VDDEXT19

T16

VDDEXT20

VDDEXT21

VDDEXT22

VDDEXT23

C11

GND1

C13

GND2

GND3

GND5

GND6

GND7

GND8

E13

GND9

F10

GND10

GND11

G14

GND12

GND13

GND14

GND15

GND16

GND17

H10

GND18

GND19

GND20

H9 J11

GND21 GND22

ADSP-BF561SKBC-600 MBGA256

VDDINT1 VDDINT2 VDDINT3 VDDINT4 VDDINT5 VDDINT6 VDDINT7 VDDINT8

VDDINT9 VDDINT10 VDDINT11 VDDINT12 VDDINT13 VDDINT14

VROUT1 VROUT2

GND41 GND40 GND39GND4 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23

NC0 NC1

E8 F7 F9 G9 H11 H6 H7 J10 J8 J9 K11 K8 L8 M8

J1 J2

M5 M13

P9 P5 P2D14 P12 N7 N14 N12 M9 M4 L9 L7 L3 L14 L11 K9 K7 K10 J7 J14

VROUT

Approvals Date

Drawn Checked Engineering

JSZ

10/10/03

ANALOG DEVICES

Title

ADSP-BF561 EZ-KIT LITE:

Size

Date

Board No.

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

DSP - PROGR. FLAGS, SPI

A0185-2003

Sheet of

Rev

1.3A

1835-6-2004_16:04

A B C D

Page 80

A B C D

SW5: PPI CLK Routing Select

(Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON)

1 or 3

PPIxCLK_SEL0 PPIxCLK_SEL1

OFF ON

3.3V R166

33 805

R165 33

R162 10K 805

1 3

U17

OE OUT 27MHZ27MHZ

OSC003

R59 33 805

3.3V

U19

OSC27MOSC_27M

GND IDT2305-1DC

SOIC8

CLKOUTREF

CLK1

CLK2

CLK3VDD

CLK4

805

R171 33 805

R172 33 805

SW5

1 2 3 4

SWT018 DIP4

1 2 3 4 5

8 7 6

VDEC_27MHZ_CLK

VENC_27MHZ_CLK

EXT_27MHZ_CLK

PPI0CLK_SEL0 PPI0CLK_SEL1 PPI1CLK_SEL0 PPI1CLK_SEL1

2 or 4

ONON

OFF

EXP_PPI0_CLK

PPI_27MHZ_CLK

VDEC_CLKOUT

EXP_PPI1_CLK

PPIxCLK PPI_27MHZ_CLK VDEC_CLKOUT EXPANSION_CLK

R174 10K 805

R175 10K 805

R182 10K 805

3.3V

R181 10K 805

U22

ADG752BRT SOT23-6

U26

ADG752BRT SOT23-6

U23

ADG752BRT SOT23-6

U25

ADG752BRT SOT23-6

R66

0.00 805

R178

0.00 805

PPI0_CLK

PPI1_CLK

U48

PPI0_D[15:0]

PPI0_CLK PPI1_CLK PPI0_SYNC1 PPI0_SYNC2 PPI0_SYNC3

PPI0_D15 PPI0_D14 PPI0_D13 PPI0_D12 PPI0_D11 PPI0_D10 PPI0_D9 PPI0_D8 PPI0_D7 PPI0_D6 PPI0_D5 PPI0_D4 PPI0_D3 PPI0_D2 PPI0_D1 PPI0_D0

PPI0_D15/PF47

PPI0_D14/PF46

PPI0_D13/PF45

PPI0_D12/PF44

PPI0_D11/PF43

PPI0_D10/PF42

PPI0_D9/PF41

PPI0_D8/PF40

PPI0_D7

PPI0_D6

PPI0_D5

PPI0_D4

PPI0_D3

PPI0_D2

PPI0_D1

PPI0_D0

PPI0_CLK

PPI0_SYN1/TMR8

PPI0_SYN2/TMR9

PPI0_SYN3

PPI1_D15/PF39 PPI1_D14/PF38 PPI1_D13/PF37 PPI1_D12/PF36 PPI1_D11/PF35 PPI1_D10/PF34

PPI1_D9/PF33 PPI1_D8/PF32

PPI1_D7 PPI1_D6 PPI1_D5 PPI1_D4 PPI1_D3 PPI1_D2 PPI1_D1 PPI1_D0

PPI1_CLK PPI1_SYN1/TMR10 PPI1_SYN2/TMR11

PPI1_SYN3

M1 K5 M2 N1 L6 N2 M3 P1 R1 R2 P3 T2 N3 R3 N4 R4

B1 K4 L2 L4

PPI1_D15 PPI1_D14 PPI1_D13 PPI1_D12 PPI1_D11 PPI1_D10 PPI1_D9 PPI1_D8 PPI1_D7 PPI1_D6 PPI1_D5 PPI1_D4 PPI1_D3 PPI1_D2 PPI1_D1 PPI1_D0

PPI1_SYNC1 PPI1_SYNC2 PPI1_SYNC3

PPI1_D8 PPI1_D9 PPI1_D10 PPI1_D11

PPI1_D12 PPI1_D13 PPI1_D14 PPI1_D15

U13

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

OE1

OE2 IDT74FCT3244APY

SSOP20

1Y1 1Y2 1Y3 1Y4

2Y1 2Y2 2Y3 2Y4

PPI1_D[15:0]

18 16 14 12

9 7 5 3

LED20 AMBER-SMT LED001

R237 270 1206

LED19 AMBER-SMT LED001

R236 270 1206

LED18 AMBER-SMT LED001

R235 270 1206

LED17 AMBER-SMT LED001

R234 270 1206

LED16 AMBER-SMT LED001

R233 270 1206

LED15 AMBER-SMT LED001

R232 270 1206

LED14 AMBER-SMT LED001

R231 270 1206

LED13 AMBER-SMT LED001

R230 270 1206

ADSP-BF561SKBC-600 MBGA256

U30 PPI0_D8 PPI0_D9 PPI0_D10 PPI0_D11

PPI0_D12 PPI0_D13 PPI0_D14 PPI0_D15

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

OE1

OE2

IDT74FCT3244APY

SSOP20

1Y1 1Y2 1Y3 1Y4

2Y1 2Y2 2Y3 2Y4

18 16 14 12

9 7 5 3

LED12 AMBER-SMT LED001

LED11 AMBER-SMT LED001

LED10 AMBER-SMT LED001

LED9 AMBER-SMT LED001

LED8 AMBER-SMT LED001

LED7 AMBER-SMT LED001

LED6 AMBER-SMT LED001

LED5 AMBER-SMT LED001

ANALOG

20 Cotton Road Nashua, NH 03063

R220 270 1206

R219 270 1206

R218 270 1206

R217 270 1206

R216 270 1206

R215 270 1206

R214 270 1206

R213 270 1206

Approvals Date

Drawn Checked Engineering

JSZ

10/10/03

DEVICES

Title

ADSP-BF561 EZ-KIT LITE:

Size

Date

Board No.

5-12-2004_16:32 4 18

PH: 1-800-ANALOGD

DSP - PPI0 AND PPI1

A0185-2003

Rev

1.3A

Sheet of

A B C D

Page 81

A B C D

FLASH A (8MB)

4M x 16

D[31:0]

A[25:2]

U27

ABE3

3.3V

AMS0

AOE

AWE

R189 10K 805

R190 10K 805

R177

10K 805

A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

FLASH_WP FLASH_RP

24 23 22 21 20 19 18

8 7 6 5 4 3 2

1 48 17 16

9 10 13

26 28 11

14 12

M29W64OD TSOP48

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

CE OE WE

WP/VPP RP

VCC

D0 D1 D2 D3 D4 D5 D6 D7 D8

D9 D10 D11 D12 D13 D14 D15

RDY

VSS2BYTE VSS1

3.3V

D10

D11

D12

D13

D14

D15

4647 27

FLASH_RDY

3.3V

R183 10K 805

SA10

SWE SCAS SRAS

ABE0 ABE1

A3 A4 A5 A6 A7 A8 A9 A10 A11

A13 A14

A18 A19

A10 A11

A13 A14

A18 A19

A2 A3 A4 A5 A6 A7 A8 A9

24 25 26 29 30 31 32 33 34 22 35 36

20 21

16 17 18

15 39

23 24 25 26 29 30 31 32 33 34 22 35 36

20 21

SDRAM 64MB

(256Mb x 2 Chips)

U32

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12_NC

BA0 BA1

WE CAS RAS

DQML DQMH

MT48LC16M16A2TG-75 TSOP54

U33

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12_NC

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

CKE

CLK

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

D10

D11

D12

D13

D14

D15

19 37 38

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

SMS0 SCKE SCLK0

Memory Map

START

END

0x0000 0000 0x03FF FFFF 0x2000 0000

0x207F FFFF

BANK

DEVICE

SDRAM Bank 0 64MB SDRAM ASYNC Memory Bank 0

8MB FLASH

ABE2 ABE3

16 17 18

15 39

WE CAS RAS

DQML DQMH

CKE

CLK

19 37 38

MT48LC16M16A2TG-75 TSOP54

ANALOG

20 Cotton Road Nashua, NH 03063

Approvals Date

Title

DEVICES

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

12-16-2003_11:03 5 18

PH: 1-800-ANALOGD

MEMORY - FLASH & SDRAM

A0185-2003

Sheet of

Rev

1.3A

A B C D

Page 82

A B C D

3.3V

R161 10K 805

U16

1 3

OE OUT

12.288MHZ OSC003

R61 33 805

3.3V

R57 10K 805

AD1836_CLK

DAC3

AUDIO CODEC

U15

DR0PRI

DR0SEC

RFS0

RSCLK0

ASDATA1

ASDATA2

ALRCLK

ABCLK

AD1836_CLK

PF4

SCK MOSI MISO

ADC1 LEFT

R46 10K 805

R45 805

R47 10K10K 805

ADC1 RIGHT

ADC2 LEFT

ADC2 RIGHT

AD1836_RESET

IN2L1 IN2L2

IN2R2 IN2R1

IN1L+

IN1L-

IN1R+

IN1R-

MCLK

CLATCH

CCLK

CDATA

COUT

IN1L+

IN1L-

IN1R+

IN1R-

IN2L+/CL2/CL2

IN2L-/CL1/CL1

NC/IN2L1/IN2L+

NC/IN2L2/IN2L-

NC/IN2R2/IN2R-

NC/IN2R1/IN2R+

IN2R-/CR1/CR1

IN2R+/CR2/CR2

PD/RST AD1836AAS

MQFP52

DSDATA1 DSDATA2 DSDATA3

OUT1L+

OUT1L-

OUT1R+

OUT1R-

OUT2L+

OUT2L-

OUT2R+

OUT2R-

OUT3L+

OUT3L-

OUT3R+

OUT3R-

DLRCLK

DBCLK

FILTR FILTD

8 9

31 30

6 7

33 32

4 5

35 34

38 41 42 36 37

13 12

CT16 10UF B

C124

0.1UF 805

DAC1

DAC2

OUT1L+ OUT1L-

OUT1R+ OUT1R-

OUT2L+ OUT2L-

OUT2R+ OUT2R-

OUT3L+ OUT3L-

OUT3R+ OUT3R-

DT0PRI DT0SEC

TFS0 TSCLK0

CT15 10UF B

ADC1

ADC2

LEFT (WHITE) RIGHT (RED)

IN (J5)OUT (J4)

DAC1 LEFT

DAC1 RIGHT

DAC2 LEFT

DAC2 RIGHT

DAC3 LEFT

DAC3 RIGHT

R159

0.00 1206

C123

0.1UF 805

OUT1R-

DAC1 RIGHT

OUT1R+

OUT1L-

DAC1 LEFT

OUT1L+

R145

11.0K 1206

R30

5.49K 1206

R151

2.74K 1206

R144

11.0K 1206

R27

5.49K 1206

R150

2.74K 1206

C96 330PF 805

C117 680PF 805

C95 330PF 805

C116 680PF 805

R18

5.49K 1206

R17

5.49K 1206

R138

3.32K 1206

R29

1.65K 1206

R137

3.32K 1206

R28

1.65K 1206

C7 100PF 1206

C14 220PF 1206

C6 100PF 1206

C13 220PF 1206

AD8606AR SOIC8

AGND

AD8606AR SOIC8

R126 604 1206

C77 2200PF 1206

CT8 10UF CAP002

DAC1_RIGHT

R109

49.9K 1206

J5 3X2 CON024

R125 604 1206

C76 2200PF 1206

CT7 10UF CAP002

DAC1_LEFT

R108

49.9K 1206

J5 3X2 CON024

R158 10K 805

AGND

C40

0.001UF 805

C38

0.001UF 805

C39

0.001UF 805

C133

0.001UF 805

AGND

SW10: Audio Loopback For Test Purposes

U12

AD8606AR SOIC8

R43

0.00 1206

R55

0.00 1206

AD1836_VREF

U12

AD8606AR SOIC8

AGND

Default = All Off

R44

R71

SW10

1 2 4 5 6

SWT017 DIP6

12 11 10 9 8

DAC1_LEFT DAC1_RIGHT DAC2_LEFT DAC2_RIGHT DAC3_LEFT DAC3_RIGHT

ADC1_LEFT

ADC1_RIGHT

ADC2_LEFT

ADC2_RIGHT

1 2 3 4 5 6 7

0.00 1206

AGND

Approvals Date

Drawn Checked Engineering

0.00 1206

JSZ

10/10/03

ANALOG DEVICES

Title

ADSP-BF561 EZ-KIT LITE:

Size

Date

Board No.

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

AUDIO CODEC

A0185-2003

Sheet of

Rev

1.3A

1865-12-2004_16:35

A B C D

Page 83

A B C D

R19

5.49K 1206

R139

3.32K 1206

OUT2R-

R146

11.0K 1206

C97 330PF 805

DAC2 RIGHT

C118

R31

5.49K 1206

OUT2R+

R152

2.74K 1206

AD1836_VREF

680PF 805

R32

1.65K 1206

C8 100PF 1206

C15 220PF 1206

AD8606AR SOIC8

R22

5.49K 1206

R149

11.0K 1206

OUT3R-

R128 604 1206

C79 2200PF 1206

CT10 10UF CAP002

DAC2_RIGHT

R111

49.9K 1206

J5 3X2 CON024

DAC3 RIGHT

OUT3R+

R38

5.49K 1206

R155

2.74K 1206

C100 330PF 805

C121 680PF 805

R142

3.32K 1206

R37

1.65K 1206

C11 100PF 1206

C18 220PF 1206

AD8606AR SOIC8

R130 604 1206

C81 2200PF 1206

CT12 10UF CAP002

DAC3_RIGHT

R113

49.9K 1206

J5 3X2 CON024

AGND

R20

5.49K 1206

R140

3.32K 1206

OUT2L-

R147

11.0K 1206

C98 330PF 805

DAC2 LEFT

R34

5.49K 1206

OUT2L+

R153

2.74K 1206

C119 680PF 805

R33

1.65K 1206

C9 100PF 1206

C16 220PF 1206

AD8606AR SOIC8

R21

5.49K 1206

R148

11.0K 1206

OUT3L-

C99

330PF 805

R141

3.32K 1206

DAC3 LEFT

R127 604 1206

C78 2200PF 1206

CT9 10UF CAP002

DAC2_LEFT

R110

49.9K 1206

J5 3X2 CON024

OUT3L+

R35

5.49K 1206

R154

2.74K 1206

C120 680PF 805

R36

1.65K 1206

C10 100PF 1206

C17 220PF 1206

AD8606AR SOIC8

R129 604 1206

C80 2200PF 1206

CT11 10UF CAP002

DAC3_LEFT

R112

49.9K 1206

J5 3X2 CON024

AGND

ANALOG

20 Cotton Road Nashua, NH 03063

Approvals Date

Title

DEVICES

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

PH: 1-800-ANALOGD

AUDIO OUT

A0185-2003

Sheet of

Rev

1.3A

18712-10-2003_18:18

A B C D

Page 84

A B C D

J4 2X2 CON013

AGND

ADC1_LEFT

FER10 600

1206

AGND

C62 100PF 1206

CT5 10UF CAP002

R121

5.76K 1206

R40

5.76K 1206

R156 750K 1206

R49

5.76K 1206

C128 120PF 1206

U11

AD8606AR SOIC8

R50

5.76K 1206

C130 120PF 1206

U11

AD8606AR SOIC8

R53 237 1206

R54 237 1206

AGND

C25

0.001UF 805

C23

0.001UF 805

C26 100PF 1206

IN1L-

ADC1 LEFT

IN1L+

J4 2X2 CON013

AGND

ADC2_LEFT

FER12 600

1206

AGND

C72 100PF 1206

CT13 10UF CAP002

R123

5.76K 1206

R58

5.76K 1206

R164 750K 1206

R62

5.76K 1206

C142 120PF 1206

U18

AD8606AR SOIC8

R63

5.76K 1206

C144 120PF 1206

U18

AD8606AR SOIC8

IN2L2

ADC2 LEFT

IN2L1

AGND

J4 2X2 CON013

AGND

ADC1_RIGHT

FER11 600

1206

AGND

C63 100PF 1206

CT6 10UF CAP002

R122

5.76K 1206

R132 750K 1206

R15

5.76K 1206

C103 120PF 1206

AD8606AR SOIC8

R16

5.76K 1206

C105 120PF 1206

AD8606AR SOIC8

R25 237 1206

R26 237 1206

AGND

C36

0.001UF 805

C33

0.001UF 805

C34 100PF 1206

IN1R-

ADC1 RIGHT

IN1R+

J4 2X2 CON013

AGND

ADC2_RIGHT

FER9 600

1206

AGND

C61 100PF 1206

AGND

CT14 10UF CAP002

R124

5.76K 1206

R64

5.76K 1206

R173 750K 1206

R69

5.76K 1206

C161 120PF 1206

U24

AD8606AR SOIC8

R70

5.76K 1206

C163 120PF 1206

U24

AD8606AR SOIC8

IN2R2

ADC2 RIGHT

IN2R1

AGND

AD1836_VREF

AGND

ANALOG

20 Cotton Road Nashua, NH 03063

Approvals Date

Title

DEVICES

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

12-10-2003_18:18 8 18

PH: 1-800-ANALOGD

AUDIO IN

A0185-2003

Rev

1.3A

Sheet of

A B C D

Page 85

A B C D

SW11

1 2 3 4

SWT018 DIP4

8 7 6

VIDEO_DAC_A VIDEO_DAC_C

VIDEO_AVIN1 VIDEO_AVIN4 VIDEO_AVIN5 VIDEO_DAC_B

1 2 3 4 5

SW11: Video Loopback For Test Purposes

Default = All Off

R136 1K 1206

A3V

VIDEO_DAC_A

Composite Video Component Video Differential Component Video S Video

J6 3X2 CON024

DAC A

VIDEO_DAC_B

DAC B

VIDEO_DAC_C

DAC C

R116 1K 1206

A3V

R118 1K 1206

A3V

AD8061ART SOT23-5

R10 1K 1206

VIDEO ENCODER

3V_B

R114 75 1206

0.68UH 805

2.2UH 805

C92 330PF 805

AGND2

0.68UH 805

C86 330PF 805

R6 75 1206

VAA1

VAA2

VAA3

VAA4

PPI1_D[15:0]

VENC_27MHZ_CLK

VENC_RESET

PF[15:0]

3V_B

R13 100K 1206

R143 10K 805

PPI1_D7 PPI1_D6 PPI1_D5 PPI1_D4 PPI1_D3 PPI1_D2 PPI1_D1 PPI1_D0

PF1 PF0

R9 100K 1206

CLOCK

RESET

ALSB

SDATA

SCLOCK

SCRESET/RTC

TTX

TTXREQ

ADV7179 LFCSP40

VAA5

DAC_A DAC_B DAC_C

COMP

VREF RSET

HSYNC

FIELD/VSYNC

BLANK

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9

GND10

29 28 24

23 30 31

13 14 15

6 7 8 9 11 12 17 19 26 40

R14 10K 805

R3 150 1206

C115

0.1UF 805

C12

0.1UF 805

D1 AD1580 SOT23D

R23

1.2K 1206

VENC_HS VENC_VS

R135 75 1206

R134 75 1206

0.68UH 805

2.2UH 805

C94 330PF 805

AGND2

2.2UH 805

C93 330PF 805

0.68UH 805

C82 330PF 805

0.68UH 805

C84 330PF 805

R4 75 1206

R5 75 1206

R115 1K 1206

R117 1K 1206

R104 75 1206

R107 75 1206

R105 75 1206

DAC A DAC B DAC C

CVSB

CVSB G B R

Y C

VUY

R133

0.00 1206

AGND2

ANALOG

20 Cotton Road Nashua, NH 03063

AGND2

Approvals Date

Title

DEVICES

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

5-12-2004_16:35 9 18

PH: 1-800-ANALOGD

VIDEO ENCODER (VIDEO OUT)

A0185-2003

Sheet of

Rev

1.3A

A B C D

Page 86

A B C D

3.3V

DAC_B

DAC_C

DAC_D

(WHITE) OUT

(RED) IN

R12 10K 805

R11 10K 805

R131 10K 805

R2 10K 805

VIDEO DECODER

Note: Signal Names in brackets refer to ADV7183KST

AVIN4

AVIN5

Differential Component Video

J6 3X2 CON024

AVIN1

AVIN4

AVIN5

AGND2

AVIN1

VIDEO_AVIN1

VIDEO_AVIN4

VIDEO_AVIN5

AVIN1 AVIN4 AVIN5

V U

CVBSCVBSComposite Video

R99

0.00 805

R103

0.00 805

R106

0.00 805

CVBS Y YS Video

AGND2

R100 75 1206

VDEC_27MHZ_CLK

VDEC_RESET

R102 75 1206

PF[15:0]

R101 75 1206

CT4 10UF B

CT3 10UF B

C60

0.1UF 805

C66

0.1UF 805

C65

0.1UF 805

C59

0.1UF 805

C58

0.1UF 805

C68

0.001UF 805

R7 10K 805

CT1 10UF B

PF1 PF0

0.1UF 805

TP1

TP2

TP3

A3V A5V

DNP FER13 600

1206

FER14 600

1206

C56

0.1UF 805

AGND2AGND2

C54

0.1UF 805

AGND2 AGND2

CT2 10UF B

0.1UF 805

C57

0.1UF 805

C67

0.001UF 805

XTAL

XTAL1

ALSB

SDA

SCLK

RESET

PWRDN

NC[ISO]

AIN1

AIN7

AIN2

AIN8

AIN3

AIN9

AIN4

AIN10

AIN5

AIN11

AIN6

AIN12

REFOUT

CML

CAPY1

CAPY2

CAPC1

CAPC2

AVDD

PVDD

AGND1

AGND2

AGND3

AGND4

AGND5

NC[AGND6]

NC[LLCREF]

NC[VREF]

NC[HREF]

NC[CLKIN]

NC[AFF]

SFL[HFF]

NC[AEF]

NC[DV]

NC[RD]

NC[GPO3] NC[GPO2] NC[GPO1] NC[GPO0]

DVDD1 DVDD2

DVDD3 DVDDIO1 DVDDIO2

DGND1 DGND2 DGND3 DGND4 DGND5

P15 P14 P13 P12 P11 P10

P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

LLC1 LLC2

ELPF

HS VS

FIELD

PPI0_D7

PPI0_D6

PPI0_D5

PPI0_D4

PPI0_D3

PPI0_D2

PPI0_D1

PPI0_D0 19 20 21 22 23 24 32 33

27 26 25 37

2 1 80 69 70

16 11 12 13 78 77 79

17 18 34 35

30 10 72 4 15

3 9 14 31 71

PVDD_ADV7183

3.3V

DVDD_ADV7183

0.01UF 805

R24 10K 805

R39 33 805

1.5K 805

FER15 600 1206

DNP FER17 600 1206

VENC_HS

VENC_VS

1.8V

1 2

C64 82NF 805

3.3V

PPI0_D[15:0]

U10

SN74LVC1G32 SOT23-5

SW2: Video Sync Signals and Encoder Enable Select Defalut = OFF, OFF, OFF, OFF, OFF, ON

Position

1-5

R41 33 805

VDEC_CLKOUT

SW2

12 11 10

9 8

SWT017 DIP6

123456

2 3 4 5

PF3

PF2

Function Connect video sync signals to DSP ON = PF2 Used to enable or disable

the encoder digital interface

OFF = Encoder digital interface always disabled

VDEC_HS VDEC_VS VDEC_FIELD VDEC_VREF VDEC_HREF

PPI1_SYNC1 PPI0_SYNC1 PPI0_SYNC2 PPI1_SYNC2 PF[15:0]

DNP FER1 600 1206

A1.8V

FER2 600

1206

PVDD_ADV7183

C55

0.1UF 805

0.01UF 805

C73

0.1UF 805

C74

0.01UF 805

AGND2

ADV7183AKST LQFP80

Approvals Date

Drawn Checked Engineering

JSZ

10/10/03

ANALOG DEVICES

Title

ADSP-BF561 EZ-KIT LITE:

Size

Date

Board No.

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

VIDEO ENCODER (VIDEO IN)

A0185-2003

Sheet of

Rev

1.3A

181012-16-2003_11:24

A B C D

Page 87

A B C D

3.3V

R248 10K 805

PF5

SW6

SWT013 SPST-MOMENTARY

PF6

SW7 SWT013 SPST-MOMENTARY

R242 100 805

R243 100 805

3.3V

CT25 1UF A

R249 10K 805

11 10

CT26 1UF A

U47

74LVC14A SOIC14

U47

74LVC14A SOIC14

R247

0.00 1206

R223

0.00 1206

R98 10K 805

U47

1 2

74LVC14A SOIC14

3.3V

R246 10K 805

13 12

74LVC14A SOIC14

RESET

SW1 SWT013 SPST-MOMENTARY

U47

3.3V

R229 10K 805

5V 3.3V

POWER LED1 GREEN-SMT LED001

R119 680 1206

U46

RESETMR

PFI

RESET

ADM708SAR SOIC8

PFO

7 5

RESET LED2 RED-SMT LED001

R120 270 1206

USB_CONFIGURED

3.3V

R185 10K 805

U28

1 2

SN74AHC1G00 SOT23-5

USB RESET LED3 RED-SMT LED001

R193 270 1206

USB_RESET

RESET

R250 10K 805

PF7

SW8 SWT013 SPST-MOMENTARY

R244 100 805

CT27 1UF A

U47

74LVC14A SOIC14

R224

0.00

1206

3.3V

PF[15:0]

SW4

1 2 3 4 5 6

2 3 4 5 6 7

SWT017 DIP6

PF5

PF6

PF7

PF8

SW9 SWT013 SPST-MOMENTARY

R245 100 805

R251 10K 805

CT28 1UF A

U47

5 6

74LVC14A SOIC14

R225

0.00 1206

TFS0

SOFT_RESET

RFS0 TSCLK0RSCLK0

C158

PF5

PF6

R184

0.00 805

DNP

R191

0.00 805

DNP

R192

0.00 805

C159

0.1UF 805

U21

C1+

C1-

C2+

C2-

T1IN

10 7

T2IN T2OUT

ADM3202ARN SOIC16

NOTE: Remove R192 when populating R191 and R184

V+

T1OUT

R1INR1OUT R2INR2OUT

3.3V

DB9M

9PIN

1 2

IDC2X1 2X1

UART

C147

0.1UF 805

2 6

V-

1312 89

C148

0.1UF 805

FER21 600

603

FER19 600

603

FER20 600

603

FER18 600

603

SW4 PB Enable Switch Default = ON, ON, ON, ON, OFF, OFF

Position

1-4

5,6

Function Connects the push buttons to the Programmable Flags of the DSP Useful if using the PFs for another purpose. OFF, OFF = AD1836A -> TDM Mode ON, ON = AD1836A -> I2S Mode

Approvals Date

ANALOG DEVICES

Title

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

12-16-2003_11:24 11 18

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

RESET, PUSH-BUTTON SWITCHES, UART

Rev

A0185-2003

1.3A

Sheet of

A B C D

Page 88

D[31:0]

A B C D

EXPANSION INTERFACE (TYPE B)

3.3V

A[25:2]

PPI0_D[15:0]

PF[15:0]

45X2 CON019

1 3 5 78 9 1112 1314 1516 1718 19 2122 2324 2526 2728 29 3132 3334 3536 3738 39 4142 4344 4546 4748 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87

2 4

6 A3 A5 A7 A9 A11 A13 A15 A17 A19 A18 A21 A23 A25 A24

D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29

PPI0_D0 PPI0_D2

PF14 PF12 PF10 PF8 PF6 PF4

50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 89

A2 A4 A6 A8 A10 A12 A14 A16

A20 A22

D0 D2D3 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30D31

PPI0_D1 PPI0_D3

PF15 PF13 PF11 PF9 PF7

EXP_PPI0_CLK

MOSI MISO

PPI0_SYNC2

DT1SEC

DT1PRI

TFS1

TSCLK1

DT0SEC

DT0PRI

TFS0

TSCLK0

ABE3 ABE2 ABE1 ABE0

AOE

AWE SMS2 SMS0

SRAS

SA10

SWE

PF5

PF0

PPI0_D5 PPI0_D7 PPI0_D9 PPI0_D11 PPI0_D13 PPI0_D15 PF2

45X2 CON019

1 3 5 78 9 1112 1314 1516 1718 19 2122 2324 2526 2728 29 3132 3334 3536 3738 39 4142 4344 4546 4748 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87

2 4 6

50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 89

PPI0_D4 PPI0_D6 PPI0_D8 PPI0_D10 PPI0_D12 PPI0_D14 PF3 PF1PF0

SCK

NMI0

PPI0_SYNC3 PPI0_SYNC1 DR1SEC DR1PRI RFS1 RSCLK1 DR0SEC DR0PRI RFS0 RSCLK0

AMS3 AMS2 AMS1 AMS0 ARDY ARE SMS3 SMS1

SCKE SCAS CLK_OUT_EXP2

PPI1_D[15:0]

PPI1_D0

TX RX

PPI1_D2 PPI1_D4 PPI1_D6 PPI1_D8 PPI1_D10 PPI1_D12 PPI1_D14

RESET

VDEC_HS

VDEC_FIELD

VDEC_HREF

DSP_VDD_EXT DSP_3V_VOUT

PPI1_SYNC2

EXT_27MHZ_CLK

2 4 6

50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 89

45X2 CON019

3.3V

1 3 5 78 9 1112 1314 1516 1718 19 2122 2324 2526 2728 29 3132 3334 3536 3738 39 4142 4344 4546 4748 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87

PPI1_D1

PPI1_D3 PPI1_D5 PPI1_D7 PPI1_D9 PPI1_D11 PPI1_D13 PPI1_D15

EXP_PPI1_CLK

CLK_OUT_EXP1 EXT_DSP_CLK VDEC_VS VDEC_VREF

PPI1_SYNC3 PPI1_SYNC1

BR BG BGH

DT0PRI

DT0SEC

TFS0

TSCLK0

R72

0.00 1206

SPORT0

CON014 10X2

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

R80

0.00 1206

RSCLK0

RFS0

DR0SEC DR0PRI

Approvals Date

Drawn Checked Engineering

JSZ

10/10/03

ANALOG DEVICES

Title

ADSP-BF561 EZ-KIT LITE:

Size

Date

Board No.

5-12-2004_16:35 12 18

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

EXTENDER CARD CONNECTORS

A0185-2003

Sheet of

Rev

1.3A

A B C D

Page 89

A B C D

2.5A FUS001

7.5V_POWER CON005

2.5MM_JACK

SHGND

C153 1000PF 1206

UNREG_IN

C160 1000PF 1206

D2 2A DO-214AA

FER5

CHOKE_COIL 4 1

D3 2A

3.3V

DO-214AA

R157 100K 1206

NOTE: R252 or R253 gets populated

3 2

UNREG_IN

CT23 10UF C

C122

0.1UF 805

Default is R252 IN and R253 OUT

R252

0.00 805

VR1

3 2

INPUT OUTPUT1

OUTPUT2

ADP3339AKC-5 SOT-223

R83

0.00 805

GND

DSP_VDD_EXT

DSP_3V_VOUT

CT24 10UF C

R163

0.00 1206

C29

0.1UF 805

FER6 600 1206

A5V

DSP_VCORE

UNREG_IN

VR3

3 2

INPUT OUTPUT1

GND

C32 1UF 805

DSP_VDD_INT

OUTPUT2

ADP3338AKC-33 SOT-223

TP7

DSP_VDD_EXT

CT17 10UF C

R73

0.00 1206

3V_B

C35

0.1UF 805

FER16 600 1206

A3V

VR6

3 2

INPUT OUTPUT1

GND

UNREG_IN D4

R79

0.00 805

C43

2.2UF 805

CT20 10UF C

VR5

VIN

SHDN

SYNC

GND

LT1765 SO-8

C53

0.1UF 805

BOOST

OUTPUT2

C46 2200PF 1206

ADP3339AKC-33 SOT-223

C170

0.18UF 805

D6 SL22 2A DO-214AA

CMDSH-3 100MA SOD-323

L10

1.5UH IND003

CT21 10UF C

R186

10.0K

1206

R180

17.4K 805

R195

3.32K 805

R253

0.00 805

DNP

C169

4.7UF 805

R74

0.00 805

CT19 100UF C

3.3V

R194

3.32K 805

VROUT

R84

0.00 805

R78 10K 805

C48

0.1UF 805

C45 1UF 805

U29

1 2 3 4

NDS8434A SO-8

VR4

IN1

IN2

GND

ADP3336ARM MSOP8

OUT1 OUT2 OUT3

FBSD

L11 10UH

D5 ZHCS1000 SOT23D 1A

IND001

R75

53.6K 805

R76 1M 805

68UF D

5 6 7 8

1 2 3 56

R77

0.00 805

1V2

CT22

C44 1UF 805

R82

0.00 805

R81

0.00 805

DNP

CT18 10UF C

DSP_VDD_INT

3.3V 3.3V

R52 10K 805

D7 2A DO-214AA

VR2

IN1

IN2

C21 1UF 805

GND

ADP3336ARM MSOP8

OUT1 OUT2 OUT3

FBSD

1.8V

FER4 600

C24 1UF 805

1206

1 2 3 56

R48

76.8K 1206

R56 147K 1206

A1.8V

FER3 600 1206

SHGND

MH4

TP5 TP11TP8

TP10

TP6

TP4

ANALOG

TP9

20 Cotton Road

FER8 600

1206

SHGND

3.3V

VR7

INPUT

6 1

C218

0.47UF 805

OUTPUT

GND

ADP3331ART SOT23-6

ERR

MH2 MH1 MH5MH3

FPGA_1V8

R207 332K 805

R90

0.00 1206

C230

0.47UF 805

R211 340K 805

Nashua, NH 03063

R210 698K 805

Approvals Date

Title

DEVICES

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

PH: 1-800-ANALOGD

POWER

A0185-2003

Sheet of

Rev

1.3A

18135-12-2004_16:35

A B C D

Page 90

A B C D

DSP_VDD_INT

C137

0.01UF 805

3.3V

C126

0.1UF 805

C140

0.01UF 805

C49

0.01UF 805

C135

0.1UF 805

C174

0.01UF 805

C136

0.01UF 805

C30

0.1UF 805

C151

0.1UF 805

C168

0.01UF 805

C179

0.1UF 805

C157

0.01UF 805

C155

0.1UF 805

C175

0.1UF 805

C156

0.01UF 805

C51

0.1UF 805

C31

10UF 1210

C50

10UF 1210

C47

10UF 1210

C173

0.01UF 805

C154

0.01UF 805

C145

0.1UF 805

C183

0.1UF 805

DSP_VDD_EXT

C172

0.1UF 805

ADSP-DM203

C184

0.1UF 805

C178

0.1UF 805

C152

0.1UF 805

C185

0.01UF 805

C176

0.01UF 805

C186

0.01UF 805

C138

0.01UF 805

C201

0.01UF 805

C52

0.1UF 805

C200

0.01UF 805

C164

0.1UF 805

C182

0.01UF 805

C139

0.1UF 805

3.3V 3.3V3.3V3.3V3.3V

C171

0.1UF 805

0.01UF 805

C177

0.1UF 805

C167

0.1UF 805

C256C180

0.01UF 805

C146

0.01UF 805

A5V A5V

C41

0.01UF 805

C125

0.22UF 805

C106

0.22UF 805

C69

0.01UF 805

AGND

U12

ADG752 ADG752

27MHZ OSC

3.3V

C134

0.01UF 805

C19

0.1UF 805

AD1836

U14

IDT2305

C37

0.1UF 805

A5V

C131

0.1UF 805

AGND

C22

0.1UF 805

M29W640D

A5V

C162

0.22UF 805

AGND

C107

0.22UF 805

C108

0.22UF 805

AGND AGND AGND

U15 U17U16 U20U18

C143

0.22UF 805

AGND

AD8606 AD8606AD8606AD8606 AD8606 AD8061AD8061

A5V

AD8606

U19

C129

0.22UF 805

A5V

AGND

C104

0.22UF 805

3.3V 3.3V 3.3V

C20

0.1UF 805

SN74AHC1G08

U21

SDRAM

A3V A3V A3VA5V A5VA5V

C71

0.1UF 805

AGND2

C75

0.01UF 805

74LVC00AD

C85 805

AD8061

U23 U24U22

0.01UF0.1UF 805

74LVC14A

U10 AD8606

C83C70

0.1UF 805

AGND2AGND2

AD8606

C149

0.01UF 805

AGND

U13

C150

0.01UF 805

U26U25

C101

0.01UF 805

C114

0.01UF 805

3V_B

C91

0.1UF 805

ADV7179

U27

C89

0.1UF 805

C102

0.1UF 805

C90

0.1UF 805

C109

0.1UF 805

C189

0.1UF 805

3.3V 3.3V3.3V3.3V3.3V DVDD_ADV7183

C110

0.1UF 805

C191

0.1UF 805

C113 C112

0.01UF 805

C202

0.01UF 805

ADV7183

U28

3.3V

0.01UF 805

C203

0.01UF 805

C87

0.1UF 805

C190

0.01UF 805

C111

0.1UF 805

C187

0.01UF 805

C88

0.1UF 805

C188

0.01UF 805

ADM708SAR

U29

C249

0.01UF 805

ADM3202

U30

C141

0.01UF 805

C181

0.01UF 805

IDT74FCT3244APY

U31

3.3V 3.3V 3.3V

C127

0.01UF 805

IDT74FCT3244APY ADG752 ADG752

C165

0.01UF 805

U40 U45U36

IDT2305

U46

C27

0.1UF 805

C166

0.01UF 805

ANALOG DEVICES

3.3V

C28

0.01UF 805

39MHZ OSC

U54

C132

0.1UF 805

20 Cotton Road Nashua, NH 03063 PH: 1-800-ANALOGD

Title

ADSP-BF561 EZ-KIT LITE:

Size

Board No.

Date

DECOUPLING CAPS

A0185-2003

SDRAM

U53

Approvals Date

Drawn Checked Engineering

JSZ

10/10/03

A B C D

Sheet of

Rev

1.3A

18145-12-2004_16:35

Page 91

A B C D

All USB interface circuitry is considered propreitary andh has been omitted from this schematic

When designin your JTAG interface please refer to the Engineer to Engineer Note EE-68 which can be found at http://www.analog.com

3.3V EMULATOR_TMS

USB_TMS

USB_TCK

R239 10K 805

R241 10K 805

1 3 5 7

9 11 13

IDC7X2 7X2

2 4 6 8 10 12 14

USB_TRST

USB_TDI

EMULATOR_EMU

USB_EMU

EMULATOR_TDO

USB_TDO

EMULATOR_TCK

EMULATOR_TRST

EMULATOR_TDI

3.3V

R201 10K 805

DSP JTAG HEADER

U36

I0A

I1A

I0B

I1B

I0C

I1C

I0D

I1D

E ADG774A

QSOP16

U37

I0A

I1A

I0B

I1B

I0C

I1C

I0D

I1D

R87

0.00 805

TMS

TCK

TRST

TDI

EMU

TDO

ADG774A QSOP16

3.3V

C209

0.1UF0.1UF 402

C196

0.1UF 402

3.3V3.3V

C195 402

ADG774A12.288MHz ADG774A

ANALOG

20 Cotton Road Nashua, NH 03063

Approvals Date

Title

DEVICES

ADSP-BF561 EZ-KIT LITE:

Drawn Checked

JSZ

10/10/03

Size

Board No.

Engineering

Date

12-11-2003_13:22 15 18

PH: 1-800-ANALOGD

DEBUG AGENT - JTAG

A0185-2003

Sheet of

Rev

1.3A

A B C D

Page 92

IINDEX

AD1836A, audio codec, 1-10, 2-3, 2-12 address bus (A25-A2), 2-3 ADSP-BF561 processor

audio interface, see SPORT0 core voltage, 2-2 External Bus Interface Unit (EBIU), 2-3 external memory, 1-6 IO voltage, 2-2 parallel peripheral interfaces (PPIs), 2-6 peripheral ports, xii SDRAM memory map, 1-7

see also input clock ADV7179, video encoder, 1-11, 2-7, 2-10 ADV7183A, video decoder, 1-11, 2-8, 2-10 ~AMS0, memory select pin, 1-7 ASYNC memory bank 0, 1-6 audio

applications, xii

connectors (J4, J5), 2-18

interface, see SPORT0

see AD1836A

background telemetry channel (BTC), 1-13 bill of materials, A-1 boot mode switch (SW3), 2-11

clock

frequency, 1-8 PPI interfaces, 2-13 select switch (SW5), 2-13

source setup, 2-13 codecs, see AD1836A, ADV7179, ADV7183A connectors, 1-3, 2-17

J1-3 (expansion interface), 2-9

J4-5 (audio), 2-18

J6 (video), 2-18

J7 (power), 2-18

J8 (USB), 2-19

P4 (JTAG), 2-9, 2-20

P9 (SPORT0), 2-20

RS232 (P2), 2-20 contents, EZ-KIT Lite package, 1-2 control bus, 2-3 customer support, xiv cycle counters, 1-16

D15-8 pins

PPI0, 1-9

PPI1, 1-9 data bus, 2-3, 2-6 default configuration, 1-3 DIP switches, 2-10

see also SW disabling breakpoints in shared memory, 1-16

ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-1

Page 93

INDEX

EBIU_SDBCTL register, 1-8, 1-9 EBIU_SDGCTL register, 1-8, 1-9 EBIU_SDRRC register, 1-8, 1-9 evaluation license restrictions, 1-6 example programs, 1-12 expansion

connectors (J3-1), 2-3

interface, 2-3, 2-8, 2-17 External Bus Interface Unit (EBIU), 2-3 external memory, 1-6, 2-9 EZ-KIT Lite board

architecture, 2-2

features, x

features, EZ-KIT Lite board, x Field pin, 2-4 FIO0_FLAG_D register, 1-9 flag pins, see programmable flags (PFs) flash

memory, xi, 2-3

ports PB39-P32, 2-16

ports PB47-P40, 2-16 flash programmer, 1-12

general purpose IO, 1-9 graphical user interface (GUI), 1-13

Help, online, xix HSYNC signal, 2-6, 2-7

input clock, 2-2, 2-6, 2-7 IO voltage, 2-2

JTAG

connector (P4), 2-20 emulation port, 2-9

jumper settings, 1-3, 2-10

LEDs, 1-3, 1-9, 2-14

J7 (power), 2-15 LED12-5, 2-5, 2-16 LED20-13, 2-5, 2-16 LED2-3, 2-15 LED4, 1-5, 2-16

memory

external memory map, 1-6 select pins, see ~AMS0 &~SMS0 writes, 1-16

notation conventions, xxi

~OE (ADV7183A video decoder) signal, 2-10 opcode scan method, 1-16

P3 (SPORT) connector, 2-3 package contents, 1-2 Parallel Peripheral Interfaces (PPIs), xii, 1-11,

1-12, 2-6

clock select switch (SW5), 2-13 see also PPI0 and PPI1

PFs, see programmable flags

I-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Page 94

INDEX

power

connector (J7), 2-18 specifications, 2-19 supply, 2-19

PPI0, 1-9, 1-11, 2-6, 2-8, 2-16

Clock, primary processor pin, 2-7 primary processor pins 7-0, 2-6 SYNC1, primary processor pin, 2-6 SYNC2, primary processor pin, 2-7

PPI1, 1-9, 2-6

Clock, primary processor pin, 2-7 primary processor pins 7-0, 2-6 SYNC1 signal, 2-7, 2-11 SYNC2 signal, 2-7, 2-11 video output, 2-7

primary processor pins (PPIs)

PPI0 Clock, 2-7 PPI0 SYNC1, 2-6 PPI0 SYNC2, 2-7 PPI1 Clock, 2-7 PPI1 SYNC1, 2-7 PPI1 SYNC2, 2-7 PPIs bits 7-0, 2-6

processor SDRAM map, see ADSP-BF561

processor

programmable flags (PFs), 2-4, 2-16

PF0-1, 1-12, 2-4 PF12-PF9, 2-5 PF13, 1-11, 2-5 PF14, 1-11, 2-5 PF15, 1-11, 2-5 PF16-19, 2-5 PF2, 1-12, 2-4, 2-10 PF20-31, 2-5 PF3, 2-4 PF39-32, 2-5 PF4, 1-10, 2-3, PF47-40, 2-5 PF5-8, 1-9, 2-4, 2-12, 2-15 see also push buttons

2-4

push buttons, 1-9, 2-14

connecting to PF pins, 2-15 see also SW

registering, this product, 1-3 reset

cycle counters, 1-16 options, 1-14 processor, 2-15

push button (SW1), 2-14 RFS0, signal, 2-12 RSCLK0

signals, 2-12

SDRAM, xi, 1-6, 1-7

default settings, 1-8

optimum settings, 1-9 SDRAM memory, 1-7

core MMRs, 1-7

data bank A SRAM, 1-7

data bank B SRAM, 1-7

instruction SRAM, 1-7

instruction SRAM/CACHE, 1-7

reserved, 1-7

scratch pad SRAM, 1-7

system MMRs, 1-7 serial

clock (SCL), 1-12

data (SDAT), 1-12 Serial Peripheral Interconnect (SPI), 2-3 setting target options, 1-14 ~SMS0, memory select pin, 1-7 SPI interface, 2-4 SPORT0, xii, 1-10, 2-3, 2-12, 2-20 starting EZ-KIT Lite, 1-5 SW1, reset push button, 2-14

ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-3

Page 95

INDEX

SW10-11, test DIP switches, 2-13 SW2, video config switch, 1-11, 2-6, 2-7, 2-8,

2-10

SW3, boot mode switch, 2-10, 2-11 SW4, enable push button, 1-10, 2-12, 2-15 SW5, clock select switch, 2-6, 2-13 SW6-9, general input push buttons, 2-4, 2-12,

2-15

synchronization (SYNC1-2) signals, 2-6 system

architecture, EZ-KIT Lite board, 2-2

target options

miscellaneous, 1-15 on emulator exit, 1-14 reset, 1-14

XML file, 1-15 Target Options dialog box, 1-14 test DIP switches (SW10, SW11), 2-13 TFS0, signal, 2-12 time-division multiplexed (TDM) mode, 1-10 Timer 0-6, 2-4 Timer 1, 2-4 Timer 10, 2-7 Timer 11, 2-7 Timer 2, 2-4 Timer 3, 2-4 Timer 4, 2-4 Timer 5, 2-4 Timer 6, 2-4 Timer 8, 2-6 Timer 9, 2-7 TSCLK0

signal, 2-12 two-wire interface (TWI) mode, 1-10, 2-12

UART, xi, xii, 2-5, 2-8 USB

cable, 1-3 connector (P7), 2-19, 2-20 interface, 2-9 interface chip (U34), 2-14, 2-15 monitor LED (LED4), 2-16

user LEDs

LED12-5, 2-16 LED20-13, 2-16 see also LEDs

video, 1-11

blanking control, 2-7 configuration switch (SW2), 2-10 connecting to PPI, xii connector (J6), 2-18 encoder/decoder, xii input mode, 2-8 interface, 1-11 output mode, 2-7

VisualDSP++

documentation, xx online Help, xix session, 1-7

VSYNC signal, 2-7

XML

file version, 1-15 parser version, 1-15 register reset values, 1-16

I-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Datasheet ADSP-BF561 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

PREFACE

Purpose of This Manual

Intended Audience

Manual Contents

What’s New in This Manual

Technical or Customer Support

Supported Processors

Product Information

MyAnalog.com

Processor Product Information

Related Documents

Online Technical Documentation

Accessing Documentation From VisualDSP++

Accessing Documentation From Windows

Accessing Documentation From Web

Printed Manuals

VisualDSP++ Documentation Set

Hardware Tools Manuals

Processor Manuals

Data Sheets

Notation Conventions

1 USING EZ-KIT LITE

Package Contents

Default Configuration

Figure 1-1. EZ-KIT Lite Hardware Setup

Installation and Session Startup

Evaluation License Restrictions

External Memory

Figure 1-2. ADSP-BF561 Processor Internal Memory Map

LEDs and Push Buttons

Audio Interface

Video Interface

Example Programs

Flash Programmer Utility

Background Telemetry Channel

VisualDSP++ Interface

Target Options

Figure 1-3. Target Options Dialog Box

Reset Options

On Emulator Exit

XML File

Other Options

Restricted Software Breakpoints

System Architecture

Figure 2-1. System Architecture

External Bus Interface Unit

SPORT0 Audio Interface

SPI Interface

Programmable Flags

PPI Interfaces

Video Output (PPI1)

Video Input (PPI0)

UART Port

Expansion Interface

JTAG Emulation Port

Jumper and DIP Switch Settings

Figure 2-2. DIP Switch Locations

Video Configuration Switch (SW2)

Boot Mode Switch (SW3)

Push Button Enable Switch (SW4)

PPI Clock Select Switch (SW5)

Test DIP Switches (SW10 and SW11)

LEDs and Push Buttons

Figure 2-3. LED and Push Button Locations

Reset Push Button (SW1)

Programmable Flag Push Buttons (SW9–6)

Power LED (J7)

Reset LEDs (LED2 and LED3)

USB Monitor LED (LED4)

User LEDs (LED12–5, LED20–13)

Connectors

Expansion Interface (J3–1)

Audio (J4 and J5)

Video (J6)

Power (J7)