Datasheet ADSP-BF531 Datasheet (Analog Devices)

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Page 1

Blackfin

ADSP-BF531/ADSP-BF532/ADSP-BF533

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of pro-

gramming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core V

3.3 V and 2.5 V tolerant I/O 160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead

LQFP packages

MEMORY

Up to 148K bytes of on-chip memory:

16K bytes of instruction SRAM/Cache 64K bytes of instruction SRAM 32K bytes of data SRAM/Cache 32K bytes of data SRAM

4K bytes of scratchpad SRAM Two dual-channel memory DMA controllers Memory management unit providing memory protection

with on-chip voltage regulation

Embedded Processor

External memory controller with glueless support for

SDRAM, SRAM, FLASH, and ROM

Flexible memory booting options from SPI and external

memory

PERIPHERALS

Parallel peripheral interface (PPI)/GPIO, supporting

ITU-R 656 video data formats

Two dual-channel, full duplex synchronous serial ports, sup-

porting eight stereo I 12-channel DMA controller SPI-compatible port Three timer/counters with PWM support UART with support for IrDA Event handler Real-time clock Watchdog timer Debug/JTAG interface On-chip PLL capable of 1x to 63x frequency multiplication Core timer

S channels

JTAG TEST AND

EMULATION

VOLTAGE

REGULATOR

INSTRUCTION

MEMORY

CORE/SYSTEM BUS INTERFACE

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

EVENT

CONTROLLER/

CORE TIMER

MMU

CONTROLLER

BOOT ROM

Figure 1. Functional Block Diagram

DMA

WATCHDOG TIMER

REAL-TIME CLOCK

UART PORT

IRDA

DATA

MEMORY

TIMER0, TIMER1,

TIMER2

PPI / GPIO

SERIAL PORTS (2)

SPI PORT

EXTERNAL PORT

FLASH, SDRAM

CONTROL

Page 2

ADSP-BF531/ADSP-BF532/ADSP-BF533

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor

Peripherals ....................................................... 3

Blackfin Processor Core .......................................... 3

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 8

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Port ......................... 9

UART Port ........................................................ 10

Programmable Flags (PFx) .................................... 10

Parallel Peripheral Interface ................................... 10

Dynamic Power Management ................................ 11

Voltage Regulation .............................................. 12

Clock Signals ..................................................... 13

Booting Modes ................................................... 13

Instruction Set Description ................................... 14

Development Tools ............................................. 14

Designing an Emulator-Compatible Processor Board .. 15

Pin Descriptions .................................................... 16

Specifications ........................................................ 19

Recommended Operating Conditions ...................... 19

Electrical Characteristics ....................................... 19

Absolute Maximum Ratings .................................. 20

ESD Sensitivity ................................................... 20

Timing Specifications .......................................... 21

Clock and Reset Timing .................................... 22

Asynchronous Memory Read Cycle Timing ........... 23

Asynchronous Memory Write Cycle Timing .......... 24

SDRAM Interface Timing .................................. 25

External Port Bus Request and Grant Cycle Timing .. 26

Parallel Peripheral Interface Timing ..................... 27

Serial Ports ..................................................... 28

Serial Peripheral Interface (SPI) Port

—Master Timing .......................................... 32

Serial Peripheral Interface (SPI) Port

—Slave Timing ............................................. 33

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 34

Programmable Flags Cycle Timing ....................... 35

Timer Cycle Timing .......................................... 36

JTAG Test and Emulation Port Timing .................. 37

Output Drive Currents ......................................... 38

Power Dissipation ............................................... 40

Test Conditions .................................................. 41

Environmental Conditions .................................... 44

160-Lead BGA Pinout ............................................. 45

169-Ball PBGA Pinout ............................................. 48

176-Lead LQFP Pinout ............................................ 50

Outline Dimensions ................................................ 52

Ordering Guide ..................................................... 55

REVISION HISTORY

1/05—Revision A: Changed from Rev. 0 to Rev. A

Deleted tolerance from voltage regulator description and

changed part in (Figure 7) Voltage Regulator Circuit........12

Defined new nominal voltage for ADSP-BF533 in Recom-

mended Operating Conditions....................................19

Clarified test voltage in Table 10, Table 11, Table12 .........21

Changed data for 400 MHz in (Table 30) Internal Power Dissi-

pation ...................................................................40

Changed package height in (Figure 46) 160-Ball Mini-BGA

(BC-160)................................................................52

Changed operating voltage for ADSP-BF532 and ADSP-BF533

parts and adds two part numbers to Ordering Guide.........55

Changes to format throughout document.

3/04—Revision 0: Initial Version

Rev. A | Page 2 of 56 | January 2005

Page 3

GENERAL DESCRIPTION

ADSP-BF531/ADSP-BF532/ADSP-BF533

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISClike microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.

Table 1. Processor Comparison

ADSP-BF531 ADSP-BF532 ADSP-BF533

Maximum Performance

Instruction SRAM/Cache

Instruction SRAM

Data SRAM/Cache

Data SRAM 32K bytes Scratchpad 4K bytes 4K bytes 4K bytes

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.

400 MHz 800 MMACs

16K bytes 16K bytes 16K bytes

16K bytes 32K bytes 64K bytes

16K bytes 32K bytes 32K bytes

400 MHz 800 MMACs

600 MHz 1200 MMACs

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances.

SYSTEM INTEGRATION

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are highly integrated system-on-a-chip solutions for the next generation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface.

ADSP-BF531/ADSP-BF532/ADSP-BF533 PROCESSOR PERIPHERALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the functional block diagram in Figure 1 on Page 1). The general- purpose peripherals include functions such as UART, timers with PWM (pulse width modulation) and pulse measurement capability, general-purpose flag I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. In addition to these generalpurpose peripherals, the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor contains high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources; and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, real-time clock, and timers, are supported by a flexible DMA structure. There is also a separate memory DMA channel dedicated to data transfers between the processor’s various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor includes an on-chip voltage regulator in support of the ADSPBF531/ADSP-BF532/ADSP-BF533 processor dynamic power management capability. The voltage regulator provides a range of core voltage levels from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user’s discretion.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing

Rev. A | Page 3 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

tasks. These include bit operations such as field extract and population count, modulo 2 saturation and rounding, and sign/exponent detection. The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).

Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information.

In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.

The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle.

multiply, divide primitives,

The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3 on Page 5,

Figure 4 on Page 5, and Figure 5 on Page 6.

The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory.

The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.

Internal (On-Chip) Memory

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has three blocks of on-chip memory providing high bandwidth access to the core.

The first is the L1 instruction memory, consisting of up to 80K bytes SRAM, of which 16K bytes can be configured as a four way set-associative cache. This memory is accessed at full processor speed.

The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

The external bus interface can be used with both asynchronous devices such as SRAM, FLASH, EEPROM, ROM, and I/O devices, and synchronous devices such as SDRAMs. The bus width is always 16 bits. A1 is the least significant address of a 16bit word. 8-bit peripherals should be addressed as if they were 16-bit devices, where only the lower eight bits of data should be used.

Rev. A | Page 4 of 56 | January 2005

Page 5

LD032BITS

LD132BITS

SD 3 2 BI TS

R7 R6 R5 R4 R3

R2 R1

R7.H R6.H R5.H R4.H R3.H

R2.H R1.H

R0.H

ADSP-BF531/ADSP-BF532/ADSP-BF533

ADDRESS ARITHMETIC UNIT

SP FP P5 P4 P3 P2 P1 P0

R7.L R6.L R5.L R4.L R3.L

R2.L R1.L

R0.L

I3 I2 I1 I0

BARREL SHIF TER

B3 L2 L1 L0

A0 A1

88 8 8

40 40

DAG0 DA G 1

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

CONTROL

UN IT

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

INSTRUCTION SRAM (64K BYTE)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

SDRAM MEMORY (16M BYTE TO 128M BYTE)

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

P A M

Y R O M E M L A N R E T N

P A M

Y R O M E M L A N R E T X E

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

INSTRUCTION SRAM (32K BYTE)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYT E)

ASYNC MEMORY BANK 2 (1M BYT E)

ASYNC MEMORY BANK 1 (1M BYT E)

ASYNC MEMORY BANK 0 (1M BYT E)

RESERVED

SDRAM MEMORY (16M BYTE TO 128M BYTE)

P A M

Y R O M E M

L A N R E T N

P A M

Y R O M E M L A N R E T X E

Figure 3. ADSP-BF533 Internal/External Memory Map

Rev. A | Page 5 of 56 | January 2005

Figure 4. ADSP-BF532 Internal/External Memory Map

Page 6

ADSP-BF531/ADSP-BF532/ADSP-BF533

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

Figure 5. ADSP-BF531 Internal/External Memory Map

The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance.

The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully populated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one of which contains the control MMRs for all core functions, and the other of which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

RESERVED

INSTRUCTION SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

SDRAM MEMORY (16M BYTE TO 128M BYTE)

P A M

Y R O M E M L A N R E T N

P A M

Y R O M E M

L A N R E T X E

Booting

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on

Page 13.

Event Handling

The event controller on the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor handles all asynchronous and synchronous events to the processor. The ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events:

• Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface.

• Reset – This event resets the processor.

• Non-Maskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system.

• Exceptions – Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF531/ADSP-BF532/

Rev. A | Page 6 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

ADSP-BF533 processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities.

Table 2. Core Event Controller (CEC)

Priority (0 is Highest)

0Emulation/Test ControlEMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3ExceptionEVX 4 Reserved 5 Hardware Error IVHW 6Core TimerIVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15

Event Class EVT Entry

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC.

Event Control

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event Default Mapping

PLL Wakeup IVG7 DMA Error IVG7 PPI Error IVG7 SPORT 0 Error IVG7 SPORT 1 Error IVG7 SPI Error IVG7 UART Error IVG7 Real-Time Clock IVG8 DMA Channel 0 (PPI) IVG8 DMA Channel 1 (SPORT 0 RX) IVG9 DMA Channel 2 (SPORT 0 TX) IVG9 DMA Channel 3 (SPORT 1 RX) IVG9 DMA Channel 4 (SPORT 1 TX) IVG9 DMA Channel 5 (SPI) IVG10 DMA Channel 6 (UART RX) IVG10 DMA Channel 7 (UART TX) IVG10 Timer 0 IVG11 Timer 1 IVG11 Timer 2 IVG11 PF Interrupt A IVG12 PF Interrupt B IVG12 DMA Channels 8 and 9

(Memory DMA Stream 1) DMA Channels 10 and 11

(Memory DMA Stream 0) Software Watchdog Timer IVG13

IVG13

the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7.

• SIC interrupt mask register (SIC_IMASK) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the

Rev. A | Page 7 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event.

• SIC interrupt status register (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.

• SIC interrupt wakeup enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 11.)

Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor’s internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor DMA controller supports both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on the fly.

Examples of DMA types supported by the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor DMA controller include:

• A single, linear buffer that stops upon completion

• A circular, autorefreshing buffer that interrupts on each full or fractionally full buffer

• 1D or 2D DMA using a linked list of descriptors

• 2D DMA using an array of descriptors, specifying only the base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.

REAL-TIME CLOCK

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor realtime clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hour counter, and a 32,768 day counter.

When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.

The stopwatch function counts down from a programmed value, with one second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated.

Like other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered-down state.

Connect RTC pins RTXI and RTXO with external components as shown in Figure 6.

Rev. A | Page 8 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

RTXI

C1 C2

SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 PF C2 = 22 PF R1 = 10 M OHM

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

Figure 6. External Components for RTC

RTXO

WATCHDOG TIMER

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum frequency of f

SCLK

TIMERS

There are four general-purpose programmable timer units in the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor. Three timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK.

The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel.

The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals.

In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTS)

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:

S capable operation.

•I

• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels

of I

S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f

/131,070) Hz to (f

SCLK

/2) Hz.

• Word length – Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync.

• Companding in hardware – Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.

• DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through DMA.

• Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS

) lets other SPI devices select the proces-

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ADSP-BF531/ADSP-BF532/ADSP-BF533

sor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.

The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI’s DMA controller can only service unidirectional accesses at any given time.

The SPI port’s clock rate is calculated as:

SCLK

SPI Clock Rate

---------------------------------

2 SPI_Baud×

Where the 16-bit SPI_Baud register contains a value of 2 to 65,535.

During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.

UART PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:

• Supporting bit rates ranging from (f (f

/16) bits per second.

SCLK

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

----------------------------------------------- -

UART Clock Rate

16 UART_Divisor×

/1,048,576) to

SCLK

Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8bits).

In conjunction with the general-purpose timer functions, autobaud detection is supported.

The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA

) Serial Infrared Physi-

cal Layer Link Specification (SIR) protocol.

PROGRAMMABLE FLAGS (PFX)

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has 16 bidirectional, general-purpose programmable flag (PF15– 0) pins. Each programmable flag can be individually controlled by manipulation of the flag control, status and interrupt registers:

• Flag direction control register – Specifies the direction of each individual PFx pin as input or output.

• Flag control and status registers – The ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor employs a “write one to modify” mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags. Four control registers are provided. One register is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. Reading the flag status register allows software to interrogate the sense of the flags.

• Flag interrupt mask registers – The two flag interrupt mask registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two flag control registers that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable interrupt function, and the other flag interrupt mask register clears bits to disable interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts.

• Flag interrupt sensitivity registers – The two flag interrupt sensitivity registers specify whether individual PFx pins are level- or edge-sensitive and specify—if edge-sensitive— whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The processor provides a parallel peripheral interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other generalpurpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate.

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ADSP-BF531/ADSP-BF532/ADSP-BF533

In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported.

Three distinct ITU-R 656 modes are supported:

• Active video only – The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI.

• Vertical blanking only – The PPI only transfers vertical blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines.

• Entire field – The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals.

Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle:

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. DMA access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the full-on or sleep modes.

Table 4. Power Settings

Mode PLL PLL

Bypassed

Full-On Enabled No Enabled Enabled On Active Enabled/

Disabled Sleep Enabled Disabled Enabled On Deep Sleep Disabled Disabled Disabled On Hibernate Disabled Disabled Disabled Off

Yes Enabled Enabled On

Core Clock (CCLK)

System Clock (SCLK)

Core Power

Hibernate Operating Mode—Maximum Static Power Savings

The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (V

) to 0 V to provide the lowest static power

DDINT

dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved. Since V

is still supplied in this mode, all of

DDEXT

the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up either by a realtime clock wakeup or by asserting the RESET

pin.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the sleep mode, assertion of wakeup will

Rev. A | Page 11 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

cause the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled, the processor will transition to the active mode.

When in the sleep mode, system DMA access to L1 memory is not supported.

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but will not be able to access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt (RESET

) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode. assertion of RESET

while in deep sleep mode causes the proces-

sor to transition to the full-on mode.

Power Savings

As shown in Table 5, the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor supports three different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management, without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains.

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC V RTC internal logic and crystal I/O V All other I/O V

DDINT

DDRTC

DDEXT

The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic.

The dynamic power management feature of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor allows both the processor’s input voltage (V (f

) to be dynamically controlled.

CCLK

) and clock frequency

DDINT

The savings in power dissipation can be modeled using the power savings factor and % power savings calculations.

The power savings factor is calculated as:

power savings factor

CCLKRED

---------------------

CCLKNOM

DDINTRED

⎛⎞

--------------------------

⎝⎠

DDINTNOM

RED

⎞

⎛

------------ -

⎠

⎝

NOM

where the variables in the equations are:

•f

•V

•T

is the nominal core clock frequency

CCLKNOM

is the reduced core clock frequency

CCLKRED

is the nominal internal supply voltage

DDINTNOM

is the reduced internal supply voltage

DDINTRED

is the duration running at f

NOM

is the duration running at f

RED

CCLKNOM

CCLKRED

The percent power savings is calculated as:

% power savings 1 power savings factor–()100%×=

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator that can generate processor core voltage levels 0.85 V to 1.2 V from an external 2.25 V to 3.6 V supply. Figure 7 shows the typical external components required to complete the power management system. voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (V

can still be applied, eliminating the need for external

DDEXT

buffers. The voltage regulator can be activated from this powerdown state either through an RTC wakeup or by asserting RESET

, which will then initiate a boot sequence. The regulator

can also be disabled and bypassed at the user’s discretion.

DDEXT

DDINT

1–0

OUT

See EE-228: Switching Regulator Design Considerations for ADSP-BF533

Blackfin Processors.

The regulator controls the internal logic

) supplied. While in hibernation,

DDEXT

100µF

10µH

0.1µF

100µF

1µF

NOTE: VR

OUT

AND DESIGNER S HOULD MINIMIZE T RACE LENGTH TO FDS 9431A.

Figure 7. Voltage Regulator Circuit

ZHCS1000

EXTERNAL CO MPONENTS

1–0 SHOULD BE TIED T OGETHER EXTERNALLY

2.25V TO 3.6V INPUT VOLTAG E RANGE

FDS9431A

Rev. A | Page 12 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

133

CLOCK SIGNALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.

If an external clock is used, it must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 8. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.

CLKIN

CLKOUTXTAL

into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Table 6. Example System Clock Ratios

Signal Name SSEL3–0

Divider Ratio VCO/SCLK

Example Frequency Ratios (MHz)

VCO SCLK

0001 1:1 100 100 0011 3:1 400 133 1010 10:1 500 50

The maximum frequency of the system clock is f

. Note that

SCLK

the divisor ratio must be chosen to limit the system clock frequency to its maximum of f

. The SSEL value can be changed

SCLK

dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

Figure 8. External Crystal Connections

As shown in Figure 9 on Page 13, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register.

“FINE” ADJUSTMENT

RE QUIRES PLL SEQ UENCING

CLKIN

PLL

0. 5×−64×

Figure 9. Frequency Modification Methods

VCO

SCL K ≤ CC L K SCL K ≤

“COARSE” ADJUSTMENT

ON-THE-FL Y

÷1,2,4,8

÷1:15

MHZ

CC LK

SCLK

Signal Name CSEL1–0

Divider Ratio VCO/CCLK

Example Frequency Ratios

VCO CCLK

00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25

BOOTING MODES

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has two mechanisms (listed in Table 8) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute from external memory, bypassing the boot sequence.

Table 8. Booting Modes

BMODE1–0 Description

00 Execute from 16-bit external memory (bypass

boot ROM) 01 Boot from 8-bit or 16-bit FLASH 10 Boot from SPI host slave mode) 11 Boot from SPI serial EEPROM (8-, 16-, or 24-bit

address range)

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed

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ADSP-BF531/ADSP-BF532/ADSP-BF533

The BMODE pins of the reset configuration register, sampled during power-on resets and software-initiated resets, implement the following modes:

• Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit or 16-bit external flash memory – The flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from SPI serial EEPROM (8, 16, or 24-bit addressable) – The SPI uses the PF2 output pin to select a single SPI EEPROM device, submits successive read commands at addresses 0x00, 0x0000, and 0x000000 until a valid 8-, 16-, or 24-bit addressable EEPROM is detected, and begins clocking data into the beginning of L1 instruction memory.

For each of the boot modes, a 10-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM.

In addition, Bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.

The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations.

• A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model.

• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and supervisor stack pointers.

• Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.

DEVELOPMENT TOOLS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor is supported with a complete set of CROSSCORE hardware development tools, including Analog Devices emulators and VisualDSP++

‡

development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to processor assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

†

software and

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. A | Page 14 of 56 | January 2005

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ADSP-BF531/ADSP-BF532/ADSP-BF533

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory, and stacks.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs.

• Maintain a one-to-one correspondence with the tool’s command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Components can be downloaded from the Web and dropped into the application. Component archives can be published from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, and examine runtime stack and heap usage.

The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD

The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

Rev. A | Page 15 of 56 | January 2005

Page 16

ADSP-BF531/ADSP-BF532/ADSP-BF533

PIN DESCRIPTIONS

ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pin definitions are listed in Table 9.

All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins, which are driven high.

is active, then the memory pins are also three-stated. All

If BR unused I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs as noted in the table footnotes.

In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics.

Table 9. Pin Descriptions

Pin Name I/O Function Driver Type

Memory Interface

ADDR19–1 O Address Bus for Async/Sync Access A DATA15–0 I/O Data Bus for Async/Sync Access A ABE1–0/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A

BR BG

IBus Request OBus Grant A

BGH OBus Grant Hang A

Asynchronous Memory Control

AMS3–0

OBank Select A

ARDY I Hardware Ready Control AOE

OOutput Enable A ARE ORead Enable A AWE OWrite Enable A

Synchronous Memory Control

SRAS

O Row Address Strobe A SCAS O Column Address Strobe A SWE OWrite Enable A SCKE O Clock Enable A CLKOUT O Clock Output B SA10 O A10 Pin A SMS OBank Select A

Timers

TMR0 I/O Timer 0 C TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1 C TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2 C

Rev. A | Page 16 of 56 | January 2005

Page 17

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function Driver Type

Parallel Peripheral Interface Port/GPIO

PF0/SPISS

I/O Programmable Flag 0/SPI Slave Select Input C PF1/SPISEL1/TMRCLK I/O Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference C PF2/SPISEL2 I/O Programmable Flag 2/SPI Slave Select Enable 2 C PF3/SPISEL3/PPI_FS3 I/O Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3 C PF4/SPISEL4/PPI15 I/O Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15 C PF5/SPISEL5/PPI14 I/O Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14 C PF6/SPISEL6/PPI13 I/O Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13 C PF7/SPISEL7/PPI12 I/O Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12 C PF8/PPI11 I/O Programmable Flag 8/PPI 11 C PF9/PPI10 I/O Programmable Flag 9/PPI 10 C PF10/PPI9 I/O Programmable Flag 10/PPI 9 C PF11/PPI8 I/O Programmable Flag 11/PPI 8 C PF12/PPI7 I/O Programmable Flag 12/PPI 7 C PF13/PPI6 I/O Programmable Flag 13/PPI 6 C PF14/PPI5 I/O Programmable Flag 14/PPI 5 C PF15/PPI4 I/O Programmable Flag 15/PPI 4 C PPI3–0 I/O PPI3–0 C PPI_CLK I PPI Clock C

Serial Ports

RSCLK0 I/O SPORT0 Receive Serial Clock D RFS0 I/O SPORT0 Receive Frame Sync C DR0PRI I SPORT0 Receive Data Primary DR0SEC I SPORT0 Receive Data Secondary TSCLK0 I/O SPORT0 Transmit Serial Clock D TFS0 I/O SPORT0 Transmit Frame Sync C DT0PRI O SPORT0 Transmit Data Primary C DT0SEC O SPORT0 Transmit Data Secondary C RSCLK1 I/O SPORT1 Receive Serial Clock D RFS1 I/O SPORT1 Receive Frame Sync C DR1PRI I SPORT1 Receive Data Primary DR1SEC I SPORT1 Receive Data Secondary TSCLK1 I/O SPORT1 Transmit Serial Clock D TFS1 I/O SPORT1 Transmit Frame Sync C DT1PRI O SPORT1 Transmit Data Primary C DT1SEC O SPORT1 Transmit Data Secondary C

SPI Port

MOSI I/O Master Out Slave In C

MISO

I/O Master In Slave Out C SCK I/O SPI Clock D

Rev. A | Page 17 of 56 | January 2005

Page 18

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function Driver Type

UART Por t

RX I UART Receive TX O UART Transmit C

Real-Time Clock

RTXI

IRTC Crystal Input

RTXO O RTC Crystal Output

JTAG Port

TCK I JTAG Clock TDO O JTAG Serial Data Out C TDI I JTAG Serial Data In TMS I JTAG Mode Select

TRST EMU

IJTAG Reset OEmulation Output C

Clock

CLKIN I Clock/Crystal Input XTAL O Crystal Output

Mode Controls

RESET NMI

I Reset INonmaskable Interrupt

BMODE1–0 I Boot Mode Strap

Voltage Regulator

VROUT1–0 O External FET Drive

Supplies

V V V

DDEXT

DDINT

DDRTC

PI/O Power Supply P Core Power Supply P Real-Time Clock Power Supply

GND G External Ground

Refer to Figure 26 on Page 38 to Figure 30 on Page 39.

See Figure 25 and Figure 26 on Page 38

This pin should be pulled HIGH when not used.

See Figure 27 and Figure 28 on Page 38

See Figure 29 and Figure 30 on Page 39

See Figure 31 and Figure 32 on Page 39

This pin should always be pulled HIGH through a 4.7 kΩ resistor if booting via the SPI port.

This pin should always be pulled LOW when not used.

This pin should be pulled LOW if the JTAG port will not be used.

Rev. A | Page 18 of 56 | January 2005

Page 19

ADSP-BF531/ADSP-BF532/ADSP-BF533

SPECIFICATIONS

Component specifications are subject to change without notice.

RECOMMENDED OPERATING CONDITIONS

Parameter Minimum Nominal Maximum Unit

DDINT

DDEXT

DDRTC

IHCLKIN

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on

the input V RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR TRST

Parameter value applies to all input and bidirectional pins except CLKIN.

Parameter value applies to CLKIN pin only.

Parameter value applies to all input and bidirectional pins.

DDEXT

, CLKIN, RESET, NMI, and BMODE1–0).

Internal Supply Voltage (ADSP-BF531 and ADSP-BF532) 0.8 1.2 1.32 V Internal Supply Voltage (ADSP-BF533) 0.8 1.26 1.32 V External Supply Voltage 2.25 2.5 or 3.3 3.6 V Real-Time Clock Power Supply Voltage 2.25 3.6 V

2, 4

1, 2

@ V

DDEXT

@ V

=maximum

DDEXT

=maximum

=minimum

DDEXT

(maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0,

DDEXT

, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS,

2.0 3.6 V

2.2 3.6 V –0.3 0.6 V

High Level Input Voltage High Level Input Voltage3 @ V Low Level Input Voltage

, because VOH (maximum) approximately equals V

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Minimum Maximum Unit

IHP

OZH

OZL

Applies to output and bidirectional pins.

Applies to input pins except JTAG inputs.

Applies to JTAG input pins (TCK, TDI, TMS, TRST).

Applies to three-statable pins.

Applies to all signal pins.

Guaranteed, but not tested.

High Level Output Voltage1 Low Level Output Voltage High Level Input Current

High Level Input Current JTAG Low Level Input Current

Three-State Leakage Current

@ V

@ V @ V

@ V Three-State Leakage Current5@ V Input Capacitance

5, 6

fIN = 1 MHz, T

= 3.0V, IOH = –0.5 mA 2.4 V

DDEXT

= 3.0V, IOL = 2.0 mA 0.4 V

DDEXT

= maximum, VIN = VDD maximum 10.0 µA

DDEXT

= maximum, VIN = VDD maximum 20.0 µA

DDEXT

= maximum, VIN = 0 V 10.0 µA

DDEXT

= maximum, VIN = VDD maximum 10.0 µA

DDEXT

= maximum, VIN = 0 V 10.0 µA

DDEXT

= 25°C, VIN = 2.5 V 8.0 pF

AMBIENT

Rev. A | Page 19 of 56 | January 2005

Page 20

ADSP-BF531/ADSP-BF532/ADSP-BF533

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0 SCKE, SA10, SRAS

Parameter Rating

Internal (Core) Supply Voltage (V External (I/O) Supply Voltage (V Input Voltage – 0.5 V to 3.6 V Output Voltage Swing –0.5 V to V Load Capacitance 200 pF ADSP-BF533 Core Clock (CCLK) 600 MHz ADSP-BF532/BF531 Core Clock (CCLK) 400 MHz Peripheral Clock (SCLK) 133 MHz Storage Temperature Range –65ºC to +150ºC Junction Temperature Under Bias 125ºC

, SCAS, SWE, and SMS.

/SDQM1–0, CLKOUT,

)–0.3 V to +1.4 V

DDINT

)–0.3 V to +3.8 V

DDEXT

+0.5 V

DDEXT

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 20 of 56 | January 2005

Page 21

ADSP-BF531/ADSP-BF532/ADSP-BF533

TIMING SPECIFICATIONS

Table 10 through Table 14 describe the timing requirements for

the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock as described

Table 10. Core and System Clock Requirements—ADSP-BF533SKBC600

Parameter Min Max Unit

t t t t t t

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

System Clock Period Maximum of 7.5 or t

SCLK

=1.2 V minimum) 1.67 ns

DDINT

=1.045 V minimum) 2.10 ns

DDINT

=0.95 V minimum) 2.35 ns

DDINT

=0.85 V minimum) 2.66 ns

DDINT

=0.8 V) 4.00 ns

DDINT

Table 11. Core and System Clock Requirements—ADSP-BF533SBBC500 and ADSP-BF533SBBZ500

Parameter Min Max Unit

t t t t t t

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

System Clock Period Maximum of 7.5 or t

SCLK

=1.2 V minimum) 2.0 ns

DDINT

=1.045 V minimum) 2.25 ns

DDINT

=0.95 V minimum) 2.50 ns

DDINT

=0.85 V minimum) 3.00 ns

DDINT

=0.8 V) 4.00 ns

DDINT

in Absolute Maximum Ratings on Page 20, and the voltage controlled oscillator (VCO) operating frequencies described in

Table 13. Table 13 describes phase-locked loop operating

conditions.

CCLK

Table 12. Core and System Clock Requirements—ADSP-BF532/ADSP-BF531 All Package Types

Parameter Min Max Unit

t t t t t t

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

Core Cycle Period (V

CCLK

System Clock Period Maximum of 7.5 or t

SCLK

=1.14 V minimum) 2.5 ns

DDINT

=1.045 V minimum) 2.75 ns

DDINT

=0.95 V minimum) 3.00 ns

DDINT

=0.85 V minimum) 3.25 ns

DDINT

=0.8 V) 4.0 ns

DDINT

CCLK

Table 13. Phase-Locked Loop Operating Conditions

Parameter Min Max Unit

VCO

Voltage Controlled Oscillator (VCO) Frequency 50 Max CCLK MHz

Table 14. Maximum SCLK Conditions

Parameter Condition V

= 3.3 V V

DDEXT

= 2.5 V Unit

DDEXT

MBGA f f

SCLK

≥ 1.14 V 133 133 MHz

DDINT

< 1.14 V 100 100 MHz

DDINT

LQFP f

SCLK

Set Bit 7 (output delay) of PLL_CTL register.

≥ 1.14 V 133 133

DDINT

< 1.14 V 83 83

DDINT

MHz MHz

Rev. A | Page 21 of 56 | January 2005

Page 22

ADSP-BF531/ADSP-BF532/ADSP-BF533

Clock and Reset Timing

Table 15 and Figure 10 describe clock and reset operations. Per Absolute Maximum Ratings on Page 20, combinations of

CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600/133 MHz.

Table 15. Clock and Reset Timing

Parameter Min Max Unit

Timing Requirements

CKIN

CKINL

CKINH

WRST

Applies to bypass mode and non-bypass mode.

Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,

assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).

CLKIN Period 25.0 100.0 ns

CKIN

10.0 ns

10.0 ns 11 t

CKIN

CLKIN Low Pulse CLKIN High Pulse RESET Asserted Pulse Width Low

CLKIN

RESET

CKINL

CKINH

WRST

Figure 10. Clock and Reset Timing

Rev. A | Page 22 of 56 | January 2005

Page 23

ADSP-BF531/ADSP-BF532/ADSP-BF533

Asynchronous Memory Read Cycle Timing

Table 16. Asynchronous Memory Read Cycle Timing

Parameter Min Max Unit

Timing Requirements

SDAT

HDAT

SARDY

HARDY

Switching Characteristics

Output pins include AMS3– 0, ABE1–0, ADDR19 –1, AOE, ARE.

CLKOUT

DATA15–0 Setup Before CLKOUT 2.1 ns DATA15–0 Hold After CLKOUT 0.8 ns ARDY Setup Before CLKOUT 4.0 ns ARDY Hold After CLKOUT 0.0 ns

Output Delay After CLKOUT Output Hold After CLKOUT

SETUP

2CYCLES

PROGRAMMED READ ACCESS

4CYCLES

ACCESS EXTENDED

3CYCLES

6.0 ns

0.8 ns

HOLD

1CYCLE

AMSx

ABE1–0

ADDR19–1

AOE

ARE

ARDY

DATA15–0

BE, ADDRESS

SARDY

HARDY

SARDY

SDAT

READ

HARDY

HDAT

Figure 11. Asynchronous Memory Read Cycle Timing

Rev. A | Page 23 of 56 | January 2005

Page 24

ADSP-BF531/ADSP-BF532/ADSP-BF533

Asynchronous Memory Write Cycle Timing

Table 17. Asynchronous Memory Write Cycle Timing

Parameter Min Max Unit

Timing Requirements

SARDY

HARDY

Switching Characteristics

DDAT

ENDAT

Output pins include AMS3– 0, ABE1–0, ADDR19 –1, DATA15–0, AOE, AWE.

ARDY Setup Before CLKOUT 4.0 ns ARDY Hold After CLKOUT 0.0 ns

DATA15–0 Disable After CLKOUT 6.0 ns DATA15–0 Enable After CLKOUT 1.0 ns Output Delay After CLKOUT Output Hold After CLKOUT

0.8 ns

6.0 ns

CLKOUT

AMSx

ABE1–0

ADDR19–1

AWE

ARDY

DATA15–0

SETUP

2CYCLES

ENDA T

PROGRAMMED WRITE

ACCESS 2 CYCLES

BE, ADDRESS

SARDY

WRITE DATA

SARDY

ACCESS

EXTENDED

1CYCLE

HOLD

1CYCLE

HARDY

DDAT

Figure 12. Asynchronous Memory Write Cycle Timing

Rev. A | Page 24 of 56 | January 2005

Page 25

SDRAM Interface Timing

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 18. SDRAM Interface Timing

Parameter Min Max Unit

Timing Requirements

SSDAT

HSDAT

DATA Setup Before CLKOUT 2.1 ns DATA Hold After CLKOUT 0.8 ns

Switching Characteristics

SCLK

SCLKH

SCLKL

DCAD

HCAD

DSDAT

ENSDAT

For V

Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

DDINT

= 1.2 V.

CLKOUT Period 7.5 ns CLKOUT Width High 2.5 ns CLKOUT Width Low 2.5 ns Command, ADDR, Data Delay After CLKOUT Command, ADDR, Data Hold After CLKOUT

0.8 ns

6.0 ns

Data Disable After CLKOUT 6.0 ns Data Enable After CLKOUT 1.0 ns

SCLKH

CLKOUT

DATA(IN)

SSDA T

SCLK

HSDAT

SCLKL

DATA(OUT)

CMND ADDR

(OUT)

DCAD

ENSDAT

DCAD

HCAD

NOTE: COMMAND = SRAS, SCAS, SWE,SDQM,SMS, SA10, SCKE.

Figure 13. SDRAM Interface Timing

DSDAT

HCAD

Rev. A | Page 25 of 56 | January 2005

Page 26

ADSP-BF531/ADSP-BF532/ADSP-BF533

External Port Bus Request and Grant Cycle Timing

Table 19 and Figure 14 describe external port bus request and

bus grant operations.

Table 19. External Port Bus Request and Grant Cycle Timing

Parameter

Timing Requirements

Switching Characteristics

DBG

EBG

DBH

EBH

These are preliminary timing parameters that are based on worst-case operating conditions.

The pad loads for these timing parameters are 20 pF.

, 1, 2

BR Asserted to CLKOUT High Setup 4.6 ns CLKOUT High to BR Deasserted Hold Time 0.0 ns

CLKOUT Low to xMS, Address, and RD/WR disable 4.5 ns CLKOUT Low to xMS, Address, and RD/WR enable 4.5 ns CLKOUT High to BG High Setup 3.6 ns CLKOUT High to BG Deasserted Hold Time 3.6 ns CLKOUT High to BGH High Setup 3.6 ns CLKOUT High to BGH Deasserted Hold Time 3.6 ns

Min Max Unit

CLKOUT

AMSx

ADDR19-1

ABE1-0

AWE

ARE

BGH

DBG

DBH

EBG

EBH

Figure 14. External Port Bus Request and Grant Cycle Timing

Rev. A | Page 26 of 56 | January 2005

Page 27

ADSP-BF531/ADSP-BF532/ADSP-BF533

Parallel Peripheral Interface Timing

Table 20 and Figure 15 on Page 27 describe parallel peripheral

interface operations.

Table 20. Parallel Peripheral Interface Timing

Parameter Min Max Unit

Timing Requirements

PCLKW

PCLK

SFSPE

HFSPE

SDRPE

HDRPE

Switching Characteristics—GP Output and Frame Capture Modes

DFSPE

HOFSPE

DDTPE

HDTPE

PPI_CLK frequency cannot exceed f

PPI_CLK Width 6.0 ns PPI_CLK Period

15.0 ns External Frame Sync Setup Before PPI_CLK 3.0 ns External Frame Sync Hold After PPI_CLK 3.0 ns Receive Data Setup Before PPI_CLK 2.0 ns Receive Data Hold After PPI_CLK 4.0 ns

Internal Frame Sync Delay After PPI_CLK 10.0 ns Internal Frame Sync Hold After PPI_CLK 0.0 ns Transmit Data Delay After PPI_CLK 10.0 ns Transmit Data Hold After PPI_CLK 0.0 ns

SCLK

PPI_CLK

PPI_FS1

PPI_FS2

PPIx

HOFSPE

HDTPE

DRIVE

EDGE

DFSPE

DDTPE

PCLKW

SFSPE

SDRPE

SAMPLE

EDGE

Figure 15. GP Output Mode and Frame Capture Timing

HFSPE

HDRPE

Rev. A | Page 27 of 56 | January 2005

Page 28

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Ports

Table 21 on Page 28 through Table 24 on Page 29 and Figure 16 on Page 29 through Figure 18 on Page 31 describe Serial Port

operations.

Table 21. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

HFSE

SDRE

HDRE

SCLKEW

SCLKE

TFS/RFS Setup Before TSCLK/RSCLK TFS/RFS Hold After TSCLK/RSCLK Receive Data Setup Before RSCLK Receive Data Hold After RSCLK TSCLK/RSCLK Width 4.5 ns TSCLK/RSCLK Period 15.0 ns

Switching Characteristics

DFSE

HOFSE

DDTE

HDTE

Referenced to sample edge.

Referenced to drive edge.

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS) TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS) Transmit Data Delay After TSCLK Transmit Data Hold After TSCLK

3.0 ns

10.0 ns

0.0 ns

10.0 ns

0.0 ns

Table 22. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

SFSI

HFSI

SDRI

HDRI

SCLKEW

SCLKE

TFS/RFS Setup Before TSCLK/RSCLK TFS/RFS Hold After TSCLK/RSCLK Receive Data Setup Before RSCLK Receive Data Hold After RSCLK TSCLK/RSCLK Width 4.5 ns TSCLK/RSCLK Period 15.0 ns

8.0 ns

−2.0 ns

6.0 ns

0.0 ns

Switching Characteristics

DFSI

HOFSI

DDTI

HDTI

SCLKIW

Referenced to sample edge.

Referenced to drive edge.

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS) TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS) Transmit Data Delay After TSCLK Transmit Data Hold After TSCLK

TSCLK/RSCLK Width 4.5 ns

−1.0 ns

3.0 ns

−2.0 ns

Table 23. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DTENE

DDTTE

DTENI

DDTTI

Referenced to drive edge.

Data Enable Delay from External TSCLK Data Disable Delay from External TSCLK Data Enable Delay from Internal TSCLK Data Disable Delay from Internal TSCLK

0ns

10.0 ns

−2.0 ns

3.0 ns

Rev. A | Page 28 of 56 | January 2005

Page 29

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 24. External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

DTENLFS

MCE = 1, TFS enable and TFS valid follow t

If external RFS/TFS setup to RSCLK/TSCLK > t

Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0 Data Enable from Late FS or MCE = 1, MFD = 0

DTENLFS

and t

SCLKE

DDTLFSE

/2, then t

DDTE/I

and t

1,2

apply; otherwise t

DTENE/I

DDTLFSE

and t

DTENLFS

1, 2

apply.

10.0 ns

0ns

DATA RECEIVE—INTERNAL CLOCK

RSCLK

TSCLK

DRIVE EDGE

DFSE

HOFSE

RFS

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE

DFSI

HOFSI

TFS

HDTI

DDTI

SCLKIW

SFSI

SDRI

SFSI

SAMPLE

EDGE

SAMPLE

EDGE

HDRI

HFSI

DATA RECEIVE—EXTERNAL CLOCK

DRIVE

EDGE

RSCLK

HOFSE

RFS

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE

EDGE

TSCLK

HOFSE

TFS

HDTE

DFSE

DDTE

SCLKEW

SFSE

SDRE

SFSE

SAMPLE

EDGE

SAMPLE

EDGE

HFSE

HDRE

HFSE

TSCLK (EXT)

TFS ("LATE", EXT.)

TSCLK (INT)

TFS ("LATE", INT.)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DTENI

DTENE

TSCLK / RSCLK

DRIVE

EDGE

DRIVE

EDGE

DDTTI

DDTTE

Figure 16. Serial Ports

Rev. A | Page 29 of 56 | January 2005

Page 30

ADSP-BF531/ADSP-BF532/ADSP-BF533

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE DRIVESAMPLE

RSCLK

RFS

LATE EXTERNAL TFS

DRIVE DRIVESAMPLE

TSCLK

TFS

SFSE/I

DTENLFS

DDTLFSE

HDTE/I

HOFSE/I

DDTE/I

HOFSE/I

2ND BIT1ST BIT

Figure 17. External Late Frame Sync (Frame Sync Setup < t

SCLKE

/2)

Rev. A | Page 30 of 56 | January 2005

Page 31

EXTERNAL RFS WITH MCE = 1, MFD = 0

ADSP-BF531/ADSP-BF532/ADSP-BF533

DRIVE SAMPLE

RSCLK

RFS

LATE EXTERNAL TFS

DRIVE SAMPLE

TSCLK

TFS

SFSE /I

DDTLSCK

SFSE/I

DTENLSCK

1ST BIT

DRIVE

HOFSE/I

HDTE/I

HOFSE/I

HDTE/I

DDTE/I

2ND BIT

1ST BIT 2ND BIT

DDTLSCK

Figure 18. External Late Frame Sync (Frame Sync Setup > t

SCLKE

/2)

Rev. A | Page 31 of 56 | January 2005

Page 32

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Peripheral Interface (SPI) Port —Master Timing

Table 25 and Figure 19 describe SPI port master operations.

Table 25. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter Min Max Unit

Timing Requirements

SSPIDM

HSPIDM

Switching Characteristics

SDSCIM

SPICHM

SPICLM

SPICLK

HDSM

SPITDM

DDSPIDM

HDSPIDM

Data Input Valid to SCK Edge (Data Input Setup) 7.5 ns SCK Sampling Edge to Data Input Invalid –1.5 ns

SPISELx Low to First SCK edge (x=0 or 1) 2t Serial Clock High period 2t Serial Clock Low period 2t Serial Clock Period 4t Last SCK Edge to SPISELx High (x= 0 or 1) 2t Sequential Transfer Delay 2t

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

SCK Edge to Data Out Valid (Data Out Delay) 0 6 ns SCK Edge to Data Out Invalid (Data Out Hold) –1.0 4.0 ns

CPHA = 1

CPHA = 0

SPISELx

(OUTPUT)

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

SSPIDM

SDSCIM

MSB VALID

SPICHMtSPICLM

SPICLM

SSPIDM

MSB VALID

HSPIDM

SPICHM

DDSPIDM

HSPIDM

DDSPIDM

SPICLK

HDSPIDM

SSPIDM

LSB VALID

HDSPIDM

LSBMSB

HDSM

LSBMSB

HSPIDM

SPITDM

Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. A | Page 32 of 56 | January 2005

Page 33

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Peripheral Interface (SPI) Port —Slave Timing

Table 26 and Figure 20 describe SPI port slave operations.

Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter Min Max Unit

Timing Requirements

SPICHS

SPICLS

SPICLK

HDS

SPITDS

SDSCI

SSPID

HSPID

Switching Characteristics

DSOE

DSDHI

DDSPID

HDSPID

Serial Clock High Period 2t Serial Clock Low Period 2t Serial Clock Period 4t Last SCK Edge to SPISS Not Asserted 2t Sequential Transfer Delay 2t SPISS Assertion to First SCK Edge 2t

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

–1.5 ns

SCLK

Data Input Valid to SCK Edge (Data Input Setup) 1.6 ns SCK Sampling Edge to Data Input Invalid 1.6 ns

SPISS Assertion to Data Out Active 0 8 ns SPISS Deassertion to Data High Impedance 0 8 ns SCK Edge to Data Out Valid (Data Out Delay) 0 10 ns SCK Edge to Data Out Invalid (Data Out Hold) 0 10 ns

CPHA = 1

CPHA = 0

SPISS

(INPUT)

SCK

(CPOL = 0)

(INPUT)

SCK

(CPOL = 1)

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

DSOE

SDSCI

SPICHStSPICLS

SPICLS

DDSPID

SSPID

MSB VALID

DDSPID

MSB

SPICHS

HDSPID

HSPID

SSPID

SPICLK

DDSPID

SSPID

LSB VALID

LSB VALI D

LSB

HSPID

HDS

DSDHI

LSBMSB

DSDHI

HSPID

SPIT DS

Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. A | Page 33 of 56 | January 2005

Page 34

ADSP-BF531/ADSP-BF532/ADSP-BF533

Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing

Figure 21 describes UART port receive and transmit operations.

The maximum baud rate is SCLK/16. As shown in Figure 21 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.

CLKOUT

(SAMPLE CLOCK)

RECEIVE

TRANSMIT

RXD

INTERNAL

UART RECE IVE

INTERRUPT

TXD

INTERNAL

UART TRANSMIT

INTERRUPT

DATA[8:5]

STOP

START

DATA[8:5]

Figure 21. UART Port—Receive and Transmit Timing

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

STOP[2:1]

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY W RITE TO TR ANSMIT

Rev. A | Page 34 of 56 | January 2005

Page 35

ADSP-BF531/ADSP-BF532/ADSP-BF533

Programmable Flags Cycle Timing

Table 27 and Figure 22 describe programmable flag operations.

Table 27. Programmable Flags Cycle Timing

Parameter Min Max Unit

Timing Requirements

WFI

Switching Characteristics

DFO

Flag Input Pulse Width t

+ 1 ns

SCLK

Flag Output Delay from CLKOUT Low 6 ns

CLKOUT

DFO

PF (OUTPUT)

PF (INPUT)

WFI

FLAG INPUT

FLAG OUTPUT

Figure 22. Programmable Flags Cycle Timing

Rev. A | Page 35 of 56 | January 2005

Page 36

ADSP-BF531/ADSP-BF532/ADSP-BF533

Timer Cycle Timing

Table 28 and Figure 23 describe timer expired operations. The

input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency of f

/2 MHz.

SCLK

Table 28. Timer Cycle Timing

Parameter Min Max Unit

Timing Characteristics

Switching Characteristics

HTO

The minimum pulse widths apply for TMRx input pins in width capture and external clock mode s. They also apply to the PF1 or PP I_CLK input pins in PWM output mode.

The minimum time for t

CLKOUT

Timer Pulse Width Input Low1 (Measured in SCLK Cycles) 1 SCLK Timer Pulse Width Input High1 (Measured in SCLK Cycles) 1 SCLK

Timer Pulse Width Output2 (Measured in SCLK Cycles) 1 (232–1) SCLK

is one cycle, and the maximum time for t

HTO

equals (232–1) cycles.

HTO

TMRx

(PWM OUTPUTMODE)

TMRx

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

Figure 23. Timer PWM_OUT Cycle Timing

Rev. A | Page 36 of 56 | January 2005

Page 37

ADSP-BF531/ADSP-BF532/ADSP-BF533

JTAG Test and Emulation Port Timing

Table 29 and Figure 24 describe JTAG port operations.

Table 29. JTAG Port Timing

Parameter Min Max Unit

Timing Requirements

TCK

STAP

HTAP

SSYS

HSYS

TRSTW

Switching Characteristics

DTDO

DSYS

System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,

RESET, NMI, BMODE1–0, BR, PP3–0.

50 MHz maximum

System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,

TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG

TCK Period 20 ns TDI, TMS Setup Before TCK High 4 ns TDI, TMS Hold After TCK High 4 ns System Inputs Setup Before TCK High System Inputs Hold After TCK High

4ns 5ns

TRST Pulse Width2 (Measured in TCK cycles) 4 TCK

TDO Delay from TCK Low 10 ns System Outputs Delay After TCK Low

012ns

, BGH, PPI3–0.

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

DSYS

DTDO

SSYS

STAP

TCK

HTAP

HSYS

Figure 24. JTAG Port Timing

Rev. A | Page 37 of 56 | January 2005

Page 38

ADSP-BF531/ADSP-BF532/ADSP-BF533

OUTPUT DRIVE CURRENTS

Figure 25 through Figure 32 show typical current-voltage char-

acteristics for the output drivers of the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor. The curves represent the current drive capability of the output drivers as a function of output voltage.

150

100

–50

SOURCE CURRENT (mA)

–100

–150

150

100

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

= 2.75V @ –40°C

DDEXT

0.5 1.0 1.5 2.0 2.5 3.0

Figure 25. Drive Current A (Low V

SOURCE VOLTAGE (V)

DDEXT

)

= 2.95V @ 95°C = 3.30V@25°C = 3.65V @ –40°C

150

100

–50

SOURCE CURRENT (mA)

–100

–150

150

100

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

= 2.75V @ –40°C

DDEXT

0.5 1.0 1.5 2.0 2.5 3.0

Figure 27. Drive Current B (Low V

SOURCE VOLTAGE (V)

DDEXT

)

= 2.95V @ 95°C = 3.30V@25°C = 3.65V @ –40°C

–50

SOURCE CURRENT (mA)

–100

–150

0.5 1.0 1.5 2.0 2.5 3.53.0

Figure 26. Drive Current A (High V

SOURCE VOLTAGE (V)

DDEXT

)

–50

SOURCE CURRENT (mA)

–100

–150

0 0.5 1.0 1.5 2.0 2.5 3.53.0

Figure 28. Drive Current B (High V

SOURCE VOLTAGE (V)

DDEXT

)

Rev. A | Page 38 of 56 | January 2005

Page 39

ADSP-BF531/ADSP-BF532/ADSP-BF533

150

100

–50

–100

–150

SOURCE CURRENT (mA)

0 0.5 1.0 1.5 2.0 2.5 3.53.0

SOURCE VOLTAGE (V)

DDEXT

= 2.95V @ 95°C

DDEXT

= 3.30V@25°C

DDEXT

= 3.65V @ –40°C

DDEXT

–20

–40

SOURCE CURRENT (mA)

–60

0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V)

Figure 29. Drive Current C (Low V

100

–20

–40

SOURCE CURRENT (mA)

–60

–80

–100

0 0.5 1.0 1.5 2.0 2.5 3.53.0

SOURCE VOLTAGE (V)

V V

DDEXT

V V V

DDEXT DDEXT

)

DDEXT DDEXT DDEXT

= 2.25V @ 95°C

= 2.50V @ 25°C

= 2.75V @ –40°C

= 2.95V @ 95°C = 3.30V@25°C = 3.65V @ –40°C

100

–20

–40

SOURCE CURRENT (mA)

–60

–80

–100

= 2.25V @ 95°C

0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V)

Figure 31. Drive Current D (Low V

V V

DDEXT

DDEXT DDEXT DDEXT

= 2.50V @ 25°C = 2.75V @ –40°C

)

Figure 30. Drive Current C (High V

)

DDEXT

Rev. A | Page 39 of 56 | January 2005

Figure 32. Drive Current D (High V

DDEXT

)

Page 40

ADSP-BF531/ADSP-BF532/ADSP-BF533

POWER DISSIPATION

Total power dissipation has two components: one due to internal circuitry (P output drivers (P internal circuitry (V dent on the instruction execution sequence and the data operands involved.

) and one due to the switching of external

INT

). Table 30 shows the power dissipation for

EXT

). Internal power dissipation is depen-

DDINT

Table 30. Internal Power Dissipation

Test Conditions2

Parameter f

CCLK

50 MHz V

DDINT

0.8 V

DDTYP

DDSLEEP

DDDEEPSLEEP

DDHIBERNATE

DDRTC

See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors.

IDD data is specified for typical process parameters at minimum voltage. All data

at 25°C.

Processor executing 75% dual Mac, 25% ADD with moderate data bus activity.

See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for defini-

tions of sleep and deep sleep operating modes.

Measured at V

26 150 190 220 mA 16 35 37 37 mA

14 29 31 31 mA

50 µA 30 µA

= 3.65V with voltage regulator off (V

DDEXT

= 3.3V at 25°C.

DDRTC

CCLK

400 MHz V

DDINT

1.14 V

CCLK

500 MHz

DDINT

1.2 V

CCLK

600 MHz V

DDINT

1.2 V

= 0V).

DDINT

Unit

The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:

• Number of output pins (O) that switch during each cycle

• Maximum frequency (f) at which they can switch

• Their load capacitance (C)

• Their voltage swing (V

DDEXT

)

The external component is calculated using:

EXT

OC× V

× f×=

The frequency f includes driving the load high and then back low. For example: DATA15–0 pins can drive high and low at a maximum rate of 1/(2ⴛ t

) while in SDRAM burst mode.

SCLK

A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation:

TOTAL

Note that the conditions causing a worst-case P those causing a worst-case P

EXTIDDVDDINT

INT

×()+=

. Maximum P

differ from

EXT

cannot occur

INT

while 100% of the output pins are switching from all ones (1s) to all zeros (0s). Note, as well, that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.

Rev. A | Page 40 of 56 | January 2005

Page 41

TEST CONDITIONS

All timing parameters appearing in this data sheet were measured under the conditions described in this section.

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time t point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the Output Enable/Disable diagram (Figure 33). The time t is the interval from when the reference signal switches to when the output voltage reaches 2.0 V (output high) or 1.0 V (output low). Time t

is the interval from when the output starts driv-

TRIP

ing to when the output reaches the 1.0 V or 2.0 V trip voltage. Time t

is calculated as shown in the equation:

ENA

is the interval from the

ENA

ENA_MEASURED

ADSP-BF531/ADSP-BF532/ADSP-BF533

REFERENCE

SIGNAL

DIS

(MEASURED)

DIS_MEASURED

VOH(MEASURED) ⴚ⌬V

VOL(MEASURED) + ⌬V

DECAY

ENA

OUTPUT STOPS DRIVING

HIGH IMPEDANCE STAT E.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

Figure 33. Output Enable/Disable

ENA-MEASURED

(MEASURED)

TRIP

2.0V

1.0V

OUTPUT STARTS DRIVING

ENAtENA_MEASUREDtTRIP

–=

If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, C load current, I

. This decay time can be approximated by the

and the

equation:

DECAY

The output disable time t and t

as shown in Figure 33. The time t

DECAY

CLV∆()IL⁄=

is the difference between t

DIS

DIS_MEASURED

is the

interval from when the reference signal switches to when the output voltage decays ∆V from the measured output high or output low voltage. The time t C

and IL, and with ∆V equal to 0.5 V.

is calculated with test loads

DECAY

Example System Hold Time Calculation

To determine the data output hold time in a particular system, first calculate t

using the equation given above. Choose ∆V

DECAY

to be the difference between the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor’s output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0.4 V. C and I

is the total leakage or three-state current (per data line).

The hold time will be t example, t

DSDAT

is the total bus capacitance (per data line),

plus the minimum disable time (for

DECAY

for an SDRAM write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 34). Figure 36 on Page 42 through

Figure 43 on Page 43 show how output rise time varies with

OUTPUT

30pF

⍀

1.5V

Figure 34. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

INPUT

1.5V 1.5V

OUTPUT

Figure 35. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown.

Rev. A | Page 41 of 56 | January 2005

Page 42

ADSP-BF531/ADSP-BF532/ADSP-BF533

ABE_B[0] (133 MHz DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

Figure 36. Typical Output Delay or Hold for Driver A at EVDD

ABE0 (133 MHz DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (p F)

= 2.25V, TEMPERATURE = 85°C

MIN

RISE TIME

FALLTIME

= 3.65V, TEMPERATURE = 85°C

MAX

RISE TIME

FALLTIME

MIN

CLKOUT (CLKOUT DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

Figure 38. Typical Output Delay or Hold for Driver B at EVDD

CLKOUT (CLKOUT DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

= 2.25V, TEMPERATURE = 85°C

MIN

RISE TIME

FALLTIME

= 3.65V, TEMPERATURE = 85°C

MAX

RISE TIME

FALLTIME

MIN

Figure 37. Typical Output Delay or Hold for Driver A at EVDD

Rev. A | Page 42 of 56 | January 2005

MAX

Figure 39. Typical Output Delay or Hold for Driver B at EVDD

MAX

Page 43

ADSP-BF531/ADSP-BF532/ADSP-BF533

TMR0 (33 MHz DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

Figure 40. Typical Output Delay or Hold for Driver C at EVDD

TMR0 (33 MHz DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

= 2.25V, TEMPERATURE = 85°C

MIN

RISE TIME

FALLTIME

= 3.65V, TEMPERATURE = 85°C

MAX

RISE TIME

FALLTIME

MIN

SCK (66 MHz DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

Figure 42. Typical Output Delay or Hold for Driver D at EVDD

SCK (66 MHz DRIVER), EVDD

RISE AND FALLTIME ns (10%-90%)

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

= 2.25V, TEMPERATURE = 85°C

MIN

RISE TIME

FALLTIME

= 3.65V, TEMPERATURE = 85°C

MAX

RISE TIME

FALLTIME

MIN

Figure 41. Typical Output Delay or Hold for Driver C at EVDD

Rev. A | Page 43 of 56 | January 2005

MAX

Figure 43. Typical Output Delay or Hold for Driver D at EVDD

MAX

Page 44

ADSP-BF531/ADSP-BF532/ADSP-BF533

ENVIRONMENTAL CONDITIONS

To determine the junction temperature on the application printed circuit board use:

TJT

where:

= junction temperature (ⴗC)

= case temperature (ⴗC) measured by customer at top cen-

CASE

ter of package.

= from Table 31

= power dissipation (see Power Dissipation on Page 40 for

the method to calculate P Values of θ

are provided for package comparison and printed

)

circuit board design considerations. θ order approximation of T

by the equation:

where:

= ambient temperature (ⴗC)

In Table 31, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board.

Thermal resistance θ

in Table 31 is the figure of merit relating

to performance of the package and board in a convective environment. θ conditions of airflow. θ periphery of the board. Ψ T

and T

represents the thermal resistance under two

JMA

. Values of θJB are provided for package comparison

CASE

represents the heat extracted from the

and printed circuit board design considerations.

ΨJTPD×()+=

CASE

can be used for a first

TAθJAPD×()+=

represents the correlation between

Table 33. Thermal Characteristics for B-169 Package

Parameter Condition Typical Unit

JMA

0 Linear m/s Airflow 28.6 ⴗC/W 1 Linear m/s Airflow 24.6 ⴗC/W 2 Linear m/s Airflow 23.8 ⴗC/W Not applicable 21.75 ⴗC/W Not applicable 12.7 ⴗC/W 0 Linear m/s Airflow 0.78 ⴗC/W

Table 31. Thermal Characteristics for BC-160 Package

Parameter Condition Typical Unit

JMA

0 Linear m/s Airflow 34.1 ⴗC/W 1 Linear m/s Airflow 30.1 ⴗC/W 2 Linear m/s Airflow 28.8 ⴗC/W Not applicable 25.55 ⴗC/W Not applicable 8.75 ⴗC/W 0 Linear m/s Airflow 0.13 ⴗC/W

Table 32. Thermal Characteristics for ST-176-1 Package

Parameter Condition Typical Unit

JMA

0 Linear m/s Airflow 34.9 ⴗC/W 1 Linear m/s Airflow 33.0 ⴗC/W 2 Linear m/s Airflow 32.0 ⴗC/W 0 Linear m/s Airflow 0.50 ⴗC/W 1 Linear m/s Airflow 0.75 ⴗC/W 2 Linear m/s Airflow 1.00 ⴗC/W

Rev. A | Page 44 of 56 | January 2005

Page 45

ADSP-BF531/ADSP-BF532/ADSP-BF533

160-LEAD BGA PINOUT

Table 34 lists the BGA pinout by signal. Table 35 on Page 46

lists the BGA pinout by ball number.

Table 34. 160-Ball BGA Pin Assignment (Alphabetically by Signal)

Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.

ABE0 ABE1 ADDR1 J14 DATA14 P5 GND L10 SMS ADDR10 M13 DATA15 P4 GND M4 SRAS ADDR11 M14 DATA2 P9 GND M10 SWE ADDR12 N14 DATA3 M8 GND P14 TCK P2 ADDR13 N13 DATA4 N8 MISO E2 TDI M3 ADDR14 N12 DATA5 P8 MOSI D3 TDO N3 ADDR15 M11 DATA6 M7 NMI B10 TFS0 H3 ADDR16 N11 DATA7 N7 PF0 D2 TFS1 E1 ADDR17 P13 DATA8 P7 PF1 C1 TMR0 L2 ADDR18 P12 DATA9 M6 PF10 A4 TMR1 M1 ADDR19 P11 DR0PRI K1 PF11 A5 TMR2 K2 ADDR2 K14 DR0SEC J2 PF12 B5 TMS N2 ADDR3 L14 DR1PRI G3 PF13 B6 TRST ADDR4 J13 DR1SEC F3 PF14 A6 TSCLK0 J1 ADDR5 K13 DT0PRI H1 PF15 C6 TSCLK1 F1 ADDR6 L13 DT0SEC H2 PF2 C2 TX K3 ADDR7 K12 DT1PRI F2 PF3 C3 VDDEXT A1 ADDR8 L12 DT1SEC E3 PF4 B1 VDDEXT C7 ADDR9 M12 EMU AMS0 AMS1 AMS2 AMS3 AOE ARDY E13 GND C11 PPI1 B8 VDDEXT J12 ARE AWE BG BGH BMODE0 N4 GND D11 RFS0 J3 VDDINT E4 BMODE1 P3 GND F4 RFS1 G2 VDDINT E11 BR CLKIN A12 GND G11 RSCLK1 G1 VDDINT L4 CLKOUT B14 GND H4 RTXI A9 VDDINT L9 DATA0 M9 GND H11 RTXO A8 VDDRTC B9 DATA1 N9 GND K4 RX L3 VROUT0 A13 DATA10 N6 GND K11 SA10 E12 VROUT1 B12 DATA11 P6 GND L5 SCAS

H13 DATA12 M5 GND L6 SCK D1 H12 DATA13 N5 GND L8 SCKE B13

C13 D13 D12

M2 PF5 B2 VDDEXT C12 E14 GND A10 PF6 B3 VDDEXT D5 F14 GND A14 PF7 B4 VDDEXT D9 F13 GND B11 PF8 A2 VDDEXT F12 G12 GND C4 PF9 A3 VDDEXT G4 G13 GND C5 PPI0 C8 VDDEXT J4

G14 GND D4 PPI2 A7 VDDEXT L7 H14 GND D7 PPI3 B7 VDDEXT L11 P10 GND D8 PPI_CLK C9 VDDEXT P1 N10 GND D10 RESET C10 VDDINT D6

D14 GND F11 RSCLK0 L1 VDDINT J11

C14 XTAL A11

Rev. A | Page 45 of 56 | January 2005

Page 46

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 35. 160-Ball BGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

A1 VDDEXT C13 SMS A2 PF8 C14 SCAS A3 PF9 D1 SCK H3 TFS0 M5 DATA12 A4 PF10 D2 PF0 H4 GND M6 DATA9 A5 PF11 D3 MOSI H11 GND M7 DATA6 A6 PF14 D4 GND H12 ABE1 A7 PPI2 D5 VDDEXT H13 ABE0 A8 RTXO D6 VDDINT H14 AWE A9 RTXI D7 GND J1 TSCLK0 M11 ADDR15 A10 GND D8 GND J2 DR0SEC M12 ADDR9 A11 XTAL D9 VDDEXT J3 RFS0 M13 ADDR10 A12 CLKIN D10 GND J4 VDDEXT M14 ADDR11 A13 VROUT0 D11 GND J11 VDDINT N1 TRST A14 GND D12 SWE J12 VDDEXT N2 TMS B1 PF4 D13 SRAS B2 PF5 D14 BR B3 PF6 E1 TFS1 K1 DR0PRI N5 DATA13 B4 PF7 E2 MISO K2 TMR2 N6 DATA10 B5 PF12 E3 DT1SEC K3 TX N7 DATA7 B6 PF13 E4 VDDINT K4 GND N8 DATA4 B7 PPI3 E11 VDDINT K11 GND N9 DATA1 B8 PPI1 E12 SA10 K12 ADDR7 N10 BGH B9 VDDRTC E13 ARDY K13 ADDR5 N11 ADDR16 B10 NMI E14 AMS0 B11 GND F1 TSCLK1 L1 RSCLK0 N13 ADDR13 B12 VROUT1 F2 DT1PRI L2 TMR0 N14 ADDR12 B13 SCKE F3 DR1SEC L3 RX P1 VDDEXT B14 CLKOUT F4 GND L4 VDDINT P2 TCK C1 PF1 F11 GND L5 GND P3 BMODE1 C2 PF2 F12 VDDEXT L6 GND P4 DATA15 C3 PF3 F13 AMS2 C4 GND F14 AMS1 C5 GND G1 RSCLK1 L9 VDDINT P7 DATA8 C6 PF15 G2 RFS1 L10 GND P8 DATA5 C7 VDDEXT G3 DR1PRI L11 VDDEXT P9 DATA2 C8 PPI0 G4 VDDEXT L12 ADDR8 P10 BG C9 PPI_CLK G11 GND L13 ADDR6 P11 ADDR19 C10 RESET C11 GND G13 AOE C12 VDDEXT G14 ARE

G12 AMS3 L14 ADDR3 P12 ADDR18

H1 DT0PRI M3 TDI H2 DT0SEC M4 GND

M8 DATA3 M9 DATA0 M10 GND

J13 ADDR4 N3 TDO J14 ADDR1 N4 BMODE0

K14 ADDR2 N12 ADDR14

L7 VDDEXT P5 DATA14 L8 GND P6 DATA11

M1 TMR1 P13 ADDR17 M2 EMU P14 GND

Rev. A | Page 46 of 56 | January 2005

Page 47

Figure 44 lists the top view of the BGA ball configuration. Figure 45 lists the bottom view of the BGA ball configuration.

1 2 3 4 5 6 7 8 9 1011121314

A B C D E F G H J K L M N P

KEY:

DDINT

DDEXT

GND

I/O

DDRTC

ROUT

ADSP-BF531/ADSP-BF532/ADSP-BF533

Figure 44. 160-Ball BGA Ball Configuration (Top View)

1234567891011121314

KEY:

DDINT

DDEXT

GND

I/O

DDRTC

ROUT

Figure 45. 160-Ball BGA Ball Configuration (Bottom View)

A B C D E F G H J K L M N P

Rev. A | Page 47 of 56 | January 2005

Page 48

ADSP-BF531/ADSP-BF532/ADSP-BF533

169-BALL PBGA PINOUT

Table 36 lists the PBGA pinout by signal. Table 37 on Page 49

lists the PBGA pinout by ball number.

Table 36. 169-Ball PBGA Pin Assignment (Alphabetically by Signal)

Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.

ABE0 H16 DATA12 U7 GND G10 PF7 A3 VDD J12 ABE1 H17 DATA13 T7 GND G11 PF8 B4 VDD K12 ADDR1 J16 DATA14 U6 GND H7 PF9 A4 VDD L12 ADDR10 N16 DATA15 T6 GND H8 PPI0 B9 VDD M10 ADDR11 P17 DATA2 U13 GND H9 PPI1 A9 VDD M11 ADDR12 P16 DATA3 T11 GND H10 PPI2 B8 VDD M12 ADDR13 R17DATA4 U12GND H11PPI3 A8 VROUT B12 ADDR14 R16 DATA5 U11 GND J7 PPI_CLK B10 VROUT B13 ADDR15 T17 DATA6 T10 GND J8 RESET A12 XTAL A13 ADDR16 U15 DATA7 U10 GND J9 RFS0 N1 ADDR17 T15 DATA8 T9 GND J10 RFS1 J1 ADDR18 U16 DATA9 U9 GND J11 RSCLK0 N2 ADDR19 T14 DR0PRI M2 GND K7 RSCLK1 J2 ADDR2 J17 DR0SEC M1 GND K8 RTCVDD F10 ADDR3 K16 DR1PRI H1 GND K9 RTXI A10 ADDR4 K17 DR1SEC H2 GND K10 RTXO A11 ADDR5 L16 DT0PRI K2 GND K11 RX T1 ADDR6 L17 DT0SEC K1 GND L7 SA10 B15 ADDR7 M16 DT1PRI F1 GND L8 SCAS A16 ADDR8 M17 DT1SEC F2 GND L9 SCK D1 ADDR9 N17 EMU U1 GND L10 SCKE B14 AMS0 D17 EVDD B2 GND L11 SMS A17 AMS1 E16 EVDD F6 GND M9 SRAS A15 AMS2 E17EVDD F7 GND T16SWE B17 AMS3 F16EVDD F8MISO E2TCK U4 AOE F17 EVDD F9 MOSI E1 TDI U3 ARDY C16 EVDD G6 NMI B11 TDO T4 ARE G16 EVDD H6 PF0 D2 TFS0 L1 AWE G17 E VDD J 6 P F1 C1 T FS1 G2 BG T13 EVDD K6 PF10 B5 TMR0 R1 BGH U17 EVDD L6 PF11 A5 TMR1 P2 BMODE0 U5 EVDD M6 PF12 A6 TMR2 P1 BMODE1 T5 EVDD M7 PF13 B6 TMS T3 BR C17 EVDD M8 PF14 A7 TRST U2 CLKIN A14 EVDD T2 PF15 B7 TSCLK0 L2 CLKOUT D16 GND B16 PF2 B1 TSCLK1 G1 DATA0 U14 GND F11 PF3 C2 TX R2 DATA1 T12 GND G7 PF4 A1 VDD F12 DATA10 T8 GND G8 PF5 A2 VDD G12 DATA11 U8 GND G9 PF6 B3 VDD H12

Rev. A | Page 48 of 56 | January 2005

Page 49

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 37. 169-Ball PBGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

A1 PF4 D16 CLKOUT J2 RSCLK1 M12 VDD U9 DATA9 A2 PF5 D17 AMS0 J6 EVDD M16 ADDR7 U10 DATA7 A3 PF7 E1 MOSI J7 GND M17 ADDR8 U11 DATA5 A4 PF9 E2 MISO J8 GND N1 RFS0 U12 DATA4 A5 PF11 E16 AMS1 J9 GND N2 RSCLK0 U13 DATA2 A6 PF12 E17 AMS2 J10 GND N16 ADDR10 U14 DATA0 A7 PF14 F1 DT1PRI J11 GND N17 ADDR9 U15 ADDR16 A8 PPI3 F2 DT1SEC J12 VDD P1 TMR2 U16 ADDR18 A9 PPI1 F6 EVDD J16 ADDR1 P2 TMR1 U17 BGH A10 RTXI F7 EVDD J17 ADDR2 P16 ADDR12 A11 RTXO F8 EVDD K1 DT0SEC P17 ADDR11 A12 RESET F9 EVDD K2 DT0PRI R1 TMR0 A13 XTAL F10 RTCVDD K6 EVDD R2 TX A14 CLKIN F11 GND K7 GND R16 ADDR14 A15 SRAS F12 VDD K8 GND R17 ADDR13 A16 SCAS F16 AMS3 K9 GND T1 RX A17 SMS F17 AOE K10 GND T2 EVDD B1 PF2 G1 TSCLK1 K11 GND T3 TMS B2 EVDD G2 TFS1 K12 VDD T4 TDO B3 PF6 G6 EVDD K16 ADDR3 T5 BMODE1 B4 PF8 G7 GND K17 ADDR4 T6 DATA15 B5 PF10 G8 GND L1 TFS0 T7 DATA13 B6 PF13 G9 GND L2 TSCLK0 T8 DATA10 B7 PF15 G10 GND L6 EVDD T9 DATA8 B8 PPI2 G11 GND L7 GND T10 DATA6 B9 PPI0 G12 VDD L8 GND T11 DATA3 B10 PPI_CLK G16 ARE L9 GND T12 DATA1 B11 NMI G17 AWE L10 GND T13 BG B12 VROUT H1 DR1PRI L11 GND T14 ADDR19 B13 VROUT H2 DR1SEC L12 VDD T15 ADDR17 B14 SCKE H6 EVDD L16 ADDR5 T16 GND B15 SA10 H7 GND L17 ADDR6 T17 ADDR15 B16 GND H8 GND M1 DR0SEC U1 EMU B17 SWE H9 GND M2 DR0PRI U2 TRST C1 PF1 H10 GND M6 EVDD U3 TDI C2 PF3 H11 GND M7 EVDD U4 TCK C16 ARDY H12 VDD M8 EVDD U5 BMODE0 C17 BR H16 ABE0 M9 GND U6 DATA14 D1 SCK H17 ABE1 M10 VDD U7 DATA12 D2 PF0 J1 RFS1 M11 VDD U8 DATA11

Rev. A | Page 49 of 56 | January 2005

Page 50

ADSP-BF531/ADSP-BF532/ADSP-BF533

176-LEAD LQFP PINOUT

Table 38 lists the LQFP pinout by signal. Table 39 on Page 51

lists the LQFP pinout by lead number.

Table 38. 176-Lead LQFP Pin Assignment (Alphabetically by Signal)

Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No.

ABE0 ABE1 ADDR1 149 DATA13 100 GND 90 PPI1 23 VDDEXT 107 ADDR10 137 DATA14 99 GND 91 PPI2 24 VDDEXT 118 ADDR11 136 DATA15 98 GND 92 PPI3 26 VDDEXT 134 ADDR12 135 DATA2 114 GND 97 RESET ADDR13 127 DATA3 113 GND 106 RFS0 75 VDDEXT 156 ADDR14 126 DATA4 112 GND 117 RFS1 64 VDDEXT 171 ADDR15 125 DATA5 110 GND 128 RSCLK0 76 VDDINT 25 ADDR16 124 DATA6 109 GND 129 RSCLK1 65 VDDINT 52 ADDR17 123 DATA7 108 GND 130 RTXI 17 VDDINT 66 ADDR18 122 DATA8 105 GND 131 RTXO 16 VDDINT 80 ADDR19 121 DATA9 104 GND 132 RX 82 VDDINT 111 ADDR2 148 DR0PRI 74 GND 133 SA10 164 VDDINT 143 ADDR3 147 DR0SEC 73 GND 144 SCAS ADDR4 146 DR1PRI 63 GND 155 SCK 53 VDDINT 168 ADDR5 142 DR1SEC 62 GND 170 SCKE 173 VDDRTC 18 ADDR6 141 DT0PRI 68 GND 174 SMS ADDR7 140 DT0SEC 67 GND 175 SRAS ADDR8 139 DT1PRI 59 GND 176 SWE ADDR9 138 DT1SEC 58 MISO 54 TCK 94 AMS0 AMS1 AMS2 AMS3 AOE ARDY 162 GND 8 PF11 33 TMR1 78 ARE AWE BG BGH BMODE0 96 GND 39 PF2 49 TSCLK1 61 BMODE1 95 GND 40 PF3 48 TX 81 BR CLKIN 10 GND 42 PF5 46 VDDEXT 12 CLKOUT 169 GND 43 PF6 38 VDDEXT 20 DATA0 116 GND 44 PF7 37 VDDEXT 31 DATA1 115 GND 56 PF8 36 VDDEXT 45 DATA10 103 GND 70 PF9 35 VDDEXT 57

151 DATA11 102 GND 88 PPI_CLK 21 VDDEXT 71 150DATA12101GND89PPI022VDDEXT93

13 VDDEXT 145

166 VDDINT 157

172 VROUT1 5 167 VROUT2 4 165 XTAL 11

161 EMU 83 MOSI 55 TDI 86 160 GND 1 NMI 14 TDO 87 159 GND 2 PF0 51 TFS0 69 158 GND 3 PF1 50 TFS1 60 154 GND 7 PF10 34 TMR0 79

153 GND 9 PF12 32 TMR2 77 152 GND 15 PF13 29 TMS 85 119 GND 19 PF14 28 TRST 84 120 GND 30 PF15 27 TSCLK0 72

163 GND 41 PF4 47 VDDEXT 6

Rev. A | Page 50 of 56 | January 2005

Page 51

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 39. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)

Lead No. Signal Lead No. Signal Lead No.Signal Lead No.Signal Lead No.Signal

1 GND 41 GND 81 TX 121 ADDR19 161 AMS0 2 GND 42 GND 82 RX 122 ADDR18 162 ARDY 3GND43GND83EMU 4VROUT244GND84TRST124 ADDR16 164 SA10 5 VROUT1 45 VDDEXT 85 TMS 125 ADDR15 165 SWE 6 VDDEXT 46 PF5 86 TDI 126 ADDR14 166 SCAS 7 GND 47 PF4 87 TDO 127 ADDR13 167 SRAS 8 GND 48 PF3 88 GND 128 GND 168 VDDINT 9 GND 49 PF2 89 GND 129 GND 169 CLKOUT 10 CLKIN 50 PF1 90 GND 130 GND 170 GND 11 XTAL 51 PF0 91 GND 131 GND 171 VDDEXT 12 VDDEXT 52 VDDINT 92 GND 132 GND 172 SMS 13 RESET 53 SCK 93 VDDEXT 133 GND 173 SCKE 14 NMI 54 MISO 94 TCK 134 VDDEXT 174 GND 15 GND 55 MOSI 95 BMODE1 135 ADDR12 175 GND 16 RTXO 56 GND 96 BMODE0 136 ADDR11 176 GND 17 RTXI 57 VDDEXT 97 GND 137 ADDR10 18 VDDRTC 58 DT1SEC 98 DATA15 138 ADDR9 19 GND 59 DT1PRI 99 DATA14 139 ADDR8 20 VDDEXT 60 TFS1 100 DATA13 140 ADDR7 21 PPI_CLK 61 TSCLK1 101 DATA12 141 ADDR6 22 PPI0 62 DR1SEC 102 DATA11 142 ADDR5 23 PPI1 63 DR1PRI 103 DATA10 143 VDDINT 24 PPI2 64 RFS1 104 DATA9 144 GND 25 VDDINT 65 RSCLK1 105 DATA8 145 VDDEXT 26 PPI3 66 VDDINT 106 GND 146 ADDR4 27 PF15 67 DT0SEC 107 VDDEXT 147 ADDR3 28 PF14 68 DT0PRI 108 DATA7 148 ADDR2 29 PF13 69 TFS0 109 DATA6 149 ADDR1 30 GND 70 GND 110 DATA5 150 ABE1 31 VDDEXT 71 VDDEXT 111 VDDINT 151 ABE0 32 PF12 72 TSCLK0 112 DATA4 152 AWE 33 PF11 73 DR0SEC 113 DATA3 153 ARE 34 PF10 74 DR0PRI 114 DATA2 154 AOE 35 PF9 75 RFS0 115 DATA1 155 GND 36 PF8 76 RSCLK0 116 DATA0 156 VDDEXT 37 PF7 77 TMR2 117 GND 157 VDDINT 38 PF6 78 TMR1 118 VDDEXT 158 AMS3 39 GND 79 TMR0 119 BG 159 AMS2 40 GND 80 VDDINT 120 BGH 160 AMS1

123 ADDR17 163 BR

Rev. A | Page 51 of 56 | January 2005

Page 52

ADSP-BF531/ADSP-BF532/ADSP-BF533

OUTLINE DIMENSIONS

Dimensions in Figure 46—160-Ball Mini-BGA (BC-160),

Figure 47—176-Lead LQFP (ST-176-1) and Figure 48—169-Ball Plastic Ball Grid Array (B-169) are shown in millimeters.

12.00 BSC SQ

BALL A1 INDICATOR

TOP V IEW

1.70

MAX

NOTES

1. DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-205, VARIATION AE WITH EXCEPTION OF THE BALL DIAMETER.

3. MINIMUM BALL HEIGHT 0.25.

DETAIL A

SEATING PLANE

Figure 46. 160-Ball Mini-BGA (BC-160)

10.40 BSC

1.31

1.21

1.11

0.40 NOM (NOTE 3)

14 12 10 8 6 4 2

13 11 9 7 5 3 1

0.80 BSC

BALL PITCH

BOTTOMVIEW

0.50

0.45

0.40

BALLDIAMETER

DETAIL A

A1 CORNER INDEX AREA

A B C D E F G H J K L M N P

0.12

MAX

COPLANARITY

Rev. A | Page 52 of 56 | January 2005

Page 53

ADSP-BF531/ADSP-BF532/ADSP-BF533

0.75

0.60

0.45

0.27

0.22

0.17

SEATING

PLANE

0.08 MAX LEAD COPLANARITY

0.15

0.05

NOTES

1. DIMENSIONS IN MILLIMETERS

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL

1.45

1.40

1.35

1.60 MAX

DETAIL A

Figure 47. 176-Lead LQFP (ST-176-1)

176

PIN 1

DETAIL A

26.00 BSC SQ

24.00 BSC SQ

0.50 BSC

LEAD PITCH

TOP VIEW (PINS DOWN)

133

132

Rev. A | Page 53 of 56 | January 2005

Page 54

ADSP-BF531/ADSP-BF532/ADSP-BF533

A1 BALL PAD CORNER

BOTTOMVIEW

19.00 BSC SQ

TOP VIEW

2.50

2.23

1.97

NOTES

1. DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAG-2 .

3. MINIMUM BALL HEIGHT 0.40

SIDE VIEW

DETAIL A

1.00 BSC BALL PITCH

A B C D

G H

M N

0.20 MAX COPLANARITY

BALL DIAMETER

16.00 BSC SQ

E F

1716151413121110987654321

0.70

0.60

0.50

DETAIL A

0.40 MIN

SEATING PLANE

Figure 48. 169-Ball Plastic Ball Grid Array (B-169)

Rev. A | Page 54 of 56 | January 2005

Page 55

ORDERING GUIDE

ADSP-BF531/ADSP-BF532/ADSP-BF533

Part Number Temperature

Range

Package Description Instruction

Rate (Max)

Operating Voltage (Nom)

(Ambient )

ADSP-BF533SKBC600 0ºC to 70ºC Chip Scale Package Ball Grid Array (Mini-BGA) BC-160 600 MHz 1.26 V internal, 2.5 V or 3.3 V I/O

ADSP-BF533SKBCZ600

0ºC to 70ºC Chip Scale Package Ball Grid Array (Mini-BGA) BC-160 600 MHz 1.26 V internal, 2.5 V or 3.3 V I/O

ADSP-BF533SBBC500 –40ºC to 85ºC Chip Scale Package Ball Grid Array (Mini-BGA) BC-160 500 MHz 1.26 V internal, 2.5 V or 3.3 V I/O

ADSP-BF533SBBZ500

–40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169 500 MHz 1.26 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBBC400 –40ºC to 85ºC Chip Scale Package Ball Grid Array (Mini-BGA) BC-160 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBST400 –40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBBZ400

–40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBBC400 –40ºC to 85ºC Chip Scale Package Ball Grid Array (Mini-BGA) BC-160 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBST400 –40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBSTZ400

ADSP-BF531SBBZ400

Z = Pb-free part.

–40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

–40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O

Rev. A | Page 55 of 56 | January 2005

Page 56

ADSP-BF531/ADSP-BF532/ADSP-BF533

D03728-0-1/05(A)

Rev. A | Page 56 of 56 | January 2005

Datasheet ADSP-BF531 Datasheet (Analog Devices)

FEATURES

MEMORY

PERIPHERALS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PORTABLE LOW POWER ARCHITECTURE

SYSTEM INTEGRATION

ADSP-BF531/ADSP-BF532/ADSP-BF533 PROCESSOR PERIPHERALS

BLACKFIN PROCESSOR CORE

MEMORY ARCHITECTURE

Internal (On-Chip) Memory

External (Off-Chip) Memory

I/O Memory Space

Booting

Event Handling

Core Event Controller (CEC)

System Interrupt Controller (SIC)

Event Control

DMA CONTROLLERS

REAL-TIME CLOCK

WATCHDOG TIMER

TIMERS

SERIAL PORTS (SPORTS)

SERIAL PERIPHERAL INTERFACE (SPI) PORT

UART PORT

PROGRAMMABLE FLAGS (PFX)

PARALLEL PERIPHERAL INTERFACE

DYNAMIC POWER MANAGEMENT

Power Savings

VOLTAGE REGULATION

CLOCK SIGNALS

BOOTING MODES

INSTRUCTION SET DESCRIPTION

DEVELOPMENT TOOLS

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD

PIN DESCRIPTIONS

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

Clock and Reset Timing

Asynchronous Memory Read Cycle Timing

Asynchronous Memory Write Cycle Timing

SDRAM Interface Timing

External Port Bus Request and Grant Cycle Timing

Parallel Peripheral Interface Timing

Serial Ports

Programmable Flags Cycle Timing

Timer Cycle Timing

JTAG Test and Emulation Port Timing

OUTPUT DRIVE CURRENTS

POWER DISSIPATION

TEST CONDITIONS

Output Enable Time

Output Disable Time

Example System Hold Time Calculation

Capacitive Loading

ENVIRONMENTAL CONDITIONS

160-LEAD BGA PINOUT

169-BALL PBGA PINOUT

176-LEAD LQFP PINOUT

OUTLINE DIMENSIONS

ORDERING GUIDE