Datasheet ADSP-BF50x Datasheet (ANALOG DEVICES)

a

ADSP-BF50x Blackfin® Processor

Hardware Reference

Revision 1.0, December 2010

Part Number

82-100101-01

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information

© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, CROSSCORE, EZ-KIT Lite,
SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of
Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual .................................................................. li

Intended Audience .......................................................................... li

Manual Contents ........................................................................... lii

What’s New in This Manual ........................................................... lv

Technical or Customer Support ..................................................... lvi

Supported Processors .................................................................... lvii

Product Information .................................................................... lvii

Analog Devices Web Site ....................................................... lviii

VisualDSP++ Online Documentation .................................... lviii

Technical Library CD .............................................................. lix

Social Networking Web Sites .................................................... lx

Notation Conventions .................................................................... lx

INTRODUCTION

General Description of Processor ................................................... 1-1

Portable Low-Power Architecture ............................................. 1-3

System Integration ................................................................... 1-3

Peripherals .................................................................................... 1-4

ADSP-BF50x Blackfin Processor Hardware Reference iii

Contents

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-6

External Memory .................................................................... 1-6

I/O Memory Space .................................................................. 1-7

DMA Support .............................................................................. 1-8

General-Purpose I/O (GPIO) ........................................................ 1-9

Two-Wire Interface ..................................................................... 1-10

RSI Interface .............................................................................. 1-11

General-Purpose (GP) Counter ................................................... 1-12

3-Phase PWM Unit .................................................................... 1-13

Parallel Peripheral Interface ......................................................... 1-14

SPORT Controllers .................................................................... 1-16

Serial Peripheral Interface (SPI) Ports .......................................... 1-18

Timers ....................................................................................... 1-18

UART Ports ............................................................................... 1-19

Controller Area Network (CAN) Interface ................................... 1-21

ACM Interface ........................................................................... 1-22

Internal ADC ............................................................................. 1-22

Watchdog Timer ......................................................................... 1-23

Clock Signals .............................................................................. 1-23

Dynamic Power Management ..................................................... 1-24

Full-On Operating Mode—Maximum Performance ............... 1-24

Active Operating Mode—Moderate Dynamic Power Savings .. 1-24

Sleep Operating Mode—High Dynamic Power Savings .......... 1-25

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Deep Sleep Operating Mode—Maximum Dynamic

Power Savings ..................................................................... 1-26

Hibernate State—Maximum Static Power Savings .................. 1-26

Instruction Set Description ......................................................... 1-27

Development Tools ..................................................................... 1-28

MEMORY

Memory Architecture .................................................................... 2-1

L1 Instruction SRAM ................................................................... 2-2

L1 Data SRAM ............................................................................. 2-3

L1 Data Cache .............................................................................. 2-4

Boot ROM ................................................................................... 2-4

External Memory .......................................................................... 2-4

Processor-Specific MMRs .............................................................. 2-5

DMEM_CONTROL Register ................................................. 2-5

DTEST_COMMAND Register ............................................... 2-6

CHIP BUS HIERARCHY

Chip Bus Hierarchy Overview ....................................................... 3-1

Interface Overview ........................................................................ 3-2

Internal Clocks ........................................................................ 3-2

Core Bus Overview .................................................................. 3-4

Peripheral Access Bus (PAB) ..................................................... 3-5

PAB Arbitration .................................................................. 3-6

PAB Agents (Masters, Slaves) ............................................... 3-6

PAB Performance ................................................................ 3-7

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Contents

DMA Access Bus (DAB), DMA Core Bus (DCB), DMA

External Bus (DEB) .............................................................. 3-7

DAB, DCB, and DEB Arbitration ...................................... 3-7

DAB Bus Agents (Masters) .................................................. 3-9

DAB, DCB, and DEB Performance ..................................... 3-9

External Access Bus (EAB) .................................................... 3-10

Arbitration of the External Bus .............................................. 3-10

DEB/EAB Performance ......................................................... 3-10

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF50x .................................... 4-1

Overview ...................................................................................... 4-1

Features .................................................................................. 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-4

Programming Model ..................................................................... 4-7

System Interrupt Initialization ................................................. 4-8

System Interrupt Processing Summary ..................................... 4-8

System Interrupt Controller Registers .......................................... 4-10

System Interrupt Assignment (SIC_IAR) Register .................. 4-11

System Interrupt Mask (SIC_IMASK) Register ...................... 4-12

System Interrupt Status (SIC_ISR) Register ........................... 4-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12

Programming Examples .............................................................. 4-13

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Clearing Interrupt Requests ................................................... 4-13

Unique Information for the ADSP-BF50x Processor .................... 4-15

Interfaces .............................................................................. 4-15

System Peripheral Interrupts .................................................. 4-18

EXTERNAL BUS INTERFACE UNIT

EBIU Overview ............................................................................ 5-1

Block Diagram ........................................................................ 5-3

Internal Memory Interfaces ...................................................... 5-4

Registers .................................................................................. 5-4

Error Detection ....................................................................... 5-5

AMC Overview and Features ......................................................... 5-5

Features ................................................................................... 5-6

Asynchronous Memory Interface .............................................. 5-6

Asynchronous Memory Address Decode .............................. 5-6

AMC Description of Operation ..................................................... 5-6

Avoiding Bus Contention ........................................................ 5-6

AMC Programming Model ............................................................ 5-7

EBIU Registers ............................................................................. 5-9

EBIU_AMGCTL Register ..................................................... 5-10

EBIU_AMBCTL Register ...................................................... 5-11

EBIU_MODECTL Register .................................................. 5-12

EBIU_FCTL Register ............................................................ 5-12

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Contents

INTERNAL FLASH MEMORY

Overview ...................................................................................... 6-1

Command Interface to Internal Flash Memory .............................. 6-6

Command Interface – Standard Commands ............................ 6-7

Read Array Command ....................................................... 6-7

Read Status Register Command ......................................... 6-7

Read Electronic Signature Command ................................. 6-8

Read CFI Query Command ............................................... 6-9

Clear Status Register Command ......................................... 6-9

Block Erase Command .................................................... 6-10

Program Command ......................................................... 6-11

Program/Erase Suspend Command .................................. 6-11

Program/Erase Resume Command ................................... 6-12

Protection Register Program Command ............................ 6-13

The Set Configuration Register Command ....................... 6-14

Block Lock Command ..................................................... 6-14

Block Unlock Command ................................................. 6-15

Block Lock-Down Command .......................................... 6-15

Status Register ..................................................................... 6-18

Program/Erase Controller Status Bit (SR7) ....................... 6-19

Erase Suspend Status Bit (SR6) ........................................ 6-20

Erase Status Bit (SR5) ...................................................... 6-20

Program Status Bit (SR4) ................................................. 6-21

VPP Status Bit (SR3) ........................................................ 6-21

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Program Suspend Status Bit (SR2) .................................... 6-22

Block Protection Status Bit (SR1) ..................................... 6-22

Bank Write Status Bit (SR0) ............................................. 6-22

Configuration Register ......................................................... 6-24

Read Select Bit (CR15) .................................................... 6-24

X Latency Bits (CR13-CR11) ........................................... 6-25

Wait Polarity Bit (CR10) .................................................. 6-25

Data Output Configuration Bit (CR9) ............................. 6-26

Wait Configuration Bit (CR8) .......................................... 6-27

Burst Type Bit (CR7) ....................................................... 6-27

Valid Clock Edge Bit (CR6) ............................................. 6-27

Wrap Burst Bit (CR3) ...................................................... 6-27

Burst Length Bits (CR2-CR0) .......................................... 6-27

Read Modes ......................................................................... 6-33

Asynchronous Read Mode ................................................ 6-33

Synchronous Burst Read Mode ......................................... 6-33

Synchronous Burst Read Suspend ..................................... 6-35

Single Synchronous Read Mode ........................................ 6-36

Dual Operations and Multiple Bank Architecture .................. 6-36

Block Locking ...................................................................... 6-38

Reading a Block’s Lock Status ........................................... 6-39

Locked State .................................................................... 6-39

Unlocked State ................................................................. 6-39

Lock-Down State ............................................................. 6-40

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Locking Operations During Erase Suspend ....................... 6-40

Block Address Table .................................................................... 6-42

Common Flash Interface ............................................................ 6-45

Flowcharts and Pseudo Codes .................................................... 6-56

Command Interface State Tables ................................................ 6-68

Internal Flash Memory Programming Guidelines ......................... 6-77

Bringing Internal Flash Memory Out of Reset ........................ 6-78

Timing Configurations for Setting the Internal Flash

Memory in Asynchronous Read Mode ................................ 6-79

Timing Configurations for Setting the Internal Flash

Memory for Write Accesses ................................................. 6-80

Enabling the Program or Erasure of Internal Flash

Memory Blocks .................................................................. 6-82

Configuring Internal Flash Memory for Synchronous

Burst Read Mode ............................................................... 6-83

Supported Configuration Register Combinations in

ADSP-BF50xF Processors .............................................. 6-84

Configuring the EBIU for Synchronous Read Mode .......... 6-85

Unsupported Programming Practices in Flash ........................ 6-87

Internal Flash Memory Control Registers .................................... 6-88

Internal Flash Memory Control

(FLASH_CONTROL) Register .......................................... 6-88

Internal Flash Memory Control Set

(FLASH_CONTROL_SET) Register ................................. 6-91

Internal Flash Memory Control Clear

(FLASH_CONTROL_CLEAR) Register ............................ 6-91

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Contents

DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF50x ..................................... 7-1

Overview and Features .................................................................. 7-2

DMA Controller Overview ............................................................ 7-4

External Interfaces ................................................................... 7-4

Internal Interfaces ................................................................... 7-4

Peripheral DMA ...................................................................... 7-5

Memory DMA ........................................................................ 7-6

Handshaked Memory DMA (HMDMA) Mode ................... 7-8

Modes of Operation ...................................................................... 7-9

Register-Based DMA Operation ............................................... 7-9

Stop Mode ........................................................................ 7-11

Autobuffer Mode .............................................................. 7-11

Two-Dimensional DMA Operation ........................................ 7-11

Examples of Two-Dimensional DMA ................................ 7-13

Descriptor-based DMA Operation ......................................... 7-14

Descriptor List Mode ........................................................ 7-15

Descriptor Array Mode ..................................................... 7-15

Variable Descriptor Size .................................................... 7-15

Mixing Flow Modes .......................................................... 7-17

Functional Description ............................................................... 7-17

DMA Operation Flow ........................................................... 7-17

DMA Startup .................................................................... 7-17

DMA Refresh ................................................................... 7-23

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Work Unit Transitions ...................................................... 7-25

DMA Transmit and MDMA Source .............................. 7-26

DMA Receive ............................................................... 7-27

Stopping DMA Transfers .................................................. 7-29

DMA Errors (Aborts) ............................................................ 7-30

DMA Control Commands .................................................... 7-32

Restrictions ...................................................................... 7-35

Transmit Restart or Finish ............................................. 7-35

Receive Restart or Finish ............................................... 7-36

Handshaked Memory DMA Operation .................................. 7-37

Pipelining DMA Requests ................................................. 7-38

HMDMA Interrupts ......................................................... 7-40

DMA Performance ................................................................ 7-41

DMA Throughput ............................................................ 7-42

Memory DMA Timing Details .......................................... 7-45

Static Channel Prioritization ............................................. 7-45

Temporary DMA Urgency ................................................ 7-45

Memory DMA Priority and Scheduling ............................. 7-47

Traffic Control ................................................................. 7-49

Programming Model ................................................................... 7-51

Synchronization of Software and DMA .................................. 7-51

Single-Buffer DMA Transfers ............................................ 7-53

Continuous Transfers Using Autobuffering ........................ 7-54

Descriptor Structures ........................................................ 7-56

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Descriptor Queue Management ......................................... 7-57

Descriptor Queue Using Interrupts on Every Descriptor 7-58

Descriptor Queue Using Minimal Interrupts .................. 7-59

Software-Triggered Descriptor Fetches ............................... 7-61

DMA Registers ........................................................................... 7-63

DMA Channel Registers ........................................................ 7-64

DMA Peripheral Map Registers (DMAx_PERIPHERAL

_MAP/MDMA_yy_PERIPHERAL_MAP) ..................... 7-67

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) .................... 7-68

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 7-72

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) .. 7-75

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) .... 7-76

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 7-76

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................. 7-77

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 7-78

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .............. 7-79

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 7-80

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DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 7-80

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 7-81

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) ................................. 7-83

HMDMA Registers ............................................................... 7-85

Handshake MDMA Control Registers

(HMDMAx_CONTROL) ............................................. 7-85

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 7-88

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ............................................... 7-88

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ............................................... 7-89

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 7-90

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ........................................... 7-90

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 7-91

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) ............................. 7-91

DMA_TC_PER Register .................................................. 7-92

DMA_TC_CNT Register ................................................. 7-92

Programming Examples .............................................................. 7-94

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Register-Based 2-D Memory DMA ........................................ 7-94

Initializing Descriptors in Memory ........................................ 7-97

Software-Triggered Descriptor Fetch Example ...................... 7-100

Handshaked Memory DMA Example ................................... 7-103

Unique Information for the ADSP-BF50x Processor .................. 7-105

Static Channel Prioritization ................................................ 7-107

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control .......................................... 8-1

PLL Overview ......................................................................... 8-2

PLL Clock Multiplier Ratios .................................................... 8-4

Core Clock/System Clock Ratio Control ............................. 8-5

Dynamic Power Management Controller ....................................... 8-7

Operating Modes ..................................................................... 8-8

Dynamic Power Management Controller States ........................ 8-9

Full-On Mode .................................................................... 8-9

Active Mode ..................................................................... 8-10

Sleep Mode ....................................................................... 8-10

Deep Sleep Mode .............................................................. 8-10

Hibernate State ................................................................. 8-11

Operating Mode Transitions .................................................. 8-12

Programming Operating Mode Transitions ............................. 8-15

Dynamic Supply Voltage Control ........................................... 8-17

Power Supply Management .................................................... 8-17

Changing Voltage .............................................................. 8-17

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Powering Down the Core (Hibernate State) ....................... 8-19

PLL and VR Registers ................................................................. 8-20

PLL_DIV Register ................................................................ 8-21

PLL_CTL Register ................................................................ 8-22

PLL_STAT Register .............................................................. 8-22

PLL_LOCKCNT Register ..................................................... 8-23

VR_CTL Register ................................................................. 8-23

System Control ROM Function .................................................. 8-24

Programming Model ............................................................. 8-26

Accessing the System Control ROM Function in C/C++ ........ 8-26

Accessing the System Control ROM Function in Assembly .... 8-27

Programming Examples .............................................................. 8-30

Full-on Mode to Active Mode and Back ................................. 8-32

Transition to Sleep Mode or Deep Sleep Mode ....................... 8-33

Set Wakeup Events and Enter Hibernate State ........................ 8-35

Perform a System Reset or Soft-Reset ..................................... 8-37

In Full-on Mode, Change VCO Frequency, Core Clock

Frequency, and System Clock Frequency ............................. 8-38

Changing Voltage Levels ....................................................... 8-40

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 9-1

Features ........................................................................................ 9-1

Interface Overview ....................................................................... 9-3

External Interface .................................................................... 9-3

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Port F Structure .................................................................. 9-3

Port G Structure ................................................................. 9-5

Port H Structure ................................................................. 9-6

Input Tap Considerations .................................................... 9-6

PWM Unit Considerations .................................................. 9-8

RSI Considerations ............................................................. 9-8

GP Counter Considerations ................................................ 9-9

SPI Considerations .............................................................. 9-9

Internal Interfaces ................................................................... 9-9

GP Timer Interaction With Other Blocks .......................... 9-10

Buffered CLKIN (CLKBUF) ......................................... 9-10

GP Counter .................................................................. 9-10

PPI ............................................................................... 9-10

UART ........................................................................... 9-10

SPORT ......................................................................... 9-11

ACM ............................................................................ 9-11

Performance/Throughput ...................................................... 9-12

Description of Operation ............................................................ 9-12

Operation ............................................................................. 9-12

General-Purpose I/O Modules ............................................... 9-13

GPIO Interrupt Processing .................................................... 9-16

Programming Model ................................................................... 9-22

Hysteresis Control ...................................................................... 9-24

PORTx Hysteresis (PORTx_HYSTERESIS) Register ............. 9-24

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Drive Strength Control ............................................................... 9-26

Memory-Mapped GPIO Registers ............................................... 9-27

Port Multiplexer Control Registers (PORTx_MUX) ............... 9-27

Function Enable Registers (PORTx_FER) ............................. 9-30

GPIO Direction Registers (PORTxIO_DIR) ......................... 9-30

GPIO Input Enable Registers (PORTxIO_INEN) ................. 9-31

GPIO Data Registers (PORTxIO) ......................................... 9-31

GPIO Set Registers (PORTxIO_SET) ................................... 9-32

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 9-32

GPIO Toggle Registers (PORTxIO_TOGGLE) ..................... 9-33

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 9-33

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................ 9-34

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ........ 9-34

GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 9-35

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 9-36

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 9-38

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 9-40

Programming Examples .............................................................. 9-41

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF50x .................................. 10-1

Overview .................................................................................... 10-2

External Interface .................................................................. 10-3

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Internal Interface ................................................................... 10-4

Description of Operation ............................................................ 10-4

Interrupt Processing .............................................................. 10-5

Illegal States .......................................................................... 10-7

Modes of Operation .................................................................. 10-10

Pulse Width Modulation (PWM_OUT) Mode ..................... 10-10

Output Pad Disable ........................................................ 10-12

Single Pulse Generation ................................................... 10-12

Pulse Width Modulation Waveform Generation ............... 10-13

PULSE_HI Toggle Mode ................................................ 10-15

Externally Clocked PWM_OUT ..................................... 10-19

Using PWM_OUT Mode With the PPI .......................... 10-20

Stopping the Timer in PWM_OUT Mode ....................... 10-21

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 10-23

Autobaud Mode .............................................................. 10-31

External Event (EXT_CLK) Mode ....................................... 10-31

Programming Model ................................................................. 10-33

Timer Registers ......................................................................... 10-34

Timer Enable Register (TIMER_ENABLE) .......................... 10-35

Timer Disable Register (TIMER_DISABLE) ........................ 10-36

Timer Status Register (TIMER_STATUS) ............................ 10-38

Timer Configuration Register (TIMER_CONFIG) .............. 10-40

Timer Counter Register (TIMER_COUNTER) ................... 10-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................. 10-42

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Summary ............................................................................ 10-45

Programming Examples ............................................................ 10-48

Unique Information for the ADSP-BF50x Processor .................. 10-57

Interface Overview .............................................................. 10-57

External Interface ........................................................... 10-57

CORE TIMER

Specific Information for the ADSP-BF50x .................................. 11-1

Overview and Features ................................................................ 11-1

Timer Overview ......................................................................... 11-2

External Interfaces ................................................................ 11-2

Internal Interfaces ................................................................. 11-3

Description of Operation ............................................................ 11-3

Interrupt Processing .............................................................. 11-3

Core Timer Registers .................................................................. 11-4

Core Timer Control Register (TCNTL) ................................. 11-5

Core Timer Count Register (TCOUNT) ............................... 11-5

Core Timer Period Register (TPERIOD) ............................... 11-6

Core Timer Scale Register (TSCALE) .................................... 11-7

Programming Examples .............................................................. 11-7

Unique Information for the ADSP-BF50x Processor .................... 11-9

WATCHDOG TIMER

Specific Information for the ADSP-BF50x .................................. 12-1

Overview and Features ................................................................ 12-1

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Interface Overview ...................................................................... 12-3

External Interface .................................................................. 12-3

Internal Interface ................................................................... 12-3

Description of Operation ............................................................ 12-4

Register Definitions .................................................................... 12-5

Watchdog Count (WDOG_CNT) Register ............................ 12-5

Watchdog Status (WDOG_STAT) Register ............................ 12-6

Watchdog Control (WDOG_CTL) Register ........................... 12-7

Programming Examples ............................................................... 12-8

Unique Information for the ADSP-BF50x Processor .................. 12-11

GENERAL-PURPOSE COUNTER

Specific Information for the ADSP-BF50x ................................... 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ...................................................................... 13-3

Description of Operation ............................................................ 13-4

Quadrature Encoder Mode .................................................... 13-4

Binary Encoder Mode ............................................................ 13-5

Up/Down Counter Mode ...................................................... 13-6

Direction Counter Mode ....................................................... 13-6

Timed Direction Mode .......................................................... 13-7

Functional Description ............................................................... 13-7

Input Noise Filtering (Debouncing) ....................................... 13-7

Zero Marker (Push Button) Operation ................................... 13-9

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Boundary Comparison Modes ............................................. 13-10

Control and Signaling Events .............................................. 13-11

Illegal Gray/Binary Code Events ..................................... 13-12

Up/Down Count Events ................................................. 13-12

Zero-Count Events ......................................................... 13-13

Overflow Events ............................................................. 13-13

Boundary Match Events .................................................. 13-13

Zero Marker Events ........................................................ 13-14

Capturing Timing Information ............................................ 13-14

Capturing Time Interval Between

Successive Counter Events ............................................ 13-14

Capturing Counter Interval and

CNT_COUNTER Read Timing .................................. 13-15

Programming Model ................................................................. 13-18

Registers ................................................................................... 13-18

Counter Module Register Overview ..................................... 13-18

Counter Configuration Register (CNT_CONFIG) .............. 13-19

Counter Interrupt Mask Register (CNT_IMASK) ................ 13-20

Counter Status Register (CNT_STATUS) ............................ 13-20

Counter Command Register (CNT_COMMAND) ............. 13-21

Counter Debounce Register (CNT_DEBOUNCE) .............. 13-23

Counter Count Value Register (CNT_COUNTER) ............ 13-24

Counter Boundary Registers (CNT_MIN and CNT_MAX) . 13-25

Programming Examples ............................................................ 13-27

Unique Information for the ADSP-BF50x Processor .................. 13-37

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PWM CONTROLLER

Specific Information for the ADSP-BF50x ................................... 14-1

Overview .................................................................................... 14-1

General Operation ...................................................................... 14-8

Functional Description ............................................................... 14-9

Three-Phase PWM Timing Unit and Dead Time

Control Unit .................................................................... 14-10

PWM Switching Frequency (PWM_TM) Register ................ 14-10

PWM Switching Dead Time (PWM_DT) Register ............... 14-12

PWM Operating Mode (PWM_CTRL and PWM_STAT)

Registers ........................................................................... 14-13

PWM Duty Cycle (PWM_CHA, PWM_CHB,

and PWM_CHC) Registers .............................................. 14-14

Special Consideration for PWM Operation in

Over-Modulation ............................................................. 14-20

Three-Phase PWM Timing Unit Operation .......................... 14-22

Effective PWM Accuracy ..................................................... 14-24

Switched Reluctance Mode .................................................. 14-25

Output Control Unit ........................................................... 14-25

Crossover Feature ............................................................ 14-25

Mode Bits (POLARITY and SRMODE) .......................... 14-26

Output Enable Function ................................................. 14-26

Brushless DC Motor (Electronically Commutated Motor)

Control ........................................................................ 14-27

Gate Drive Unit .................................................................. 14-29

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High-Frequency Chopping ............................................. 14-29

PWM Polarity Control ................................................... 14-30

Output Control Feature Precedence ..................................... 14-31

Switched Reluctance (SR) Mode .......................................... 14-31

PWM Sync Operation ......................................................... 14-34

Internal PWM SYNC Generation ................................... 14-35

External PWM SYNC Generation ................................... 14-35

PWM Shutdown and Interrupt Control Unit ....................... 14-36

PWM Registers ........................................................................ 14-37

PWM Control (PWM_CTRL) Register ............................... 14-38

PWM Status (PWM_STAT) Register ................................... 14-40

PWM Period (PWM_TM) Register ..................................... 14-41

PWM Dead Time (PWM_DT) Register .............................. 14-42

PWM Chopping Control (PWM_GATE) Register ............... 14-42

PWM Channel A, B, C Duty Control

(PWM_CHA, PWM_CHB, PWM_CHC) Registers ......... 14-43

PWM Crossover and Output Enable (PWM_SEG)

Register ............................................................................ 14-45

PWM Sync Pulse Width Control (PWM_SYNCWT)

Register ............................................................................ 14-47

PWM Channel AL, BL, CL Duty Control

(PWM_CHAL, PWM_CHBL, PWM_CHCL) Registers ... 14-47

PWM Low Side Invert (PWM_LSI) Register ....................... 14-49

PWM Simulation Status (PWM_STAT2) Register ............... 14-49

Unique Information for the ADSP-BF50x Processor .................. 14-50

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UART PORT CONTROLLERS

Overview .................................................................................... 15-1

Features ................................................................................. 15-2

Interface Overview ...................................................................... 15-3

External Interface .................................................................. 15-3

Internal Interface ................................................................... 15-5

Description of Operation ............................................................ 15-5

UART Transfer Protocol ........................................................ 15-6

UART Transmit Operation .................................................... 15-7

UART Receive Operation ...................................................... 15-8

Hardware Flow Control ....................................................... 15-10

IrDA Transmit Operation .................................................... 15-13

IrDA Receive Operation ...................................................... 15-13

Interrupt Processing ............................................................ 15-15

Bit Rate Generation ............................................................. 15-18

Autobaud Detection ............................................................ 15-20

Programming Model ................................................................. 15-22

Non-DMA Mode ................................................................ 15-22

DMA Mode ........................................................................ 15-23

Mixing Modes ..................................................................... 15-25

UART Registers ........................................................................ 15-26

UARTx_LCR Registers ........................................................ 15-28

UARTx_MCR Registers ...................................................... 15-31

UARTx_LSR Registers ........................................................ 15-33

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UARTx_MSR Registers ....................................................... 15-36

UARTx_THR Registers ...................................................... 15-37

UARTx_RBR Registers ....................................................... 15-38

UARTx_DLL and UARTx_DLH Registers .......................... 15-43

UARTx_SCR Registers ........................................................ 15-44

UARTx_GCTL Registers .................................................... 15-45

Programming Examples ............................................................ 15-46

TWO WIRE INTERFACE CONTROLLER

Specific Information for the ADSP-BF50x .................................. 16-1

Overview .................................................................................... 16-2

Interface Overview ..................................................................... 16-3

External Interface .................................................................. 16-4

Serial Clock Signal (SCL) ................................................. 16-4

Serial Data Signal (SDA) .................................................. 16-4

TWI Pins ......................................................................... 16-5

Internal Interfaces ................................................................. 16-5

Description of Operation ............................................................ 16-6

TWI Transfer Protocols ......................................................... 16-6

Clock Generation and Synchronization ............................. 16-7

Bus Arbitration ................................................................. 16-8

Start and Stop Conditions ................................................. 16-8

General Call Support ........................................................ 16-9

Fast Mode ...................................................................... 16-10

Functional Description ............................................................. 16-10

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General Setup ...................................................................... 16-10

Slave Mode .......................................................................... 16-11

Master Mode Clock Setup ................................................... 16-12

Master Mode Transmit ........................................................ 16-12

Master Mode Receive ........................................................... 16-14

Repeated Start Condition ................................................ 16-15

Transmit/Receive Repeated Start Sequence ................... 16-15

Receive/Transmit Repeated Start Sequence ................... 16-16

Clock Stretching ............................................................. 16-17

Clock Stretching During FIFO Underflow ....................... 16-17

Clock Stretching During FIFO Overflow ......................... 16-19

Clock Stretching During Repeated Start Condition .......... 16-20

Programming Model ................................................................. 16-22

Register Descriptions ................................................................ 16-24

TWI CONTROL Register (TWI_CONTROL) ................... 16-24

SCL Clock Divider Register (TWI_CLKDIV) ...................... 16-25

TWI Slave Mode Control Register (TWI_SLAVE_CTL) ...... 16-26

TWI Slave Mode Address Register (TWI_SLAVE_ADDR) ... 16-28

TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 16-28

TWI Master Mode Control Register

(TWI_MASTER_CTL) .................................................... 16-30

TWI Master Mode Address Register

(TWI_MASTER_ADDR) ................................................ 16-33

TWI Master Mode Status Register

(TWI_MASTER_STAT) .................................................. 16-34

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TWI FIFO Control Register (TWI_FIFO_CTL) ................. 16-37

TWI FIFO Status Register (TWI_FIFO_STAT) .................. 16-39

TWI FIFO Status ........................................................... 16-39

TWI Interrupt Mask Register (TWI_INT_MASK) .............. 16-40

TWI Interrupt Status Register (TWI_INT_STAT) .............. 16-41

TWI FIFO Transmit Data Single Byte

Register (TWI_XMT_DATA8) ......................................... 16-43

TWI FIFO Transmit Data Double Byte

Register (TWI_XMT_DATA16) ....................................... 16-44

TWI FIFO Receive Data Single Byte

Register (TWI_RCV_DATA8) ......................................... 16-45

TWI FIFO Receive Data Double Byte

Register (TWI_RCV_DATA16) ........................................ 16-46

Programming Examples ............................................................ 16-47

Master Mode Setup ............................................................. 16-47

Slave Mode Setup ................................................................ 16-52

Electrical Specifications ............................................................ 16-59

Unique Information for the ADSP-BF50x Processor .................. 16-59

CAN MODULE

Overview .................................................................................... 17-1

Interface Overview ..................................................................... 17-2

CAN Mailbox Area ............................................................... 17-4

CAN Mailbox Control .......................................................... 17-6

CAN Protocol Basics ............................................................. 17-7

CAN Operation ......................................................................... 17-9

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Bit Timing .......................................................................... 17-10

Transmit Operation ............................................................. 17-12

Retransmission ................................................................ 17-13

Single Shot Transmission ................................................. 17-14

Auto-Transmission .......................................................... 17-15

Receive Operation ............................................................... 17-15

Data Acceptance Filter .................................................... 17-18

Remote Frame Handling ................................................. 17-19

Watchdog Mode ............................................................. 17-19

Time Stamps ....................................................................... 17-20

Temporarily Disabling Mailboxes ......................................... 17-21

Functional Operation ................................................................ 17-22

CAN Interrupts ................................................................... 17-22

Mailbox Interrupts .......................................................... 17-23

Global CAN Status Interrupt .......................................... 17-23

Event Counter ..................................................................... 17-26

CAN Warnings and Errors ................................................... 17-27

Programmable Warning Limits ........................................ 17-28

CAN Error Handling ...................................................... 17-28

Error Frames ............................................................... 17-29

Error Levels ................................................................ 17-31

Debug and Test Modes ........................................................ 17-33

Low Power Features ............................................................. 17-37

CAN Built-In Suspend Mode .......................................... 17-37

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CAN Built-In Sleep Mode .............................................. 17-38

CAN Wakeup From Hibernate State ............................... 17-38

CAN Register Definitions ......................................................... 17-39

Global CAN Registers ......................................................... 17-43

CAN_CONTROL Register ............................................ 17-43

CAN_STATUS Register ................................................. 17-44

CAN_DEBUG Register .................................................. 17-45

CAN_CLOCK Register .................................................. 17-45

CAN_TIMING Register ................................................. 17-46

CAN_INTR Register ...................................................... 17-46

CAN_GIM Register ....................................................... 17-47

CAN_GIS Register ......................................................... 17-47

CAN_GIF Register ......................................................... 17-48

Mailbox/Mask Registers ...................................................... 17-48

CAN_AMxx Registers ..................................................... 17-48

CAN_MBxx_ID1 Registers ............................................ 17-52

CAN_MBxx_ID0 Registers ............................................ 17-54

CAN_MBxx_TIMESTAMP Registers ............................. 17-56

CAN_MBxx_LENGTH Registers ................................... 17-58

CAN_MBxx_DATAx Registers ....................................... 17-59

Mailbox Control Registers ................................................... 17-68

CAN_MCx Registers ...................................................... 17-68

CAN_MDx Registers ...................................................... 17-69

CAN_RMPx Register ..................................................... 17-70

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CAN_RMLx Register ...................................................... 17-71

CAN_OPSSx Register ..................................................... 17-72

CAN_TRSx Registers ...................................................... 17-73

CAN_TRRx Registers ..................................................... 17-74

CAN_AAx Register ......................................................... 17-75

CAN_TAx Register ......................................................... 17-76

CAN_MBTD Register .................................................... 17-77

CAN_RFHx Registers ..................................................... 17-77

CAN_MBIMx Registers .................................................. 17-78

CAN_MBTIFx Registers ................................................. 17-79

CAN_MBRIFx Registers ................................................. 17-80

Universal Counter Registers ................................................. 17-82

CAN_UCCNF Register .................................................. 17-82

CAN_UCCNT Register .................................................. 17-83

CAN_UCRC Register ..................................................... 17-83

Error Registers ..................................................................... 17-84

CAN_CEC Register ........................................................ 17-84

CAN_ESR Register ......................................................... 17-84

CAN_EWR Register ....................................................... 17-84

Programming Examples ............................................................. 17-85

CAN Setup Code ................................................................ 17-85

Initializing and Enabling CAN Mailboxes ............................ 17-86

Initiating CAN Transfers and Processing Interrupts .............. 17-88

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SPI-COMPATIBLE PORT CONTROLLER

Specific Information for the ADSP-BF50x .................................. 18-1

Overview .................................................................................... 18-2

Features ...................................................................................... 18-2

Interface Overview ..................................................................... 18-3

External Interface .................................................................. 18-4

SPI Clock Signal (SCK) .................................................... 18-4

Master-Out, Slave-In (MOSI) Signal ................................. 18-5

Master-In, Slave-Out (MISO) Signal ................................. 18-5

SPI Slave Select Input Signal (SPISS) ................................ 18-6

SPI Slave Select Enable Output Signals ............................. 18-7

Slave Select Inputs ............................................................ 18-8

Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems 18-8

Internal Interfaces ............................................................... 18-10

DMA Functionality ........................................................ 18-10

Description of Operation .......................................................... 18-11

SPI Transfer Protocols ......................................................... 18-11

SPI General Operation ........................................................ 18-14

Clock Signals ...................................................................... 18-15

Interrupt Output ................................................................ 18-16

Functional Description ............................................................. 18-16

Master Mode Operation (Non-DMA) .................................. 18-17

Transfer Initiation From Master (Transfer Modes) ................ 18-18

Slave Mode Operation (Non-DMA) .................................... 18-19

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Slave Ready for a Transfer .................................................... 18-21

Programming Model ................................................................. 18-21

Beginning and Ending an SPI Transfer ................................. 18-21

Master Mode DMA Operation ............................................. 18-23

Slave Mode DMA Operation ............................................... 18-26

SPI Registers ............................................................................. 18-33

SPI Baud Rate (SPI_BAUD) Register ................................... 18-34

SPI Control (SPI_CTL) Register .......................................... 18-35

SPI Flag (SPI_FLG) Register ................................................ 18-37

SPI Status (SPI_STAT) Register ........................................... 18-39

Mode Fault Error (MODF) ............................................. 18-40

Transmission Error (TXE) ............................................... 18-41

Reception Error (RBSY) .................................................. 18-41

Transmit Collision Error (TXCOL) ................................. 18-41

SPI Transmit Data Buffer (SPI_TDBR) Register .................. 18-41

SPI Receive Data Buffer (SPI_RDBR) Register ..................... 18-42

SPI RDBR Shadow (SPI_SHADOW) Register ..................... 18-43

Programming Examples ............................................................. 18-44

Core-Generated Transfer ...................................................... 18-44

Initialization Sequence .................................................... 18-44

Starting a Transfer ........................................................... 18-45

Post Transfer and Next Transfer ....................................... 18-46

Stopping ......................................................................... 18-47

DMA-Based Transfer ........................................................... 18-47

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DMA Initialization Sequence .......................................... 18-48

SPI Initialization Sequence ............................................. 18-49

Starting a Transfer .......................................................... 18-50

Stopping a Transfer ......................................................... 18-50

Unique Information for the ADSP-BF50x Processor .................. 18-53

SPORT CONTROLLER

Specific Information for the ADSP-BF50x .................................. 19-1

Overview .................................................................................... 19-2

Features ................................................................................ 19-2

Interface Overview ..................................................................... 19-4

SPORT Pin/Line Terminations .............................................. 19-9

Description of Operation .......................................................... 19-10

SPORT Disable .................................................................. 19-10

Setting SPORT Modes ........................................................ 19-11

Stereo Serial Operation ....................................................... 19-11

Multichannel Operation ...................................................... 19-15

Multichannel Enable ....................................................... 19-18

Frame Syncs in Multichannel Mode ................................ 19-19

The Multichannel Frame ................................................ 19-20

Multichannel Frame Delay .............................................. 19-21

Window Size .................................................................. 19-21

Window Offset ............................................................... 19-22

Other Multichannel Fields in SPORT_MCMC2 ............. 19-22

Channel Selection Register .............................................. 19-23

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Multichannel DMA Data Packing ................................... 19-24

Support for H.100 Standard Protocol ................................... 19-25

2× Clock Recovery Control ............................................. 19-25

Functional Description ............................................................. 19-26

Clock and Frame Sync Frequencies ...................................... 19-26

Maximum Clock Rate Restrictions .................................. 19-27

Word Length ....................................................................... 19-28

Bit Order ............................................................................ 19-28

Data Type ........................................................................... 19-28

Companding ....................................................................... 19-29

Clock Signal Options .......................................................... 19-30

Frame Sync Options ............................................................ 19-31

Framed Versus Unframed ................................................ 19-31

Internal Versus External Frame Syncs ............................... 19-32

Active Low Versus Active High Frame Syncs .................... 19-33

Sampling Edge for Data and Frame Syncs ........................ 19-33

Early Versus Late Frame Syncs (Normal Versus

Alternate Timing) ........................................................ 19-35

Data Independent Transmit Frame Sync .......................... 19-37

Moving Data Between SPORTs and Memory ....................... 19-38

SPORT RX, TX, and Error Interrupts ................................. 19-38

Peripheral Bus Errors ........................................................... 19-39

Timing Examples ................................................................ 19-39

SPORT Registers ...................................................................... 19-45

Register Writes and Effective Latency ................................... 19-46

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SPORT Transmit Configuration

(SPORT_TCR1 and SPORT_TCR2) Registers ................. 19-47

SPORT Receive Configuration

(SPORT_RCR1 and SPORT_RCR2) Registers ................. 19-52

Data Word Formats ............................................................. 19-56

SPORT Transmit Data (SPORT_TX) Register ..................... 19-57

SPORT Receive Data (SPORT_RX) Register ....................... 19-59

SPORT Status (SPORT_STAT) Register ............................. 19-62

SPORT Transmit and Receive Serial Clock Divider

(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers ... 19-63
SPORT Transmit and Receive Frame Sync Divider

(SPORT_TFSDIV and SPORT_RFSDIV) Registers ......... 19-64

SPORT Multichannel Configuration

(SPORT_MCMC1 and SPORT_MCMC2) Registers ....... 19-65

SPORT Current Channel (SPORT_CHNL) Register ........... 19-66

SPORT Multichannel Receive Selection

(SPORT_MRCSn) Registers ............................................. 19-67

SPORT Multichannel Transmit Selection

(SPORT_MTCSn) Registers ............................................. 19-68

Programming Examples ............................................................ 19-69

SPORT Initialization Sequence ........................................... 19-70

DMA Initialization Sequence .............................................. 19-72

Interrupt Servicing .............................................................. 19-74

Starting a Transfer ............................................................... 19-75

Unique Information for the ADSP-BF50x Processor .................. 19-76

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PARALLEL PERIPHERAL INTERFACE

Specific Information for the ADSP-BF50x ................................... 20-1

Overview .................................................................................... 20-2

Features ...................................................................................... 20-2

Interface Overview ...................................................................... 20-3

Description of Operation ............................................................ 20-4

Functional Description ............................................................... 20-5

ITU-R 656 Modes ................................................................. 20-5

ITU-R 656 Background .................................................... 20-5

ITU-R 656 Input Modes ................................................... 20-9

Entire Field ................................................................... 20-9

Active Video Only ....................................................... 20-10

Vertical Blanking Interval (VBI) Only ......................... 20-10

ITU-R 656 Output Mode ............................................... 20-11

Frame Synchronization in ITU-R 656 Modes .................. 20-11

General-Purpose PPI Modes ................................................ 20-12

Data Input (RX) Modes .................................................. 20-14

No Frame Syncs .......................................................... 20-15

1, 2, or 3 External Frame Syncs ................................... 20-16

2 or 3 Internal Frame Syncs ......................................... 20-16

Data Output (TX) Modes ............................................... 20-17

No Frame Syncs .......................................................... 20-17

1 or 2 External Frame Syncs ........................................ 20-18

1, 2, or 3 Internal Frame Syncs .................................... 20-19

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Frame Synchronization in GP Modes .............................. 20-19

Modes With Internal Frame Syncs ............................... 20-19

Modes With External Frame Syncs .............................. 20-21

Programming Model ................................................................. 20-22

DMA Operation ................................................................. 20-22

PPI Registers ............................................................................ 20-25

PPI Control Register (PPI_CONTROL) ............................ 20-25

PPI Status Register (PPI_STATUS) ..................................... 20-29

PPI Delay Count Register (PPI_DELAY) ............................. 20-32

PPI Transfer Count Register (PPI_COUNT) ....................... 20-32

PPI Lines Per Frame Register (PPI_FRAME) ....................... 20-33

Programming Examples ............................................................ 20-34

Unique Information for the ADSP-BF50x Processor .................. 20-37

REMOVABLE STORAGE INTERFACE

Overview .................................................................................... 21-1

Interface Overview ..................................................................... 21-2

Description of Operation ............................................................ 21-6

Functional Description ............................................................... 21-9

RSI Clock Configuration ...................................................... 21-9

RSI Interface Configuration ................................................ 21-10

Card Detection ................................................................... 21-11

RSI Power Saving Configuration ......................................... 21-13

RSI Commands and Responses ............................................ 21-13

IDLE State ..................................................................... 21-19

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PEND State .................................................................... 21-19

SEND State .................................................................... 21-19

WAIT State .................................................................... 21-20

RECEIVE State .............................................................. 21-20

CEATA_INT_WAIT State .............................................. 21-21

CEATA_INT_DIS State .................................................. 21-21

RSI Command Path CRC .................................................... 21-22

RSI Data ............................................................................. 21-22

RSI Data Transmit Path ....................................................... 21-25

RSI Data Receive Path ......................................................... 21-26

RSI Data Path CRC ............................................................. 21-28

RSI Data FIFO ................................................................... 21-28

SDIO Interrupt and Read Wait Support ............................... 21-30

Programming Model ................................................................. 21-31

Card Identification .............................................................. 21-31

SD Card Identification Procedure .................................... 21-31

MMC Identification Procedure ....................................... 21-33

Single Block Write Operations ............................................. 21-34

Using Core ..................................................................... 21-35

Using DMA .................................................................... 21-36

Single Block Read Operation ............................................... 21-38

Using Core ..................................................................... 21-39

Using DMA .................................................................... 21-41

Multiple Block Write Operation .......................................... 21-42

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Using Core ..................................................................... 21-43

Using DMA ................................................................... 21-45

Multiple Block Read Operation ........................................... 21-47

Using Core ..................................................................... 21-47

Using DMA ................................................................... 21-49

RSI Registers ............................................................................ 21-51

RSI Power Control Register (RSI_PWR_CONTROL) ......... 21-53

RSI Clock Control Register (RSI_CLK_CONTROL) .......... 21-54

RSI Argument Register (RSI_ARGUMENT) ....................... 21-56

RSI Command Register (RSI_COMMAND) ....................... 21-56

RSI Response Command Register (RSI_RESP_CMD) ......... 21-58

RSI Response Registers (RSI_RESPONSEx) ........................ 21-59

RSI Data Timer Register (RSI_DATA_TIMER) .................. 21-60

RSI Data Length Register (RSI_DATA_LGTH) ................... 21-61

RSI Data Control Register (RSI_DATA_CONTROL) ......... 21-61

RSI Data Counter Register (RSI_DATA_CNT) ................... 21-63

RSI Status Register (RSI_STATUS) ..................................... 21-64

RSI Status Clear Register (RSI_STATUSCL) ....................... 21-67

RSI Interrupt Mask Registers (RSI_MASKx) ....................... 21-69

RSI FIFO Counter Register (RSI_FIFO_CNT) ................... 21-72

RSI CE-ATA Control Register (RSI_CEATA_CONTROL) .. 21-73

RSI Data FIFO Register (RSI_FIFO) .................................. 21-74

RSI Exception Status Register (RSI_ESTAT) ....................... 21-74

RSI Exception Mask Register (RSI_EMASK) ....................... 21-76

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RSI Configuration Register (RSI_CONFIG) ........................ 21-77

RSI Read Wait Enable Register (RSI_RD_WAIT_EN) ......... 21-79

RSI Peripheral ID Registers (RSI_PIDx) .............................. 21-80

ADC CONTROL MODULE (ACM)

Interface Overview ...................................................................... 22-3

Events ................................................................................... 22-6

Timers .................................................................................. 22-6

External Triggers ................................................................... 22-7

Event Register Pairs ............................................................... 22-9

Event Comparators ............................................................... 22-9

Timing Generation Unit ........................................................ 22-9

Interrupts ............................................................................ 22-10

Description of Operation .......................................................... 22-10

ADC Power Down .............................................................. 22-11

Single-Shot Sequencing Mode Emulation ............................. 22-11

Continuous Sequencing Mode Emulation ........................... 22-12

Functional Description ............................................................. 22-15

ADC Sampling Latency ....................................................... 22-18

ACM External Pin Timing ................................................... 22-20

Case 1—Chip Select Asserted During the

High Phase of ACLK .................................................... 22-22

Case 2—Chip Select Asserted During the

Low Phase of ACLK ..................................................... 22-23

Case 3—Chip Select Asserted Right Before the

Falling Edge of ACLK .................................................. 22-24

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Contents

Case 4—Chip Select Asserted Right Before the

Rising Edge of ACLK ................................................... 22-25

Case 5—ACLK Polarity Set to 1 (CLKPOL=1) ............... 22-26

ACM Timing Specifications ................................................ 22-26

Programming Model ................................................................. 22-27

ACM Registers ......................................................................... 22-28

ACM Control (ACM_CTL) Register ................................... 22-29

ACM Status (ACM_STAT) Register .................................... 22-30

ACM Event Status (ACM_ES) Register ............................... 22-31

ACM Event Interrupt Mask (ACM_IMSK) Register ............ 22-32

ACM Missed Event Status (ACM_MS) Register ................... 22-33

ACM Event Missed Interrupt Mask (ACM_EMSK) Register 22-34

ACM Event Control (ACM_ERx) Registers ......................... 22-35

ACM Event Time (ACM_ETx) Registers ............................. 22-36

ACM Timing Configuration (ACM_TCx) Registers ............ 22-36

ACM Timing Configuration 0 (ACM_TC0) Register ...... 22-37

ACM Timing Configuration 1 (ACM_TC1) Register ...... 22-38

Programming Examples ............................................................ 22-38

ANALOG/DIGITAL CONVERTER (ADC)

ADC Architecture ...................................................................... 23-1

Maximum ADC Sampling Rate .................................................. 23-4

Interfacing the ADC With the ACM and the SPORT ............ 23-4

Interfacing the ADC With the SPORT and With TMR Pins .. 23-6

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SYSTEM RESET AND BOOTING

Overview .................................................................................... 24-1

Reset and Power-up .................................................................... 24-3

Hardware Reset ..................................................................... 24-4

Software Resets ...................................................................... 24-5

Reset Vector .......................................................................... 24-6

Servicing Reset Interrupts ...................................................... 24-6

Basic Booting Process .................................................................. 24-8

Block Headers ..................................................................... 24-10

Block Code ..................................................................... 24-12

DMA Code Field ........................................................ 24-12

Block Flags Field ......................................................... 24-14

Header Checksum Field .............................................. 24-15

Header Sign Field ........................................................ 24-16

Target Address ................................................................ 24-16

Byte Count ..................................................................... 24-17

Argument ....................................................................... 24-17

Boot Host Wait (HWAIT) Feedback Strobe ......................... 24-18

Using HWAIT as Reset Indicator .................................... 24-19

Boot Termination ................................................................ 24-19

Single Block Boot Streams ................................................... 24-20

Direct Code Execution .................................................... 24-21

Advanced Boot Techniques ........................................................ 24-22

Initialization Code ............................................................... 24-22

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Quick Boot ......................................................................... 24-27

Indirect Booting .................................................................. 24-28

Callback Routines ............................................................... 24-29

Error Handler ..................................................................... 24-31

CRC Checksum Calculation ................................................ 24-32

Load Functions ................................................................... 24-32

Calling the Boot Kernel at Runtime .................................... 24-33

Debugging the Boot Process ................................................ 24-34

Boot Management .................................................................... 24-36

Booting a Different Application .......................................... 24-37

Multi-DXE Boot Streams ................................................ 24-38

Determining Boot Stream Start Addresses ....................... 24-42

Initialization Hook Routine ............................................ 24-42

Specific Boot Modes ................................................................. 24-43

No Boot Mode .................................................................... 24-44

Flash Boot Modes ............................................................... 24-44

SPI Master Boot Modes ....................................................... 24-46

SPI Device Detection Routine ........................................ 24-48

SPI Slave Boot Mode ........................................................... 24-50

PPI Boot Mode ................................................................... 24-52

UART Slave Mode Boot ...................................................... 24-54

Reset and Booting Registers ...................................................... 24-58

Software Reset (SWRST) Register ....................................... 24-58

System Reset Configuration (SYSCR) Register ..................... 24-60

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Boot Code Revision Control (BK_REVISION) .................... 24-62

Boot Code Date Code (BK_DATECODE) .......................... 24-63

Zero Word (BK_ZEROS) .................................................... 24-64

Ones Word (BK_ONES) ..................................................... 24-65

Data Structures ......................................................................... 24-65

ADI_BOOT_HEADER ...................................................... 24-66

ADI_BOOT_BUFFER ........................................................ 24-66

ADI_BOOT_DATA ............................................................ 24-66

dFlags Word ................................................................... 24-71

Callable ROM Functions for Booting ........................................ 24-72

BFROM_FINALINIT ......................................................... 24-72

BFROM_PDMA ................................................................. 24-73

BFROM_MDMA .............................................................. 24-73

BFROM_MEMBOOT ........................................................ 24-74

BFROM_SPIBOOT ............................................................ 24-76

BFROM_BOOTKERNEL .................................................. 24-78

BFROM_CRC32 ................................................................ 24-78

BFROM_CRC32POLY ....................................................... 24-79

BFROM_CRC32CALLBACK ............................................. 24-80

BFROM_CRC32INITCODE ............................................. 24-80

Programming Examples ............................................................. 24-81

Example System Reset ......................................................... 24-81

Example Exiting Reset to User Mode ................................... 24-82

Example Exiting Reset to Supervisor Mode .......................... 24-82

ADSP-BF50x Blackfin Processor Hardware Reference xlv

Contents

Example Power Management with Initcode .......................... 24-83

Example XOR Checksum .................................................... 24-85

Example Direct Code Execution .......................................... 24-87

SYSTEM DESIGN

Pin Descriptions ......................................................................... 25-1

Managing Clocks ........................................................................ 25-1

Managing Core and System Clocks ........................................ 25-2

Configuring and Servicing Interrupts .......................................... 25-2

Semaphores ................................................................................ 25-2

Example Code for Query Semaphore ..................................... 25-3

Data Delays, Latencies and Throughput ...................................... 25-4

Bus Priorities .............................................................................. 25-4

High-Frequency Design Considerations ...................................... 25-5

Signal Integrity ..................................................................... 25-5

Decoupling Capacitors and Ground Planes ............................ 25-6

5 Volt Tolerance .................................................................... 25-8

Test Point Access ................................................................... 25-8

Oscilloscope Probes ............................................................... 25-8

Recommended Reading ......................................................... 25-9

Resetting the Processor ............................................................. 25-10

Recommendations for Unused Pins ........................................... 25-10

Programmable Outputs ............................................................. 25-11

Voltage Regulation Interface ..................................................... 25-11

xlvi ADSP-BF50x Blackfin Processor Hardware Reference

Contents

SYSTEM MMR ASSIGNMENTS

Processor-Specific Memory Registers ............................................ A-2

Core Timer Registers .................................................................... A-3

System Reset and Interrupt Control

Registers ................................................................................... A-4

DMA/Memory DMA Control Registers ....................................... A-5

Ports Registers .............................................................................. A-8

Timer Registers .......................................................................... A-11

Watchdog Timer Registers .......................................................... A-15

GP Counter Registers ................................................................. A-15

Dynamic Power Management Registers ....................................... A-17

PPI Registers .............................................................................. A-17

SPI Controller Registers ............................................................. A-18

SPORT Controller Registers ....................................................... A-19

UART Controller Registers ........................................................ A-23

TWI Registers ............................................................................ A-25

CAN Registers ........................................................................... A-26

ACM Registers ........................................................................... A-42

PWM Registers .......................................................................... A-44

RSI Registers ............................................................................. A-46

ACM Registers ........................................................................... A-47

TEST FEATURES

JTAG Standard ............................................................................ B-1

Boundary-Scan Architecture ......................................................... B-2

ADSP-BF50x Blackfin Processor Hardware Reference xlvii

Contents

Instruction Register ................................................................. B-4

Public Instructions .................................................................. B-6

EXTEST – Binary Code 00000 ........................................... B-6

SAMPLE/PRELOAD – Binary Code 10000 ........................ B-6

BYPASS – Binary Code 11111 ............................................ B-6

Boundary-Scan Register .......................................................... B-7

INDEX

xlviii ADSP-BF50x Blackfin Processor Hardware Reference

Contents

ADSP-BF50x Blackfin Processor Hardware Reference xlix

Contents

l ADSP-BF50x Blackfin Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using an enhanced

Blackfin® processor from Analog Devices.

Purpose of This Manual

The ADSP-BF50x Blackfin Processor Hardware Reference provides architec-

tural information about the ADSP-BF50x processors. This hardware

reference provides the main architectural information about these proces-

sors. The architectural descriptions cover functional blocks, buses, and

ports, including all features and processes that they support. For program-

ming information, see the Blackfin Processor Programming Reference. For

timing, electrical, and package specifications, see the ADSP-BF504,

ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet.

Intended Audience

The primary audience for this manual is a programmer who is familiar

with Analog Devices processors. The manual assumes the audience has a

working knowledge of the appropriate processor architecture and instruc-

tion set. Programmers who are unfamiliar with Analog Devices processors

can use this manual, but should supplement it with other texts, such as

hardware reference and programming reference manuals, that describe

their target architecture.

ADSP-BF50x Blackfin Processor Hardware Reference li

Manual Contents

Manual Contents

This manual consists of one volume:

• Chapter 1, “Introduction”

Provides a high level overview of the processor, including peripher­als, power management, and development tools.

• Chapter 2, “Memory”

Describes processor-specific memory topics, including L1memories
and processor-specific memory MMRs.

• Chapter 3, “Chip Bus Hierarchy”

Describes on-chip buses, including how data moves through the
system.

• Chapter 4, “System Interrupts”

Describes the system peripheral interrupts, including setup and
clearing of interrupt requests.

• Chapter 5, “External Bus Interface Unit”

Describes the external bus interface unit of the processor and mem­ory interface.

• Chapter 6, “Internal Flash Memory”

Describes the internal flash memory and programmable features.

• Chapter 7, “Direct Memory Access”

Describes the peripheral DMA and Memory DMA controllers.
Includes performance, software management of DMA, and DMA
errors.

• Chapter 8, “Dynamic Power Management”

Describes the clocking, including the PLL, and the dynamic power
management controller.

lii ADSP-BF50x Blackfin Processor Hardware Reference

Preface

• Chapter 9, “General-Purpose Ports”

Describes the general-purpose I/O ports, including the structure of
each port, multiplexing, configuring the pins, and generating
interrupts.

• Chapter 10, “General-Purpose Timers”

Describes the eight general-purpose timers.

• Chapter 11, “Core Timer”

Describes the core timer.

• Chapter 12, “Watchdog Timer”

Describes the watchdog timer.

• Chapter 13, “General-Purpose Counter”

Describes the Rotary (up/down) Counter. This counter provides
support for manually controlled rotary controllers, such as the vol­ume wheel on a radio device. This unit also supports industrial or
motor-control type of wheels.

• Chapter 14, “PWM Controller”

Describes the The PWM controller—a flexible, programmable,
three-phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a three-phase volt­age source inverter for ac induction motor (ACIM) or permanent
magnet synchronous motor (PMSM) control.

• Chapter 15, “UART Port Controllers”

Describes the Universal Asynchronous Receiver/Transmitter port
that converts data between serial and parallel formats. The UART
supports the half-duplex IrDA® SIR protocol as a mode-enabled
feature.

• Chapter 16, “Two Wire Interface Controller”

Describes the Two Wire Interface (TWI) controller, which allows a
device to interface to an Inter IC bus as specified by the Philips I2C
Bus Specification version 2.1 dated January 2000.

ADSP-BF50x Blackfin Processor Hardware Reference liii

Manual Contents

• Chapter 17, “CAN Module”

Describes the CAN module, a low bit rate serial interface intended
for use in applications where bit rates are typically up to 1Mbit/s.

• Chapter 18, “SPI-Compatible Port Controller”

Describes the Serial Peripheral Interface (SPI) port that provides an
I/O interface to a variety of SPI compatible peripheral devices.

• Chapter 19, “SPORT Controller”

Describes the independent, synchronous Serial Port Controller
which provides an I/O interface to a variety of serial peripheral
devices.

• Chapter 20, “Parallel Peripheral Interface”

Describes the Parallel Peripheral Interface (PPI) of the processor.
The PPI is a half-duplex, bidirectional port accommodating up to
16 bits of data and is used for digital video and data converter
applications.

• Chapter 21, “Removable Storage Interface”

Describes the RSI interface for multimedia cards (MMC), secure
digital memory cards (SD), secure digital input/output cards
(SDIO) and consumer electronic ATA devices (CE-ATA).

• Chapter 22, “ADC Control Module (ACM)”

Describes the ADC control module (ACM), which provides an
interface to synchronize the controls between the processor and the
internal analog-to-digital converter (ADC) module.

• Chapter 23, “Analog/Digital Converter (ADC)”

Describes the internal ADC, which is a dual, 12-bit, high speed,
low power, successive approximation ADC that operates from a
single 2.7 V to 5.25 V power supply and features throughput rates
up to 1.66 MSPS. The device contains two ADCs, each preceded
by a 3-channel multiplexer, and a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 30 MHz.

liv ADSP-BF50x Blackfin Processor Hardware Reference

Preface

• Chapter 24, “System Reset and Booting”

Describes the booting methods, booting process and specific boot
modes for the processor.

• Chapter 25, “System Design”

Describes how to use the processor as part of an overall system. It
includes information about bus timing and latency numbers, sema­phores, and a discussion of the treatment of unused pins.

• Appendix A, “System MMR Assignments”

Lists the memory-mapped registers included in this manual, their
addresses, and cross-references to text.

• Appendix B, “Test Features”

Describes test features for the processor, discusses the JTAG stan­dard, boundary-scan architecture, instruction and boundary
registers, and public instructions.



This hardware reference is a companion document to the Blackfin
Processor Programming Reference.

What’s New in This Manual

This revision (1.0) is the third release of the ADSP-BF50x Blackfin Proces-

sor Hardware Reference. This revision corrects the following issues:

• Reset value for the PLL_CTL register in Chapter 8, “Dynamic

Power Management”

• Pin and port control information in Chapter 15, “UART Port

Controllers”

• Decoupling capacitor diagram in Chapter 25, “System Design”

ADSP-BF50x Blackfin Processor Hardware Reference lv

Technical or Customer Support

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technical_support

• E-mail tools questions to

[e-mail]

• E-mail processor questions to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

lvi ADSP-BF50x Blackfin Processor Hardware Reference

Preface

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in
VisualDSP++®.

Blackfin (ADSP-BFxxx) Processors

The name Blackfin refers to a family of 16-bit, embedded processors.
VisualDSP++ currently supports the following Blackfin families
ADSP-BF50x, ADSP-BF51x, ADSP-BF52x, ADSP-BF53x, ADSP-BF54x,
and ADSP-BF561 processors.

TigerSHARC® (ADSP-TSxxx) Processors

The name TigerSHARC refers to a family of floating-point and fixed-point
[8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently supports the
following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.

SHARC® (ADSP-21xxx) Processors

The name SHARC refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++ currently supports the following
SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x,
ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x, and
ADSP-2148x.

Product Information

Product information can be obtained from the Analog Devices Web site,
VisualDSP++ online Help system, and a technical library CD.

ADSP-BF50x Blackfin Processor Hardware Reference lvii

Product Information

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.

To access a complete technical library for each processor family, go to

http://www.analog.com/processors/technical_library. The manuals

selection opens a list of current manuals related to the product as well as a
link to the previous revisions of the manuals. When locating your manual
title, note a possible errata check mark next to the title that leads to the
current correction report against the manual.

Also note, MyAnalog.com is a free feature of the Analog Devices Web site
that allows customization of a Web page to display only the latest infor­mation about products you are interested in. You can choose to receive
weekly e-mail notifications containing updates to the Web pages that meet
your interests, including documentation errata against all manuals.

MyAnalog.com provides access to books, application notes, data sheets,

code examples, and more.

Visit MyAnalog.com to sign up. If you are a registered user, just log on.
Your user name is your e-mail address.

VisualDSP++ Online Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, Dinkum
Abridged C++ library, and FLEXnet License Tools software documenta­tion. You can search easily across the entire VisualDSP++ documentation
set for any topic of interest.

For easy printing, supplementary Portable Documentation Format (.
files for all manuals are provided on the VisualDSP++ installation CD.

lviii ADSP-BF50x Blackfin Processor Hardware Reference

pdf)

Each documentation file type is described as follows.

File Description

.chm Help system files and manuals in Microsoft help format

Preface

.htm or
.html

.pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the

Dinkum Abridged C++ library and FLEXnet License Tools software documenta­tion. Viewing and printing the
Explorer 6.0 (or higher).

.pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

.html files requires a browser, such as Internet

Technical Library CD

The technical library CD contains seminar materials, product highlights, a
selection guide, and documentation files of processor manuals, Visu­alDSP++ software manuals, and hardware tools manuals for the following
processor families: Blackfin, SHARC, TigerSHARC, ADSP-218x, and
ADSP-219x.

To order the technical library CD, go to http://www.analog.com/proces-

sors/technical_library, navigate to the manuals page for your

processor, click the request CD check mark, and fill out the order form.

Data sheets, which can be downloaded from the Analog Devices Web site,
change rapidly, and therefore are not included on the technical library
CD. Technical manuals change periodically. Check the Web site for the
latest manual revisions and associated documentation errata.

EngineerZone

EngineerZone is a technical support forum from Analog Devices. It allows
you direct access to ADI technical support engineers. You can search
FAQs and technical information to get quick answers to your embedded
processing and DSP design questions.

ADSP-BF50x Blackfin Processor Hardware Reference lix

Notation Conventions

Use EngineerZone to connect with other DSP developers who face similar
design challenges. You can also use this open forum to share knowledge
and collaborate with the ADI support team and your peers. Visit

http://ez.analog.com to sign up.

Social Networking Web Sites

You can now follow Analog Devices Blackfin development on Twitter and
LinkedIn. To access:

• Twitter:

http://twitter.com/blackfin

• LinkedIn: Network with the LinkedIn group, Analog Devices
Blackfin: http://www.linkedin.com

Notation Conventions

Text conventions used in this manual are identified and described as fol­lows. Additional conventions, which apply only to specific chapters, may
appear throughout this document.

Example Description

Close command
(File menu)

{this | that} Alternative required items in syntax descriptions appear within curly

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

[this,…] Optional item lists in syntax descriptions appear within brackets delim-

Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close com­mand appears on the File menu).

brackets and separated by vertical bars; read the example as
One or the other is required.

rated by vertical bars; read the example as an optional

ited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of

this.

this or that.

this or that.

lx ADSP-BF50x Blackfin Processor Hardware Reference

Preface







Example Description

.SECTION Commands, directives, keywords, and feature names are in text with let-

ter gothic font.

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the

online version of this book, the word Note appears instead of this symbol.

Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...

A Caution identifies conditions or inappropriate usage of the product that
could lead to undesirable results or product damage. In the online version
of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the devices
users. In the online version of this book, the word War ni ng appears
instead of this symbol.

ADSP-BF50x Blackfin Processor Hardware Reference lxi

Notation Conventions

lxii ADSP-BF50x Blackfin Processor Hardware Reference

1 INTRODUCTION

The ADSP-BF50x processors are members of the Blackfin processor fam­ily that offer significant high performance and low power features while
retaining their ease-of-use benefits. The ADSP-BF504, ADSP-BF504F,
and ADSP-BF506F processors have differing peripheral features. For
details, see Table 1-1. Note that the ADSP-BF504 and ADSP-BF504F are
pin-compatible.



This hardware reference is a companion document to the Blackfin
Processor Programming Reference.

General Description of Processor

The ADSP-BF50x processor is a member of the Blackfin® family of prod­ucts, incorporating the Analog Devices/Intel Micro Signal Architecture
(MSA). Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantages of a clean, orthogonal RISC-like micro­processor instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set architecture.

The ADSP-BF50x processor is completely code compatible with other
Blackfin processors. ADSP-BF50x processors offer performance up to
400 MHz and reduced static power consumption. The processor features
are shown in Table 1-1.

ADSP-BF50x Blackfin Processor Hardware Reference 1-1

General Description of Processor

Table 1-1. Processor Comparison

Feature ADSP-BF504 ADSP-BF504F ADSP-BF506F

Up/Down/Rotary Counters 2 2 2

Timer/Counters with PWM 8 8 8

3-Phase PWM Units 2 2 2

SPORTs 2 2 2

SPIs 2 2 2

UARTs 2 2 2

Parallel Peripheral Interface 1 1 1

Removable Storage Interface 1 1 1

CAN 1 1 1

TWI 1 1 1

Internal 32M Bit Flash – 1 1

ADC Control Module (ACM) 1 1 1

Internal ADC – – 1

GPIOs 35 35 35

L1 Instruction SRAM 16K 16K 16K

L1 Instruction SRAM/Cache 16K 16K 16K

L1 Data SRAM 16K 16K 16K

L1 Data SRAM/Cache 16K 16K 16K

L1 Scratchpad 4K 4K 4K

Memory (bytes)

L3 Boot ROM 4K 4K 4K

By integrating a rich set of industry-leading system peripherals and mem­ory, Blackfin processors are the platform of choice for next-generation
applications that require RISC-like programmability, multimedia support,
and leading-edge signal processing in one integrated package.

1-2 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

Portable Low-Power Architecture

Blackfin processors provide world-class power management and perfor­mance. They are produced with a low-power and low-voltage design
methodology and feature on-chip dynamic power management, which
provides the ability to vary both the voltage and frequency of operation to
significantly lower overall power consumption. This capability can result
in a substantial reduction in power consumption, compared with just
varying the frequency of operation. This allows longer battery life for
portable appliances.

System Integration

The ADSP-BF50x processors are highly integrated system-on-a-chip solu­tions for the next generation of embedded industrial, instrumentation,
and power/motion control applications. By combining industry-standard
interfaces with a high-performance signal processing core, cost-effective
applications can be developed quickly, without the need for costly external
components. The system peripherals include a watchdog timer; two 32-bit
up/down counters with rotary support; eight 32-bit timers/ counters with
PWM support; two pairs of three-phase 16-bit center-based PWM units;
two dual-channel, full-duplex synchronous serial ports (SPORTs); two
serial peripheral interface (SPI) compatible ports; two UARTs with IrDA
support; a parallel peripheral interface (PPI); a removable storage interface
(RSI) controller; an internal ADC with 12 channels, 12 bits, up to 2
MSPS, an ACM controller; a controller area network (CAN) controller; a
two-wire interface (TWI) controller; and an internal 32M bit flash.

ADSP-BF50x Blackfin Processor Hardware Reference 1-3

Peripherals

SPORT1–0

VOLTAGE REGULATOR INTERFACE

GPIO

PORT F

PORT G

PORT H

JTAG TEST AND EMULATION

PERIPHERAL

ACCESS BUS

PWM 1–0

WATCHDOG TIMER

SPI1–0

RSI

ACM

PPI

CAN

COUNTER1–0

TWI

BOOT

ROM

DMA

ACCESS

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

L1 DATA

MEMORY

L1 INSTRUCTION

MEMORY

16

DCB

EAB

MEMORY PORT

FLASH CONTROL

B

UART1–0

DEB

32M BIT

FLASH

TIMER7–0

ADC

Peripherals

The ADSP-BF50x processors contain a rich set of peripherals connected
to the core via several high-bandwidth buses, providing flexibility in sys­tem configuration as well as excellent overall system performance. (See

Figure 1-1.) Most of the peripherals are supported by a flexible DMA

structure. There are also two separate memory DMA channels dedicated
to data transfers between the processor’s memory spaces. Multiple on-chip
buses provide enough bandwidth to keep the processor core running even
when there is also activity on all of the on-chip and external peripherals.

Figure 1-1. ADSP-BF50x Processor Block Diagram

Memory Architecture

The Blackfin processor architecture structures memory as a single, unified
4G byte address space using 32-bit addresses. All resources, including
internal memory, external memory, and I/O control registers, occupy sep­arate sections of this common address space. The memory portions of this

1-4 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

address space are arranged in a hierarchical structure to provide a good
cost/performance balance of some very fast, low latency on-chip memory
as cache or SRAM, and larger, lower cost and lower performance off-chip
memory systems. Table 1-2 shows the memory for the ADSP-BF50x
processors.

Table 1-2. Memory Configurations

Type of Memory ADSP-BF50x

Instruction SRAM/cache, lockable by way or line 16K byte

Instruction SRAM 16K byte

Data SRAM/cache 16K byte

Data SRAM 16K byte

Data scratchpad SRAM 4K byte

L3 Boot ROM 4K byte

Total 72K byte

The L1 memory system is the primary highest performance memory avail­able to the core. The off-chip memory system, accessed through the
external bus interface unit (EBIU), provides expansion with flash memory
on the ADSP-BF504F and ADSP-BF506F processors.

The memory DMA controller provides high bandwidth data movement
capability. It can perform block transfers of code or data between the
internal memory and the external memory spaces.

ADSP-BF50x Blackfin Processor Hardware Reference 1-5

Memory Architecture

Internal Memory

The processor has three blocks of on-chip memory that provide high
bandwidth access to the core:

• L1 instruction memory, consisting of SRAM and a 4-way set-asso­ciative cache. This memory is accessed at full processor speed.

• L1 data memory, consisting of SRAM and/or a 2-way set-associa­tive cache. This memory block is accessed at full processor speed.

• L1 scratchpad RAM, which runs at the same speed as the L1 mem­ories but is only accessible as data SRAM and cannot be configured
as cache memory.

External Memory

External memory is accessed via the EBIU memory port. This 16-bit
interface provides a glue-less connection to the internal flash memory and
boot ROM. The EBIU on the processor interfaces with an internal flash
memory on the ADSP-BF504F and ADSP-BF506F devices. The internal
chip flash memory is a 32M bit (×16, multiple bank, burst) memory. The
features of this memory include:

• Synchronous/asynchronous read

• Synchronous burst read mode: 50 MHz

• Asynchronous/synchronous read mode

• Random access times: 70 ns

• Synchronous burst read suspend

• Memory blocks

• Multiple bank memory array: 4 Mbit banks

1-6 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

• Parameter blocks (top location)

• Dual operations

• Program erase in one bank while read in others

• No delay between read and write operations

• Block locking

• All blocks locked at power-up

• Any combination of blocks can be locked or locked down

• Security

• 128-bit user programmable OTP cells

• 64-bit unique device number

• Common flash interface (CFI)

• 100 000 program/erase cycles per block

Flash memory ships from the factory in an erased state except for block 0
of the parameter bank. Block 0 of the flash memory parameter bank ships
from the factory in an unknown state. An erase operation should be per­formed prior to programming this block.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are
mapped through the flat 32-bit address space. Control registers for
on-chip I/O devices are mapped into memory-mapped registers (MMRs)
at addresses near the top of the 4G byte address space. These are separated
into two smaller blocks: one contains the control MMRs for all core func­tions and the other contains the registers needed for setup and control of
the on-chip peripherals outside of the core. The MMRs are accessible only
in supervisor mode. They appear as reserved space to on-chip peripherals.

ADSP-BF50x Blackfin Processor Hardware Reference 1-7

DMA Support

DMA Support

The processor has multiple, independent DMA channels that support
automated data transfers with minimal overhead for the processor core.
DMA transfers can occur between the processor’s internal memories and
any of its DMA-capable peripherals. Additionally, DMA transfers can be
accomplished between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capable
peripherals include the SPORTs, SPI ports, UARTs, RSI, and PPI. Each
individual DMA-capable peripheral has at least one dedicated DMA
channel.

The processor DMA controller supports both one-dimensional (1-D) and
two-dimensional (2-D) DMA transfers. DMA transfer initialization can
be implemented from registers or from sets of parameters called descriptor
blocks.

The 2-D DMA capability supports arbitrary row and column sizes up to
64K elements by 64K elements, and arbitrary row and column step sizes
up to ±32K elements. Furthermore, the column step size can be less than
the row step size, allowing implementation of interleaved data streams.
This feature is especially useful in video applications where data can be
de-interleaved on the fly.

Examples of DMA types supported by the processor DMA controller
include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each full or
fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the base
DMA address within a common page

1-8 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

In addition to the dedicated peripheral DMA channels, there are two
memory DMA channels, which are provided for transfers between the var­ious memories of the processor system with minimal processor
intervention. Memory DMA transfers can be controlled by a very flexible
descriptor-based methodology or by a standard register-based autobuffer
mechanism.

General-Purpose I/O (GPIO)

Because of the rich set of peripherals, the processor groups the many
peripheral signals to three ports—Port F, Port G, and Port H. Most of the
associated pins are shared by multiple signals. The ports function as multi­plexer controls.

The processor has 35 bidirectional, general-purpose I/O (GPIO) pins allo­cated across three separate GPIO modules—PORTFIO, PORTGIO, and
PORTHIO, associated with Port F, Port G, and Port H, respectively.
Each GPIO-capable pin shares functionality with other processor periph­erals via a multiplexing scheme; however, the GPIO functionality is the
default state of the device upon power-up. Neither GPIO output nor
input drivers are active by default. Each general-purpose port pin can be
individually controlled by manipulation of the port control, status, and
interrupt registers:

• GPIO direction control register – Specifies the direction of each
individual GPIO pin as input or output.

• GPIO control and status registers – The processor employs a “write
one to modify” mechanism that allows any combination of individ­ual GPIO pins to be modified in a single instruction, without
affecting the level of any other GPIO pins. Four control registers
are provided. One register is written in order to set pin values, one
register is written in order to clear pin values, one register is written

ADSP-BF50x Blackfin Processor Hardware Reference 1-9

Two-Wire Interface

in order to toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows soft­ware to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt mask
registers allow each individual GPIO pin to function as an inter­rupt to the processor. Similar to the two GPIO control registers
that are used to set and clear individual pin values, one GPIO
interrupt mask register sets bits to enable interrupt function, and
the other GPIO interrupt mask register clears bits to disable inter­rupt function. GPIO pins defined as inputs can be configured to
generate hardware interrupts, while output pins can be triggered by
software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO interrupt sen­sitivity registers specify whether individual pins are level- or
edge-sensitive and specify—if edge-sensitive—whether just the ris­ing edge or both the rising and falling edges of the signal are
significant. One register selects the type of sensitivity, and one reg­ister selects which edges are significant for edge-sensitivity.

Two-Wire Interface

The Two-Wire Interface (TWI) is fully compatible with the widely used
I2C bus standard. It was designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations. To preserve
processor bandwidth, the TWI controller can be set up and a transfer ini­tiated with interrupts only to service FIFO buffer data reads and writes.
Protocol related interrupts are optional.

1-10 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

The TWI externally moves 8-bit data while maintaining compliance with

2

the I

C bus protocol. The Philips I2C Bus Specification version 2.1 covers

many variants of I2C. The TWI controller includes these features:

• Simultaneous master and slave operation on multiple device
systems

• Support for multi-master data arbitration

• 7-bit addressing

• 100K bits/second and 400K bit/second data rates

• General call address support

• Master clock synchronization and support for clock low extension

• Separate multiple-byte receive and transmit FIFOs

• Low interrupt rate

• Individual override control of data and clock lines in the event of
bus lock-up

• Input filter for spike suppression

• Serial camera control bus support as specified in the OmniVision

Serial Camera Control Bus (SCCB) Functional Specification
version 2.1

RSI Interface

The removable storage interface (RSI) controller acts as the host interface
for multi-media cards (MMC), secure digital memory cards (SD Card),
secure digital input/output cards (SDIO), and CE-ATA hard disk drives.

ADSP-BF50x Blackfin Processor Hardware Reference 1-11

General-Purpose (GP) Counter

The following list describes the main features of the RSI controller:

• Support for a single MMC, SD memory, SDIO card or CE-ATA
hard disk drive

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit and 8-bit MMC modes

• Support for 4-bit and 8-bit CE-ATA hard disk drives

• A ten-signal external interface with clock, command, and up to
eight data lines

• Card detection using one of the data signals

• Card interface clock generation from SCLK

• SDIO interrupt and read wait features

• CE-ATA command completion signal recognition and disable

General-Purpose (GP) Counter

Two 32-bit GP counters are provided that can sense 2-bit quadrature or
binary codes as typically emitted by industrial drives or manual thumb
wheels. Each counter can also operate in general-purpose up/down count
modes. Then, count direction is either controlled by a level-sensitive input
signal or by two edge detectors. A third input can provide flexible zero
marker support and can alternatively be used to input the push-button sig­nal of thumb wheels. All three signals have a programmable debouncing
circuit. An internal signal forwarded to the GP timer unit enables one
timer to measure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by interrupts when
programmable count values are exceeded.

1-12 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

3-Phase PWM Unit

The processors integrate two flexible and programmable 3-phase PWM
waveform generators that can each be programmed to generate the
required switching patterns to drive a 3-phase voltage source inverter for
ac induction (ACIM) or permanent magnet synchronous (PMSM) motor
control. In addition, each PWM block contains special functions that con­siderably simplify the generation of the required PWM switching patterns
for control of the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode for switched reluc­tance motors (SRM).

Features of each 3-phase PWM generation unit are:

• 16-bit center-based PWM generation unit

• Programmable PWM pulse width

• Single/double update modes

• Programmable dead time and switching frequency

• Twos-complement implementation which permits smooth transi­tion to full ON and full OFF states

• Possibility to synchronize the PWM generation to an external
synchronization

• Special provisions for BDCM operation (crossover and output
enable functions)

• Wide variety of special switched reluctance (SR) operating modes

• Output polarity and clock gating control

• Dedicated asynchronous PWM shutdown signal

ADSP-BF50x Blackfin Processor Hardware Reference 1-13

Parallel Peripheral Interface

The six PWM output signals in each PWM controller consist of three
high-side drive signals (
drive signals (PWM_AL, PWM_BL, and PWM_CL). The polarity of the generated
PWM signal can be set with software, so that either active high or active
low PWM patterns can be produced. The switching frequency of the gen­erated PWM pattern is programmable. The PWM generator can operate
in single update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period, so that
the resultant PWM patterns are symmetrical about the midpoint of the
PWM period. In the double update mode, a second updating of the PWM
registers is implemented at the midpoint of the PWM period. In this
mode, it is possible to produce asymmetrical PWM patterns that produce
lower harmonic distortion in 3-phase PWM inverters.

PWM_AH, PWM_BH, and PWM_CH) and three low-side

Parallel Peripheral Interface

The processor provides a Parallel Peripheral Interface (PPI) that can con­nect directly to parallel A/D and D/A converters, ITU-R 601/656 video
encoders and decoders, and other general-purpose peripherals. The PPI
consists of a dedicated input clock pin and three multiplexed frame sync
pins. The input clock supports parallel data rates up to half the system
clock rate.

In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or
10-bit data elements. On-chip decode of embedded preamble control and
synchronization information is supported.

1-14 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

Three distinct ITU-R 656 modes are supported:

• Active video only - The PPI does not read in any data between the
End of Active Video (EAV) and Start of Active Video (SAV) pre­amble symbols, or any data present during the vertical blanking
intervals. In this mode, the control byte sequences are not stored to
memory; they are filtered by the PPI.

• Vertical blanking only - The PPI only transfers Vertical Blanking
Interval (VBI) data, as well as horizontal blanking information and
control byte sequences on VBI lines.

• Entire field - The entire incoming bit stream is read in through the
PPI. This includes active video, control preamble sequences, and
ancillary data that may be embedded in horizontal and vertical
blanking intervals.

Though not explicitly supported, ITU-R 656 output functionality can be
achieved by setting up the entire frame structure (including active video,
blanking, and control information) in memory and streaming the data out
the PPI in a frame sync-less mode. The processor’s 2-D DMA features
facilitate this transfer by allowing the static frame buffer (blanking and
control codes) to be placed in memory once, and simply updating the
active video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a wide variety
of data capture and transmission applications. The modes are divided into
four main categories, each allowing up to 16 bits of data transfer per

PPI_CLK cycle:

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

ADSP-BF50x Blackfin Processor Hardware Reference 1-15

SPORT Controllers

These modes support ADC/DAC connections, as well as video communi­cation with hardware signalling. Many of the modes support more than
one level of frame synchronization. If desired, a programmable delay can
be inserted between assertion of a frame sync and reception/transmission
of data.

SPORT Controllers

The processor incorporates two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor communications.
The SPORTs support these features:

• Bidirectional, I2S capable operation

Each SPORT has two sets of independent transmit and receive
pins, which enable eight channels of I2S stereo audio.

• Buffered (eight-deep) transmit and receive ports

Each port has a data register for transferring data words to and
from other processor components and shift registers for shifting
data in and out of the data registers.

• Clocking

Each transmit and receive port can either use an external serial
clock or can generate its own in a wide range of frequencies.

• Word length

Each SPORT supports serial data words from 3 to 32 bits in
length, transferred in most significant bit first or least significant
bit first format.

1-16 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

• Framing

Each transmit and receive port can run with or without frame sync
signals for each data word. Frame sync signals can be generated
internally or externally, active high or low, and with either of two
pulse widths and early or late frame sync.

• Companding in hardware

Each SPORT can perform A-law or µ-law companding according
to ITU recommendation G.711. Companding can be selected on
the transmit and/or receive channel of the SPORT without addi­tional latencies.

• DMA operations with single cycle overhead

Each SPORT can automatically receive and transmit multiple buf­fers of memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.

• Interrupts

Each transmit and receive port generates an interrupt upon com­pleting the transfer of a data word or after transferring an entire
data buffer or buffers through DMA.

• Multichannel capability

Each SPORT supports 128 channels out of a 1024-channel win­dow and is compatible with the H.100, H.110, MVIP-90, and
HMVIP standards.

ADSP-BF50x Blackfin Processor Hardware Reference 1-17

Serial Peripheral Interface (SPI) Ports

Serial Peripheral Interface (SPI) Ports

The processor has two SPI-compatible ports that enable the processor to
communicate with multiple SPI-compatible devices.

Each SPI interface uses three pins for transferring data: two data pins and
a clock pin. An SPI chip select input pin lets other SPI devices select the
processor, and several SPI chip select output pins let the processor select
other SPI devices. The SPI select pins are reconfigured general-purpose
I/O pins. Using these pins, the SPI port provides a full-duplex, synchro­nous serial interface, which supports both master and slave modes and
multimaster environments.

Each SPI port’s baud rate and clock phase/polarities are programmable,
and it has an integrated DMA controller, configurable to support either
transmit or receive data streams. The SPI’s DMA controller can only ser­vice unidirectional accesses at any given time.

During transfers, the SPI port simultaneously transmits and receives by
serially shifting data in and out of its two serial data lines. The serial clock
line synchronizes the shifting and sampling of data on the two serial data
lines.

Timers

There are nine general-purpose programmable timer units in the proces­sor. Eight timers have an external pin that can be configured either as a
Pulse Width Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths of external events.
These timer units can be synchronized to an external clock input con­nected to the TMRCLK/PPI_CLK pin or to the internal SCLK.

The timer units can be used in conjunction with the UARTs to measure
the width of the pulses in the datastream to provide an autobaud detect
function for a serial channel.

1-18 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

The timers can generate interrupts to the processor core to provide peri­odic events for synchronization, either to the processor clock or to a count
of external signals.

In addition to the eight general-purpose programmable timers, a 9th timer
is also provided. This extra timer is clocked by the internal processor clock
and is typically used as a system tick clock for generation of operating sys­tem periodic interrupts.

UART Ports

The ADSP-BF50x Blackfin processors provide two full-duplex universal
asynchronous receiver/transmitter (UART) ports. Each UART port pro­vides a simplified UART interface to other peripherals or hosts, enabling
full-duplex, DMA-supported, asynchronous transfers of serial data. A
UART port includes support for five to eight data bits, one or two stop
bits, and none, even, or odd parity. Each UART port supports two modes
of operation:

• PIO (programmed I/O). The processor sends or receives data by
writing or reading I/O-mapped UART registers. The data is dou­ble-buffered on both transmit and receive.

• DMA (direct memory access). The DMA controller transfers both
transmit and receive data. This reduces the number and frequency
of interrupts required to transfer data to and from memory. Each
UART has two dedicated DMA channels, one for transmit and one
for receive. These DMA channels have lower default priority than
most DMA channels because of their relatively low service rates.
Flexible interrupt timing options are available on the transmit side.

ADSP-BF50x Blackfin Processor Hardware Reference 1-19

UART Ports

UART Clock Rate

f

SCLK

16

1EDBO–()

UART_Divisor×

--------------------------------------------------------------------- -

=

Each UART port’s baud rate, serial data format, error code generation and
status, and interrupts are programmable:

• Supporting bit rates ranging from (f

/1,048,576) to (f

SCLK

SCLK

)

bits per second.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to generate
maskable interrupts to the processor.

The UART port’s clock rate is calculated as

Where the 16-bit UART divisor comes from the UARTx_DLH register (most
significant 8 bits) and UARTx_DLL register (least significant eight bits), and
the EDBO is a bit in the UARTx_GCTL register.

In conjunction with the general-purpose timer functions, autobaud detec­tion is supported.

The UARTs feature a pair of

UAx_RTS (request to send) and UAx_CTS (clear

to send) signals for hardware flow purposes. The transmitter hardware is
automatically prevented from sending further data when the UAx_CTS
input is deasserted. The receiver can automatically deassert its

UAx_RTS output when the enhanced receive FIFO exceeds a certain

high-water level. The capabilities of the UARTs are further extended with
support for the Infrared Data Association (IrDA®) Serial Infrared Physi­cal Layer Link Specification (SIR) protocol.

1-20 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

Controller Area Network (CAN) Interface

The ADSP-BF50x processors provide a CAN controller that is a commu­nication controller implementing the Controller Area Network (CAN)
V2.0B protocol. This protocol is an asynchronous communications proto­col used in both industrial and automotive control systems. CAN is well
suited for control applications due to its capability to communicate reli­ably over a network since the protocol incorporates CRC checking,
message error tracking, and fault node confinement.

The CAN controller is based on a 32-entry mailbox RAM and supports
both the standard and extended identifier (ID) message formats specified
in the CAN protocol specification, revision 2.0, part B.

Each mailbox consists of eight 16-bit data words. The data is divided into
fields, which includes a message identifier, a time stamp, a byte count, up
to 8 bytes of data, and several control bits. Each node monitors the mes­sages being passed on the network. If the identifier in the transmitted
message matches an identifier in one of its mailboxes, the module knows
that the message was meant for it, passes the data into its appropriate
mailbox, and signals the processor of message arrival with an interrupt.

The CAN controller can wake up the processor from sleep mode upon
generation of a wake-up event, such that the processor can be maintained
in a low-power mode during idle conditions. Additionally, a CAN
wake-up event can wake up the on-chip internal voltage regulator from
the powered-down hibernate state.

The electrical characteristics of each network connection are very strin­gent. Therefore, the CAN interface is typically divided into two parts: a
controller and a transceiver. This allows a single controller to support dif­ferent drivers and CAN networks. The ADSP-BF50x CAN module
represents the controller part of the interface. This module’s network I/O

ADSP-BF50x Blackfin Processor Hardware Reference 1-21

ACM Interface

is a single transmit output and a single receive input, which connect to a
line transceiver.

The CAN clock is derived from the processor system clock (SCLK)
through a programmable divider and therefore does not require an addi­tional crystal.

ACM Interface

The ADC control module (ACM) provides an interface that synchronizes
the controls between the processor and analog-to-digital converter (ADC)
modules like the internal ADC of the ADSP-BF506F. The analog-to-digi­tal conversions are initiated by the processor, based on external or internal
events.

The ACM allows for flexible scheduling of sampling instants and provides
precise sampling signals to the ADC. The ACM synchronizes the ADC
conversion process; generating the ADC controls, the ADC conversion
start signal, and other signals. The actual data acquisition from the ADC
is done by SPORT peripherals.

Internal ADC

The ADSP-BF506F processor includes an ADC. All internal ADC signals
are connected out to package pins to enable maximum flexibility in mixed
signal applications.

The internal ADC is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V power
supply and features throughput rates up to 2 MSPS. The device contains
two ADCs, each preceded by a 3-channel multiplexer, and a low noise,
wide bandwidth track-and-hold amplifier that can handle input frequen­cies in excess of 30 MHz.

1-22 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

Watchdog Timer

The processor includes a 32-bit timer that can be used to implement a
software watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through generation
of a hardware reset, nonmaskable interrupt (NMI), or general-purpose
interrupt, if the timer expires before being reset by software. The pro­grammer initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value. This protects
the system from remaining in an unknown state where software that
would normally reset the timer has stopped running due to an external
noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both
the CPU and the peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating a status bit
in the watchdog control register.

The timer is clocked by the system clock (SCLK), at a maximum frequency
of f

SCLK

.

Clock Signals

The processor can be clocked by an external crystal, a sine wave input, or a
buffered, shaped clock derived from an external clock oscillator.

This external clock connects to the processor’s CLKIN pin. The CLKIN input
cannot be halted, changed, or operated below the specified frequency dur­ing normal operation. This clock signal should be a TTL-compatible
signal.

The core clock (
the input clock (
capable of multiplying the

ADSP-BF50x Blackfin Processor Hardware Reference 1-23

CCLK) and system peripheral clock (SCLK) are derived from

CLKIN) signal. An on-chip Phase Locked Loop (PLL) is

CLKIN signal by a user-programmable (0.5× to

Dynamic Power Management

64×) multiplication factor (bounded by specified minimum and maxi­mum

VCO frequencies). The default multiplier is 6×, but it can be modified

by a software instruction sequence. On-the-fly frequency changes can be
made by simply writing to the PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK). The system
clock frequency is programmable by means of the SSEL[3:0] bits of the

PLL_DIV register.

Dynamic Power Management

The processor provides five operating modes, each with a different perfor­mance/power profile. In addition, dynamic power management provides
the control functions to dynamically alter the processor core supply volt­age, further reducing power dissipation. When configured for a 0 volt core
supply voltage, the processor enters the hibernate state. Control of clock­ing to each of the processor peripherals also reduces power consumption.
See Table 1-3 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed, providing
capability for maximum operational frequency. This is the power-up
default execution state in which maximum performance can be achieved.
The processor core and all enabled peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power Savings

In the active mode, the PLL is enabled but bypassed. Because the PLL is
bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run
at the input clock (CLKIN) frequency. DMA access is available to appro­priately configured L1 memories.

1-24 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

In the active mode, it is possible to disable the control input to the PLL by
setting the PLL_OFF bit in the PLL control register. This register can be
accessed with a user-callable routine in the on-chip ROM called
bfrom_SysControl(). If disabled, the PLL control input must be
re-enabled before transitioning to the full-on or sleep modes.

Table 1-3. Power Settings

Mode/State PLL PLL Bypassed Core Clock

(CCLK)

Full On Enabled No Enabled Enabled On

Active Enabled/Disabled Yes Enabled Enabled On

Sleep Enabled — Disabled Enabled On

Deep Sleep Disabled — Disabled Disabled On

Hibernate Disabled — Disabled Disabled Off

System Clock
(SCLK)

Core Power

For more information about PLL controls, see the “Dynamic Power Man-

agement” on page 8-1.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling the clock
to the processor core (CCLK). The PLL and system clock (SCLK), how­ever, continue to operate in this mode. Typically, an external event wakes
up the processor. When in the sleep mode, asserting a wakeup enabled in
the SIC_IWRx registers causes the processor to sense the value of the BYPASS
bit in the PLL control register (
sor transitions to the full on mode. If
transitions to the active mode.

PLL_CTL). If BYPASS is disabled, the proces-

BYPASS is enabled, the processor



ADSP-BF50x Blackfin Processor Hardware Reference 1-25

DMA accesses to L1 memory are not supported in sleep mode.

Dynamic Power Management

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

The deep sleep mode maximizes dynamic power savings by disabling the
clocks to the processor core (CCLK) and to all synchronous peripherals
(SCLK). Asynchronous peripherals may still be running but cannot access
internal resources or external memory. Deep sleep mode can be exited
only by a hardware reset event, by a wakeup event on a programmable flag
pin (including PH0, PF8, or PF9), or by a wakeup event on the programma­ble flag pin associated with the CAN_RX signal (PG1). A programmable flag
event causes the processor to transition to active mode, and execution
resumes at the program counter value at which the processor entered deep
sleep mode. Assertion of RESET while in deep sleep mode causes the pro­cessor to transition to the full on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling the volt­age and clocks to the processor core (CCLK) and to all of the peripherals
(SCLK). This setting sets the internal power supply voltage (V

DDINT

) to
0 V to provide the lowest static power dissipation. Any critical informa­tion stored internally (for example, memory contents, register contents,
and other information) must be written to a non-volatile storage device
prior to removing power if the processor state is to be preserved. Writing 0
to the HIBERNATEB bit causes EXT_WAKE to transition low, which can be
used to signal an external voltage regulator to shut down.

Since V

DDEXT

can still be supplied in this mode, all of the external pins
three-state, unless otherwise specified. This allows other devices that may
be connected to the processor to still have power applied without drawing
unwanted current.

The processor can be woken up by asserting the

RESET pin. All hibernate

wakeup events initiate the hardware reset sequence. Individual sources are

1-26 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

enabled by the
rence of a wakeup event.

As long as V
ing hibernation. All other internal registers and memories, however, lose
their content in the hibernate state.

VR_CTL register. The EXT_WAKE signal indicates the occur-

DDEXT

is applied, the VR_CTL register maintains its state dur-

Instruction Set Description

The Blackfin processor family assembly language instruction set employs
an algebraic syntax designed for ease of coding and readability. Refer to
the Blackfin Processor Programming Reference for detailed information. The
instructions have been specifically tuned to provide a flexible, densely
encoded instruction set that compiles to a very small final memory size.
The instruction set also provides fully featured multifunction instructions
that allow the programmer to use many of the processor core resources in
a single instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C
and C++ source code. In addition, the architecture supports both user
(algorithm/application code) and supervisor (O/S kernel, device drivers,
debuggers, ISRs) modes of operation, allowing multiple levels of access to
core resources.

The assembly language, which takes advantage of the processor’s unique
architecture, offers these advantages:

• Embedded 16/32-bit microcontroller features, such as arbitrary bit
and bit field manipulation, insertion, and extraction; integer opera­tions on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers

• Seamlessly integrated DSP/CPU features optimized for both 8-bit
and 16-bit operations

ADSP-BF50x Blackfin Processor Hardware Reference 1-27

Development Tools

• A multi-issue load/store modified Harvard architecture, which sup­ports two 16-bit MAC or four 8-bit ALU + two load/store + two
pointer updates per cycle

• All registers, I/O, and memory mapped into a unified 4G byte
memory space, providing a simplified programming model

Code density enhancements include intermixing of 16- and 32-bit
instructions with no mode switching or code segregation. Frequently used
instructions are encoded in 16 bits.

Development Tools

The processor is supported with a complete set of CROSSCORE® soft­ware and hardware development tools, including Analog Devices
emulators and the VisualDSP++ development environment. The same
emulator hardware that supports other Analog Devices products also fully
emulates the Blackfin processor family.

The VisualDSP++ project management environment lets programmers
develop and debug an application. This environment includes an
easy-to-use assembler that is based on an algebraic syntax, an archiver
(librarian/library builder), a linker, a loader, a cycle-accurate instruc­tion-level simulator, a C/C++ compiler, and a C/C++ runtime library that
includes DSP and mathematical functions. A key point for these tools is
C/C++ code efficiency. The compiler has been developed for efficient
translation of C/C++ code to Blackfin processor assembly. The Blackfin
processor has architectural features that improve the efficiency of com­piled C/C++ code.

1-28 ADSP-BF50x Blackfin Processor Hardware Reference

Introduction

Debugging both C/C++ and assembly programs with the VisualDSP++
debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and
object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ Integrated Development and Debugging Environment
(IDDE) lets programmers define and manage software development. Its
dialog boxes and property pages let programmers configure and manage all
development tools, including color syntax highlighting in the Visu­alDSP++ editor. These capabilities permit programmers to:

• Control how the development tools process inputs and generate
outputs

• Maintain a one-to-one correspondence with the tool’s com­mand-line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource
management tailored specifically to address the memory and timing con­straints of DSP programming. These capabilities enable engineers to
develop code more effectively, eliminating the need to start from the very
beginning, when developing new application code. The VDK features
include threads, critical and unscheduled regions, semaphores, events, and
device flags. The VDK also supports priority-based, pre-emptive,

ADSP-BF50x Blackfin Processor Hardware Reference 1-29

Development Tools

cooperative and time-sliced scheduling approaches. In addition, the VDK
was designed to be scalable. If the application does not use a specific fea­ture, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or
not. The VDK is integrated into the VisualDSP++ development environ­ment but can also be used with standard command-line tools. The VDK
development environment assists in managing system resources, automat­ing the generation of various VDK-based objects, and visualizing the
system state during application debug.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of
the processor to monitor and control the target board processor during
emulation. The emulator provides full speed emulation, allowing inspec­tion and modification of memory, registers, and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system loading or
timing.

In addition to the software and hardware development tools available
from Analog Devices, third parties provide a wide range of tools support­ing the Blackfin processor family. Hardware tools include the
ADSP-BF50x EZ-KIT Lite standalone evaluation/development cards.
Third party software tools include DSP libraries, real-time operating sys­tems, and block diagram design tools.

1-30 ADSP-BF50x Blackfin Processor Hardware Reference

2MEMORY

This chapter discusses memory population specific to the ADSP-BF50x
processors. Functional memory architecture is described in the Blackfin
Processor Programming Reference.

Memory Architecture

Figure 2-1 provides an overview of the ADSP-BF50x processor system

memory map. For a detailed discussion of how to use them, see the Black-
fin Processor Programming Reference.

Note the architecture does not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. The memory is
byte-addressable.

The upper portion of internal memory space is allocated to the core and
system MMRs. Accesses to this area are allowed only when the processor is
in supervisor or emulation mode (see the Operating Modes and States
chapter of the Blackfin Processor Programming Reference).

ADSP-BF50x Blackfin Processor Hardware Reference 2-1

L1 Instruction SRAM

INTERNAL

(CORE-ACCESSIBLE)

MEMORY MAP

EXTERNAL

(INTERFACE-ACCESSIBLE)

MEMORY MAP

0x0000 0000

0x2000 0000

0x2040 0000

0xEF00 0000

0xEF00 1000

0xFF80 0000

0xFF80 4000

0xFF80 8000

0xFFA0 0000

0xFFA0 4000

0xFFA0 8000

0xFFA1 4000

0xFFB0 0000

0xFFB0 1000

0xFFC0 0000

0xFFE0 0000

0xFFFF FFFF

SYNC FLASH (32M BITS) *

RESERVED

RESERVED

BOOT ROM (4K BYTES)

L1 DATA BANK A SRAM (16K BYTES)

RESERVED

L1 DATA BANK A SRAM/CACHE (16K BYTES)

RESERVED

L1 INSTRUCTION SRAM/CACHE (16K BYTES)

RESERVED

L1 INSTRUCTION BANK A SRAM (16K BYTES)

RESERVED

INTERNAL SCRATCHPAD RAM (4K BYTES)

RESERVED

SYSTEM MEMORY MAPPED REGISTERS

CORE MEMORY MAPPED REGISTERS

* AVAILABLE ON PARTS WITH SYNC FLASH (F)

Figure 2-1. ADSP-BF50x Memory Map

L1 Instruction SRAM

The processor core reads the instruction memory through the 64-bit wide
instruction fetch bus. All addresses from this bus are 64-bit aligned. Each
instruction fetch can return any combination of 16-, 32-, or 64-bit
instructions (for example, four 16-bit instructions, two 16-bit instructions
and one 32-bit instruction, or one 64-bit instruction).

2-2 ADSP-BF50x Blackfin Processor Hardware Reference

Memory

Table 2-1 lists the memory start locations of the L1 instruction memory

subbanks.

Table 2-1. L1 Instruction Memory Subbanks

Memory Subbank

0 0xFFA0 0000

1 0xFFA0 1000

2 0xFFA0 2000

3 0xFFA0 3000

4 0xFFA0 4000

5 0xFFA0 5000

6 0xFFA0 6000

7 0xFFA0 7000

Memory Start Location for
ADSP-BF50x Processors

L1 Data SRAM

Table 2-2 shows how the subbank organization is mapped into memory.

Table 2-2. L1 Data Memory SRAM Subbank Start Addresses

Memory Bank and Subbank ADSP-BF50x Processors

Data Bank A, Subbank 0 0xFF80 0000

Data Bank A, Subbank 1 0xFF80 1000

Data Bank A, Subbank 2 0xFF80 2000

Data Bank A, Subbank 3 0xFF80 3000

Data Bank A, Subbank 4 0xFF80 4000

Data Bank A, Subbank 5 0xFF80 5000

Data Bank A, Subbank 6 0xFF80 6000

Data Bank A, Subbank 7 0xFF80 7000

ADSP-BF50x Blackfin Processor Hardware Reference 2-3

L1 Data Cache

L1 Data Cache

When data cache is enabled (controlled by bits DMC[1:0] in the

DMEM_CONTROL register), 16K byte of data bank A can be set to serve as

cache.

Boot ROM

There are 4K bytes of memory space occupied by the boot ROM, starting
from address 0xEF00 0000. This 16-bit boot ROM is not part of the L1
memory module. Read accesses take one SCLK cycle and no wait states are
required. The read-only memory can be read by the core as well as by
DMA. It can be cached and protected by CPLD blocks like external mem­ory. The boot ROM not only contains boot-strap loader code, it also
provides some subfunctions that are user-callable at runtime. For more
information, see “System Reset and Booting” in Chapter 24, System Reset

and Booting.

External Memory

External memory (shown in Figure 2-1) is accessed via the EBIU memory
port. This 16-bit interface provides a glue-less connection to the internal
flash memory (on ADSP-BF504F and ADSP-BF506F devices) and boot
ROM. Internal flash memory ships from the factory in an erased state
except for block 0 of the parameter bank.



2-4 ADSP-BF50x Blackfin Processor Hardware Reference

Block 0 of the flash memory parameter bank ships from the factory
in an unknown state. An erase operation should be performed prior
to programming this block.

Processor-Specific MMRs

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

000000000 0000000

00 0 100000000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000

Reset = 0x0000 1001

ENDCPLB (Data Cacheability
Protection Lookaside Buffer
Enable)

0 - CPLBs disabled. Minimal
address checking only
1 - CPLBs enabled

DMC (L1 Data Memory
Configure)

DCBS (L1 Data Cache Bank Select)

Valid only when DMC = 1. Determines whether
Address bit A[14] or A[23] is used to select the L1
data cache bank.
0 - Address bit 14 is used to select Bank A
for cache access. If bit 14 of address is 1,
select L1 Data Memory Data Bank A; if bit 14
of address is 0, no bank selected.
1 - Address bit 23 is used to select Bank A for
cache access. If bit 23 of address is 1, select
L1 Data Memory Data Bank A; if bit 23 of
address is 0, no bank selected.

0xFFE0 0004

For ADSP-BF50x:
0 - Data Bank A is SRAM,
also invalidates all
cache lines if previously
configured as cache
1 - Data Bank A is lower
16K byte SRAM, upper
16K byte cache

Data Memory Control Register (DMEM_CONTROL)

The complete set of memory-related MMRs is described in the Blackfin
Processor Programming Reference. Several MMRs have bit definitions spe-

cific to the processors described in this manual. These registers are
described in the following sections.

DMEM_CONTROL Register

The data memory control register (DMEM_CONTROL), shown in Figure 2-2,
contains control bits for the L1 data memory.

Memory

Figure 2-2. L1 Data Memory Control Register

Note that both DAG 0 and 1 use Port-A for non-cacheable fetches.



ADSP-BF50x Blackfin Processor Hardware Reference 2-5

Processor-Specific MMRs

X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

XXXXXXX XXXXXXXX

Data Test Command Register (DTEST_COMMAND)

00 - Access subbank 0
01 - Access subbank 1
10 - Access subbank 2
11 - Access subbank 3

Subbank Access[1:0]
(SRAM ADDR[13:12])

Reset = Undefined

Read/Write Access

Access Way/Instruction
Address Bit 11

0 - Access Way0/Instruction bit 11 = 0
1 - Access Way1/Instruction bit 11 = 1

Data/Instruction Access

0 - Access Data
1 - Access Instruction

0 - Read access
1 - Write access

Array Access

0 - Access tag array
1 - Access data array

Double Word Index[1:0]

Selects one of four 64-bit
double words in a 256-bit line

Set Index[5:0]

Selects one of 64 sets

Data Cache Select/
Address Bit 14

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XXXXXXXXX XXXXXXX

0xFFE0 0300

0 - Reserved when bit 24=0
1 - Select Data Cache Bank when bit 24=1

DTEST_COMMAND Register

When the data test command register (DTEST_COMMAND) is written to, the
L1 cache data or tag arrays are accessed, and the data is transferred
through the data test data registers (DTEST DATA[1:0]). This register is
shown in Figure 2-3.

Figure 2-3. Data Test Command Register

The data/instruction access bit allows direct access via the DTEST_COMMAND
MMR to L1 instruction SRAM.

Note that

ITEST_COMMAND must be used to access to L1 Instruction SRAM

from 0xFA00 4000 to 0xFFA0 7FFF.

2-6 ADSP-BF50x Blackfin Processor Hardware Reference

3 CHIP BUS HIERARCHY

This chapter discusses on-chip buses, how data moves through the system,
and other factors that determine the system organization. Following an
overview and a list of key features is a block diagram of the chip bus hier­archy and a description of its operation. The chapter concludes with
details about the system interconnects and associated system buses.

This chapter provides

• “Chip Bus Hierarchy Overview”

• “Interface Overview” on page 3-2

Chip Bus Hierarchy Overview

ADSP-BF50x Blackfin processors feature a powerful chip bus hierarchy on
which all data movement between the processor core, internal memory,
external memory, and its rich set of peripherals occurs. The chip bus hier­archy includes the controllers for system interrupts, test/emulation, and
clock and power management. Synchronous clock domain conversion is
provided to support clock domain transactions between the core and the
system.

ADSP-BF50x Blackfin Processor Hardware Reference 3-1

Interface Overview

The processor system includes:

• The peripheral set including GP timers and counters, ACM, TWI,
RSI, UARTs, SPORTs, SPIs, PPI, watchdog timer, and PWM
units. The ADSP-BF506F processor peripherals include an ADC
and a flash memory, and the ADSP-BF504F processor peripherals
include a flash memory (but does not include an ADC).

• The External Bus Interface Unit (EBIU)

• The Direct Memory Access (DMA) controller

• The interfaces between these, the system, and the optional external
(off-chip) resources

The following sections describe the on-chip interfaces between the system
and the peripherals via the:

• Peripheral Access Bus (PAB)

• DMA Access Bus (DAB)

• DMA Core Bus (DCB)

• DMA External Bus (DEB)

Interface Overview

Figure 3-1 shows the core processor and system boundaries as well as the

interfaces between them.

Internal Clocks

The core processor clock (CCLK) rate is highly programmable with respect
to

CLKIN. The CCLK rate is divided down from the Phase Locked Loop

(PLL) output rate. This divider ratio is set using the
PLL divide register.

3-2 ADSP-BF50x Blackfin Processor Hardware Reference

CSEL parameter of the