Page 1
a
PRELIMINARY TECHNICAL DATA
MultiPort Internet
Gateway Processor
Preliminary Technical Data
PERFORMANCE FEATURES
Complete Single Device Multi-Port Internet Gateway
Processor (No External Memory Required)
Implements Sixteen Modem Channels or Forty Voice
Channels in One Package
Each DSP Can Implement two V.34/V.90 Data/Fax
Modem Channels (includes Datapump and
Controller)
Low Power Version: 640 MIPS Sustained Performance,
12.5 ns Instruction Time @ 1.9 Volts nominal
(internal)
Open Architecture Extensible to Voice-over-Network
(VoN) and Other Applications
Low Power Dissipation, 25 mW (typical) per Channel
Powerdown Mode Featuring Low CMOS Standby Power
Dissipation
ADSP-21mod980N
INTEGRATION FEATURES
ADSP-2100 Family Code-Compatible, with Instruction
Set Extensions
16 Mbits of On-Chip SRAM, Configured as 9 Mbits of
Program Memory and 7 Mbits of Data Memory
Dual-Purpose Program Memory, for Both Instruction
and Data Storage
ⴛ
352-Ball PBGA with a 35mm
SYSTEM CONFIGURATION FEATURES
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode-Selectable)
Programmable Multichannel Serial Port Supports 24/32
Channels
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate Reset Pins for Each Internal Processor
35mm footprint
Host IDMA
SPORT0
SPORT1
CONTROL
REV. PrB 6/2001
21mod980N
2188N
DSP 1
Figure 1. MOD980N MultiPort Internet Gateway Processor Block Diagram
2188N
DSP 2
2188N
DSP 3
2188N
DSP 4
2188N
DSP 5
2188N
DSP 6
2188N
DSP 7
2188N
DSP 8
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703 ©Analog Devices,Inc., 2001
Page 2
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
GENERAL DESCRIPTION
The ADSP-21mod980N is a multi-port Internet gateway
processor optimized for implementation of a complete
V.34/V.90 digital modem. All datapump and controller
functions can be implemented on a single device, offering
the lowest power consumption and highest possible modem
port density.
The ADSP-21mod980N combines the ADSP-2100 Family
base architecture (three computational units, data address
generators, and a program sequencer) with two serial ports,
a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and
on-chip program and data memory.
The ADSP-21mod980N integrates 16 Mbits of on-chip
memory, configured as 384 Kwords (24-bit) of program
RAM, and 448 Kwords (16-bit) of data RAM. Power-down
circuitry is also provided to reduce the average and standby
power consumption of equipment which in turn reduces
equipment cooling requirements. The ADSP-21mod980N
is available in a 35 mm x 35 mm, 352-lead PBGA package.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-21mod980N operates with a 12.5 ns instruction
cycle time. Every instruction can execute in a single processor cycle.
The ADSP-21mod980N’s flexible architecture and comprehensive instruction set allow the processor to perform
multiple operations in parallel. In one processor cycle, the
ADSP-21mod980N can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal
DMA port
• Receive and/or transmit data through the byte DMA
port
• Decrement timer
For current information contact Analog Devices at (800) ANALOGD
MODEM SOFTWARE
The following software is available as object code from
Analog Devices Inc.
• ADSP-21mod Family Dynamic Internet Voice
• ADSP-21mod980-210N Multiport Internet Gateway
A complete system implementation requires the
ADSP-21mod980N device plus modem or voice software.
The modem software executes general modem control,
command sets, error correction, and data compression,
data modulations (for example, V.34 and V.90), and host
interface functions.The host interface allows system access
to modem statistics, such as call progress, connect speed,
retrain count, symbol rate, and other modulation
parameters.
The modem datapump and controller software reside in
on-chip SRAM and do not require additional memory. You
can configure the ADSP-21mod980N dynamically by
downloading software from the host through the 16-bit
IDMA interface. This SRAM-based architecture provides a
software upgrade path to other applications, such as
voice-over-IP, and to future standards.
DEVELOPMENT SYSTEM
Analog Devices' wide range of software and hardware development tools supports the ADSP-218x N Series. The DSP
tools include an integrated development environment
(IDE), an evaluation kit, and a serial port emulator.
VisualDSP® is an integrated development environment,
allowing for fast and easy development, debug and deployment. The VisualDSP project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library
builder); a linker; a loader; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library
that includes DSP and mathematical functions.
Debugging both C and assembly programs with the VisualDSP debugger, programmers can:
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Fill and dump memor y
• Source level debugging
TM
Access
Processor Modem Solution.
(DIVA) Voice Over Network Solution.
2 6/2001 REV. PrB
Page 3
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
The VisualDSP IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the
ADSP-218x development tools, including the syntax highlighting in the VisualDSP editor. This capability controls
how the development tools process inputs and generate
outputs.
The ADSP-218x EZ-ICE ® Emulator provides an easier
and more cost-effective method for engineers to develop
and optimize DSP systems, shortening product development cycles for faster time-to-market. The
ADSP-21mod980N integrates on-chip emulation support
with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer
mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. The ADSP-21mod980N
device need not be removed from the target system when
using the EZ-ICE, nor are any adapters needed. Due to the
small footprint of the EZ-ICE connector, emulation can be
supported in final board designs.The EZ-ICE performs a
full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and
altered
• PC upload and download functions
• Instruction-level emulation of program booting and
execution
• Complete assembly and disassembly of instructions
• C source-level debugging
ADSP-21mod980N
ADDITIONAL INFORMATION
This data sheet provides a general overview of
ADSP-21mod980N functionality. For specific information
about the modem processors, refer to the ADSP-2188N
data sheet. For additional information on the architecture
and instruction set of the modem processors, refer to the
ADSP-2100 Family User’s Manual (3rd edition). For more
information about the development tools, refer to the
ADSP-2100 Family Development Tools Data Sheet.
3REV. PrB 6/2001
Page 4
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
ARCHITECTURE OVERVIEW
Figure 2 on page 4 is a functional block diagram of the
ADSP-21mod980N. It contains eight independent digital
signal processors.
DATA<23:8>, A<0>
CLKIN
IAD<15:0>, IDMA CNT L
PF<0:2>/MODE A:C
SPORT0A
SPORT1
EMULATOR
17
20
3
2188N
DSP 1 DSP 2 DSP 3 DSP 4
4
4
8
SIGNALS ROUTED TO EACH RESPECTIVE DIE
BR <8:1>
BG <8:1>
RESET <8:1>
CLKOUT <8:1>
EE <8:1>
IS <8:1>
TFS0 <8:1>
DT1 <8:1>
INTERRUPTS < 8:1>
SUBTOTAL = 177 S IGNAL BAL LS
GND
VDDINT
VDDEXT
2188N
8
8
8
8
8
8
8
8
32
109
44
22
2188N2188N
2188N
DSP 5
IDMA CNTL = IAL, IRD, IW R, IACK
INTERRUPT S = IRQ E (PF4), IRQL0(P F5), IRQ L1 (PF 6), IRQ 2(PF 7)
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK
SPORT0A, SPORT 0B
SPORT1 = RFS1, TFS1, DR1, SCKL1
NOTE:
1. PWD AND PF3/MODE D ARE TIED HIGH
2188N
DSP 6
ELOUT, ERESET
= RFS0, DR0, DT0, SCKL0
2188N
DSP 7
2188N
DSP 8
IAD <15:0>,
IDMA CNT L
4
SPORT0B
20
SUBTOTAL = 175 P OW ER BA LLS
TOTAL = 352 BALLS
Figure 2. ADSP-21mod980N Functional Block Diagram
Every modem processor has:
• A DSP core
• 256K bytes of RAM
• Two s er i a l p o r ts
• An IDMA host.
The signals of each modem processor are accessed through
accessed through a single external pin. Other signals remain
separate and they are accessed through separate external
pins for each processor.
The arrangement of the eight modem processors in the
ADSP-21mod980N makes one basic configuration possible: a slave configuration. In this configuration, the data
pins of all eight processors connect to a single bus structure.
the external pins of the ADSP-21mod980N. Some signals
are bussed with the signals of the other processors and are
4 6/2001 REV. PrB
Page 5
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
All eight modem processors have identical functions and
have equal status. Each of the modem processors is connected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in “Memory
Architecture” on page 10). The slave mode is considered to
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTS
The ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem processor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User’s Manual. Each
SPORT:
• is bidirectional and has a separate, double-buffered
transmit and receive section.
• can use an external serial clock or generate its own
serial clock internally.
• has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.
• supports serial data word lengths from 3 to 16 bits and
provides optional A-law and µ-law companding according to CCITT recommendation G.711.
• receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An interrupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
ADSP-21mod980N
PIN DESCRIPTIONS
The ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are configured during RESET
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page 6 lists the pin names and their functions. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
only, while ser i a l por t p i ns are software
5REV. PrB 6/2001
Page 6
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
Table 1. Common Mode Pins
Pin Name(s) # of Pins Input/Output Function
For current information contact Analog Devices at (800) ANALOGD
RESET 8 I Processor Reset Input
BR
BG
IRQ2
/ 8 I Edge- or Level-Sensitive Interrupt Request
8 I Bus Request Input
8 O Bus Grant Output
PF7 8 I/O Programmable I/O Pin
IRQL1
/ 8 I Level-Sensitive Interrupt Requests
PF6 8 I/O Programmable I/O Pin
/ 8 I Level-Sensitive Interrupt Requests
IRQL0
PF5 8 I/O Programmable I/O Pin
/ 8 I Edge-Sensitive Interrupt Requests
IRQE
1
1
1
1
PF4 8 I/O Programmable I/O Pin
Mode C / 1 I Mode Select Input - Checked Only During RESET
PF2 1 I/O Programmable I/O Pin During Normal Operation
Mode B / 1 I Mode Select Input - Checked Only During RESET
PF1 1 I/O Programmable I/O Pin During Normal Operation
Mode A / 1 I Mode Select Input - Checked Only During RESET
PF0 1 I/O Programmable I/O Pin During Normal Operation
CLKIN 1 I Clock Input
CLKOUT 8 O Processor Clock Output
SPORT 28 I/O Serial Port I/O Pins
2
VDD and GND 175 I Power and Ground
EZ-Port 16 I/O For Emulation Use
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21mod980N will vector
to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the ADSP-21mod980N System Control Register. Software configurable.
MEMORY INTERFACE PINS
The ADSP-21mod980N modem pool is used in Slave
Mode. In Slave Mode, the Modem Processors operate in
host configuration. The operating mode is determined by
the state of the Mode C pin during RESET
and cannot be
changed while the modem pool is running. See the “Mem-
ory Architecture” section for more information.
6 6/2001 REV. PrB
Page 7
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
Table 2. Host Pins (Mode C = 1) Modem Processors 1-8
Pin Name
# of
Pins
IAD[15:0] 32
Input/
Output
1
I/O IDMA Port
Function
Address/Data Bus
A0 1 O Address Pin for Exter-
nal I/O, Program,
Data, or Byte access
D[23:8] 16 I/O Data I/O Pins for Pro-
gram, Data Byte and
I/O spaces
IWR
IRD
IAL 2
1
2
2
I IDMA Write Enable
1
I IDMA Read Enable
1
I IDMA Address Latch
Pin
IS
IACK
8 I IDMA Selects
1
2
O IDMA Port Acknowl-
edge Configurable in
Mode D; Open Drain
1
There are two distinct IAD buses. One addresses DSPs 1-4 and the other
communicates with DSPs 5-8. See Figure 2 for details.
INTERRUPTS
The interrupt controller allows each modem processor in
the modem pool to respond individually to eleven possible
interrupts and RESET
with minimum overhead. The
ADSP-21mod980N provides four dedicated external interrupt input pins, IRQ2
, IRQL1, IRQL0, and IRQE (shared
with the PF[7:4] pins) for each modem processor. The
ADSP-21mod980N also supports internal interrupts from
the timer, the byte DMA port, the serial port, software, and
the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except
power down and RESET
). The IRQ2, IRQ1, and IRQ0
input pins can be programmed to be either level- or
edge-sensitive. IRQL0
and IRQL1 are level-sensitive and
ADSP-21mod980N
IRQE
is edge sensitive. The priorities and vector addresses
of all interrupts are shown in Table on page 7. When the
modem pool is reset, interrupt servicing is disabled.
Table 3. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
RESET (or Power-Up
with PUCR = 1)
Power Down
(Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit 0x0010
SPORT0 Receive 0x0014
IRQE
BDMA Interrupt 0x001C
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer 0x0028 (Lowest Priority)
LOW POWER OPERATION
The ADSP-21mod980N has three low power modes that
significantly reduce the power dissipation when the device
operates under standby conditions. These modes are:
• Power Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
POWER D OW N
The ADSP-21mod980N modem pool has a low power feature that lets the modem pool enter a very low power
dormant state through software control. Here is a brief list
Interrupt Vector Address
(Hex)
0x0000 (Highest Priority)
0x002C
0x0004
0x0008
0x000C
0x0018
0x0020
0x0024
7REV. PrB 6/2001
Page 8
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
of power-down features. Refer to the ADSP-2100 Family
User’s Manual, “System Interface” chapter, for detailed
information about the power-down feature.
• Quick recovery from power down. The modem pool
begins executing instructions in as few as 200 CLKIN
cycles.
• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running during power down without affecting the lowest
power rating and 200 CLKIN cycle recovery.
• Power down is initiated by the software power-down
force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally
powering down.
• Context clear/save control allows the modem pool to
continue where it left off or start with a clean context
when leaving the power down state.
• The RESET
down.
IDLE
When the ADSP-21mod980N is in the Idle Mode, the
modem pool waits indefinitely in a low power state until an
interrupt occurs. When an unmasked interrupt occurs, it is
serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA
and autobuffer cycle steals still occur.
pin also can be used to terminate power
For current information contact Analog Devices at (800) ANALOGD
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the modem pool’s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the modem pool takes to come out of the
idle state (a maximum of n cycles).
SYSTEM CONFIGURATION
Figure on page 9 shows the hardware interfaces for a typi-
cal multichannel modem configuration with the
ADSP-21mod980N. Other system design considerations
such as host processing requirements, electrical loading,
and overall bus timing must all be met. A line interface can
be used to connect the multichannel subscriber or client
data stream to the multichannel serial port of the
ADSP-21mod980N. The IDMA port of the
ADSP-21mod980N is used to give a host processor full
access to the internal memory of the ADSP-21mod980N.
This lets the host dynamically configure the
ADSP-21mod980N by loading code and data into its internal memory. This configuration also lets the host access
server data directly from the ADSP-21mod980N’s internal
memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.
SLOW IDLE
The IDLE instruction is enhanced on the
ADSP-21mod980N to let the modem pool’s internal clock
signal be slowed, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the
normal clock rate, is specified by a selectable divisor given
in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the
modem pool fully functional, but operating at the slower
clock rate. While it is in this state, the modem pool’s other
internal clock signals, such as SCLK, CLKOUT, and timer
clock, are reduced by the same ratio. The default form of
the instruction, when no clock divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the modem pool’s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, the
ADSP-21mod980N will remain in the idle state for up to a
maximum of n modem pool cycles (n = 16, 32, 64, or 128)
before resuming normal operation.
8 6/2001 REV. PrB
Page 9
PRELIMINARY TECHNICA L DATA
For current information contact Analog Devices at (800) ANALOGD
T1/E1
LINE
INTERFACE
SPORT
21mod980N
ST/CNTL IDMA
T1/E1
LINE
INTERFACE
SPORT
21mod980N
ST/CNTL IDMA
ADSP-21mod980N
T1/E1
LINE
INTERFACE
SPORT
21mod980N
ST/CNTL IDMA
Figure 3. Multichannel Modem Configuration
CLOCK SIGNALS
The ADSP-21mod980N is clocked by a TTL-compatible
clock signal that runs at half the instruction rate; a 40 MHz
input clock yields a 12.5 ns processor cycle, which is equivalent to 80 MHz. Normally, instructions are executed in a
single processor cycle. All device timing is relative to the
internal instruction clock rate, which is indicated by the
CLKOUT signal when enabled. The clock input signal is
connected to the processor’s CLKIN input.
The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power down state. For additional information, refer
to Chapter 9, ADSP-2100 Family User’s Manual for a
detailed explanation of this power down feature.
9REV. PrB 6/2001
Page 10
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
For current information contact Analog Devices at (800) ANALOGD
• Figure on page 11 shows Data Memory
• Table on page 11 shows the generation of address bits
based on the DMOVLAY values. Access to external
memory is not available
RESET
The RESET signals initiate a reset of each modem processor in the ADSP-21mod980N. The RESET signals must be
asserted during the power-up sequence to assure proper initialization. RESET
during initial power-up must be held
long enough to let the internal clocks stabilize. If RESETs
PM M OD E B = 0
ALW AYS
ACCESSIBLE
AT ADDRESS
0x0000 - 0x1FFF
are activated any time after power up, the clocks continue to
run and do not require stabilization time.
The power-up sequence is defined as the total time required
for the oscillator circuits to stabilize after a valid V
DD
is
ACCE SSIBL E W HEN
PM OVLAY = 0
applied to the processors, and for the internal phase-locked
loops (PLL) to lock onto the specific frequency. A minimum of 2000 CLKIN cycles ensures that the PLLs have
locked, but this does not include the oscillators’ start-up
time. During this power-up sequence, the RESET
signals
should be held low. On any subsequent resets, the RESET
signals must meet the minimum pulse width specification,
t
.
RSP
The RESET
use an RC circuit to generate your RESET
input contains some hysteresis; however, if you
signals, the use
of an external Schmidt triggers are recommended.
The RESET
for each individual modem processor sets the
ACCE SSIBL E W HEN
PM OVLAY = 4
ACCE SSIBL E W HEN
PM OVLAY = 5
ACCESSIBLE
WHEN
PM OVLAY = 6
INTERNAL
MEMORY
internal stack pointers to the empty stack condition, masks
all interrupts and clears the MSTAT register. When a
RESET
is released, if there is no pending bus request and
PROGRAM MEMORY
MODE B=0
the modem processor is configured for booting, the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000
once boot loading completes.
MEMORY ARCHITECTURE
The ADSP-21mod980N provides a variety of memory and
8K INTERNAL
PMOVLAY =
0, 4, 5, 6, 7
8K
INTERNAL
peripheral interface options for Modem Processor 1. The
key functional groups are Program Memory, Data Memory,
Byte Memory, and I/O. Refer to the following figures and
tables for PM and DM memory allocations in the
ADSP-21mod980N.
The ADSP-21mod980N modem pool operates in one
memory mode: Slave Mode. The following figures and
tables describe the memory of the ADSP-21mod980N:
• Figure on page 10 shows Program Memory
Table 4. PMOVLAY bits
PMOVLAY Memory A13 A[12:0]
0, 4, 5, 6, 7 Internal Not
Figure 4. Program Memory Map
• Table on page 10 shows the generation of address bits
based on the PMOVLAY values
0x2000 0x3FFF
0x2000 0x3FFF
0x2000 0x3FFF
0x2000 0x3FFF
0x2000 0x3FFF
ACCE SSIBLE
WHEN
PM OVLAY = 7
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
Not Applicable
Applicable
10 6/2001 REV. PrB
Page 11
PRELIMINARY TECHNICAL DATA
DATA MEM O RY
ALWA YS
ACCESS IBLE
AT ADDRE SS
0x2000 - 0x3FFF
ACCE SSIBL E W HEN
DM O VLAY = 0
ACCE SSIBL E W H EN
DM O VL AY = 4
ACCE SSIBL E W HEN
DM O VL AY = 5
INTERNAL
MEMORY
0x0000 - 0x1FFF
0x0000 - 0x1FFF
ACCE SSIBL E W HEN
DM O VL AY = 6
ACCE SSIBL E W HEN
DM O VL AY = 7
ACCE SSIBL E W H EN
DM O VL AY = 8
For current information contact Analog Devices at (800) ANALOGD
Table 5. DMOVLAY bits
DMOVLAY Memory A13 A[12:0]
0, 4, 5, 6, 7, 8 Internal Not
MEMORY MAPPED REGISTERS (NEW TO THE
0x0000 - 0x1FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
ADSP-21MOD980N)
The ADSP-21mod980N has three memory mapped registers that differ from other ADSP-21xx Family DSPs. See
“Waitstate Control Register” on page 11. See
“Programmable Flag & Composite Select Control Regis-
0x0000 - 0x1FFF
ter” on page 12. See “System Control Register” on
page 12. The slight modifications to these registers provide
the ADSP-21mod980N’s waitstate and BMS
features.
ADSP-21mod980N
Not
Applicable
Applicable
control
DATA ME M ORY
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160 WORDS
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7, 8
ADDR
0x3FFF
0x3FE0
0x3FDF
0x2000
0x1FFF
Figure 5. Data Memory Map
1514131211109876543210
11111111 1111
Wait State M od e Select
0 = Normal mo de (P WA IT, DW AIT , IO W AIT 0-3 = N wait states, rang ing fro m 0 to 7)
1 = 2N+ 1 m ode (PW AIT , D WA IT, IOWA IT0 -3 = 2N +1 wait state s, rang ing from 0 to 15)
11 1 1
IOW AIT 1IOW AIT 2IOW AIT 3DWAIT
Figure 6. Waitstate Control Register
.
DM(0x3FFE)
IOW AIT 0
11REV. PrB 6/2001
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PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
1514131211109876543210
11111011 000000 0 0
BMWAIT
CMSSEL
0 = Disable CMS
1 = Enabl e CMS
(where bit: 11-IOM, 10-BM, 9-DM, 8-PM)
PFTYPE
0 = Input
1 = Output
DM(0x3FE6)
Figure 7. Programmable Flag1 & Composite Select Control Register
1
Since they are multiplexed within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [3] of DM
(0x3FE6) must also be 0 to ensure that PF[3] is never an output.
1514131211109876543210
00000100 0111
00 0 0
DM(0x3FFF)
Reserved Set
To 0
SPORT0 Enable
0 = Disa ble
1 = En able
SPORT1 Enable
0 = Disable
1 = Enable
SPORT1 Configure
0 = F I, FO , IR Q0, IRQ 1, S CL K
1= SPORT1
RESERVED
SET TO 0
PWAIT
Program Memory
Wait States
Disable BMS
0 = En able B MS
1 = Disable BM S, exc ept w hen
me mory strobes are three-stated
Figure 8. System Control Register
Table 6. ADSP-21mod980N Mode of Operation
MODE C MODE B MODE A Booting Method
101
1
Considered standard operating settings. These configurations simplify your design and improve memory management.
2
IDMA timing details and the correct usage of IACK are described in the
SLAVE MODE
This section describes the Slave Mode memory configuration of the Modem Processors.
IDMA feature is used to load internal memory as desired. Program execution is held off until internal
program memory location 0x0000 is written to. Chip is configured in Slave Mode.
external pulldown.
2
ADSP-2100 Family User’s Manual
.
INTERNAL MEMORY DMA PORT (IDMA PORT)
The IDMA Port provides an efficient way for a host system
and the ADSP-21mod980N to communicate. The port is
used to access the on-chip program memory and data memory of each modem processor with only one processor cycle
per word overhead. The IDMA port cannot be used, how-
1
IACK requires
12 6/2001 REV. PrB
Page 13
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ever, to write to the processor’s memory-mapped control
registers. A typical IDMA transfer process is described as
follows:
1. Host starts IDMA transfer
2. Host uses IS
and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the processor’s IDMA control
registers.
If IAD [15] = 1, the value of IAD [7:0] represents the
IDMA overlay: IAD[14:8] must be set to 0.
If IAD [15] = 0, the value of IAD [13:0] represents the
starting address of internal memory to be accessed and
IAD [14] reflects PM or DM for access.
1. Host uses IS
and IRD (or IWR) to read (or write) processor internal memory (PM or DM).
2. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written to, while the
ADSP-21mod980N is operating at full speed.
The processor memory address is latched and then automatically incremented after each IDMA transaction. An
external device can therefore access a block of sequentially
addressed memory by specifying only the starting address of
the block. This increases throughput as the address does
not have to be sent for each memory access.
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is
asserted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address
ADSP-21mod980N
specifies an on-chip memory location, the destination type
specifies whether it is a DM or PM access. The falling edge
of the address latch signal latches this value into the
IDMAA register.
Once the address is stored, data can then be either read
from, or written to, the ADSP-21mod980N’s on-chip
memory. Asserting the select line (IS
read or write line (IRD
and IWR respectively) signals the
ADSP-21mod980N that a particular transaction is
required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
Through the IDMAA register, the processor can also specify the starting address and data format for DMA operation.
Asserting the IDMA port select (IS
enable (IAL) directs the ADSP-21mod980N to write the
address onto the IAD [14:0] bus into the IDMA Control
Register. If IAD [15] is set to 0, IDMA latches the address.
If IAD [15] is set to 1, IDMA latches OVLAY memory. The
IDMAA register is memory mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) or overlay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address
DM(0x3FE7). See Figure on page 13 for more information on IDMA memory mapping. When bit 14 in 0x3FE7
is set to 1, then timing in Figure on page 35 applies for
short reads. When bit 14 in 0x3FE7 is set to zero short
reads use the timing shown in Figure on page 34.
) and the appropriate
) and address latch
IDM A O VER LAY
1514131211109876543210
0 0 0 0 0 0
RESERVED
RESERVED
ALWA YS SET
TO 0
RESERVED
ALWA YS SET
TO 0
Short Read Only
Enable
1 = Enable
0 = Disable
1514131211109876543210
U
0
SET TO 0
IDMA CONTRO L (U=UNDEFINED AT RESET)
UUUUUUUU UUUUUU
IDM AD
Destination memory type:
0=PM
1=DM
0
0
ID DM OVLAY
IDM AA
ADDRESS
00
0
0
0
ID PM O VLA Y
Figure 9. IDMA Control/OVLAY Registers
000
DM(0x3FE7)
DM(0x3FE0)
13REV. PrB 6/2001
Page 14
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 - 0x1FFF
ACCESSIBLE WHEN
PM OVLAY = 0
ACCESSIBLE WHEN
PM OVLAY = 4
ACCESSIBLE WHEN
PM OVLAY = 5
ACCESSIBLE WHE N
PM OVLAY = 6
ACCESSIBLE WHEN
PM OVLAY = 7
For current information contact Analog Devices at (800) ANALOGD
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 - 0x3FFF
0x2000 - 0x3FF F
0x2000 - 0x3FFF
0x2000 - 0x3FFF
0x2000 - 0x3FF F
0x2000 - 0x3FFF
ACCESSIBLE WHEN
DM OVLAY = 0
ACCESSIBLE WHEN
DM OVLAY = 4
ACCESSIBLE WHEN
DM OVLAY = 5
ACCESSIBLE WHEN
DM OVLAY = 6
ACCESSIBLE WHEN
DM OVLAY = 7
0x0000 - 0x1FFF
0x0000 - 0x1FF F
0x0000 - 0x1FFF
0x0000 - 0x1FF F
ACCESSIBLE WHE N
DM OVLAY = 8
0x0000 - 0x1FFF
0x0000 - 0x1FF F
Figure 10. Direct Memory Access - PM and DM Memory Maps
14 6/2001 REV. PrB
Page 15
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
IDMA PORT BOOTING
The ADSP-21mod980N boots programs through its Internal DMA port.When Mode C = 1, Mode B = 0, and Mode
A = 1, the ADSP-21mod980N boots from the IDMA port.
IDMA feature can load as much on-chip memory as
desired. Program execution is held off until on-chip program memory location 0 is written to.
FLAG I/O PINS
Each modem processor has eight general purpose programmable input/output flag pins. They are controlled by two
memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The
PFDATA register is used to read and write the values on the
pins. Data being read from a pin configured as an input is
synchronized to the ADSP-21mod980N’s clock. Bits that
are programmed as outputs will read the value being output. The PF pins default to input during RESET
Note: Pins PF0, PF1, and PF2 are also used for device configuration during RESET
within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time.
. Since they are multiplexed
.
ADSP-21mod980N
15REV. PrB 6/2001
Page 16
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21mod980N has on-chip emulation support
and an ICE-Port, a special set of pins that interface to the
EZ-ICE. These features allow in-circuit emulation without
replacing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target
systems must have a 14-pin connector to accept the
For current information contact Analog Devices at (800) ANALOGD
The EZ-ICE can emulate only one modem processor at a
time. You must include hardware to select which processor
in the ADSP-21mod980N you want to emulate. Figure on
page 16 is a functional representation of the modem proces-
sor selection hardware. You can use one ICE-Port
connector with two ADSP-21mod980N processors without
using additional buffers.
EZ-ICE’s in-circuit probe, a 14-pin plug.
ADSP-21MOD980N
ELOUT
EBR
EBG
EINT
ELIN
ECLK
EMS
ERESET
GND
EBG
EBR
KEY
ELOUT
RESET
EE
1 2
BG
BR
3 4
ENT
5 6
ELIN
7 8
ECLK
9 10
EMS
11 12
ERESET
13 14
BG0
BR0
RESET0
EE0
BG1
BR1
RESET1
EE1
BG2
BR2
RESET2
EE2
BG3
BR3
RESET3
EE3
BG4
BR4
RESET4
EE4
BG5
BR5
RESET5
EE5
BG6
BR6
RESET6
EE6
BG7
BR7
RESET7
EE7
Figure 11. Selecting a Modem Processor in the ADSP-21mod980N
Issuing the “chip reset” command during emulation causes
the modem processor to perform a full chip reset, including
a reset of its memory mode. Therefore, it is vital that the
mode pins are set correctly PRIOR to issuing a chip reset
command from the emulator user interface. As the mode
pins share functionality with PF[2:0] on the
16 6/2001 REV. PrB
Page 17
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N, it may be necessary to reset the target
hardware separately to insure the proper mode selection
state on emulator chip reset. See the ADSP-2100 Family
EZ-Tools data sheet for complete information on ICE
products.
The ICE-Port interface consists of the following
ADSP-21mod980N pins:
EBR
EINT
EE
EBG
ECLK
ERESET
ELIN
EMS
ELOUT
These ADSP-21mod980N pins must be connected only to
the EZ-ICE connector in the target system. These pins have
no function except during emulation, and do not require
pull-up or pull-down resistors. The traces for these signals
between the ADSP-21mod980N and the connector must
be kept as short as possible—no longer than 3 inches.
The following pins are also used by the EZ-ICE:
• BR
• BG
• RESET
• GND
The EZ-ICE uses the EE (emulator enable) signal to take
control of the ADSP-21mod980N in the target system.
This causes the processor to use its ERESET
EBG
pins instead of the RESET, BR, and BG pins. The BG
, EBR, and
output is three-stated. These signals do not need to be
jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon
cable and a 14-pin female plug. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target
board.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The EZ-ICE connector (a standard pin strip header) is
shown in Figure on page 17. You must add this connector
to your target board design if you intend to use the EZ-ICE.
Be sure to allow enough room in your system to fit the
EZ-ICE probe onto the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7
location—you must remove Pin 7 from the header. The pins
must be 0.025 inch square and at least 0.20 inch in length.
ADSP-21mod980N
Pin spacing should be 0.1 ⴛ 0.1 inches. The pin strip
header must have at least 0.15 inch clearance on all sides to
accept the EZ-ICE probe plug.
GND
EBG
EBR
KEY (NO PIN)
ELOUT
RESET
12
34
56
78
∞∞∞∞
910
11 12
EE
13 14
TOP VIEW
Figure 12. Target Board Connector for EZ-ICE
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
TA R GE T M EM O R Y I N T E RF A C E
For your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guidelines listed below.
TARGET SYSTEM INTERFACE SIGNALS
When the EZ-ICE board is installed, the performance on
some system signals change. Design your system to be compatible with the following system interface signal changes
introduced by the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation
delay between your target circuitry and the processor
on the RESET
signal.
• EZ-ICE emulation introduces an 8 ns propagation
delay between your target circuitry and the processor
on the BR
signal.
• EZ-ICE emulation ignores RESET
single-stepping.
• EZ-ICE emulation ignores RESET
Emulator Space (processor halted).
• EZ-ICE emulation ignores the state of target BR
tain modes. As a result, the target system may take
control of the processor’s external memory bus only if
bus grant (BG
) is asserted by the EZ-ICE board’s
processor.
BG
BR
EINT
ELIN
ECLK
EMS
ERESET
and BR when
and BR when in
in cer-
17REV. PrB 6/2001
Page 18
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Description Min Max Unit
V
DDEXT
V
DDINT
V
INPUT
T
AMB
External supply 2.98 3.63 V
Internal supply 1.81 2.0 V
Input Voltage VIL= –0.3 VIH= +3.6 V
Ambient temperature 0 +70 °C
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Typ Max Unit
VIH, Hi-Level Input Voltage
V
, Hi-Level CLKIN Voltage @ V
IH
, Lo-Level Input Voltage
V
IL
V
, Hi-Level Output Voltage
OH
V
, Lo-Level Output Voltage
OL
, Hi-Level Input Leakage Current
I
IH
I
, Lo-Level Input Leakage Current
IL
, Three-State Leakage Current
I
OZH
I
, Three-State Leakage Current
OZL
1, 2
1, 3
1, 4, 5
1, 4, 5
3
3
7
7
@ V
DDINT
DDINT
@ V
DDINT
@ V
DDEXT
I
= –0.5 mA
OH
@ V
DDEXT
= –100 µA
I
OH
@ V
DDEXT
I
= 2 mA
OL
@ V
DDINT
= 3.6V
V
IN
@ V
DDINT
= 0 V
V
IN
@ V
DDEXT
V
= 3.6V
IN
@ V
DDEXT
= 0 V
V
IN
= max 1.5 V
= max 2.0 V
= min 0.7 V
= min
= min
6
= min
= max
= max
= max
8
= max
8
2.4 V
V
DDEXT
-0.3
0.4 V
10 A
10 A
10 A
10 A
V
18 6/2001 REV. PrB
Page 19
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter Test Conditions Min Typ Max Unit
IDD, Supply Current (Idle) @ V
t
CK
, Supply Current (Dynamic) @ V
I
DD
I
, Supply Current (Powerdown)
DD
C
, Input Pin Capacitance
I
RESET, BR, IS, TFS0, PF[7:4]
, Input Pin Capacitance
C
I
IWR, IRD, IAL, DR0, RFS0, SCLK0, IAD [15:0]
C
, Input Pin Capacitance
I
TFS1, PF[2:0], CLKIN, DR1, RFS1, SCLK1
C
, Output Pin Capacitance
O
BG, CLKOUT, TFS0, PF[7:4], DT1
, Output Pin Capacitance
C
O
IAD [15:0], DT0, IACK, RFS0, SCLK0
C
, Output Pin Capacitance
O
SCLK1, TFS1, PF[2:0], DATA [23:8], A0, RFS1
1
Bidirectional pins: RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD [15:0], PF[2:0], PF[7:4].
2
Input only pins: RESET, BR, DR0, DR1, IS, IAL,IRD, IWR.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1.
4
Output pins: BG, A0, DT0, DT1, CLKOUT, IACK.
5
Although specified for TTL outputs, all ADSP-21mod980N outputs are CMOS-compatible and will drive to V
loads.
6
Guaranteed but not tested.
7
Three-statable pins: DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD[15:0].
8
0 Volts on BR.
9
Vin = 0V and 3V. For typical supply current figures refer to “Power Dissipation” section.
10
11
ADSP-2100 Family User’s Manual
See the
Output pin capacitance is the capacitive load for any three-stated output pin
10
1, 6, 7, 10, 11
1, 6, 7, 9, 10
1, 6, 7, 9, 10
for details.
t
CK
T
AMB
Lowest power mode 800 µA
@ VIN = 2.5 V, fIN = 1.0 MHz,
T
AMB
@ VIN = 2.5 V, fIN = 1.0 MHz,
T
AMB
@ VIN = 2.5 V, fIN = 1.0 MHz,
T
AMB
@ VIN = 2.5 V, fIN = 1.0 MHz,
T
@ VIN = 2.5 V, fIN = 1.0 MHz,
T
@ VIN = 2.5 V, fIN = 1.0 MHz,
T
= 1.9V
DDINT
= 12.5 ns
= 1.9V
DDINT
= 12.5 ns
= +25°C
= +25°C
= +25°C
= +25°C
= +25°C
AMB
= +25°C
AMB
= +25°C
AMB
9
50 mA
200 mA
8pF
32 pF
64 pF
8pF
32 pF
64 pF
and GND, assuming no DC
DDEXT
19REV. PrB 6/2001
Page 20
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
ABSOLUTE MAXIMUM RATINGS
Parameter Description Min. Max Unit
V
DDINT
V
DDEXT
1
Applies to bidirectional pins (D0:D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1:A13, PF0:PF7) and input only pins (CLKIN, RESET, BR,
DR0, DR1).
2
Applies to output pins (BG, PWDACK, A0, DT0, DT1, CLKOUT).
Internal Supply Voltage –0.3 +2.5 V
External Supply Voltage –0.3 +4.6 V
Input Voltage
Output Voltage Swing
Storage Temperature Range –65 °C +150 °C °C
1
2
–0.5 +4.6 V
–0.5 V
+ 0.5 V
DDEXT
ESD SENSITIVITY
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high
as 4000V readily accumulate on the human body and test equipment and can discharge
without detection. Although the device features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
20 6/2001 REV. PrB
Page 21
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
POWER DISSIPATION
Assumptions:
Assumptions:
• External data memory is accessed every fourth cycle
To determine total power dissipation in a specific application, the following equation should be applied for each
output:
2
DD
ⴛ f
C ⴛ V
• External data memory writes occur every fourth cycle
• Each address and data pin has a 64 pF total load at the
C = load capacitance
f = output switching frequency
Example:
In an application where an external host is accessing internal memory and no other outputs are active, power
dissipation is calculated as follows:
Table 7. Example Power Dissipation Calculation
Parameters # of Pins × C (pF) × V
• Application operates at V
Total Power Dissipation = P
P
INT
(C
example in Table 7.
Address 8 64 3.3
Data Output, WR
9643.3218.8 117.9
ADSP-21mod980N
with 50% of the address pins switching.
with 50% of the data pins switching.
pin.
= 3.3 V and tCK = 30 ns.
DDEXT
+ (C
INT
ⴛ
= internal power dissipation from Figure 15
2
ⴛ
V
2
ⴛ
DDEXT
DDEXT
f) is calculated for each output, as in the
2
(V) × f (MHz) PD (mW)
18.8 104.8
V
DDEXT
2
ⴛ f)
Total power dissipation for this example is:
PD = P
+ 222.7 mW
INT
222.7
21REV. PrB 6/2001
Page 22
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
ENVIRONMENTAL CONDITIONS
120
110
100
90
84mW
80
76mW
70
68mW
60
50
55 60 65 70 75 80 85
475
425
375
336mW
325
287mW
275
256mW
225
MOD980N Core POWER, IDLE
V
= 2.0v
DD
VDD = 1.9v
VDD = 1.8v
1/tCK - MHz
MOD980N Core POWER, DYNAMIC
VDD = 2.0V
= 1.9V
V
DD
VDD = 1.8V
108mW
96mW
84mW
440mW
375mW
336mW
Table 8. Thermal Resistance
Rating
Description
1
Thermal Resistance
Symbol PBGA
θ
CA
(Case-toAmbient)
Thermal Resistance
θ
JA
(Junction-toAmbient)
Thermal Resistance
θ
JC
(Junction-toCase)
1
Where the Ambient Temperature Rating (T
= T
T
AMB
T
CASE
PD = Power Dissipation in W
– (PD ×
CASE
= Case Temperature in °C
)
θ
CA
23ºC
/W
28.2ºC
/W
5.2ºC
/W
) is:
AMB
175
55 60 65 70 75 80 85
1/tCK - MHz
Figure 13. Power vs. Frequency
22 6/2001 REV. PrB
Page 23
PRELIMINARY TECHNICAL DATA
t
DIStMEASUREDtDECAY
–=
For current information contact Analog Devices at (800) ANALOGD
TEST CONDITIONS
INPU T
OUTPUT
Figure 14. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
I
OL
TO
OUTPUT
PIN
50pF
0.8V
1.5V
1.5V
2.0V
1.5V
ADSP-21mod980N
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t
, as shown in Figure 16. The time is the interval from
t
DECAY
when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage.
The decay time, t
C
, and the current load, iL, on the output pin. It can be
L
approximated by the following equation:
0.5V×
C
L
t
DECAY
-------------------------
=
i
L
from which
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
) is the difference of t
DIS
, is dependent on the capacitive load,
DECAY
MEASURED
and
IOH
Figure 15. Equivalent Loading for AC Measurements
(Including All Fixtures)
REFERENC E
SIGNAL
(ME A S U R E D )
OUTPUT
(ME A S U R E D )
t
MEASURED
t
V
DIS
OH
V
OL
OUTPUT STOPS
DRIV ING
t
ENA
V
OH
(ME A S U R E D ) - 0.5 V
V
OH
V
(MEA S U R E D ) + 0.5V
OL
t
DECAY
HIGH-IMPEDANCE S TATE . TEST CO ND ITIONS CAUS E
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
1.0V
OUTPUT STARTS
2.0V
DRIV ING
(ME A S U R E D )
V
OL
(ME A S U R E D )
Figure 16. Output Enable/Disable
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high-impedance state to when they
start driving. The output enable time (t
) is the interval
ENA
from when a reference signal reaches a high or low voltage
level to when the output has reached a specified high or low
trip point, as shown in Figure 16. If multiple pins (such as
the data bus) are enabled, the measurement value is that of
the first pin to start driving.
23REV. PrB 6/2001
Page 24
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s
external signals.
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful
results for an individual device, the values given in this data
For current information contact Analog Devices at (800) ANALOGD
30
25
- ns
)
V
20
2.4
V
4
15
(0.
IME
10
SE T
RI
5
ⴗⴗⴗⴗ
T = 85
C
= 0V TO 2.0V
V
DD
sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to
derive longer times.
Timing Notes
Switching characteristics specify how the processor changes
Figure 17. Typical Output Rise Time vs.Load Capacitance
0
50
(at Maximum Ambient Operating Temperature)
its signals. You have no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
tell you what the processor will do in a given circumstance.
You can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for
a read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
Frequency Dependency For Timing Specifications
tCK is defined as 0.5 t
. The ADSP-21mod980N uses an
CKI
input clock with a frequency equal to half the instruction
ns
D -
HOL
OR
LAY
DE
PUT
OUT
NOMINAL
LID
VA
18
16
14
12
10
8
6
4
2
-2
-4
-6
0
50 100 150 250200
rate. For example, a 40 MHz input clock (which is equivalent to 25 ns) yields a 12.5 ns processor cycle (equivalent to
80 MHz). t
values within the range of 0.5 t
CK
period
CKI
Figure 18. Typical Output Valid Delay or Hold vs.Load
Capacitance, CL (at Maximum Ambient Operating
should be substituted for all relevant timing parameters to
obtain the specification value.
Example: t
= 0.5 tCK – 2 ns = 0.5 (12.5 ns) – 2 ns = 4.25
CKH
ns
100 150 200 250
CL - pF
CL - pF
Temperature)
3000
Output Drive Currents
Figure 14 shows typical I-V characteristics for the output
drivers on the ADSP-21mod980N. The cur ves represent
the current drive capability of the output drivers as a function of output voltage
Capacitive Loading
Figure 16 and Figure 17 show the capacitive loading char-
acteristics of the ADSP-21mod980N.
24 6/2001 REV. PrB
Page 25
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Clock and Reset Signals
Table 9. Clock and Reset Signals
Parameter Description Min. Max Unit
Clock signals (Timing Requirements):
t
CKI
t
CKIL
t
CKIH
t
CKRISE
t
CKFALL
Clock signals (Switching Characteristics)
t
CKL
t
CKH
t
CKOH
CLKIN Period 25.0 40.0 ns
CLKIN Width Low 8 ns
CLKIN Width High 8 ns
CLKIN rise time
1
4ns
CLKIN fall time 4 ns
2
:
CLKOUT Width Low 0.5tCK - 3 ns
CLKOUT Width High 0.5tCK - 3 ns
CLKIN High to CLKOUT High 0 8 ns
Control Signals (Timing Requirements):
t
RSP
RESET Width Low 5t
CK
3
ns
t
MS
t
MH
1
t
CKRISE
2
If it is not needed by the application, CLKOUT should be disabled to reduce noise (DM(0x3FF3) bit 14).
3
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including
crystal oscillator start-up time).
Mode Setup Before RESET High 4 ns
Mode Hold After RESET High 5 ns
and t
are specified between the 10% and 90% points on the signal edge.
CKFALL
25REV. PrB 6/2001
Page 26
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
CLKIN
CLKOUT
PF(2:0 )*
RESE T
For current information contact Analog Devices at (800) ANALOGD
t
CKI
t
CKIH
t
CKIL
t
CKOH
t
CKH
t
CKL
t
t
MS
MH
*PF2 is Mode C, PF1 is M ode B, PF0 is Mode A
Figure 19. Clock and Reset Signals
26 6/2001 REV. PrB
Page 27
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Interr upts and Flags
Table 10. Interrupts and Flags
Parameter Description Min. Max Unit
Timing Requirements:
t
IFS
t
IFH
IRQx, FI, or PFx Setup before CLKOUT Low1,
IRQx, FI, or PFx Hold after CLKOUT High
2, 3, 4
1, 2, 3, 4
0.25tCK + 10 ns
0.25t
CK
Switching Characteristics:
t
FOH
t
FOD
1
If IRQx and FI inputs meet t
recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the
further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, Flag_out4.
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
and t
IFS
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be
IFH
5
5
0.5tCK - 5 ns
0.5tCK + 4 ns
ADSP-2100 Family User’s Manual
ns
for
CLKOUT
IRQ
PFx
t
IFH
x
FI
t
IFS
Figure 20. Interrupts and Flags
27REV. PrB 6/2001
Page 28
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
Serial Ports
Table 11. Serial Ports
Parameter Description Min. Max Unit
Timing Requirements:
t
t
t
t
SCK
SCS
SCH
SCP
SCLK Period 30 ns
DR/TFS/RFS Setup before SCLK Low 4 ns
DR/TFS/RFS Hold after SCLK Low 7 ns
SCLKIN Width 12 ns
Switching Characteristics:
t
CC
t
SCDE
t
SCDV
t
RH
t
RD
CLKOUT High to SCLKOUT 0.25t
CK
0.25tCK + 6 ns
SCLK High to DT Enable 0 ns
SCLK High to DT Valid 12 ns
TFS/RFSOUT Hold after SCLK High 0 ns
TFS/RFSOUT Delay from SCLK High 12 ns
t
SCDH
t
TDE
t
TDV
t
SCDD
t
RDV
DT Hold after SCLK High 0 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 12 ns
SCLK High to DT Disable 12 ns
RFS (Multichannel, Frame Delay Zero to DT Valid 12 ns
28 6/2001 REV. PrB
Page 29
PRELIMINARY TECHNICAL DATA
CLKOUT
SCLK
DR
TFS
RFS
RFS
OUT
TFS
OUT
DT
TFS
OUT
ALTERNATE
FRAME M O DE
RFS
MULTICHANNEL
MODE,
FRAME D E LAY 0
(MFD = 0)
TFSIN
ALTERNATE
FRAME M O DE
RFSIN
MULTICHA NNE L
MODE,
FRAME DELAY 0
(MFD = 0 )
For current information contact Analog Devices at (800) ANALOGD
IN
IN
OUT
t
CC
t
t
RH
t
SCDV
t
SCDE
t
TDE
t
TDE
t
CC
t
t
SCP
SCDD
t
SCStSCH
RD
t
SCDH
t
TDV
t
RDV
t
TDV
t
RDV
ADSP-21mod980N
t
SCK
t
SCP
Figure 21. Serial Ports
29REV. PrB 6/2001
Page 30
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
IDMA Address Latch
Table 12. IDMA Address Latch
Parameter Description Min. Max Unit
Timing Requirements:
t
IALP
t
IASU
t
IAH
t
IKA
t
IALS
t
IALD
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
For IDMA, please refer to the
4
Start of Write or Read = IS Low and IWR Low or IRD Low.
Duration of Address Latch
IAD[15:0] Address Setup before Address Latch End
IAD[15:0] Address Hold after Address Latch End
IACK Low before Start of Address Latch
Start of Write or Read after Address Latch End2,
Address Latch Start after Address Latch End1,
ADSP-2100 Family User’s Manual
1, 2, 3
10 ns
2, 3
2, 3
2, 3, 4
3, 4
2, 3
.
5ns
3ns
0ns
3ns
2ns
IACK
IAL
IAD 15-0
IRD
OR
IWR
t
IKA
t
IAL P
IS
t
IASU
t
IAL D
t
IAL P
t
t
IAH
IAS U
t
IAH
t
IAL S
Figure 22. IDMA Address Latch
30 6/2001 REV. PrB
Page 31
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Write, Short Write Cycle
Table 13. IDMA Write, Short Write Cycle
Parameter Description Min. Max Unit
Timing Requirements:
t
IKW
t
IWP
t
IDSU
t
IDH
IACK Low before Start of Write
Duration of Write
1, 2, 3
IAD[15:0] Data Setup before End of Write
IAD[15:0] Data Hold after End of Write
1, 2
2, 3, 4, 5
2, 3, 4, 5
0ns
10 ns
3ns
2ns
Switching Characteristics:
t
IKHW
1
Start of Write = IS Low and IWR Low.
2
For IDMA, please refer to the
3
End of Write = IS High or IWR High.
4
If Write Pulse ends before IACK Low, use specifications t
5
If Write Pulse ends after IACK Low, use specifications t
Start of Write to IACK High 10 ns
ADSP-2100 Family User’s Manual
IDSU
IKSU
.
, t
.
IDH
, t
.
IKH
IACK
IW R
IAD 15- 0
t
IKW
t
IKH W
IS
t
IW P
t
t
IDS U
IDH
DATA
Figure 23. IDMA Write, Short Write Cycle
31REV. PrB 6/2001
Page 32
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
IDMA Write, Long Write Cycle
Table 14. IDMA Write, Long Write Cycle
Parameter Description Min. Max Unit
Timing Requirements
t
IKW
t
IKSU
t
IKH
IACK Low before Start of Write
IAD[15:0] Data Setup before End of Write
IAD[15:0] Data Hold after End of Write
1
2, 3, 4
2, 3, 4
0ns
0.5tCK + 5 ns
0ns
Switching Characteristics:
t
IKLW
t
IKHW
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t
3
If Write Pulse ends after IACK Low, use specifications t
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the
Start of Write to IACK Low
Start of Write to IACK High 10 ns
4
IDSU
IKSU
1.5t
CK
, t
.
IDH
, t
.
IKH
ADSP-2100 Family User’s Manual
ns
.
IAC K
IW R
IAD 15-0
t
IKW
t
IKH W
t
IKLW
IS
t
IKSU
DATA
t
IKH
Figure 24. IDMA Write, Long Write Cycle
32 6/2001 REV. PrB
Page 33
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Read, Long Read Cycle
Table 15. IDMA Read, Long Read Cycle
Parameter Description Min. Max Unit
Timing Requirements:
t
IKR
t
IRK
IACK Low before Start of Read
End of Read after IACK Low2,
1, 2
3
0ns
2ns
Switching Characteristics:
t
IKHR
t
IKDS
t
IKDH
t
IKDD
t
IRDE
t
IRDV
t
IRDH
1
IACK High after Start of Read
IAD[15:0 Data Setup before IACK Low
IAD[15:0] Data Hold after End of Read
IAD[15:0] Data Disabled after End of Read
IAD[15:0] Previous Data Enabled after Start of Read
IAD[15:0] Previous Data Valid after Start of Read
IAD[15:0] Previous Data Hold after Start of Read
(DM/PM1)
2
t
IRDH
1
Start of Read = IS Low and IRD Low.
2
For IDMA, please refer to the
3
End of Read = IS High or IRD High.
4
DM read or first half of PM read.
5
Second half of PM read.
IAD[15:0] Previous Data Hold after Start of Read (PM2)
2, 4
ADSP-2100 Family User’s Manual
1, 2
10 ns
2
2, 3
2, 3
2
2
0.5tCK - 2 ns
0ns
10 ns
0ns
10 ns
2tCK - 5 ns
2, 5
.
tCK - 5 ns
IACK
IRD
IAD 15- 0
t
t
IRD V
IKHR
PREVIOUS
DATA
t
IRDH
t
IKD S
t
READ
DATA
IRK
t
IKDD
t
IKDH
t
IKR
IS
t
IRD E
Figure 25. IDMA Read, Long Read Cycle
33REV. PrB 6/2001
Page 34
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
IDMA Read, Short Read Cycle
Table 16. IDMA Read, Short Read Cycle
1
Parameter Description Min. Max Unit
Timing Requirements:
t
IKR
t
IRP
IACK Low before Start of Read
Duration of Read 10 ns
2
0ns
Switching Characteristics:
t
IKHR
t
IKDH
t
IKDD
t
IRDE
t
IRDV
1
t
IRDH
2
t
IRDH
1
Timing applies to ADSP-21mod980N when Short Read Only mode is disabled. See Table on page 35.
2
Start of Read = IS Low and IRD Low.
3
For IDMA, please refer to the
4
End of Read = IS High or IRD High.
5
DM read or first half of PM read.
6
Second half of PM read.
IACK High after Start of Read
IAD[15:0] Data Hold after End of Read
IAD[15:0] Data Disabled after End of Read
IAD[15:0] Previous Data Enabled after Start of Read
IAD[15:0] Previous Data Valid after Start of Read
IAD[15:0] Previous Data Hold after Start of Read
(DM/PM1)
3,5
IAD[15:0] Previous Data Hold after Start of Read (PM2)
ADSP-2100 Family User’s Manual
2, 3
10 ns
3, 4
3, 4
3
3
3, 6
.
0ns
10 ns
0ns
10 ns
2t
- 5 ns
CK
tCK - 5 ns
IACK
t
t
IRDV
IKHR
Previous Data New Read Data
IS
IR D
IAD[15:0]
t
IRDE
t
IKR
Figure 26. IDMA Read, Short Read Cycle
34 6/2001 REV. PrB
Page 35
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Read - Short Read Cycle in Short Read Only Mode
Table 17. IDMA Read - Short Read Cycle in Short Read Only Mode
1
Parameter Description Min. Max Unit
Timing Requirements:
t
IKR
t
IRP
IACK Low before Start of Read
Duration of Read after IACK Low
2, 4
3, 4
0ns
10 ns
Switching Characteristics:
t
IKHR
t
IKDH
t
IKDD
t
IRDE
t
IRDV
1
Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Shor t Read Only can be enabled by the processor core writing
to the register or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
4
For IDMA, please refer to the
IACK High after Start of Read
IAD[15:0] Previous Data Hold after End of Read
IAD[15:0] Previous Data Disabled after End of Read
IAD[15:0] Previous Data Enabled after Start of Read
IAD[15:0] Previous Data Valid after Start of Read
ADSP-2100 Family User’s Manual
2, 4
10 ns
3, 4
3, 4
4
4
.
0ns
10 ns
0ns
10 ns
IACK
t
t
RDV
IKHR
Previous Data
IS
IR D
IAD [15 :0]
t
IRDE
t
IKR
Figure 27. IDMA Read, Short Read Only Mode
t
IKDD
t
IKDH
35REV. PrB 6/2001
Page 36
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
352-BALL PBGA
For current information contact Analog Devices at (800) ANALOGD
Table 18. Pinout by
Signal Name (Continued)
Table 18. Pinout by
Signal Name (Continued)
PACKAGE PINOUT
A physical layout of all signals is shown in the
following tables. Figure on
page 40 shows the signals
on the left side of the device
when viewed from the top.
Figure on page 41 shows
the signals on the right side
of the device when viewed
from the top. The pin number for each signal is listed
in Table on page 36.
Table 18. Pinout by
Signal Name
Signal Name Pin
A0 A2
BG
_1 F3
_2 D14
BG
BG
_3 F25
_4 AC5
BG
BG
_5 R25
BG
_6 R4
BG
_7 AD15
_8 AD25
BG
BR
_1 G4
_2 B13
BR
BR
_3 G25
_4 AC9
BR
BR
_5 N24
_6 U4
BR
BR
_7 AE15
_8 AE26
BR
CLKIN E3
CLKOUT_1 G1
CLKOUT_2 A10
Signal Name Pin
CLKOUT_3 C20
CLKOUT_4 AC1
CLKOUT_5 L24
CLKOUT_6 P4
CLKOUT_7 AD10
CLKOUT_8 AF15
D08 F23
D09 E25
D10 E24
D11 D26
D12 D25
D13 D24
D14 C26
D15 C25
D16 B26
D17 B24
D18 A25
D19 B23
D20 C23
D21 A24
D22 A23
D23 A22
DR0A E1
DR0B AF22
DR1 AE7
DT0A P2
DT0B AF20
DT1_1 P3
DT1_2 A12
DT1_3 D21
Signal Name Pin
DT1_4 AF2
DT1_5 T25
DT1_6 U3
DT1_7 AD13
DT1_8 AE20
EBG
EBR
ECLK J23
EE_1 M4
EE_2 C13
EE_3 G23
EE_4 AE9
EE_5 T26
EE_6 Y2
EE_7 AC13
EE_8 AE22
EINT
ELIN J25
ELOUT J24
EMS
ERESET
GND D19
GND D20
GND D23
GND F1
GND F2
GND F4
GND G2
GND G3
GND H1
F26
G26
J26
E23
E26
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
GND H2
GND H3
GND H4
GND H23
GND H24
GND H25
GND H26
GND N1
GND N2
GND N3
GND N4
GND R23
GND R24
GND T3
GND T24
GND U1
GND U2
GND U23
GND U24
GND U25
GND U26
GND W1
GND W2
GND W3
GND W4
GND AF1
GND AF4
GND AF8
GND AF10
GND AF12
36 6/2001 REV. PrB
Page 37
PRELIMINARY TECHNICAL DATA
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
GND AF16
GND AF17
GND AF21
GND AF23
GND AF26
GND B2
GND B5
GND B11
GND B12
GND B16
GND B19
For current information contact Analog Devices at (800) ANALOGD
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
GND AD4
GND AD5
GND AD7
GND AD8
GND AD11
GND AD12
GND AD16
GND AD17
GND AD21
GND AD22
GND AD23
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
GND A26
GND AA23
GND AA24
GND AA25
GND AA26
GND AC4
GND AC6
GND AC8
GND AC10
GND W23
IACK
_A T4
ADSP-21mod980N
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
IAD3_A D3
IAD3_B W24
IAD4_A C1
IAD4_B W25
IAD5_A D2
IAD5_B W26
IAD6_A V4
IAD6_B M26
IAD7_A Y4
IAD7_B N26
IAD8_A AD6
GND B21
GND B25
GND C3
GND C5
GND C11
GND C16
GND C19
GND C21
GND C24
GND D4
GND D5
GND D11
GND D16
GND AC12
GND AC17
GND AD24
GND AE1
GND AE2
GND AE4
GND AE8
GND AE10
GND AE12
GND AE16
GND AE17
GND AE21
GND AE23
GND AE25
GND A1
GND A5
GND A11
_B AC26
IACK
IAD0_A B4
IAD0_B V26
IAD1_A B1
IAD1_B V23
IAD10_A AA2
IAD10_B L26
IAD11_A V3
IAD11_B L23
IAD12_A AA4
IAD12_B M25
IAD13_A E2
IAD13_B AD26
IAD14_A D1
IAD14_B AC24
IAD8_B M23
IAD9_A Y3
IAD9_B M24
IAL_A C8
IAL_B Y25
IRD
_A C4
_B Y24
IRD
IS
_1 D6
_2 A14
IS
IS
_3 F24
_4 AA3
IS
IS
_5 V25
_6 AC7
IS
IS
_7 AC16
_8 Y26
IS
GND AC21
GND AC23
GND AD2
GND AD3
GND A16
GND A19
GND A20
GND A21
IAD15_A E4
IAD15_B AC25
IAD2_A C2
IAD2_B V24
IWR
_A D8
_B Y23
IWR
PF0 A6
PF1 B6
37REV. PrB 6/2001
Page 38
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
PF2 C6
PF4_1 M1
PF4_2 C10
PF4_3 D18
PF4_4 AC2
PF4_5 L25
PF4_6 T1
PF4_7 AF7
PF4_8 AD18
PF5_1 M2
PF5_2 D10
For current information contact Analog Devices at (800) ANALOGD
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
PF7_6 V2
PF7_7 AF9
PF7_8 AF18
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
_1 J1
_2 D13
_3 C22
_4 AF6
_5 T23
_6 AA1
_7 AC11
_8 AC22
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
VDDEXT C15
VDDEXT C17
VDDEXT D7
VDDEXT D9
VDDEXT D15
VDDEXT D17
VDDEXT D22
VDDEXT K1
VDDEXT K2
VDDEXT K3
VDDEXT K4
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
VDDEXT AE14
VDDEXT AE19
VDDEXT AF14
VDDEXT AF19
VDDEXT B7
VDDEXT B8
VDDEXT B9
VDDEXT B14
VDDEXT B15
VDDEXT B17
VDDINT A3
PF5_3 C18
PF5_4 AC3
PF5_5 G24
PF5_6 V1
PF5_7 AE11
PF5-8 AE18
PF6_1 M3
PF6_2 B10
PF6_3 B18
PF6_4 AD1
PF6_5 R26
PF6_6 T2
PF6_7 AD9
PF6_8 AC18
PF7_1 J4
RFS0A J3
RFS0B AD20
RFS1 AE6
SCLK0A P1
SCLK0B AE24
SCLK1 AF5
TFS0_1 J2
TFS0_2 C12
TFS0_3 B20
TFS0_4 AE5
TFS0_5 N23
TFS0_6 Y1
TFS0_7 AF11
TFS0_8 AC20
TFS1 AF3
VDDEXT K23
VDDEXT K24
VDDEXT K25
VDDEXT K26
VDDEXT L1
VDDEXT L2
VDDEXT L3
VDDEXT L4
VDDEXT A7
VDDEXT A8
VDDEXT A9
VDDEXT A13
VDDEXT A15
VDDEXT A17
VDDEXT AC14
VDDINT A4
VDDINT AB1
VDDINT AB2
VDDINT AB3
VDDINT AB4
VDDINT AB23
VDDINT AB24
VDDINT AB25
VDDINT AB26
VDDINT AE13
VDDINT AF13
VDDINT AF24
VDDINT AF25
VDDINT B3
VDDINT P23
PF7_2 D12
PF7_3 A18
PF7_4 AE3
PF7_5 N25
38 6/2001 REV. PrB
VDDEXT B22
VDDEXT C7
VDDEXT C9
VDDEXT C14
VDDEXT AC15
VDDEXT AC19
VDDEXT AD14
VDDEXT AD19
VDDINT P24
VDDINT P25
VDDINT P26
Page 39
PRELIMINARY TECHNICAL DATA
Table 18. Pinout by
Signal Name (Continued)
Signal Name Pin
VDDINT R1
VDDINT R2
VDDINT R3
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
39REV. PrB 6/2001
Page 40
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
Signals by Pin Location—Top View, Left to Right
1 234 5678910 111213
A GND A0 VDDINT VDDINT GND PF0 VDDEXT V DDEXT VDDEXT CLKOUT_2 GND DT1_2 VDDEXT
B IAD1 _A GND VDDINT IAD0_A GND PF1 VDDEXT VDDEXT VDDEXT PF6_2 GND GND BR_2
C IAD4_A IAD2_A GND IRD_A GND PF2 VDDEXT IAL_A VDDEXT PF4_2 GND TFS0_2 EE_2
D IAD14_A IAD6_A IAD3_A G ND GND IS_1 V DDEXT IWR_A VDDEXT PF5_2 GND PF7_2 RESET_2
E DR0A IAD13_A CLKIN IAD15_A
F GND GND BG_1 GND
G CLKOUT_1 GND GND BR_1
H GND GND GND GND
J RESET_1 TFS0_1 RFS0A PF7_1
K VDDEXT VDDEXT VDDEXT VDDEXT
L VD DEXT VDDEXT VDDEXT VDDEXT
M PF4_1 PF5_1 PF6_1 EE_1
N GND GND GND GND
P SCLK0A DT0A DT1_1 CLKOUT_6
R VDDINT V DDINT VDDINT BG_6
T PF4_6 PF6_6 GND IACK_A
U GND GND DT1_6 BR_6
V PF5_6 PF7_6 IAD11_A IAD6_A
W GND GND G ND GND
Y TFS0_6 EE_6 IAD9_A IAD7_A
AA RESET_6 IAD10_A IS_4 IAD12_A
AB VDDINT VDDI NT VDDINT VDDINT
AC CLKOUT_4 PF4_4 PF5_4 GND BG_4 GND IS_6 GND BR_4 GND RESET_7 GND EE_7
AD PF6_4 G ND GND GND GND IAD8_A GND GND PF6_7 CLKOUT_7 GND GND DT1_7
AE GND GND PF7_4 GND TFS0_4 RFS1 DR1 GND EE_4 GND PF5_7 GND VDDINT
AF GND DT1_4 TFS1 GND SCLK1 RESET_4 PF4_7 GND PF7_7 GND TFS0_7 GND VDDINT
1 234 5678910 111213
40 6/2001 REV. PrB
Page 41
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
OUTLINE DIMENSIONS – 352 PLASTIC BALL GRID ARRAY
Signals by Pin Location—Top View, Left to Right (Continued)
14 15 16 17 18 19 20 21 22 23 24 25 26
IS_2 VDDEXT GND VDDEXT PF7_3 GND GND GND D23 D22 D21 D18 GND A
VDDEXT VDDEXT GND VDDEXT PF6_3 GND TRS0_3 GND VDDEXT D19 D17 GND D16 B
VDDEXT VDDEXT GND VDDEXT PF5_3 GND CLKOUT_3 GND RESET_3 D20 GND D15 D14 C
BG_2 VDDEXT GND VDDEXT PF4_3 GND GND DT1_3 VDDEXT GND D13 D12 D11 D
EMS D10 D09 ERESET E
D08 IS _3 BG_3 EBG F
EE_3 PF5_5 BR_3 EBR G
GND GND GND GND H
ECLK ELOUT ELIN EINT J
VDDEXT VDDEXT VDDEXT VDDEXT K
IAD11_B CLKOUT_5 PF4_5 IAD10_B L
IAD8_B IAD9_B IAD12_B IAD6_B M
TFS0_5 BR_5 PF7_5 IAD7_B N
VDDINT VDDINT VDDINT VDDINT P
GND GND BG_5 PF6_5 R
RESET_5 GND DT1_5 EE_5 T
GND GND GND GND U
IAD1_B IAD2_B IS_5 IAD0_B V
GND IAD3_B IAD4_B IAD5_B W
IWR_B IRD_B IAL_B IS_8 Y
GND GND GND GND AA
VDDINT VDDINT VDDINT VDDINT AB
VDDEXT VDDEXT IS_7 GND PF6_8 VDDEXT TFS0_8 GND RESET_8 GND IAD14_B IAD15_B IACK_B AC
VDDEXT BG_7 GND GND PF4_8 VDDEXT RFS0B G ND GND GND GND BG_8 IAD13_B AD
VDDEXT BR_7 GND GND PF5_8 V DDEXT DT1_8 GND EE_8 GND SCLK0B GND BR_8 AE
VDDEXT CLKOUT_8 GND GND PF7_8 VDDEXT DT0B GND DR0B GND VDDINT VDDINT GND AF
14 15 16 17 18 19 20 21 22 23 24 25 26
41REV. PrB 6/2001
Page 42
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
BALL A1
INDIC ATOR
2.62
2.37
2.12
NOTES:
1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30
OF THE IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
2. THE ACTUAL POSITIO N OF EACH BALL IS WITHIN 0.15 OF ITS
IDEAL POSITION RELATIVE TO THE BALL GRID.
3. CENTER FIGURES ARE NOMINAL UNLESS OTHERWISE NOTED.
For current information contact Analog Devices at (800) ANALOGD
35.00 B S C S Q
TOP VIEW
30.70
30.00 SQ
29.50
DETAIL A
26 24 22 20 18 16 14 12 10 8 6 4 2
25 23 21 19 17 15 13 11 9 7 5 3 1
BOTTOM VIEW
1.27 BSC SQ
BALL PITCH
31.75 BSC SQ
0.70
0.60
0.50
0.70
SEATING
0.60
PLANE
0.50
BALL DIAMETE R
DETAIL A
0.90
0.75
0.60
0.20 MAX
1.22
1.17
1.12
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Figure 28. 352-Lead metric Plastic Ball Grid Array (PBGA) (B-352)
ORDERING GUIDE
A complete modem requires the device listed in Table 19
plus a software solution as described in
MODEM SOFTWARE
on page 2.
Table 19. Ordering Guide
Part Number
Ambient Temperature
Range
Instruction Rate
Package
Description
Package Option
ADSP-21mod980N-000 0ºC to +70ºC 80 MHz 352-Ball PBGA B-352
42 6/2001 REV. PrB
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