Datasheet ADSP-219x Datasheet (ANALOG DEVICES)

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ADSP-219x DSP

Instruction Set Reference

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 2.0, December 2005

Part Number

82-000390-07

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

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The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

PREFACE

Purpose of This Manual ................................................................ xiii

Intended Audience ........................................................................ xiii

Manual Contents ........................................................................... xiv

What’s New in This Manual ............................................................ xv

Technical or Customer Support ....................................................... xv

Supported Processors ...................................................................... xvi

Product Information ..................................................................... xvii

MyAnalog.com ........................................................................ xvii

Processor Product Information ................................................ xviii

Related Documents .................................................................. xix

Online Technical Documentation ............................................. xix

Accessing Documentation From VisualDSP++ ....................... xx

Accessing Documentation From Windows ............................. xx

Accessing Documentation From the Web .............................. xxi

Printed Manuals ....................................................................... xxi

VisualDSP++ Documentation Set ........................................ xxii

Hardware Tools Manuals ..................................................... xxii

Processor Manuals ............................................................... xxii

ADSP-219x DSP Instruction Set Reference iii

CONTENTS

Data Sheets ........................................................................ xxii

Conventions ................................................................................ xxiii

INSTRUCTION SET SUMMARY

Core Registers Summary ............................................................... 1-2

Arithmetic Status (ASTAT) Register .............................................. 1-3

Condition Code (CCODE) Register ............................................. 1-5

Interrupt Control (ICNTL) Register ............................................. 1-6

Interrupt Mask (IMASK) Register and

Interrupt Latch (IRPTL) Register ............................................... 1-7

Mode Status (MSTAT) Register .................................................... 1-8

System Status (SSTAT) Register .................................................. 1-10

Condition Codes Summary ......................................................... 1-11

Instruction Summary .................................................................. 1-12

ALU Instructions .................................................................. 1-14

Multiplier Instructions .......................................................... 1-15

Shifter Instructions ............................................................... 1-16

Data Move Instructions ......................................................... 1-16

Program Flow Instructions .................................................... 1-18

Multifunction Instructions .................................................... 1-19

ALU INSTRUCTIONS

ALU Instruction Conventions ....................................................... 2-1

Input Registers ........................................................................ 2-1

Output Registers ..................................................................... 2-2

Constants ............................................................................... 2-2

iv ADSP-219x DSP Instruction Set Reference

CONTENTS

ALU Mode Control ................................................................. 2-3

ALU Status Flags ..................................................................... 2-4

ALU Instruction Reference ............................................................ 2-4

Add/Add with Carry ..................................................................... 2-5

Subtract X−Y/Subtract X−Y with Borrow ....................................... 2-9

Subtract Y−X/Subtract Y−X with Borrow ..................................... 2-13

Bitwise Logic: AND, OR, XOR ................................................... 2-16

Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT ............. 2-19

Clear: PASS ................................................................................ 2-22

Negate: NOT .............................................................................. 2-25

Absolute Value: ABS ................................................................... 2-28

Increment ................................................................................... 2-31

Decrement .................................................................................. 2-34

Divide Primitives: DIVS and DIVQ ............................................ 2-37

Generate ALU Status Only: NONE ............................................. 2-46

MAC INSTRUCTIONS

Multiply Instruction Conventions ................................................. 3-2

MAC Input Registers ............................................................... 3-2

MAC Output Registers ............................................................ 3-2

Data Format Options .............................................................. 3-3

Rounding Modes ..................................................................... 3-4

Numeric Format Modes ........................................................... 3-6

Status Flags ............................................................................. 3-7

Multiply ....................................................................................... 3-8

ADSP-219x DSP Instruction Set Reference v

CONTENTS

Multiply with Cumulative Add ................................................... 3-11

Multiply with Cumulative Subtract ............................................. 3-14

MAC Clear ................................................................................ 3-17

MAC Round/Transfer ................................................................. 3-19

MAC Saturate ............................................................................ 3-21

Generate MAC Status Only: NONE ........................................... 3-24

SHIFTER INSTRUCTIONS

Shifter Operation Conventions ..................................................... 4-2

Shifter Registers ...................................................................... 4-2

Shifter Instruction Options ..................................................... 4-3

Shifter Status Flags .................................................................. 4-5

Arithmetic Shift ............................................................................ 4-6

Arithmetic Shift Immediate .......................................................... 4-8

Logical Shift ............................................................................... 4-10

Logical Shift Immediate .............................................................. 4-12

Normalize .................................................................................. 4-14

Normalize Immediate ................................................................. 4-17

Exponent Derive ........................................................................ 4-20

Exponent (Block) Adjust ............................................................. 4-23

Denormalization ......................................................................... 4-26

MULTIFUNCTION INSTRUCTIONS

Order of Execution of Multifunction Operations ........................... 5-2

Multifunction Instruction Reference ............................................. 5-3

vi ADSP-219x DSP Instruction Set Reference

CONTENTS

Compute with Dual Memory Read ................................................ 5-4

Dual Memory Read ....................................................................... 5-8

Compute with Memory Read ...................................................... 5-11

Compute with Memory Write ..................................................... 5-15

Compute with Register-to-Register Move .................................... 5-19

DATA MOVE INSTRUCTIONS

Core Registers ............................................................................... 6-2

PX Register ................................................................................... 6-3

DAG Registers .............................................................................. 6-5

Address Registers ..................................................................... 6-5

DAG Memory Page Registers (DMPGx) .................................. 6-6

Secondary DAG Registers ........................................................ 6-7

Data Addressing Methods ............................................................ 6-11

Direct Addressing .................................................................. 6-11

Indirect Addressing ................................................................ 6-12

Circular Data Buffer Addressing ............................................ 6-14

Bit-Reversed Addressing ........................................................ 6-16

Data Move Instruction Reference ................................................ 6-21

Direct Memory Read/Write—Immediate Address ........................ 6-24

Direct Register Load ................................................................... 6-27

Indirect 16-Bit Memory Read/Write—Postmodify ....................... 6-30

Indirect 16-Bit Memory Read/Write—Premodify ......................... 6-34

ADSP-219x DSP Instruction Set Reference vii

CONTENTS

Indirect 24-Bit Memory Read/Write—Postmodify ....................... 6-38

Indirect 24-Bit Memory Read/Write—Premodify ........................ 6-43

Indirect DAG Register Write (Premodify or Postmodify),

with DAG Register Move ......................................................... 6-47

Indirect Memory Read/Write—Immediate Postmodify ................ 6-51

Indirect Memory Read/Write—Immediate Premodify .................. 6-54

Indirect 16-Bit Memory Write—Immediate Data ........................ 6-57

Indirect 24-Bit Memory Write—Immediate Data ........................ 6-59

External I/O Port Read/Write ..................................................... 6-62

System Control Register Read/Write ........................................... 6-65

Modify Address Register—Indirect .............................................. 6-68

Modify Address Register—Direct ................................................ 6-70

PROGRAM FLOW INSTRUCTIONS

Conditions ................................................................................... 7-2

Counter-Based Conditions ............................................................ 7-2

CCODE Register ......................................................................... 7-3

Mode Control .............................................................................. 7-4

Branch Options ............................................................................ 7-4

Addressing Branch Targets ............................................................ 7-6

Stacks ........................................................................................... 7-7

PC and Status Stack Operation ................................................ 7-8

Loop Stacks Operation .......................................................... 7-10

Stack Status Flags ....................................................................... 7-12

Interrupts ................................................................................... 7-13

viii ADSP-219x DSP Instruction Set Reference

CONTENTS

Enabling Interrupts ............................................................... 7-14

Switching Contexts ................................................................ 7-16

Nesting Interrupts ................................................................. 7-16

Application Performance ............................................................. 7-17

Exiting a Loop ....................................................................... 7-18

Using Long Jumps and Calls .................................................. 7-20

Effect Latencies ..................................................................... 7-22

Program Flow Instruction Reference ............................................ 7-23

DO UNTIL (PC Relative) .......................................................... 7-24

Direct JUMP (PC Relative) ......................................................... 7-29

CALL (PC Relative) .................................................................... 7-33

JUMP (PC Relative) ................................................................... 7-37

Long Call (LCALL) ..................................................................... 7-40

Long Jump (LJUMP) .................................................................. 7-43

Indirect CALL ............................................................................ 7-46

Indirect JUMP ............................................................................ 7-50

Return from Interrupt (RTI) ....................................................... 7-53

Return from Subroutine (RTS) .................................................... 7-57

PUSH or POP Stacks .................................................................. 7-61

FLUSH CACHE ......................................................................... 7-67

Set Interrupt (SETINT) .............................................................. 7-69

Clear Interrupt (CLRINT) .......................................................... 7-71

NOP .......................................................................................... 7-73

IDLE .......................................................................................... 7-74

ADSP-219x DSP Instruction Set Reference ix

CONTENTS

Mode Control ............................................................................ 7-76

INSTRUCTION OPCODES

Opcode Mnemonics ..................................................................... 8-1

ALU or Multiplier Function (AMF) Codes .............................. 8-6

Condition Codes .................................................................... 8-8

Constant Codes ...................................................................... 8-9

Core Register Codes .............................................................. 8-11

Shift Function (SF) Codes ..................................................... 8-12

Index Register and Modify Register Codes ............................. 8-13

DMI, DMM, PMI, and PMM Codes .................................... 8-14

IREG/MREG Codes ............................................................. 8-15

XOP and YOP Codes ............................................................ 8-15

Opcode Definitions .................................................................... 8-16

Type 1: Compute | DregX«···DM | DregY«···PM ......................... 8-17

Type 3: Dreg/Ireg/Mreg «···» DM/PM ......................................... 8-18

Type 4: Compute | Dreg «···» DM ............................................... 8-19

Type 6: Dreg «··· Data16 ............................................................. 8-20

Type 7: Reg1/2 «··· Data16 ......................................................... 8-21

Type 8: Compute | Dreg1 «··· Dreg2 ........................................... 8-22

Type 9: Compute ........................................................................ 8-23

Type 9a: Compute ...................................................................... 8-26

Type 10: Direct Jump ................................................................. 8-28

Type 10a: Direct Jump/Call ........................................................ 8-29

Type 11: Do ··· Until .................................................................. 8-30

x ADSP-219x DSP Instruction Set Reference

CONTENTS

Type 12: Shift | Dreg «···» DM .................................................... 8-31

Type 14: Shift | Dreg1 «··· Dreg2 ................................................. 8-32

Type 15: Shift Data8 ................................................................... 8-33

Type 16: Shift Reg0 .................................................................... 8-34

Type 17: Any Reg «···Any Reg ..................................................... 8-35

Type 18: Mode Change ............................................................... 8-36

Type 19: Indirect Jump/Call ........................................................ 8-37

Type 20: Return .......................................................................... 8-38

Type 21: Modify DagI ................................................................. 8-39

Type 21a: Modify DagI ............................................................... 8-40

Type 22: DM «··· Data16 ............................................................ 8-41

Type 22a: PM «··· Data24 ............................................................ 8-42

Type 23: Divide primitive, DIVQ ................................................ 8-43

Type 24: Divide primitive, DIVS ................................................. 8-44

Type 25: Saturate ........................................................................ 8-45

Type 26:Push/Pop/Cache ............................................................ 8-46

Type 29: Dreg «···» DM .............................................................. 8-47

Type 30: NOP ............................................................................ 8-48

Type 31: Idle ............................................................................... 8-49

Type 32: Any Reg «···» PM/DM .................................................. 8-50

Type 32a: DM«···DAG Reg | DAG Reg«···Ireg ............................. 8-51

Type 33: Reg3 «··· Data12 ........................................................... 8-52

Type 34: Dreg «···» IOreg ............................................................ 8-53

Type 35: Dreg «···»Sreg ............................................................... 8-54

ADSP-219x DSP Instruction Set Reference xi

CONTENTS

Type 36: Long Jump/Call ........................................................... 8-55

Type 37: Interrupt ...................................................................... 8-56

INDEX

xii ADSP-219x DSP Instruction Set Reference

PREFACE

Thank you for purchasing and developing systems using ADSP-219x DSPs from Analog Devices.

Purpose of This Manual

The ADSP-219x DSP Instruction Set Reference provides assembly syntax information for ADSP-219x DSPs. The syntax descriptions cover instructions that execute within the DSP’s processor core (processing elements, program sequencer, and data address generators). For architecture and design information on the DSP, see the ADSP-219x/2192 DSP Hardware Reference.

Intended Audience

The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate hardware reference manuals and data sheets) that describe your target architecture.

ADSP-219x DSP Instruction Set Reference xiii

Manual Contents

This reference presents instruction information organized by the type of the instruction. Instruction types relate to the machine language opcode for the instruction. On this DSP, the opcodes categorize the instructions by the portions of the DSP architecture that execute the instructions. The following chapters cover the different types of instructions.

• “Instruction Set Summary” on page 1-1—This chapter provides a syntax summary of all instructions and describes the conventions that are used on the instruction reference pages.

• “ALU Instructions” on page 2-1—These instruction specify opera- tions that occur in the DSP’s ALU.

• “MAC Instructions” on page 3-1—These instructions specify operations that occur in the DSP’s Shifter.

• “Shifter Instructions” on page 4-1—These instructions specify operations that occur in the DSP’s Shifter.

• “Multifunction Instructions” on page 5-1—These instructions specify parallel, single-cycle operations.

• “Data Move Instructions” on page 6-1—These instructions specify memory and register access operations.

• “Program Flow Instructions” on page 7-1—These instructions specify program sequencer operations.

• “Instruction Opcodes” on page 8-1—This chapter lists the instruction encoding fields for all instructions.

Each of the DSP’s instructions is specified in this text. The reference page for an instruction shows the syntax of the instruction, describes its function, gives one or two assembly-language examples, and identifies fields of

xiv ADSP-219x DSP Instruction Set Reference

Preface

its opcode. The instructions are referred to by type, ranging from 1 to 37. These types correspond to the opcodes that ADSP-219x DSPs recognize, but are for reference only and have no bearing on programming.

Some instructions have more than one syntactical form; for example, the instruction “Type 9: Compute” on page 8-23 has many distinct forms.

Many instructions can be conditional. These instructions are prefaced by

IF COND; for example:

If COND compute;

In a conditional instruction, the execution of the entire instruction is based on the specified condition.

What’s New in This Manual

Revision 2.0 of the ADSP-219x DSP Instruction Set Reference corrects all known document errata issues.

This instruction set reference is a companion document to the ADSP-219x/2192 DSP Hardware Reference (Rev 1.1, April 2004).

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

processor.tools.support@analog.com

ADSP-219x DSP Instruction Set Reference xv

Supported Processors

• E-mail processor questions to

processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized distributor

• Send questions by mail to:

Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®.

TigerSHARC® (ADSP-TSxxx) Processors

The name TigerSHARC refers to a family of floating-point and fixed-point [8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently supports the following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.

SHARC® (ADSP-21xxx) Processors

The name SHARC refers to a family of high-performance, 32-bit, floating-point processors that can be used in speech, sound, graphics, and imaging applications. VisualDSP++ currently supports the following SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, and ADSP-2136x.

xvi ADSP-219x DSP Instruction Set Reference

Blackfin® (ADSP-BFxxx) Processors

The name Blackfin refers to a family of 16-bit, embedded processors. VisualDSP++ currently supports the following Blackfin families: ADSP-BF53x and ADSP-BF56x.

ADSP-21xx Processors

The ADSP-21xx processors are high-performance 16-bit DSPs for communications, instrumentation, industrial/control, voice/speech, medical and military applications. The family includes the ADSP-218x, ADSP-219x, and mixed-signal products (ADSP-21990, ADSP-21991, and ADSP-21992).

Product Information

You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).

Preface

Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows

customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.

ADSP-219x DSP Instruction Set Reference xvii

Product Information

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Registration takes about five minutes and serves as a means to select the information you want to receive.

If you are already a registered user, just log on. Your user name is your e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product announcements.

You may also obtain additional information about Analog Devices and its products in any of the following ways.

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xviii ADSP-219x DSP Instruction Set Reference

Preface

1 INSTRUCTION SET SUMMARY

This chapter provides a summary of the instructions in the ADSP-219x DSP’s instruction set. Chapters 2 through 8 describe these instructions in more detail as follows:

• “ALU Instructions” on page 2-1

• “MAC Instructions” on page 3-1

• “Shifter Instructions” on page 4-1

• “Multifunction Instructions” on page 5-1

• “Data Move Instructions” on page 6-1

• “Program Flow Instructions” on page 7-1

• “Instruction Opcodes” on page 8-1

Also, this chapter identifies mnemonics for using DSP registers, bits, and operating conditions. This information appears in the following summaries:

• “Core Registers Summary” on page 1-2

• “Arithmetic Status (ASTAT) Register” on page 1-3

• “Condition Code (CCODE) Register” on page 1-5

• “Interrupt Control (ICNTL) Register” on page 1-6

• “Interrupt Mask (IMASK) Register and Interrupt Latch (IRPTL)

ADSP-219x DSP Instruction Set Reference 1-1

Core Registers Summary

• “Mode Status (MSTAT) Register” on page 1-8

• “System Status (SSTAT) Register” on page 1-10

• “Condition Codes Summary” on page 1-11

For information on instruction reference notation, see “Conventions” on

page xxiii.

Core Registers Summary

The DSP has three categories of registers: core registers, system control registers, and I/O registers. Table 1-1 lists and describes the DSP’s core registers. For information about system control and I/O registers, see the ADSP-219x/2192 DSP Hardware Reference.

Table 1-1. Core Registers

Type Registers Function

ALU data AX0, AX1, AY0, AY1,

AR, AF

Multiplier data MX0, MX1, MY0, MY1,

MR0, MR1, MR2

Shifter data SI, SE, SB, SR0, SR1, SR2

DAG address I0, I1, I2, I3

I4, I5, I6, I7

M0, M1, M2, M3 M4, M5, M6, M7

L0, L1, L2, L3 L4, L5, L6, L7

16-bit data registers (X and Y) provide input for ALU, multiplier, and shifter operations. AR and AF are ALU result and feedback registers. MR and SR are multiplier result and feedback registers. SR also is the shifter results register. In this text, Dreg denotes unrestricted use of data registers as a data register file, while “ XOP” and “YOP” denote restricted use. The data registers (except AF, SE, and SB) serve as a register file for unconditional, single-function instructions.

DAG1 index registers DAG2 index registers

DAG1 modify registers DAG2 modify registers

DAG1 length registers DAG2 length registers

1-2 ADSP-219x DSP Instruction Set Reference

Table 1-1. Core Registers (Cont’d)

Type Registers Function

Instruction Set Summary

System control B0, B1, B2, B3, B4, B5,

B6, B7, SYSCTL, CACTL

Program flow CCODE

LPSTACKA LPSTACKP STACKA STACKP

Interrupt ICNTL

IMASK IRPTL

Status ASTAT

MSTAT SSTAT (read-only)

Page DMPG1

DMPG2 IJPG IOPG

Bus exchange PX Holds eight LSBs of 24-bit memory data for

Shifter SE

DAG1 base address registers (B0-3), DAG2 base address registers (B4-7), System control, and Cache control

Software condition register Loop PC stack A register, 16 address LSBs Loop PC stack P register, 8 address MSBs PC stack A register, 16 address LSBs PC stack P register, 8 address MSBs

Interrupt control register Interrupt mask register Interrupt latch register

Arithmetic status flags Mode control and status flags System status

DAG1 page register, 8 address MSBs DAG2 page register, 8 address MSBs Indirect jump page register, 8 address MSBs I/O page register, 8 address MSBs

transfers between memory and data registers only.

Shifter exponent register Shifter block exponent register

Arithmetic Status (ASTAT) Register

The DSP updates the status bits in ASTAT, indicating the status of the most recent ALU, multiplier, or shifter operation.

ADSP-219x DSP Instruction Set Reference 1-3

Arithmetic Status (ASTAT) Register

Table 1-2. ASTAT Register Bit Definitions

Bit Name Description

0 AZ ALU result zero. Logical NOR of all bits written to the ALU result register

(AR) or ALU feedback register (AF). 0 =ALU output ≠ 0 1 =ALU output = 0

1 AN ALU result negative. Sign of the value written to the ALU result register

(AR) or ALU feedback register (AF). 0 =ALU output positive (+) 1 =ALU output negative (−)

2 AV ALU result overflow.

0 =No overflow 1 =Overflow

3 AC ALU result carry.

0 =No carry 1 =Carry

4AS ALU x input sign. Sign bit of the ALU x-input operand; set by the ABS

instruction only. 0 =Positive (+) 1 =Negative (−)

5 AQ ALU quotient. Sign of the resulting quotient; set by the DIVS or DIVQ

instructions. 0 =Positive (+) 1 =Negative (−)

6 MV Multiplier overflow. Records overflow/underflow condition for MR result

7 SS Shifter input sign. Sign of the shifter input operand.

0 =Positive (+) 1 =Negative (−)

8 SV Shifter overflow. Records overflow/underflow condition for SR result reg-

ister. 0 =No overflow or underflow 1 =Overflow or underflow

1-4 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Condition Code (CCODE) Register

Using the CCODE register (shown in Table 1-3), conditional instructions may base execution on a comparison of the CCODE value (user-selected) and the SWCOND condition (DSP status). The CCODE register holds a value between 0x0 and 0xF, which the instruction tests against when the conditional instruction uses SWCOND or NOT SWCOND. Note that the CCODE register has a one-cycle effect latency.

Table 1-3. CCODE Register Bit Definitions

CCODE Software Condition

Value SWCOND (1010) NOT SWCOND (1011)

0x00 PF0 pin high PF0 pin low

0x01 PF1 pin high PF1 pin low

0x02 PF2 pin high PF2 pin low

0x03 PF3 pin high PF3 pin low

0x04 PF4 pin high PF4 pin low

0x05 PF5 pin high PF5 pin low

0x06 PF6 pin high PF6 pin low

0x07 PF7 pin high PF7 pin low

0x08 AS NOT AS

0x09 SV NOT SV

0x0A PF8 pin high PF8 pin low

0x0B PF9 pin high PF9 pin low

0x0C PF10 pin high PF10 pin low

0x0D PF11 pin high PF11 pin low

0x0E PF12 pin high PF12 pin low

0x0F PF13 pin high PF13 pin low

ADSP-219x DSP Instruction Set Reference 1-5

Interrupt Control (ICNTL) Register

Refer to Table 1-4 for ICNTL register bit definitions.

Table 1-4. ICNTL Register Bit Definitions

Bit Name Description

0reserved write 0

1reserved write 0

2reserved write 0

3reserved write 0

4 INE Interrupt nesting enable.

0 =Disabled 1 =Enabled

5 GIE Global interrupt enable.

0 =Disabled 1 =Enabled

6reserved write 0

7 BIASRND MAC biased rounding mode.

0 =Disabled 1 =Enabled

8-9 reserved write 0

10 PCSTKE PC stack interrupt enable.

0 =Disabled 1 =Enabled

11 EMUCNTE Emulator cycle counter interrupt enable.

0 =Disabled 1 =Enabled

12-15 reserved write 0

1-6 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Interrupt Mask (IMASK) Register and Interrupt Latch (IRPTL) Register

Refer to Table 1-5 for IMASK register and IRPTL register bit definitions.

Table 1-5. IMASK and IRPTL Register Bit Definitions

Bit Name Description

0 EMU Emulator interrupt mask. Nonmaskable. Highest priority

1 PWDN Power-down interrupt mask. Maskable only with GIE bit in ICNTL.

2 SSTEP Single-step interrupt mask (during emulation)

3 STACK Stack interrupt mask. Generated from any of the following stack status

states: (if PCSTKE enabled) PC stack is pushed or popped and hits high-water mark, any stack overflows, or the status or PC stacks underflow.

4User-defined

5User-defined

6User-defined

7User-defined

8User-defined

9User-defined

10 User-defined

11 User-defined

12 User-defined

13 User-defined

14 User-defined

15 User-defined Lowest priority

ADSP-219x DSP Instruction Set Reference 1-7

Mode Status (MSTAT) Register

Refer to Table 1-6 for MSTAT register bit definitions.

Table 1-6. MSTAT Register Bit Definitions

Bit Name Description

0SEC_REG

or SR

1 BIT_REV

or BR

2AV_LATCH

or OL

Secondary data registers enable. Determines which set of data registers is currently active. 0 =Deactivate secondary set of data registers (default). Primary register set (set that is active at reset) enabled and used for normal operation; secondary register set disabled. 1 =Activate secondary set of data registers. Secondary register set enabled and used for alternate DSP context (for example, interrupt servicing); primary register set disabled, current contents preserved. For details, see “Switching Contexts” on page 7-16.

Bit-reversed addressing enable. Enables and disables bit-reversed addressing on DAG1 index registers only. 0 =Disable 1 =Enable For details, see “Bit-Reversed Addressing” on page 6-16.

ALU overflow latch mode enable. Determines how the ALU overflow flag, 0 =Disable Once an ALU overflow occurs and sets the ister, the subsequent ALU operation that does not generate an overflow. 1 =Enable Once an ALU overflow occurs and sets the ister, the For details on clearing the

SETBIT, CLRBIT, TGLBIT” on page 2-19 and “Register-to-Register Move” on page 6-22.

AV, gets cleared.

AV bit in the ASTAT reg-

AV bit remains set until explicitly cleared or is cleared by a

AV bit in the ASTAT reg-

AV bit remains set until the application explicitly clears it.

AV bit, see “Bit Manipulation: TSTBIT,

1-8 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Table 1-6. MSTAT Register Bit Definitions (Cont’d)

Bit Name Description

3AR_SAT

or AS

4M_MODE

or MM

5TIMER

or TI

ALU saturation mode enable. For signed values, determines whether ALU AR results that overflowed or underflowed are saturated or not. Enables or disables saturation for all subsequent ALU operations. 0 =Disable AR results remain unsaturated and return as is. 1 =Enable AR results saturated according to the state of the AV and AC status flags in ASTAT.

AVACAR register

00ALU output 01ALU output 100x7FFF

110x8000 Only the results written to the AR register are saturated. If results are written to the AF register, wraparound occurs, but the AV and AC flags reflect the saturated result.

MAC result mode. Determines the numeric format of multiplier operands. For all MAC operations, the multiplier adjusts the format of the result according to the selected mode. 0 =Fractional mode, 1.15 format. 1 =Integer mode, 16.0 format. For details, see “Data Format Options” on page 3-3.

Timer enable. Starts and stops the timer counter. 0 =Stops the timer count. 1 =Starts the timer count. For details on timer operation, see the ADSP-219x/2192 DSP Hardware Reference.

6SEC_DAG

or SD

Secondary DAG registers enable. Determines which set of DAG address registers is currently active. 0 =Primary registers. 1 =Secondary registers. For details, see “Secondary DAG Registers” on page 6-7 and

“Switching Contexts” on page 7-16.

ADSP-219x DSP Instruction Set Reference 1-9

System Status (SSTAT) Register

Refer to Table 1-7 for SSTAT register bit definitions.

Table 1-7. SSTAT Register Bit Definitions

Bit Name Description

0PCSTKEMPTY

or PCE

1PCSTKFULL

or PCF

2PCSTKLVL

or PCL

3Reserved

4LPSTKEMPTY

or LSE

5LPSTKFULL

or LSF

6 STSSTKEMPTY

or SSE

7STKOVERFLOW

or SOV

PC stack empty. 0 =PC stack contains at least one pushed address. 1 =PC stack is empty.

PC stack full. 0 =PC stack contains at least one empty location. 1 =PC stack is full.

PC stack level. 0 =PC stack contains between 3 and 28 pushed addresses. 1 =PC stack is at or above the high-water mark (28 pushed addresses), or it is at or below the low-water mark (3 pushed addresses).

Loop stack empty. 0 =Loop stack contains at least one pushed address. 1 =Loop stack is empty.

Loop stack full. 0 =Loop stack contains at least one empty location. 1 =Loop stack is full.

Status stack empty. 0 =Status stack contains at least one pushed status. 1 =Status stack is empty.

Stacks overflowed. 0 =Overflow/underflow has not occurred. 1 =At least one of the stacks (PC, loop, counter, status) has overflowed, or the PC or status stack has underflowed. This bit cleared only on reset. Loop stack underflow is not detected because it occurs only as a result of a POP LOOP operation.

1-10 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Condition Codes Summary

Refer to Table 1-8 for CCODE register bit definitions.

Table 1-8. Condition Codes Summary

Code Condition Description

0000 EQ Equal to zero (= 0).

0001 NE Not equal to zero (≠ 0).

0010 GT Greater than zero (> 0).

0011 LE Less than or equal to zero (≤ 0).

0100 LT Less than zero (< 0).

0101 GE Greater than or equal to zero (≥ 0).

0110 AV ALU overflow.

0111 NOT AV Not ALU overflow.

1000 AC ALU carry.

1001 NOT AC Not ALU carry.

1010 SWCOND SWCOND (based on CCODE register condition). (For

CCODE details, see Table 1-3 on page 1-5.)

1011 NOT SWCOND Not SWCOND (based on CCODE register condition). (For

CCODE details, see Table 1-3 on page 1-5.)

1100 MV MAC overflow.

1101 NOT MV Not MAC overflow.

1110 NOT CE Counter not expired.

1111 TRUE Always true.

ADSP-219x DSP Instruction Set Reference 1-11

Instruction Summary

The conventions for ADSP-219x instruction syntax descriptions appear in

Table 1-9. Other parts of the instruction syntax and opcode information

also appear in this section. The following sections provide summaries of the DSP’s instruction set:

• “ALU Instructions” on page 1-14

• “Multiplier Instructions” on page 1-15

• “Shifter Instructions” on page 1-16

• “Data Move Instructions” on page 1-16

• “Program Flow Instructions” on page 1-18

• “Multifunction Instructions” on page 1-19

For a list of instructions by types, see “Instruction Opcodes” on page 8-1.

Table 1-9. Instruction Set Notation

Notation Meaning

UPPERCASE Explicit syntax—assembler keyword (notation only; the assembler is

case-insensitive and lowercase is the preferred programming convention)

; Semicolon—instruction terminator

, Comma—separates multiple optional items within vertical bars

or separates parallel operations in multifunction instructions

| option1, option2 | Vertical bars—lists options separated with commas (choose one)

[optional] Square brackets—encloses optional part of instruction

Compute ALU, multiplier, shifter or multifunction operation

ALU, MAC, SHIFT ALU, multiplier, or shifter operation

Cond Status condition

1-12 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Table 1-9. Instruction Set Notation (Cont’d)

Notation Meaning

Term Loop termination condition

Reg Any register from register groups Reg0, Reg1, Reg2, or Reg3

Dreg Data register (register file) registers—subset of Reg0 registers

Ireg Any DAG I register

Mreg Any DAG M register

Lreg Any DAG L register

Ia I3-I0 (DAG1 index register)

Mb M3-M0 (DAG1 modify register)

Ic I7-I4 (DAG2 index register)

Md M7-M4 (DAG2 modify register)

<Datan> n-bit immediate data value

<Immn> n-bit immediate modify value

<Addrn> n-bit immediate address value

<Reladdrn> n-bit immediate PC-relative address value

Const constant value; For valid constant values, see Table 2-1 on page 2-3.

Ccarry bit

(DB) Delayed branch

ADSP-219x DSP Instruction Set Reference 1-13

Instruction Summary

ALU Instructions

Refer to Table 1-10 for a summary of ALU instructions.

Table 1-10. Summary of ALU Instructions

Instruction Type Details

|AR, AF| = Dreg1 + |Dreg2, Dreg2 + C, C |; 9, 9a on page 2-5

[IF Cond] |AR, AF| = Xop + |Yop, Yop + C, C, Const, Const + C|; 9 on page 2-5

|AR, AF| = Dreg1 − |Dreg2, Dreg2 + C −1, +C −1|; 9, 9a on page 2-9

[IF Cond] |AR, AF| = Xop − |Yop, Yop+C−1, +C− 1, Const, Const +C

−1|;

|AR, AF| = Dreg2 − |Dreg1, Dreg1 + C −1|; 9, 9a on page 2-13

[IF Cond] |AR, AF| = Yop − |Xop, Xop+C−1|; 9 on page 2-13

[IF Cond] |AR, AF| = − |Xop + C −1, Xop + Const, Xop + Const + C

−1|;

|AR, AF| = Dreg1 |AND, OR, XOR| Dreg2; 9, 9a on page 2-16

[IF Cond] |AR, AF| = |TSTBIT, SETBIT, CLRBIT, TGLBIT| n of Xop;

|AR, AF| = PASS |Dreg1, Dreg2, Const|; 9, 9a on page 2-22

|AR, AF| = PASS 0; 9, 9a on page 2-22

[IF Cond] |AR, AF| = PASS |Xop, Yop, Const|; 9 on page 2-22

|AR, AF| = NOT |Dreg|; 9, 9a on page 2-25

[IF Cond] |AR, AF| = NOT |Xop, Yop|; 9 on page 2-25

|AR, AF| = ABS Dreg; 9, 9a on page 2-28

[IF Cond] |AR, AF| = ABS Xop; 9 on page 2-28

|AR, AF| = Dreg +1; 9, 9a on page 2-31

9 on page 2-9

9 on page 2-13

9, 9a on page 2-19

[IF Cond] |AR, AF| = Yop +1; 9 on page 2-31

|AR, AF| = Dreg −1; 9, 9a on page 2-34

1-14 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Table 1-10. Summary of ALU Instructions (Cont’d)

Instruction Type Details

[IF Cond] |AR, AF| = Yop −1; 9 on page 2-34

DIVS Yop, Xop; 24 on page 2-37

DIVQ Xop; 23 on page 2-37

NONE = ALU (Xop, Yop); 8 on page 2-46

Multiplier Instructions

Refer to Table 1-11 for a summary of multiplier instructions.

Table 1-11. Summary of Multiplier Instructions

Instruction Type Details

|MR, SR| = Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; 9a on page 3-8

[IF Cond] |MR, SR| = Xop * Yop [(|RND, SS, SU, US, UU|)]; 9 on page 3-8

[IF Cond] |MR, SR| = Yop * Xop [(|RND, SS, SU, US, UU|)]; 9 on page 3-8

[IF Cond] |MR, SR| = 0; 9 on page 3-17

9 on page 3-11

9 on page 3-14

ADSP-219x DSP Instruction Set Reference 1-15

Instruction Summary

Table 1-11. Summary of Multiplier Instructions (Cont’d)

Instruction Type Details

[IF Cond] MR = MR [(RND)]; [IF Cond] SR = SR [(RND)];

SAT MR; SAT SR;

9 on page 3-19

25 on page 3-21

Shifter Instructions

Refer to Table 1-12 for a summary of shifter instructions.

Table 1-12. Summary of Shifter Instructions

Instruction Type Details

[IF Cond] SR = [SR OR] ASHIFT Dreg [(|HI, LO|)]; 16 on page 4-6

SR = [SR OR] ASHIFT BY <Imm8> [(|HI, LO|)]; 15 on page 4-8

[IF Cond] SR = [SR OR] LSHIFT Dreg [(|HI, LO|)]; 16 on page 4-10

SR = [SR OR] LSHIFT BY <Imm8> [(|HI, LO|)]; 15 on page 4-12

[IF Cond] SR = [SR OR] NORM Dreg [(|HI, LO|)]; 16 on page 4-14

[IF Cond] SE = EXP Dreg [(|HIX, HI, LO|)]; 16 on page 4-20

[IF Cond] SB = EXPADJ Dreg; 16 on page 4-23

Data Move Instructions

Refer to Table 1-13 for a summary of data move instructions.

Table 1-13. Summary of Data Move Instructions

Instruction Type Details

Reg = Reg; 17 on page 6-22

|DM(<Addr16>) = |Dreg, Ireg, Mreg|; 3 on page 6-24

1-16 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Table 1-13. Summary of Data Move Instructions (Cont’d)

Instruction Type Details

|Dreg, Ireg, Mreg| = |DM(<Addr16>)|; 3 on page 6-24

|<Dreg>, <Reg1>, <Reg2>| = <Data16>; 6, 7, 7A on page 6-27

Reg3 = <Data12>; 33 on page 6-27

|DM(Ia += Mb), DM(Ic += Md)| = Reg; 32 on page 6-30

Reg = |DM(Ia += Mb), DM(Ic += Md)|; 32 on page 6-30

|DM(Ia + Mb), DM(Ic + Md)| = Reg; 32 on page 6-34

Reg = |DM (Ia + Mb), DM (Ic + Md)|; 32 on page 6-34

|PM(Ia += Mb), PM(Ic += Md)| = Reg; 32 on page 6-38

Reg = |PM(Ia += Mb), PM(Ic += Md)|; 32 on page 6-38

|PM(Ia + Mb), PM(Ic + Md)| = Reg; 32 on page 6-43

Reg = |PM(Ia + Mb), PM(Ic + Md)|; 32 on page 6-43

DM(Ireg1 += Mreg1) = |Ireg2, Mreg2, Lreg2|, |Ireg2, Mreg2, Lreg2| = Ireg1;

Dreg = DM(Ireg += <Imm8>); 29 on page 6-51

DM(Ireg += <Imm8>) = Dreg; 29 on page 6-51

Dreg = DM(Ireg + <Imm8>); 29 on page 6-54

DM(Ireg + <Imm8>) = Dreg; 29 on page 6-54

|DM(Ia += Mb), DM (Ic += Md)| = <Data16>; 22 on page 6-57

|PM (Ia += Mb), PM (Ic += Md)| = <Data24>:24; 22A on page 6-59

IO(<Addr10>) = Dreg; 34 on page 6-62

Dreg = IO (<Addr10>); 34 on page 6-62

REG(<Addr8>) = Dreg; 35 on page 6-65

Dreg = REG(<Addr8>); 35 on page 6-65

|MODIFY (Ia += Mb), MODIFY (Ic += Md)|; 21 on page 6-68

MODIFY (Ireg += <Imm8>); 21A on page 6-70

32A on page 6-47

ADSP-219x DSP Instruction Set Reference 1-17

Instruction Summary

Program Flow Instructions

Refer to Table 1-14 for a summary of program flow instructions.

Table 1-14. Summary of Program Flow Instructions

Instruction Type Details

DO <Reladdr12> UNTIL [CE, FOREVER]; 11 on page 7-24

[IF Cond] JUMP <Reladdr13> [(DB)]; 10 on page 7-29

CALL <Reladdr16> [(DB)]; 10a on page 7-33

JUMP <Reladdr16> [(DB)]; 10a on page 7-37

[IF Cond] CALL <Addr24>; 36 on page 7-40

[IF Cond] JUMP <Addr24>; 36 on page 7-43

[IF Cond] CALL <Ireg> [(DB)]; 19 on page 7-46

[IF Cond] JUMP <Ireg> [(DB)]; 19 on page 7-50

[IF Cond] RTI [(DB)]; 20 on page 7-53

[IF Cond] RTS [(DB)]; 20 on page 7-57

PUSH |PC, LOOP, STS|; 26 on page 7-61

POP |PC, LOOP, STS|; 26 on page 7-61

FLUSH CACHE; 26 on page 7-67

SETINT <Imm4>; 37 on page 7-69

CLRINT <Imm4>; 37 on page 7-71

NOP; 30 on page 7-73

IDLE; 31 on page 7-74

ENA | TI, MM, AS, OL, BR, SR, BSR, INT | ; 18 on page 7-76

DIS | TI, MM, AS, OL, BR, SR, BSR, INT | ; 18 on page 7-76

1-18 ADSP-219x DSP Instruction Set Reference

Instruction Set Summary

Multifunction Instructions

Refer to Table 1-15 for a summary of multifunction instructions.

Table 1-15. Summary of Multifunction Instructions

Instruction Type Details

|<ALU>, <MAC>|, Xop = DM(Ia += Mb), Yop = PM(Ic += Md); 1 on page 5-4

Xop = DM(Ia += Mb), Yop = PM(Ic += Md); 1 on page 5-8

|<ALU>, <MAC>,<SHIFT> |, Dreg = DM(Ia += Mb)|; 4, 12 on page 5-11

|<ALU>, <MAC>, <SHIFT>|, DM(Ia += Mb) = Dreg; 4, 12 on page 5-15

|<ALU>, <MAC>, <SHIFT>|, Dreg = Dreg; 8, 14 on page 5-19

ADSP-219x DSP Instruction Set Reference 1-19

Instruction Summary

1-20 ADSP-219x DSP Instruction Set Reference

2 ALU INSTRUCTIONS

The instruction set provides ALU instructions for performing arithmetic and logical operations on 16- and 24-bit fixed-point data. This chapter includes the following sections:

• “ALU Instruction Conventions” on page 2-1

• “ALU Instruction Reference” on page 2-4

ALU Instruction Conventions

This chapter describes each of the arithmetic instructions and the following related topics:

• “Input Registers” on page 2-1

• “Output Registers” on page 2-2

• “Constants” on page 2-2

• “ALU Mode Control” on page 2-3

• “ALU Status Flags” on page 2-4

Input Registers

The unconditional single-function ALU instructions described in this chapter can use any of the DSP’s 16 data registers ( ands. The conditional single-function ALU instructions are restricted to

ADSP-219x DSP Instruction Set Reference 2-1

Dregs) as input oper-

the use of specific data registers for both the x and y input operands. When restrictions apply,

XOP refers to the x operand, and YOP refers to the

y operand.

Output Registers

ALU instructions use one of two output registers:

AF—ALU Feedback register. Results are directly available for the y

• input only in the next conditional ALU operation.

•

AR—ALU Result register. Results output to this register are imme-

diately available as the x-input only in the next conditional ALU, MAC, or shifter operation or as either x or y input into the next unconditional ALU, MAC, or shifter operation.

Constants

You can use constants in any of the following single-function ALU instructions:

• Add operations

• Subtract operations

• Bitwise logic operations

• PASS operation

Valid constants are those formed from powers of two that fall within the range of −

32768 (0x8000) and +32767 (0x7FFF). Table 2-1 lists the valid

constants.

2-2 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Table 2-1. Valid Constant Values

Positive (+) Negative (−)

Decimal Hexadecimal Decimal Hexadecimal

1 0x0001 2 0xFFFE

2 0x0002 3 0xFFFD

4 0x0004 5 0xFFFB

8 0x0008 9 0xFFF7

16 0x0010 17 0xFFEF

32 0x0020 33 0xFFDF

64 0x0040 65 0xFFBF

128 0x0080 129 0xFF7F

256 0x0100 257 0xFEFF

512 0x0200 513 0xFDFF

1024 0x0400 1025 0xFBFF

2048 0x0800 2049 0xF7FF

4096 0x1000 4097 0xEFFF

8192 0x2000 8193 0xDFFF

16384 0x4000 16385 0xBFFF

32767 0x7FFF 32768 0x8000

ALU Mode Control

The MSTAT register’s AV_LATCH bit and AR_SAT bit enable and disable two ALU modes: ALU overflow latch mode and ALU saturation mode. For more information on these modes, see the bit descriptions in Table 1-6 on

page 1-8.

ADSP-219x DSP Instruction Set Reference 2-3

ALU Status Flags

The ASTAT register’s AZ, AN, AV, AC, AS, and AQ bits record the status of ALU operations, indicating whether the result of the operation was equal to zero, negative, overflowed, carried, signed, or produced a quotient. For information on these modes, see the bit descriptions in Table 1-2 on

page 1-4.

ALU Instruction Reference

ALU instructions include:

• “Add/Add with Carry” on page 2-5

• “Subtract X−Y/Subtract X−Y with Borrow” on page 2-9

• “Subtract Y−X/Subtract Y−X with Borrow” on page 2-13

• “Bitwise Logic: AND, OR, XOR” on page 2-16

• “Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on

page 2-19

• “Clear: PASS” on page 2-22

• “Negate: NOT” on page 2-25

• “Absolute Value: ABS” on page 2-28

• “Increment” on page 2-31

• “Decrement” on page 2-34

• “Divide Primitives: DIVS and DIVQ” on page 2-37

• “Generate ALU Status Only: NONE” on page 2-46

2-4 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Add/Add with Carry

AR = DREG1 + DREG2 ;

AF DREG + C

[IF COND] AR = XOP + YOP ;

AF YOP + C

constant

constant + C

Function

Adds the input operands and stores the result in the specified result register.

If execution is based on a condition, the ALU performs the addition only if the condition evaluates true, and it performs a

NOP operation if the con-

dition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

DREG inputs:

ADSP-219x DSP Instruction Set Reference 2-5

Add/Add with Carry

For the conditional form of this instruction, the input operands are restricted. Valid

Xops Yops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 AY0, AY1, AF, 0

XOP and YOP registers are:

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV, AC AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction. This instruction uses binary addition to add the x and y operands and the carry bit, when specified.

The operands are stored in data registers, or, in the case of constants, supplied in the instruction. For the conditional form of this instruction, data registers are restricted.

2-6 ADSP-219x DSP Instruction Set Reference

ALU Instructions

You can substitute a constant for the y operand. For a list of valid constants, see Table 2-1 on page 2-3. To add a negative constant, use either of the following syntaxes:

AR = AR - 4097; AR = AR + 0xEFFF;

Carry Option

IF AC AR = AX0 + AY0 + C;

The above instruction executes if a carry occurs in the previous instruction. The AR register receives the result of the addition of the x and y operands and the carry-in bit from the previous instruction. Otherwise, it performs a NOP operation.

The form XOP + C is a special case of XOP + YOP + C in which YOP = 0.

You cannot add or subtract constants in multifunction instructions, and you are restricted to the use of particular data registers in multifunction and conditional instructions.

Examples

AR = AX0 + AX1; /* add Dregs */ AF = MY0 + MR1 + C; /* add Dregs and carry */ AR = SR0 + C; /* add Dreg and carry */ IF EQ AR = AX0 + AY0; /* add X and Y ops */ IF LT AF = AX1 + AF + C; /* add Xop, Yop, and carry */ IF AV AR = SR0 + C; /* add Xop and carry */ IF AC AR = AR + 1024; /* add Xop and constant */ IF SWCOND AR = MR0 + 1024 + C; /* add Xop, constant, */

/* and carry */

ADSP-219x DSP Instruction Set Reference 2-7

Add/Add with Carry

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-8 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Subtract X−Y/Subtract X−Y with Borrow

AR = DREG1 − DREG2 ;

AF DREG + C - 1

+ C - 1

[IF COND] AR = XOP − YOP ;

AF YOP + C - 1

+ C - 1

constant

constant + C - 1

Function

Subtracts the input operands and stores the result in the specified result register.

If execution is based on a condition, the ALU performs the subtraction only if the condition evaluates true, and it performs a

NOP operation if the

condition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

DREG inputs:

ADSP-219x DSP Instruction Set Reference 2-9

Subtract X−Y/Subtract X−Y with Borrow

For the conditional form of this instruction, the input operands are restricted. Valid

Xops Yops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 AY0, AY1, AF, 0

XOP and YOP registers are:

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV, AC AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction. This instruction uses binary addition to subtract the y operand from the x operand and then adds the carry bit minus one, when specified. The quantity C−1 effectively implements a borrow capability for multiprecision subtractions.

2-10 ADSP-219x DSP Instruction Set Reference

ALU Instructions

The operands are stored in data registers, or, in the case of constants, supplied in the instruction. For the conditional form of this instruction, data registers are restricted.

You can substitute a constant for the y operand. For a list of valid constants, see Table 2-1 on page 2-3. To subtract a negative constant, use either of the following syntaxes:

AR = AX0 - 4097; AR = AX0 + 0xEFFF;

Using the borrow option for example:

IF AC AR = AX0 - AY0 + C - 1;

The instruction executes if a carry occurs in the previous instruction. The

AR register receives the result of the subtraction of the x and y operands

and the carry bit from the previous instruction. Otherwise, it performs a

NOP operation.

The form XOP + C - 1 is a special case of XOP - YOP + C - 1 in which

YOP = 0.

You cannot add or subtract constants in multifunction instructions, and you are restricted to the use of particular data registers in multifunction and conditional instructions.

Examples

AR = AX0 - AX1; /* sub Dregs */ AF = MY0 - MR1 + C - 1; /* sub Dregs and carry */ AR = SR0 + C - 1; /* sub Dreg and carry */

IF EQ AR = AX0 - AY0; /* sub X and Y ops */ IF LT AF = AX1 - AF + C - 1; /* sub Xop, Yop, and carry */ IF AV AR = SR0 + C - 1; /* sub Xop and carry */

ADSP-219x DSP Instruction Set Reference 2-11

Subtract X−Y/Subtract X−Y with Borrow

IF AC AR = AR - 1024; /* sub Xop and constant */ IF SWCOND AR = MR0 - 1024 + C - 1; /* sub Xop, const, and carry */

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-12 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Subtract Y−X/Subtract Y−X with Borrow

AR = DREG2 - DREG1 ;

AF DREG1 + C -1

[IF COND] AR = YOP - XOP ;

AF XOP + C -1

Function

Subtracts the input operands and stores the result in the specified result register.

If execution is based on a condition, the ALU performs the subtraction only if the condition evaluates true, and it performs a

NOP operation if the

condition evaluates false.

Input

For the unconditional form of this instruction, you can use any of these data registers for the DREG inputs:

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

For the conditional form of this instruction, the input operands are restricted. Valid XOP and YOP registers are:

Xops Yops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 AY0, AY1, AF, 0

ADSP-219x DSP Instruction Set Reference 2-13

Subtract Y−X/Subtract Y−X with Borrow

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV, AC AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction. This instruction uses binary addition to subtract the x operand from the y operand and then adds the carry bit minus one, when specified. The quantity C - 1 effectively implements a borrow capability for multiprecision subtractions.

The operands are stored in data registers, or, in the case of constants, supplied in the instruction. For the conditional form of this instruction, data registers are restricted.

You can substitute a constant for the y operand. For a list of valid constants, see Table 2-1 on page 2-3. To subtract a negative constant, you use this syntax:

AR = -4097 - AR; AR = 0xEFFF - AR;

2-14 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Using the borrow option for example:

IF AC AR = AY0 - AX0 + C - 1;

The instruction executes if a carry occurs in the previous instruction. The

AR register receives the result of the subtraction of the y and x operands

and the carry bit from the previous instruction. Otherwise, it performs a

NOP operation.

The form -XOP + C - 1 is a special case of YOP - XOP + C - 1 in which

YOP = 0.

You cannot add or subtract constants in multifunction instructions, and you are restricted to the use of particular data registers in multifunction and conditional instructions.

Examples

AR = AY0 - AY1; /* sub Dregs */ AF = MR0 - SR1 + C -1; /* sub Dregs, add carry */ IF EQ AR = AY0 - AX1; /* sub Xop from Yop */ IF LT AF = AF - AX0 + C -1; /* sub Xop from Yop, add carry */

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

ADSP-219x DSP Instruction Set Reference 2-15

Bitwise Logic: AND, OR, XOR

AR = DREG1 AND DREG2;

AF OR

XOR

[IF COND] AR = XOP AND YOP ;

AF OR constant

XOR

Function

Performs the specified bitwise logical operation (logical

AND, inclusive OR,

or exclusive XOR) and stores the result in the specified result register.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a NOP operation if the condition evaluates false.

Only the conditional form of the bitwise operations accept a constant for the y operand.

Input

For the unconditional form of this instruction, you can use any of these data registers for the

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

DREG inputs:

For the conditional form of this instruction, the input operands are restricted. Valid XOP and YOP registers are:

2-16 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Xops Yops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 AY0, AY1, AF, 0

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV (cleared), AC (cleared) AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction.

The operands are stored in data registers, or, in the case of constants, supplied in the instruction. For the conditional form of this instruction, data registers are restricted.

You can substitute a constant for the y operand. For a list of valid constants, see Table 2-1 on page 2-3.

ADSP-219x DSP Instruction Set Reference 2-17

Bitwise Logic: AND, OR, XOR

Examples

AX0 = 0xAAAA; /* load 1010 1010 1010 1010 */ AX1 = 0x5555; /* load 0101 0101 0101 0101 */ AY0 = 0xAAAA; /* load 1010 1010 1010 1010 */ AY1 = 0x5555; /* load 0101 0101 0101 0101 */ AR = AX0 AND AX1; /* AR = 0000 0000 0000 0000 */ AF = AY0 OR AY1; /* AF = 1111 1111 1111 1111 */ AR = AX0 XOR AY0; /* AR = 0000 0000 0000 0000 */

IF EQ AR = AX0 AND AY0; /* AR = 1010 1010 1010 1010 */ IF LT AF = AX1 OR AY0; /* AF = 1111 1111 1111 1111 */ IF SWCOND AR = AX0 XOR 0x1000; /* AR = 1011 1010 1010 1010 */

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-18 ADSP-219x DSP Instruction Set Reference

Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT

[IF COND] AR = TSTBIT n OF XOP ;

AF SETBIT

CLRBIT

TGLBIT

Function

ALU Instructions

Performs the specified bit-manipulation operation on the n bit of the input operand and stores the result in the specified result register.

• TSTBIT Performs an AND operation with 1 in the selected bit.

• SETBIT Performs an OR operation with 1 in the selected bit.

• CLRBIT Performs an AND operation with 0 in the selected bit.

• TGLBIT Performs an XOR operation with 1 in the selected bit.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a NOP operation if the condition evaluates false.

Input

For this instruction, the x operand is restricted. Valid

Xops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1

XOP registers are:

ADSP-219x DSP Instruction Set Reference 2-19

Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV (cleared), AC (cleared) AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction. The operand is stored in an XOP data register and the instruction specifies the particular bit within it. You cannot perform any of the bit manipulation operations in multifunction instructions.

Examples

AX0 = 0xAAAA; /* load 1010 1010 1010 1010 */ AR = TSTBIT 0x5 OF AX0; /* AR = 0x0020 */ AF = SETBIT 0x4 OF AX0; /* AF = 0xAABA */ AF = CLRBIT 0xB OF AX0; /* AF = 0xA2AA */ AR = TGLBIT 0xF OF AX0; /* AR = 0x2AAA */

2-20 ADSP-219x DSP Instruction Set Reference

See Also

ALU Instructions

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

ADSP-219x DSP Instruction Set Reference 2-21

Clear: PASS

AR = PASS DREG ;

AF constant

AR = [PASS] 0 ;

[IF COND] AR = PASS XOP ;

AF YOP

constant

Function

Passes the source operand unmodified through the ALU unit and stores it in the specified result register. Unlike the move register instruction, this instruction affects the

ASTAT status flags.

The PASS 0 operation (the PASS keyword is optional) provides another way to clear the AR register.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a NOP operation if the condition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the DREG inputs:

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

2-22 ADSP-219x DSP Instruction Set Reference

ALU Instructions

For the conditional form of this instruction, the input operands are restricted. Valid

Xops Yops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 AY0, AY1, AF, 0

XOP and YOP registers are:

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV (cleared), AC (cleared) AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction.

The operands are stored in the data registers, or, in the case of constants, supplied in the instruction. For the conditional form of this instruction, data registers are restricted.

You can substitute a constant for the y operand. For a list of valid constants, see Table 2-1 on page 2-3.

ADSP-219x DSP Instruction Set Reference 2-23

Clear: PASS

Combine

PASS 0 with memory read and write operations in multifunction

instructions to clear the AR register; for example:

AR = PASS 0, AX0 = DM(I0, M0), AY0 = PM(I4, M4);

You cannot use DREG data registers or the PASS constant operation (other than -1, 0, or 1) in multifunction instructions.

Some forms of the PASS instruction result from the special case of the y input operand is 0, and other forms of the PASS instruction result from the special case of YOP is a constant.

Examples

AR = PASS SI; /* pass Dreg to AR */ AF = PASS 1024; /* pass constant to AF */

AR = PASS 0; /* pass 0 to AR */ AF = PASS 0; /* pass 0 to AF */

IF EQ AR = PASS AX1; /* pass Xop to AR */ IF LT AF = PASS AY0; /* pass Yop to AR */ IF AV AR = PASS 1024; /* pass constant to AR */

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-24 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Negate: NOT

AR = NOT DREG ;

[IF COND] AR = NOT XOP ;

AF YOP

Function

Performs a logical ones complement operation on the source operand and stores it in the specified result register.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a

NOP operation if the con-

dition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the DREG inputs:

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

For the conditional form of this instruction, the input operands are restricted. Valid

Xops Yops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 AY0, AY1, AF, 0

XOP and YOP registers are:

ADSP-219x DSP Instruction Set Reference 2-25

Negate: NOT

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV (cleared), AC (cleared) AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction.

The operands are stored in the data registers. For the conditional form of this instruction or in multifunction instructions, data registers are restricted.

Examples

AR = NOT SI; /* put neg SI in AR */ AF = NOT AY0; /* put neg AY0 in AF */

IF EQ AR = NOT AX0; /* put neg AX0 in AR */ IF LT AF = NOT AF; /* put neg AF in AR */

2-26 ADSP-219x DSP Instruction Set Reference

See Also

ALU Instructions

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

ADSP-219x DSP Instruction Set Reference 2-27

Absolute Value: ABS

AR = ABS DREG ;

[IF COND] AR = ABS XOP ;

Function

Performs a logical ones complement operation on the x input operand and stores it in the specified result register.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a

NOP operation if the con-

dition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the DREG inputs:

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

For this instruction, the x operand is restricted. Valid

Xops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1

XOP registers are:

2-28 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN (set if xop is 0x8000), AV (set if xop is 0x8000), AC (cleared), AS (set if xop is negative)

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

AQ, MV, SS, SV

Details

Omitting the condition forces unconditional execution of the instruction.

The operands are stored in the data registers. For the conditional form of this instruction or in multifunction instructions, data registers are restricted.

Examples

AR = ABS SI; /* put abs SI in AR */ AF = ABS AY0; /* put abs AY0 in AF */

IF EQ AR = ABS AX0; /* put abs AX0 in AR */ IF LT AF = ABS SR0; /* put abs SR0 in AF */

ADSP-219x DSP Instruction Set Reference 2-29

Absolute Value: ABS

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-30 ADSP-219x DSP Instruction Set Reference

Increment

AR = DREG + 1 ;

[IF COND] AR = YOP + 1 ;

Function

ALU Instructions

Increments the y input operand by adding

0x0001 to it and stores the value

in the specified result register.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a NOP operation if the condition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the DREG inputs:

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

For this instruction, the y operand is restricted. Valid

Yop s

AY0, AY1, AF, 0

IOP registers are:

ADSP-219x DSP Instruction Set Reference 2-31

Increment

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV, AC AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction.

The operands are stored in the data registers. For the conditional form of this instruction or in multifunction instructions, data registers are restricted.

Examples

AR = SI + 1; /* inc SI and place in AR */ AF = AX0 + 1; /* inc AX0 and place in AF */

IF EQ AR = AY0 + 1; /* inc AY0 and place in AR */ IF LT AF = AF + 1; /* inc AF and place in AF */

2-32 ADSP-219x DSP Instruction Set Reference

See Also

ALU Instructions

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

ADSP-219x DSP Instruction Set Reference 2-33

Decrement

AR = DREG - 1 ;

[IF COND] AR = YOP - 1 ;

Function

Decrements the y operand by subtracting

0x0001 from it and stores the

value in the specified result register.

If execution is based on a condition, the ALU performs the operation only if the condition evaluates true, and it performs a NOP operation if the condition evaluates false.

Input

For the unconditional form of this instruction, use any of these data registers for the DREG inputs:

AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI

For this instruction, the y operand is restricted. Valid

Yop s

AY0, AY1, AF, 0

IOP registers are:

2-34 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Output

AR ALU Result register. Results are directly available

for x input only in the next conditional ALU, MAC, or shifter operation or as either x or y input in the next unconditional ALU, MAC, or shifter operation.

AF ALU Feedback register. Results are directly avail-

able for the y input only in the next conditional ALU operation.

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AZ, AN, AV, AC AS, AQ, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Omitting the condition forces unconditional execution of the instruction.

The operands are stored in the data registers. For the conditional form of this instruction or in multifunction instructions, data registers are restricted.

Examples

AR = SI - 1; /* dec SI and place in AR */ AF = AX0 - 1; /* dec AX0 and place in AF */

IF EQ AR = AY0 - 1; /* dec AY0 and place in AR */ IF LT AF = AF - 1; /* dec AF and place in AF */

ADSP-219x DSP Instruction Set Reference 2-35

Decrement

See Also

• “Type 9: Compute” on page 8-23

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-36 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Divide Primitives: DIVS and DIVQ

DIVS YOP, XOP ;

DIVQ XOP ;

Function

The

DIVS primitive calculates the quotient’s sign bit. The DIVQ primitive

calculates the quotient one bit at a time.

Use both divide primitives to implement a YOP ÷ XOP operation on signed (twos complement) numbers. Use the DIVQ primitive alone to implement a

YOP ÷ XOP operation on unsigned (ones complement) numbers.

The divide primitives perform a single-precision divide on a 32-bit numerator by a 16-bit denominator to yield a 16-bit, truncated quotient. Single-precision divides executes in sixteen cycles. Higher precision divides require more cycles since you must execute the DIVQ primitive for each bit in the quotient.

The divide operation requires four data registers—one 16-bit data register to hold the 16-bit divisor, two 16-bit data registers to hold the 32-bit dividend, and one 16-bit data register to hold the resulting 16-bit quotient.

Input

Use signed (twos complement) or unsigned (ones complement) operands, but both operands must be the same number format. The resulting quotient has the same number format as its operands.

XOP Divisor. Both divide primitives take an x input

operand. Valid

Xops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1

XOP registers are:

ADSP-219x DSP Instruction Set Reference 2-37

Divide Primitives: DIVS and DIVQ

YOP Dividend. Only the DIVS primitive, which calcu-

lates the sign bit of the quotient, takes a y input operand. The y input operand must contain the upper 16 bits of the dividend. Valid YOP registers are:

Yop s

AY1, AF

For unsigned division (DIVQ only), AF must be used as the y input operand to hold the upper 16 bits of the dividend. Before issuing the DIVQ primitive, you must explicitly load the lower 16 bits of the dividend into either

AY0.

For signed division (DIVS and DIVQ), use AY1 or AF as they input operand to contain the upper 16 bits of the dividend. Before issuing either of the divide primitives, you must explicitly load the lower 16 bits of the dividend into AY0.

Output

AY0 ALU divide result register. At the end of the divide

operation, the AYO data register contains the quotient.

AF ALU Feedback register. At the end of the divide

operation,

AF contains the final remainder. This

value is incorrect. If you need to use it, correct it before doing so.

2-38 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

AQ AZ, AN, AV, AC, AS, MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

These instructions implement

DIVS and DIVQ. A single-precision divide, with a 32-bit numerator and a

YOP ÷ XOP. There are two divide primitives,

16-bit denominator, yielding a 16-bit quotient, executes in 16 cycles. Higher precision divides are also possible.

The division can be signed or unsigned, but both the numerator and denominator must be the same, signed or unsigned. Set up the divide by sorting the upper half of the numerator in any permissible YOP (AY1 or AF), the lower half of the numerator in AY0, and the denominator in any permissible XOP. The divide operation is then executed with the divide primitives, DIVS and DIVQ. Repeated execution of DIVQ implements a non-restoring conditional add-subtract division algorithm. At the conclusion of the divide operation, the quotient will be in AY0.

To implement a signed divide, first execute the DIVS instruction once, which computes the sign of the quotient. Then execute the DIVQ instruction as many times as there are bits remaining in the quotient (for example, for a signed, single-precision divide, execute

DIVS once and DIVQ

15 times).

To implement an unsigned divide, place the upper half of the numerator in

AF and then set the AQ bit to zero by manually clearing it in the Arith-

metic Status register (

ASTAT). This indicates that the sign of the quotient is

positive. Then execute the DIVQ instruction as many times as there are bits in the quotient (for example, for an unsigned single-precision divide, execute DIVQ 16 times).

ADSP-219x DSP Instruction Set Reference 2-39

Divide Primitives: DIVS and DIVQ

The quotient bit generated on each execution of

DIVS and DIVQ is the AQ

bit, which is written to the ASTAT register at the end of each cycle. The final remainder produced by this algorithm (left over in the AF register) is not valid and must be corrected if it is needed.

Examples

For example code and code walk-through, see “Division Applications” on

page 2-45.

See Also

• For more information, see “Division Theory” on page 2-40, “Divi-

sion Exceptions” on page 2-43, and “Division Applications” on page 2-45.

• “Type 23: Divide primitive, DIVQ” on page 8-43

• “Type 24: Divide primitive, DIVS” on page 8-44

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

Division Theory

The ADSP-219x DSP family’s instruction set contains two instructions for implementing a non-restoring divide algorithm. These instructions take as their operands’ twos complement or unsigned numbers, and in 16 cycles produce a truncated quotient of 16 bits. For most numbers and applications, these primitives produce the correct results. However, certain situations produce results that are off by one LSB. This section describes these situations, and presents alternatives for producing the correct results.

2-40 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Computing a 16-bit fixed-point quotient from two numbers is accomplished by 16 executions of the

DIVQ instruction for unsigned numbers.

Signed division uses the DIVS instruction first, followed by fifteen DIVQ instructions. Regardless of the division you perform, both input operands must be of the same type (signed or unsigned) and produce a result of the same type.

These two instructions are used to implement a conditional add/subtract, non-restoring division algorithm. As its name implies, the algorithm functions by adding or subtracting the divisor to/from the dividend. The decision as to which operation to perform is based on the previously generated quotient bit. Each add/subtract operation produces a new partial remainder, which is used in the next step.

The term “non-restoring” refers to the fact that the final remainder is not correct. With a restoring algorithm, it is possible, at any step, to take the partial quotient, multiply it by the divisor, and add the partial remainder to recreate the dividend. With this non-restoring algorithm, it is necessary to add two times the divisor to the partial remainder if the previously determined quotient bit is zero. It is easier to compute the remainder using the multiplier than in the ALU.

Signed Division

Signed division is accomplished by first storing the 16-bit divisor in an

XOP register (AX0, AX1, AR, MR2, MR1, MR0, SR1, or SR0). The 32-bit dividend

must be stored in two separate 16-bit registers. The lower 16-bits must be stored in

AY0, and the upper 16-bits can be in AY1 or AF.

The DIVS primitive is executed once, with the proper operands (such as

DIVS AY1, AX0) to compute the sign of the quotient. The sign bit of the

quotient is determined by XORing (exclusive ORing) the sign bits of each operand. The entire 32-bit dividend is shifted left one bit. The lower 15 bits of the dividend with the recently determined sign bit appended are stored in the lower word appended is stored in

AY0, and the lower 15 bits of the upper word, with the MSB of

AF.

ADSP-219x DSP Instruction Set Reference 2-41

Divide Primitives: DIVS and DIVQ

To complete the division, 15

DIVQ instructions are executed. Operation of

the DIVQ primitive is described below.

Unsigned Division

Computing an unsigned division is done like signed division, except the first instruction is not a DIVS, but another DIVQ. The upper word of the dividend must be stored in AF, and the AQ bit of the ASTAT register must be set to zero before the divide begins.

The DIVQ instruction uses the AQ bit of the ASTAT register to determine whether the dividend should be added to or subtracted from the partial remainder stored in AF and AY0. If AQ is zero, a subtraction occurs. A new value for AQ is determined by XORing the MSB of the divisor with the MSB of the dividend. The 32-bit dividend is shifted left one bit, and the inverted value of AQ is moved into the LSB.

Output Formats

As in multiplication, the format of a division result is based on the format of the input operands. The division logic is designed to work most efficiently with fully fractional numbers—those most commonly used in fixed-point DSP applications. A signed, fully fractional number uses one bit before the binary point as the sign, with 15 bits (or 31 bits in double precision) to the right, for magnitude.

If the dividend is in M.N format (M bits before the binary point, N bits after), and the divisor is in O.P format, the quotient’s format will be (M-O+1).(N-P-1). Dividing a 1.31 number by a 1.15 number produces a quotient whose format is (1-1+1).(31-15-1) or 1.15.

Before dividing two numbers, ensure that the format of the quotient will be valid. For example, if you attempt to divide a 32.0 number by a 1.15 number, the result attempts to be in (32-1+1).(0-15-1) or 32.-16 format. This cannot be represented in a 16-bit register.

2-42 ADSP-219x DSP Instruction Set Reference

ALU Instructions

In addition to proper output format, ensure that a divide overflow does not occur. Even when a division of two numbers produces a valid output format, it is possible that the number will overflow and be unable to fit within the constraints of the output. For example, to divide a 16.16 number by a 1.15 number, the output format would be (16-1+1).(16-15-1) or

16.0, which is valid. Assume you have 16384 (0x4000) as the dividend

and .25 (0x2000) as the divisor, the quotient is 65536, which does not fit in 16.0 format. This operation overflows, producing an erroneous result.

Check input operands before division to ensure that an overflow will not result. If the magnitude of the upper 16 bits of the dividend is larger than the magnitude of the divisor, an overflow will result.

Integer Division

One special case of division that deserves special mention is integer division. There may be some cases where you wish to divide two integers, and produce an integer result. It can be seen that an integer-integer division will produce an invalid output format of (32-16+1).(0-0-1), or 17.-1.

To generate an integer quotient, shift the dividend to the left one bit, placing it in 31.1 format. The output format for this division will be (31-16+1).(1-0-1), or 16.0. Ensure that no significant bits are lost during the left shift, or an invalid result will be generated.

Division Exceptions

Although the divide primitives for the ADSP-219x DSP family work correctly in most instances, there are two cases where an invalid or inaccurate result can be generated. The first case involves signed division by a negative number. If you attempt to use a negative number as the divisor, the quotient generated may be one LSB less than the correct result. The other case concerns unsigned division by a divisor greater than 0x7FFF. If the divisor in an unsigned division exceeds

0x7FFF, an invalid quotient will be

generated.

ADSP-219x DSP Instruction Set Reference 2-43

Divide Primitives: DIVS and DIVQ

Negative Divisor Error

The quotient produced by a divide with a negative divisor will generally be one LSB less than the correct result. The divide algorithm implemented on the ADSP-219x DSP family, which does not correctly compensate for the twos complement format of a negative number, causes this inaccuracy.

There is one case where this discrepancy does not occur. When the result of the division operation equals

0x8000, it is correctly represented, and is

not one LSB off.

There are several ways to correct for this error. Before changing any code, however, determine if a one-LSB error in your quotient is a significant problem. In some cases, the LSB is small enough to be insignificant.

If exact results are necessary, two solutions are possible. One is to avoid division by negative numbers. If your divisor is negative, take its absolute value and invert the sign of the quotient after division. This will produce the correct result.

Another technique is to check the result by multiplying the quotient by the divisor. Compare this value with the dividend; if they are off by more than the value of the divisor, increase the quotient by one.

Unsigned Division Error

Unsigned divisions can produce erroneous results if the divisor is greater

0x7FFF. Do not attempt to divide two unsigned numbers when the

than divisor has a one in the MSB. If you must perform such a division, shift both operands right one bit. This will maintain the correct orientation of operands.

Shifting both operands may result in a one LSB error in the quotient. This can be solved by multiplying the quotient by the original (not shifted) divisor. Subtract this value from the original dividend to calculate the error. If the error is greater than the divisor, add one to the quotient; if it is negative, subtract one from the quotient.

2-44 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Division Applications

Each of the problems mentioned in “Division Exceptions” on page 2-43 can be compensated in software. Listing 2-1 shows the program section divides. This code can be used to divide two signed or unsigned numbers to produce the correct quotient, or an error condition.

Listing 2-1. Division Routine Using DIVS and DIVQ

/* signed division algorithm with fix for negative division error

inputs:

AYy1 - 16 MSB of numerator AYy0 - 16 LSB of numerator AR - denominator

outputs:

AR - corrected quotient

intermediate (scratch) registers:

MR0, AF

signed_div:

MR0 = AR, AR = ABS AR; /* save copy of denominator, make it positive */ DIVS AY1, AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; AR = AY0, AF = PASS MR0; /* get sign of denominator */ IF LT AR = -AY0; /* if neg, invert output, place in ar */ RTS;

ADSP-219x DSP Instruction Set Reference 2-45

Generate ALU Status Only: NONE

NONE = <ALU Operation> ;

Function

Performs the indicated unconditional ALU operation but does not load the results into the AR or AF result registers. Generates ALU status flags only. Use this instruction to set ALU status without disturbing the contents of the AR and AF result registers.

Input

XOP Limits the registers for the x input operand. Valid

XOP registers are:

Xops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1

YOP Limits the registers for the x input operand. Valid

YOP registers are:

Yop s

AY0, AY1, AF, 0

Output

None. Generates ALU status flags only.

2-46 ADSP-219x DSP Instruction Set Reference

ALU Instructions

Status Flags

Affected Flags–set or cleared by the operation Unaffected Flags

Depending on ALU operation—AZ, AN, AV, AC, AS, AQ MV, SS, SV

For information on these status bits in the ASTAT register, see Table 1-2 on page 1-4.

Details

Use any unconditional ALU operation (except ALU operations that use constants) to generate ALU status flags.

The following ALU operations may not appear in the

• NONE = <XOP> + <constant>; For other add operations, see

“Add/Add with Carry” on page 2-5.

• NONE = <XOP> - <constant>;

-or-

NONE = -<XOP> + <constant>;

For other subtract operations, see “Subtract X−Y/Subtract X−Y

with Borrow” on page 2-9.

• NONE = PASS <constant>; with any constant other than -1, 0, or 1. For other clear operations, see “Clear: PASS” on page 2-22.

NONE = <XOP> <AND|OR|XOR> <constant>;

• For other logical operations, see “Bitwise Logic: AND, OR, XOR”

on page 2-16.

•

NONE with TSTBIT, SETBIT, CLRBIT, or TGLBIT.

NONE with the division primitives (DIVS or DIVQ).

•

Examples

NONE= syntax:

NONE = AX0 - AF; /* generate status from sub */ NONE = AX1 + AF; /* generate status from add */

ADSP-219x DSP Instruction Set Reference 2-47

Generate ALU Status Only: NONE

NONE = AF - AX1; /* generate status from sub */ NONE = PASS 0; /* generate status from pass */ NONE = AX1 OR AY0; /* generate status from or */

See Also

• “Type 8: Compute | Dreg1 «··· Dreg2” on page 8-22

• “Condition Code (CCODE) Register” on page 1-5

• “Mode Status (MSTAT) Register” on page 1-8

2-48 ADSP-219x DSP Instruction Set Reference

3 MAC INSTRUCTIONS

The instruction set provides MAC instructions that perform high-speed multiplication and multiply with cumulative add/subtract operations. MAC instructions include:

• “Multiply” on page 3-8

• “Multiply with Cumulative Add” on page 3-11

• “Multiply with Cumulative Subtract” on page 3-14

• “MAC Clear” on page 3-17

• “MAC Round/Transfer” on page 3-19

• “MAC Saturate” on page 3-21

• “Generate MAC Status Only: NONE” on page 3-24

This chapter describes the individual MAC instructions and these related topics:

• “MAC Input Registers” on page 3-2

• “MAC Output Registers” on page 3-2

• “Data Format Options” on page 3-3

• “Status Flags” on page 3-7

For details on condition codes and data input and output registers, see

“Condition Codes” on page 8-8 and “Core Register Codes” on page 8-11.

ADSP-219x DSP Instruction Set Reference 3-1

MAC Input Registers

Multiply Instruction Conventions

MAC Input Registers

All unconditional, single-function multiply and multiply with accumulative add or subtract instructions can use any and y input operands (for details, see “Core Register Codes” on

page 8-11). A program can use, for example, the ALU registers for the

multiplication or shifter operations, without issuing a separate data move instruction. This capability simplifies register allocation in algorithm coding. For example, using the DSP’s dual accumulator:

SR = SR + MX0 * MY0 (SS);

In multifunction operations, you can use only certain registers for the x-input operand (AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1) and the y-input operand (MY0, MY1, SR1, 0).

DREG data register for the x

All conditional MAC instructions must use the restricted XOP and YOP data registers for the x and y input operands, or an XOP register for the x-input and 0 for the y-input.

MAC Output Registers

All MAC instructions can use the multiplier MR output registers or the shifter Availability of the shifter SR output registers for multiplier operations provides dual-accumulator functionality.

When MR is the result register, results are directly available from MR0, MR1, or MR2 as the x-input operand into the very next multiplier operation.

MR = MR + AX0 * AX0 (SS);

3-2 ADSP-219x DSP Instruction Set Reference

SR output registers to receive the result of a multiplier operation.

MAC Instructions

When

SR is the result register, the 16-bit value in SR1 (bits 31:16 of the

40-bit result) is directly available as the y-input operand into the very next multiplier operation. This functionality is most useful when shifting the results of a multiply/accumulate operation since it decreases the number of required data moves.

SR = SR + AX0 * AY0 (SS); SR = SR + SR1 * AY0 (SS);

Data Format Options

Multiplier operations require the instruction to specify the data format of the input operands (signed or unsigned) or specify that the multiplier rounds (RND) the product of two signed operands.

All data format options, except the round (RND) option, which affects the product stored in the result register, specify the format of both input operands in x/y order. The data format options are:

• (RND) Round value in result register.

When overflow occurs, rounds the product to the most significant twenty-four bits—SR2/SR1 or MR2/MR1 represent the rounded 24-bit result. Otherwise, rounds bits 31:16 to16 bits—MR1 or SR1 contain the rounded 16-bit result.

With (

RND) selected, the multiplier considers both input operands

signed (twos complement). If the DSP is in fractional mode (MSTAT:M_MODE = 0), the multiplier rounds the result after adjusting for fractional data format. For details, see “Numeric Format

Modes” on page 3-6.

The DSP provides two rounding modes (biased and unbiased) to support a variety of application algorithms. For details, see

“Rounding Modes” on page 3-4.

ADSP-219x DSP Instruction Set Reference 3-3

Rounding Modes

•

(SS) Both input operands are signed numbers. Signed numbers

are in twos complement format.

Use this option to multiply two signed single-precision numbers or to multiply the upper portions of two signed multi-precision numbers.

• (SU) X-input operand is signed; y-input operand is unsigned.

Use this option to multiply a signed single-precision number by an unsigned single-precision number.

• (US) X-input operand is unsigned; y-input operand is signed.

Use this option to multiply an unsigned single-precision number by a signed single-precision number.

• (UU) Both input operands are unsigned numbers. Unsigned numbers are in ones complement format.

Use this option to multiply two unsigned single-precision numbers or to multiply the lower portions of two signed multi-precision numbers.

Rounding Modes

Rounding operates on the boundary between bits 15 and 16 of the 40-bit adder result. The multiplier directs the rounded output to the MR or the

SR result registers.

ADSP-219x DSPs provide two modes for rounding. The rounding algorithm is the same for both modes, but the final results can differ when the product equals the midway value (MR0 = 0x8000).

3-4 ADSP-219x DSP Instruction Set Reference

MAC Instructions

In both methods, the multiplier adds

1 to the value of bit 15 in the adder

chain. But when MR0 = 0x8000, the multiplier forces bit 16 in the result output to 0. Although applied on every rounding operation, the result of this algorithm is evident only when MR0 = 0x8000 in the adder chain.

The rounding mode determines the final result. The BIASRND bit in the

ICNTL register selects the mode. BIASRND = 0 selects unbiased rounding,

and BIASRND = 1 selects biased rounding.

• Unbiased rounding. Default mode. Rounds up only when MR1/SR1 set to an odd value; otherwise, rounds down. Yields a zero large-sample bias.

• Biased rounding. Always rounds up when MR0/SR0 is set to 0x8000.

Table 3-1 shows the results of rounding for both modes.

Table 3-1. MR result values

MR Value before RND Biased RND Result Unbiased RND Result

00-0000-8000 00-0001-0000 00-0000-0000

00-0001-8000 00-0002-0000 00-0002-0000

00-0000-8001 00-0001-0001 00-0001-0001

00-0001-8001 00-0002-0001 00-0002-0001

00-0000-7FFF 00-0000-FFFF 00-0000-FFFF

00-0001-7FFF 00-0001-FFFF 00-0001- FFFF

Unbiased rounding, which is preferred for most algorithms, yields a zero large-sample bias, assuming uniformly distributed values. Biased rounding supports efficient implementation of bit-specified algorithms, such as GSM speech compression routines.

ADSP-219x DSP Instruction Set Reference 3-5

Numeric Format Modes

The multiplier can operate on integers or fractions. The M_MODE bit in the

MSTAT register selects the mode. M_MODE = 0 selects fractional mode, and M_MODE = 1 selects integer mode.

The mode determines whether the multiplier shifts the product before adding or subtracting it from the result register.

Integer mode 16.0 integer format.

The LSB of the 32-bit product is aligned with the LSB of MR0/SR0.

In multiply and accumulate operations, the multiplier sign-extends the 32-bit product (8 bits) and then adds or subtracts that value from the result register to form the new 40-bit result.

The multiplier sets the MV/SV overflow bit when the result falls outside the range of −1 to +1−231.

Fractional mode 1.15 fraction format.

Fractions range from −1 to +1−215. The MSB of the product is aligned with the MSB of MR1/SR1.

MR1-0/SR1-0 hold a 32-bit fraction (1.31 format) in

the range of −

1 to +1−2

the eight sign-extended bits. In total, the

, and MR2/SR2 contains

MR/SR reg-

isters contains a fraction in 9.31 format.

In multiply and accumulate operations, the multiplier adjusts the format of the 32-bit product before adding or subtracting it from the result register. To do so, the multiplier sign-extends the product

3-6 ADSP-219x DSP Instruction Set Reference

MAC Instructions

(seven bits), shifts it one bit to the left, and then adds or subtracts that value from the result register to form the new 40-bit result.

The multiplier sets the

MV/SV overflow bit when the

result falls outside the range of −1 to +1−231.

Status Flags

Two status flags in the ASTAT register record the status of multiplier operations. MV = 1 records an overflow or underflow state when MR is the specified result register, and SV = 1 records an overflow or underflow state when SR is the specified result register.

ADSP-219x DSP Instruction Set Reference 3-7

Multiply

MR = DREG1 * DREG2 ( RND ) ;

SR SS

[IF COND] MR = XOP * YOP ( RND ) ;

SR XOP SS

Function

Multiplies the input operands and stores the result in the specified result register. Optionally, inputs may be signed or unsigned, and output may be rounded. For more information on input and output options, see “Data

Format Options” on page 3-3.

If execution is based on a condition, the multiplier performs the multiplication only if the condition evaluates true, and it performs a

NOP operation

if the condition evaluates false. Omitting the condition forces unconditional execution of the instruction.

3-8 ADSP-219x DSP Instruction Set Reference

Datasheet ADSP-219x Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

1 INSTRUCTION SET SUMMARY

Core Registers Summary

Arithmetic Status (ASTAT) Register

Condition Code (CCODE) Register

Interrupt Control (ICNTL) Register

Interrupt Mask (IMASK) Register and Interrupt Latch (IRPTL) Register

Mode Status (MSTAT) Register

System Status (SSTAT) Register

Condition Codes Summary

Instruction Summary

ALU Instructions

Multiplier Instructions

Shifter Instructions

Data Move Instructions

Program Flow Instructions

Multifunction Instructions

2 ALU INSTRUCTIONS

ALU Instruction Conventions

Input Registers

Output Registers

Constants

ALU Mode Control

ALU Status Flags

ALU Instruction Reference

Add/Add with Carry

Bitwise Logic: AND, OR, XOR

Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT

Clear: PASS

Negate: NOT

Absolute Value: ABS

Increment

Decrement

Divide Primitives: DIVS and DIVQ

Generate ALU Status Only: NONE

3 MAC INSTRUCTIONS

MAC Input Registers

Multiply Instruction Conventions

MAC Output Registers

Data Format Options

Rounding Modes

Numeric Format Modes

Status Flags

Multiply