Datasheet ADSP-2185L Datasheet (Analog Devices)

a

DSP Microcomputer

ADSP-2185L

FEATURES
PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS

Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition
Low Power Dissipation in Idle Mode

INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction

Set Extensions
80K Bytes of On-Chip RAM, Configured as 16K Words

Program Memory RAM and 16K Words

Data Memory RAM
Dual Purpose Program Memory for Instruction␣ and Data

Storage
Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP

SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory

Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System

Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

DATA ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ALU

MAC

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

SHIFTER

8K324 OVERLAY 1

()

8K324 OVERLAY 2

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

CONTROL
MEMORY

16K324 PM 16K316 DM

8K316 OVERLAY 1
8K316 OVERLAY 2

()

SERIAL PORTS

SPORT 1SPORT 0

PROGRAMMABLE

TIMER

I/O

AND

FLAGS

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA
PORT

HOST MODE

GENERAL NOTE

This data sheet represents specifications for the ADSP-2185L

3.3 V processor.

GENERAL DESCRIPTION

The ADSP-2185L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.

The ADSP-2185L combines the ADSP-2100 family base archi­tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.

The ADSP-2185L integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. Power-down circuitry is also pro­vided to meet the low power needs of battery operated portable
equipment. The ADSP-2185L is available in 100-lead LQFP
package.

In addition, the ADSP-2185L supports instructions which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
ALU constants, multiplication instruction (x squared), biased
rounding, result free ALU operations, I/O memory transfers and
global interrupt masking, for increased flexibility.

Fabricated in a high speed, low power, CMOS process, the
ADSP-2185L operates with a 19 ns instruction cycle time. Ev­ery instruction can execute in a single processor cycle.

ICE-Port is a trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

␣␣

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADSP-2185L

The ADSP-2185L’s flexible architecture and comprehensive in­struction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-2185L can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive or transmit data through the internal DMA port

• Receive or transmit data through the byte DMA port

• Decrement timer

DEVELOPMENT SYSTEM

The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup­ports the ADSP-2185L. The System Builder provides a high
level method for defining the architecture of systems under de­velopment. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruc­tion-level simulation with a reconfigurable user interface to dis­play different portions of the hardware environment.

A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2185L assembly source
code. The source code debugger allows programs to be cor­rected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator, and PROM Splitter soft­ware. The ADSP-218x EZ-KIT Lite is a low cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite includes the fol­lowing features:

• 33 MHz ADSP-218x

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort

• RS-232 Interface to PC with Windows 3.1 Control Software

• EZ-ICE

®

Connector for Emulator Control

®

Codec

• DSP Demo Programs

The ADSP-218x EZ-ICE Emulator aids in the hardware debug­ging of ADSP-2185L system. The emulator consists of hard­ware, host computer resident software and the target board
connector. The ADSP-2185L integrates on-chip emulation sup­port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family
EZ-ICEs. The ADSP-2185L device need not be removed from
the target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector, emu­lation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.

Additional Information

This data sheet provides a general overview of ADSP-2185L
functionality. For additional information on the architecture and
instruction set of the processor, see the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Develop­ment Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2185L instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro­cessor cycle. The ADSP-2185L assembly language uses an alge­braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.

POWER-DOWN

DATA ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ALU

MAC

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

SHIFTER

8K324 OVERLAY 1

()

8K324 OVERLAY 2

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

CONTROL

MEMORY

16K324 PM 16K316 DM

8K316 OVERLAY 1
8K316 OVERLAY 2

()

SERIAL PORTS

SPORT 1SPORT 0

PROGRAMMABLE

TIMER

I/O

AND

FLAGS

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA
PORT

HOST MODE

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the ADSP-2185L. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi­sions to support multiprecision computations. The ALU per­forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith­metic shifts, normalization, denormalization and derive expo­nent operations.

The shifter can be used to efficiently implement numeric for­mat control including multiword and block floating-point
representations.

The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.

–2–

REV. A

ADSP-2185L

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa­tional units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2185L executes looped code with zero over­head; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro­gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos­sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.

Efficient data transfer is achieved with the use of five internal
buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus
The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit­ting the ADSP-2185L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2185L can fetch an operand from program memory and
the next instruction in the same cycle.

In lieu of the address and data bus for external memory connec­tion, the ADSP-2185L may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program­mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2185L to con­tinue running from on-chip memory. Normal execution mode re­quires the processor to halt while buses are granted.

The ADSP-2185L can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two level­sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchro­nous serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.

Each port can generate an internal programmable serial clock or
accept an external serial clock.

The ADSP-2185L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro­cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2185L incorporates two complete synchronous se­rial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2185L
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual, Third Edition.

• SPORTs are bidirectional and have a separate, double­buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their
own serial clock internally.

• SPORTs have independent framing for the receive and trans­mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique in­terrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.

• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.

PIN DESCRIPTIONS

The ADSP-2185L is available in a 100-lead LQFP package. In
order to maintain maximum functionality and reduce package
size and pin count, some serial port, programmable flag, inter­rupt and external bus pins have dual, multiplexed functionality.
The external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concur­rently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics. See Common-Mode Pin
Descriptions.

REV. A

–3–

ADSP-2185L

Common-Mode Pin Descriptions

Pin # of Input/
Name(s) Pins Output Function

RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2/ 1 I Edge- or Level-Sensitive Interrupt

PF7 I/O Request.

IRQL1/ 1 I Level-Sensitive Interrupt Requests

1

Programmable I/O Pin

1

PF6 I/O Programmable I/O Pin
IRQL0/ 1 I Level-Sensitive Interrupt Requests

1

PF5 I/O Programmable I/O Pin
IRQE/ 1 I Edge-Sensitive Interrupt Requests

1

PF4 I/O Programmable I/O Pin
PF3 I/O Programmable I/O Pin During

Normal Operation

Mode C/ 1 I Mode Select Input—Checked

Only During RESET

PF2 I/O Programmable I/O Pin During

Normal Operation

Mode B/ 1 I Mode Select Input—Checked

Only During RESET

PF1 I/O Programmable I/O Pin During

Normal Operation

Mode A/ 1 I Mode Select Input—Checked

Only During RESET

PF0 I/O Programmable I/O Pin During

Normal Operation
CLKIN,
XTAL 2 I Clock or Quartz Crystal Input

CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
IRQ1:0 Edge- or Level-Sensitive Interrupts,
FI, FO Flag In, Flag Out

2

PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1,

FL2 3 O Output Flags
VDD and

GND 16 I Power and Ground
EZ-Port 9 I/O For Emulation Use

N

OTES

1

Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the
corresponding interrupts, then the DSP will vector to the appropriate interrupt vec­tor address when the pin is asserted, either by external devices, or set as a program­mable flag.

2

SPORT configuration determined by the DSP System Control Register. Software
configurable.

Memory Interface Pins

The ADSP-2185L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.

Full Memory Mode Pins (Mode C = 0)

Pin # of Input/
Name(s) Pins Output Function

A13:0 14 O Address Output Pins for Program,

Data, Byte and I/O Spaces

D23:0 24 I/O Data I/O Pins for Program, Data,

Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)

Host Mode Pins (Mode C = 1)

Pin # of Input/
Name(s) Pins Output Function

IAD15:0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O, Pro-

gram, Data or Byte access

D23:8 16 I/O Data I/O Pins for Program, Data

Byte and I/O spaces

IWR 1 I IDMA Write Enable
IRD 1 I IDMA Read Enable

IAL 1 I IDMA Address Latch Pin

IS 1 I IDMA Select
IACK 1 O IDMA Port Acknowledge

In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals

Terminating Unused Pin

The following table shows the recommendations for terminating
unused pins.

Pin Terminations

I/O Hi-Z*
Pin 3-State Reset Caused Unused
Name (Z) State By Configuration

XTAL I I Float
CLKOUT O O Float
A13:1 or O (Z) Hi-Z BR, EBR Float
IAD12:0 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
D23:8 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR I I High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD IIBR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)

–4–

REV. A

ADSP-2185L

Pin Terminations (Continued)

I/O Hi-Z*
Pin 3-State Reset Caused Unused
Name (Z) State By Configuration

D4 or I/O (Z) Hi-Z BR, EBR Float
IS I I High (Inactive)
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float

D2:0 or I/O (Z) Hi-Z BR, EBR Float
IAD15:13 I/O (Z) Hi-Z IS Float

PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR I I High (Inactive)
BG O (Z) O EE Float
BGH O O Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive)

or Program as Output,
Set to 1, Let Float

IRQL1/PF6 I/O (Z) I Input = High (Inactive)

or Program as Output,
Set to 1, Let Float

IRQL0/PF5 I/O (Z) I Input = High (Inactive)

or Program as Output,
Set to 1, Let Float

IRQE/PF4 I/O (Z) I Input = High (Inactive)

or Program as Output,
Set to 1, Let Float

SCLK0 I/O I Input = High or Low,

Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O O High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low,

Output = Float
RFS1/RQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/RQ1 I/O O High or Low
DT1/FO O O Float
EE I I

EBR II
EBG OO
ERESET II
EMS OO
EINT II

ECLK I I
ELIN I I
ELOUT O O

NOTES

**Hi-Z = High Impedance.

1. If the CLKOUT pin is not used, turn it OFF.

2. If the Interrupt/Programmable Flag pins are not used, there are two options:

Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.

3. All bidirectional pins have three-stated outputs. When the pins is configured

as an output, the output is Hi-Z (high impedance) when inactive.

4. CLKIN, RESET, and PF3:0 are not included in the table because these pins

must be used.

Interrupts

The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2185L provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP­2185L also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level­sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt Address (Hex)

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable) 002C

IRQ2 0004
IRQL1 0008
IRQL0 000C

SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority inter­rupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Indi­vidual interrupt requests are logically ANDed with the bits in
IMASK; the highest priority unmasked interrupt is then se­lected. The power-down interrupt is nonmaskable.

The ADSP-2185L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port auto­buffering or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest­ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks are
twelve levels deep to allow interrupt, loop and subroutine nest­ing. The following instructions allow global enable or disable
servicing of the interrupts (including power down), regardless of
the state of IMASK. Disabling the interrupts does not affect se­rial port autobuffering or DMA.

ENA INTS;
DIS INTS;

When the processor is reset, interrupt servicing is enabled.

REV. A

–5–

ADSP-2185L

LOW POWER OPERATION

The ADSP-2185L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external
power dissipation.

Power-Down

The ADSP-2185L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.

• Quick recovery from power-down. The processor begins ex­ecuting instructions in as few as 400 CLKIN cycles.

• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power­down without affecting the 400 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let­ting the oscillator run to allow 400 CLKIN cycle start up.

• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit Interrupt support allows
an unlimited number of instructions to be executed before op­tionally powering down. The power-down interrupt also can
be used as a non-maskable, edge-sensitive interrupt.

• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor
has entered power-down.

Idle

When the ADSP-2185L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then con­tinues with the instruction following the IDLE instruction. In
Idle Mode IDMA, BDMA and autobuffer cycle steals still occur.

Slow Idle

The IDLE instruction on the ADSP-2185L slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the nor­mal clock rate, is specified by a selectable divisor given in the

IDLE instruction. The format of the instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the proces­sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in­coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2185L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).

SYSTEM INTERFACE

Figure 2 shows a typical basic system configuration with the
ADSP-2185L, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode se­lectable). Programmable wait state generation allows the proces­sor to connect easily to slow peripheral devices. The ADSP-2185L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode al­lows access to the full external data bus, but limits addressing to
a single address bit (A0). Additional system peripherals can be
added in this mode through the use of external hardware to gen­erate and latch address signals.

Clock Signals

The ADSP-2185L can be clocked by either a crystal or a TTL­compatible clock signal.

The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera­tion. The only exception is while the processor is in the power­down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed in­formation on this power-down feature.

If an external clock is used, it should be a TTL-compatible sig­nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.

The ADSP-2185L uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally, in­structions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.

Because the ADSP-2185L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.

A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.

–6–

REV. A

ADSP-2185L

FULL MEMORY MODE

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

SYSTEM

INTERFACE

OR

mCONTROLLER

ADSP-2185L

CLKIN
XTAL

FL0-2
PF3

IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6

PF2 [MODE C]
PF1 [MODE B]
PF0 [MODE A]

SPORT1

SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FL0
DR1 OR FL1

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

HOST MEMORY MODE

ADSP-2185L

CLKIN
XTAL

FL0-2
PF3

IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6

PF2 [MODE C]
PF1 [MODE B]
PF0 [MODE A]

SPORT1

SCLK1
RFS1 OR IRQ0

TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

IDMA PORT

IRD/D6
IWR/D7
IS/D4

IAL/D5
IACK/D3

16

IAD15-0

ADDR13-0

DATA23-0

BMS

WR

IOMS

PMS
DMS
CMS

BGH
PWD

PWDACK

DATA23-8

BMS

WR

IOMS

PMS
DMS
CMS

BGH

PWD

PWDACK

14

A

13-0

D

A0-A21

23-16

D

24

RD

BR
BG

1

A0

16

RD

BR
BG

15-8

DATA

CS

A

10-0

ADDR

D

23-8

DATA

CS

A

13-0

ADDR

D

23-0

DATA

Figure 2. ADSP-2185L Basic System Configuration

CLKIN CLKOUT

XTAL

DSP

Figure 3. External Crystal Connections

BYTE

MEMORY

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

OVERLAY

MEMORY

TWO 8K

PM SEGMENTS

TWO 8K

DM SEGMENTS

Reset

The RESET signal initiates a master reset of the ADSP-2185L.
The RESET signal must be asserted during the power-up se­quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

DD

is ap­plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini­mum pulsewidth specification, t

RSP

.

The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.

MODES OF OPERATION

Table II summarizes the ADSP-2185L memory modes.

Setting Memory Mode

Memory Mode selection for the ADSP-2185L is made during
chip reset through the use of the Mode C pin. This pin is multi­plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.

Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power con­sumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of

100 kΩ, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the
pull-up or pull-down will hold the pin in a known state, and will
not switch.

Active configuration involves the use of a three-statable exter­nal driver connected to the Mode C pin. A driver’s output en­able should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allow­ing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three­stated buffer. This ensures that the pin will be held at a con­stant level and not oscillate should the three-state driver’s level
hover around the logic switching point.

REV. A

–7–

ADSP-2185L

Table II. Modes of Operations

1

MODE C2MODE B3MODE A4Booting Method

0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is configured
in Full Memory Mode.

5

0 1 0 No Automatic boot operations occur. Program execution starts at external memory location

0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does
not automatically use or wait for these operations.

1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is config­ured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)

1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off

until internal program memory location 0 is written to. Chip is configured in Host Mode.

NOTES

1

All mode pins are recognized while RESET is active (low).

2

When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.

3

When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.

4

When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.

5

Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

MEMORY ARCHITECTURE

The ADSP-2185L provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory, and I/O. Refer to the
following figures and tables for PM and DM memory alloca­tions in the ADSP-2185L.

Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.

Table III. PMOVLAY Bits

5

PMOVLAY Memory A13 A12:0

PROGRAM MEMORY

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. The
ADSP-2185L has 16K words of Program Memory RAM on
chip, and the capability of accessing up to two 8K external
memory overlay spaces using the external data bus.

0 Internal Not Applicable Not Applicable
1 External 0 13 LSBs of Address

Overlay 1 Between 0x2000

and 0x3FFF

2 External 1 13 LSBs of Address

Overlay 2 Between 0x2000

and 0x3FFF

INTERNAL
MEMORY

EXTERNAL
MEMORY

PM (MODE B = 0)

ALWAYS
ACCESSIBLE
AT ADDRESS

0x0000 – 0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN
PMOVLAY = 1

ACCESSIBLE WHEN
PMOVLAY = 2

PROGRAM MEMORY

MODE B = 0

8K INTERNAL
PMOVLAY = 0

OR

8K EXTERNAL

PMOVLAY = 1 OR 2

8K INTERNAL

PM (MODE B = 1)

RESERVED

INTERNAL

0x2000–
0x3FFF

0x2000–
0x3FFF

ADDRESS

0x3FFF

0x2000

0x1FFF

0x0000

2

0x2000–
0x3FFF

MEMORY

2

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN
PMOVLAY = 0

EXTERNAL
MEMORY

1

WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

2

SEE TABLE III FOR PMOVLAY BITS

PROGRAM MEMORY

MODE B = 1

8K INTERNAL

PMOVLAY = 0

8K EXTERNAL

Figure 4. Program Memory

–8–

1

RESERVED

0x2000–
0x3FFF

0x0000–
0x1FFF

ADDRESS

0x3FFF

0x2000
0x1FFF

0x0000

2

REV. A

ADSP-2185L

DATA MEMORY

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped
control registers. The ADSP-2185L has 16K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible lo­cations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus. All internal accesses complete in one cycle.
Accesses to external memory are timed using the wait states
specified by the DWAIT register.

INTERNAL
MEMORY

ACCESSIBLE WHEN

EXTERNAL
MEMORY

DATA MEMORY

ALWAYS
ACCESSIBLE
AT ADDRESS

0

x2000 – 0x3FFF

DMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 1

ACCESSIBLE WHEN
DMOVLAY = 2

x0000–

0
0

x1FFF

0

x0000–
x1FFF

0

0

x0000–
x1FFF

0

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

INTERNAL

8160

WORDS

8K INTERNAL
DMOVLAY = 0

OR

EXTERNAL 8K

DMOVLAY = 1, 2

ADDRESS

0x3FFF

x3FE0

0

x3FDF

0

0

x2000

0

x1FFF

x

0000

0

Figure 5. Data Memory Map

Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table IV.

Table IV. DMOVLAY Bits

DMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable
1 External 0 13 LSBs of Address

Overlay 1 Between 0x2000

and 0x3FFF

2 External 1 13 LSBs of Address

Overlay 2 Between 0x2000

and 0x3FFF

I/O Space (Full Memory Mode)

The ADSP-2185L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup­ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are un­defined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table V.

Table V. Wait States

Address Range Wait State Register

0x000–0x1FF IOWAIT0
0x200–0x3FF IOWAIT1
0x400–0x5FF IOWAIT2
0x600–0x7FF IOWAIT3

REV. A

–9–

Composite Memory Select (CMS)

The ADSP-2185L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.

Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as­serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory; use either DMS or PMS as the additional
address bit.

The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at re­set, except the BMS bit.

Boot Memory Select (BMS) Disable

The ADSP-2185L also lets you boot the processor from one ex­ternal memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for
BDMA transfers and BMS to select the second external memory
space for booting. The BMS signal can be disabled by setting
Bit 3 of the System Control Register to 1. The System Control
Register is illustrated in Figure 6.

15 14 13 12 11 10

00 000100 00 00011 1

SPORT0 ENABLE

1 = ENABLED, 0 = DISABLED

SPORT1 ENABLE

1 = ENABLED, 0 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

SYSTEM CONTROL REGISTER

9876543210

DM (033FFF)

PWAIT
PROGRAM MEMORY
WAIT STATES

BMS ENABLE
0 = ENABLED, 1 = DISABLED

Figure 6. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 7. The byte memory space consists of 256 pages,

each of which is 16K × 8.

1514131211109876543210

0000000000001000

BMPAGE

BDMA CONTROL

DM (033FE3)

BTYPE

BDIR
0 = LOAD FROM BM
1 = STORE TO BM

BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA

Figure 7. BDMA Control Register

The byte memory space on the ADSP-2185L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by
the BMWAIT register.

ADSP-2185L

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.

The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup­ported by the BDMA circuit.

Table VI. Data Formats

Internal

BTYPE Memory Space Word Size Alignment

00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the 14­bit BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT
register.

The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener­ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be
on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to ex­ternal memory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur­ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port; Host Memory
Mode)

The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2185L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory­mapped control registers. A typical IDMA transfer process is
described as follows:

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is busy.

3. Host uses IS and IAL control lines to latch the DMA starting

address (IDMAA) into the DSP’s IDMA control registers.
IAD[15] must be set = 0.

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-

nal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.

6. Host ends IDMA transfer.

The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2185L is operating at full speed.

The DSP memory address is latched and then automatically in­cremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.

Once the address is stored, data can either be read from or
written to the ADSP-2185L’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2185L that a particular
transaction is required. In either case, there is a one-processor­cycle delay for synchronization. The memory access consumes
one additional processor cycle.

Once an access has occurred, the latched address is automati­cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) di­rects the ADSP-2185L to write the address onto the IAD0–14
bus into the IDMA Control Register. The IDMAA register,
shown below, is memory mapped at address DM (0x3FE0).
Note that the latched address (IDMAA) cannot be read back by
the host. See Figure 8 for more information on IDMA and
DMA memory maps.

–10–

REV. A

ADSP-2185L

IDMA CONTROL (U = UNDEFINED AT RESET)

1514131211109876543210

UUUUUUUUUUUUUUU

IDMAA

IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM

Figure 8. IDMA Control/OVLAY Registers

Bootstrap Loading (Booting)

ADDRESS

DM(033FE0)

The ADSP-2185L has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting after reset is controlled by the Mode A, B and C
configuration bits.

When the mode pins specify BDMA booting, the ADSP-2185L
initiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the following de­faults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on­chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro­gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.

The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad­dresses to boot memory must be constructed externally to the
ADSP-2185L. The only memory address bit provided by the
processor is A0.

IDMA Port Booting

The ADSP-2185L can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
ADSP-2185L boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.

Bus Request and Bus Grant (Full Memory Mode)

The ADSP-2185L can relinquish control of the data and ad­dress buses to an external device. When the external device re­quires access to memory, it asserts the bus request (BR) signal.
If the ADSP-2185L is not performing an external memory ac­cess, it responds to the active BR input in the following proces­sor cycle by:

• three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,

• asserting the bus grant (BG) signal, and

• halting program execution.

If Go Mode is enabled, the ADSP-2185L will not halt program
execution until it encounters an instruction that requires an ex­ternal memory access.

If the ADSP-2185L is performing an external memory access
when the external device asserts the BR signal, it will not three­state the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single in­struction requires two external memory accesses, the bus will be
granted between the two accesses.

When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program ex­ecution from the point at which it stopped.

The bus request feature operates at all times, including when
the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2185L is ready to ex­ecute an instruction, but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2185L deasserts BG and BGH and executes the external
memory access.

Flag I/O Pins

The ADSP-2185L has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc­tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2185L’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2185L has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.

Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.

INSTRUCTION SET DESCRIPTION

The ADSP-2185L assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read­ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.

• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan­guage and is completely source and object code compatible
with other family members. Programs may need to be relo­cated to utilize on-chip memory and conform to the ADSP­2185L’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.

• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.

REV. A

–11–

ADSP-2185L

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2185L has on-chip emulation support and an ICE­Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete in­formation on ICE products.

Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes)
then it does not matter that the mode information is latched by
an emulator reset. However, if you are using the RESET pin as
a method of setting the value of the mode pins, then you have to
take into consideration the effects of an emulator reset.

One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 9. This circuit forces the value located on the Mode A
pin to logic high; regardless if it latched via the RESET or
ERESET pin.

ERESET
RESET

ADSP-2185L

1kV

MODE A/PFO

PROGRAMMABLE I/O

Figure 9. Mode A Pin/EZ-ICE Circuit

The ICE-Port interface consists of the following ADSP-2185L
pins:

EBR EBG ERESET
EMS EINT ECLK

ELIN ELOUT EE

These ADSP-2185L pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function ex­cept during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the ADSP-2185L
and the connector must be kept as short as possible, no longer
than three inches.

The following pins are also used by the EZ-ICE:

BR BG
RESET GND

The EZ-ICE uses the EE (emulator enable) signal to take con­trol of the ADSP-2185L in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated. These
signals do not need to be jumper-isolated in your system.

The EZ-ICE

connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in
Figure 10. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.

12

GND

EBG

EBR

KEY (NO PIN)

ELOUT

EE

RESET

34

56

78

3

9

11 12

13 14

TOP VIEW

BG

BR

EINT

ELIN

10

ECLK

EMS

ERESET

Figure 10. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca­tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1 × 0.1 inches. The pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.

Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emu­lator, it must comply with the memory interface guidelines listed
below.

PM, DM, BM, IOM and CM

Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE

may approach published worst case specification for
some memory access timing requirements and switching
characteristics.

Note: If your target does not meet the worst case chip specifica­tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De­pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require­ments within published limits.

–12–

REV. A

Restriction: All memory strobe signals on the ADSP-2185L
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your

target system must have 10 kΩ pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE

• EZ-ICE

board:

emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the RESET
signal.

• EZ-ICE

emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the BR signal.

• EZ-ICE

emulation ignores RESET and BR when single-

stepping.

• EZ-ICE

emulation ignores RESET and BR when in Emulator

Space (DSP halted).

• EZ-ICE

emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE

board’s DSP.

ADSP-2185L

REV. A

–13–

ADSP-2185L–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade B Grade

Parameter Min Max Min Max Unit

V
T

DD

AMB

Supply Voltage 3.0 3.6 3.0 3.6 V

Ambient Operating Temperature 0 +70 –40 +85 °C

ELECTRICAL CHARACTERISTICS

␣␣␣␣␣ ␣K/B Grades

Parameter Test Conditions Min Typ Max Unit

V

IH

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

I

OZH

I

OZL

I

DD

I

DD

C

I

C

O

NOTES

11

Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

12

Input only pins: RESET, BR, DR0, DR1, PWD.

13

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

14

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

15

Although specified for TTL outputs, all ADSP-2185L outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

16

Guaranteed but not tested.

17

Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

18

0 V on BR.

19

Idle refers to ADSP-2185L state of operation during execution of IDLE instruction. Deasserted pins are driven to either

10

VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

11

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

and type 6, and 20% are idle instructions.

12

Applies to LQFP package type.

13

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

Hi-Level Input Voltage
Hi-Level CLKIN Voltage @ VDD = max 2.2 V
Lo-Level Input Voltage
Hi-Level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

Three-State Leakage Current

Three-State Leakage Current

Supply Current (Idle)

Supply Current (Dynamic)

Input Pin Capacitance

Output Pin Capacitance

1, 2

1, 3

3

3

9

3, 6, 12

6, 7, 12, 13

1, 4, 5

1, 4, 5

11

@ VDD = max 2.0 V

@ VDD = min 0.8 V
@ VDD = min

= –0.5 mA 2.4 V

I

OH

@ V

= min

DD

I

= –100 µA

OH

6

VDD – 0.3 V
@ VDD = min
I

= 2 mA 0.4 V

OL

@ VDD = max

= V

V

IN

max 10 µA

DD

@ VDD = max
V

= 0 V 10 µA

7

7

IN

@ VDD = max
V

= V

DD

= 0 V

max

8

10

10

10

IN

@ VDD = max
V

IN

@ VDD = 3.3
t

= 19 ns

CK

= 25 ns

t

CK

t

= 30 ns

CK

8

10 µA
10 µA

8.6 mA
7mA
6mA

@ VDD = 3.3

= +25°C

T

AMB

t

= 19 ns

CK

t

= 25 ns

CK

= 30 ns

t

CK

10

10

10

49 mA
38 mA

31.5 mA
@ VIN = 2.5 V
f

= 1.0 MHz

IN

= +25°C8pF

T

AMB

@ VIN = 2.5 V
f

= 1.0 MHz

IN

T

= +25°C8pF

AMB

VDD or GND.

–14–

REV. A

ADSP-2185L

ABSOLUTE MAXIMUM RATINGS

*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

DD

+ 0.5 V

DD

Operating Temperature Range (Ambient) . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ESD SENSITIVITY

The ADSP-2185L is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.

The ADSP-2185L features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2185L has been classified
as a Class 1 device.

Proper ESD precautions are recommended to avoid performance degradation or loss of function­ality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.

TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to de-

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications
and the corresponding ADSP-2185L timing parameters, for

your convenience.
rive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch­ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir­cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

Memory ADSP-2185L Timing

Device Timing Parameter

Specification Parameter Definition

Address Setup to t

ASW

Write Start WR Low

Address Setup to t

AW

Write End WR Deasserted

Address Hold Time t

Data Setup Time t

Data Hold Time t

OE to Data Valid t

Address Access Time t

xMS = PMS, DMS, BMS, CMS, IOMS.

WRA

DW

DH

RDD

AA

FREQUENCY DEPENDENCY FOR TIMING

SPECIFICATIONS

tCK = Instruction Clock Period. t

t

is defined as 0.5t

CK

. The ADSP-2185L uses an input clock

CKI

CKI

with a frequency equal to half the instruction rate: a 26 MHz

input clock (which is equivalent to 38 ns) yields a 19 ns processor

cycle (equivalent to 52 MHz). t

0.5t

period should be substituted for all relevant timing

CKI

CK

parameters to obtain the specification value.

Example: t

= 0.5tCK – 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns

CKH

WARNING!

ESD SENSITIVE DEVICE

A0–A13, xMS Setup before

A0–A13, xMS Setup before

A0–A13, xMS Hold before
WR Low
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Vali

= External Clock Period.

values within the range of

d

REV. A

–15–

ADSP-2185L

OUTPUT DRIVE CURRENTS

Figure 11 shows typical I-V characteristics for the output drivers
of the ADSP-2185L. The curves represent the current drive
capability of the output drivers as a function of output voltage.

P

graph, see Figure 13.

(C × V

80

3.6V, –408C

60

40

20

0

–20

SOURCE CURRENT – mA

–40

–60

–80

04

0.5 1 1.5 2 2.5 3.5

3.3V, +258C

3.0V, +858C

3.0V, +858C

3.6V, –408C

SOURCE VOLTAGE – Volts

3.3V, +258C

Address, DMS 8 × 10 pF × 3.32 V × 33.3 MHz = 29.0 mW
Data Output, WR 9 × 10 pF × 3.32 V × 16.67 MHz = 16.3 mW
RD 1 × 10 pF × 3.32 V × 16.67 MHz = 1.8 mW
CLKOUT 1 × 10 pF × 3.32 V × 33.3 MHz = 3.6 mW

Total power dissipation for this example is P

3

Total Power Dissipation = P

= internal power dissipation from Power vs. Frequency

INT

2

× f ) is calculated for each output:

DD

Figure 11. Typical Drive Currents

Figure 12 shows the typical power-down supply current.

1000

100

10

CURRENT (LOG SCALE) – mA

1

08525 55

NOTES:

1. REFLECTS ADSP-2187L OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE

USER'S MANUAL

2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS.

FOR DETAILS.)

VDD = 3.6V

VDD = 3.3V

TEMPERATURE –

8C

ADSP-2100 FAMILY

POWER – mW

POWER – mW

Figure 12. Power-Down Supply Current (Typical)

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

DD

2

× f

POWER – mW

C × V

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no other
outputs are active, power dissipation is calculated as follows:

Assumptions:

•

External data memory is accessed every cycle with 50% of the
address pins switching.

•

External data memory writes occur every other cycle with
50% of the data pins switching.

•

Each address and data pin has a 10 pF total load at the pin.

•

The application operates at V

= 3.3 V and t

DD

= 34.7 ns.

CK

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-2187L STATE OF OPERATION DURING EXECUTION OF IDLE

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

3

TYPICAL POWER DISSIPATION AT 3.3V VDD AND 258C EXCEPT WHERE SPECIFIED.

4

IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

+ (C × V

INT

# of

Pins × C × V

2185L POWER, INTERNAL

250

200

150

128mW
104mW

100

84mW

50

0

45
40

35
30

25
20

15
10

45
40
35
30
25
20
15
10

5
0

5
8

33.33

33.3

25mW

20mW
16mW

33.33

20mW

FREQUENCY – MHz

POWER, IDLE

FREQUENCY – MHz

POWER, IDLE n MODES

10mW

9mW

FREQUENCY – MHz

DD

VDD = 3.6V

VDD = 3.3V

VDD = 3.0V

VDD = 3.6V

VDD = 3.3V

VDD = 3.0V

2

1, 2, 3

× f

INT

1, 3, 4

197mW

161mW

130mW

35mW

28mW

22mW

3

28mW

13mW

12mW

Figure 13. Power vs. Frequency

2

× f )

DD

50.7 mW

+ 50.7 mW.

52

52

IDLE (16)
IDLE (128)

52

OR GND.

DD

–16–

REV. A

CAPACITIVE LOADING

1.5V

INPUT

OR

OUTPUT

1.5V

Figures 14 and 15 show the capacitive loading characteristics of
the ADSP-2185L.

ADSP-2185L

18

T = +858C

16

V

= 3.0V

DD

14

12

10

8

6

RISE TIME (0.4V – 2.4V) – ns

4

2

0

0

CL – pF

20050 100 150

250

Figure 14. Typical Output Rise Time vs. Load Capacitance,
C

(at Maximum Ambient Operating Temperature)

L

10

9
8
7
6
5
4
3

OR HOLD – ns

2

VALID OUTPUT DELAY

1

NOMINAL

–1
–2
–3
–4

0 20040 80 120 160

20 60 100 140 180

CL – pF

Figure 16. Voltage Reference Levels for AC Measure­ments (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

) is the interval from when

ENA

a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, see
Figure 17. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.

REFERENCE

SIGNAL

t

(MEASURED)

OUTPUT

(MEASURED)

MEASURED

t

V

DIS

OH

V

OL

OUTPUT STOPS

DRIVING

(MEASURED) – 0.5V

V

OH

V

(MEASURED) +0.5V

OL

t

DECAY

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

t

ENA

V

OH

(MEASURED)

2.0V

1.0V

OUTPUT STARTS

DRIVING

V

OL

(MEASURED)

Figure 17. Output Enable/Disable

I

OL

TO

OUTPUT

PIN

50pF

+1.5V

Figure 15. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating

L

Temperature)

TEST CONDITIONS
Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out­put high or low voltage to a high impedance state, see Figure

16. The output disable time (t
t

MEASURED

and t

, see Figure 17. The time is the interval

DECAY

) is the difference between

DIS

from when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage. The decay time, t
dependent on the capacitive load, C

, and the current load, iL,

L

DECAY

, is

on the output pin. It can be approximated by the following
equation:

•0.5V

C

t

DECAY

L

=

i

L

from which

t

= t

DIS

MEASURED

– t

DECAY

is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.

REV. A

–17–

I

OH

Figure 18. Equivalent Device Loading for AC Measure­ments (Including All Fixtures)

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating is shown below:

T

= T

AMB

T

= Case Temperature in °C

CASE

CASE

– (PD × θ

CA

)

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

θ

CA

θ

= Thermal Resistance (Junction-to-Ambient)

JA

= Thermal Resistance (Junction-to-Case)

θ

JC

Package θ

JA

θ

JC

θ

CA

LQFP 50°C/W 2°C/W 48°C/W

ADSP-2185L

TIMING PARAMETERS

(See page 15, Frequency Depending for Timing Specifications, for timing definitions.)

Parameter Min Max Unit

Clock Signals and Reset

Timing Requirements:
t

CKI

t

CKIL

t

CKIH

CLKIN External Clock Period 38 100 ns
CLKIN Width Low 15 ns
CLKIN Width High 15 ns

Switching Characteristics:
t

CKL

t

CKH

t

CKOH

CLKOUT Width Low 0.5t
CLKOUT Width High 0.5t
CLKIN High to CLKOUT High 0 20 ns

– 7 ns

CK

– 7 ns

CK

Control Signals

Timing Requirement:
t

RSP

t

MS

t

MH

NOTE

1

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).

RESET Width Low 5t
Mode Setup before RESET High 2 ns
Mode Hold after RESET High 5 ns

t

CKI

CK

1

t

CKIH

ns

CLKIN

CLKOUT

PF(3:0)

RESET

t

CKIL

t

CKL

*

t

MS

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

t

MH

Figure 19. Clock Signals

t

CKOH

t

CKH

–18–

REV. A

ADSP-2185L

Parameter Min Max Unit

Interrupts and Flag

Timing Requirements:
t
t

IFS

IFH

IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High

Switching Characteristics:

t

FOH

t

FOD

NOTES

1

If IRQx and FI inputs meet t
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

2

Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

4

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5

Flag outputs = PFx, FL0, FL1, FL2, Flag_out.

Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low

and t

IFS

setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

IFH

CLKOUT

FLAG

OUTPUTS

IRQx

FI

PFx

1, 2, 3, 4

1, 2, 3, 4

5

5

t

FOD

t

FOH

0.25tCK + 15 ns

0.25t

CK

0.25tCK – 7 ns

0.5t

+ 6 ns

CK

t

IFH

t

IFS

ns

Figure 20. Interrupts and Flags

REV. A

–19–

ADSP-2185L

Parameter Min Max Unit

Bus Request–Bus Grant

Timing Requirements:
t

BH

t

BS

BR Hold after CLKOUT High
BR Setup before CLKOUT Low

Switching Characteristics:
t

SD

t

SDB

t

SE

t

SEC

t

SDBH

t

SEH

NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.

1

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.

2

BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT High to xMS, RD, WR Disable 0.25tCK + 10 ns

xMS, RD, WR Disable to BG Low 0 ns
BG High to xMS, RD, WR Enable 0 ns
xMS, RD, WR Enable to CLKOUT High 0.25tCK – 7 ns
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable

CLKOUT

1

1

2

2

t

BH

0.25tCK + 2 ns

0.25tCK + 17 ns

0ns
0ns

BR

CLKOUT

PMS, DMS

BMS, RD

WR

BG

BGH

t

BS

t

SD

t

SDB

t

SDBH

Figure 21. Bus Request–Bus Grant

t

SEC

t

SE

t

SEH

–20–

REV. A

ADSP-2185L

Parameter Min Max Unit

Memory Read

Timing Requirements:
t

RDD

t

AA

t

RDH

Switching Characteristics:
t

RP

t

CRD

t

ASR

t

RDA

t

RWR

w = wait states x t

xMS = PMS, DMS, CMS, IOMS, BMS.

RD Low to Data Valid 0.5tCK – 9 + w ns

A0–A13, xMS to Data Valid 0.75tCK – 12.5 + w ns
Data Hold from RD High 1 ns

RD Pulsewidth 0.5tCK – 5 + w ns
CLKOUT High to RD Low 0.25tCK – 5 0.25tCK + 7 ns
A0–A13, xMS Setup before RD Low 0.25tCK – 6 ns
A0–A13, xMS Hold after RD Deasserted 0.25tCK – 3 ns
RD High to RD or WR Low 0.5t

CK

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

RD

D

WR

t

t

CRD

ASR

t

AA

t

t

RDD

– 5 ns

CK

t

RDA

RP

t

RDH

t

RWR

Figure 22. Memory Read

REV. A

–21–

ADSP-2185L

Parameter Min Max Unit

Memory Write

Switching Characteristics:
t

DW

t

DH

t

WP

t

WDE

t

ASW

t

DDR

t

CWR

t

AW

t

WRA

t

WWR

w = wait states x tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.

Data Setup before WR High 0.5t
Data Hold after WR High 0.25t

WR Pulsewidth 0.5tCK – 5 + w ns
WR Low to Data Enabled 0 ns

A0–A13, xMS Setup before WR Low 0.25t
Data Disable before WR or RD Low 0.25tCK – 7 ns
CLKOUT High to WR Low 0.25t
A0–A13, xMS, Setup before Deasserted 0.75t
A0–A13, xMS Hold after WR Deasserted 0.25t
WR High to RD or WR Low 0.5tCK – 5 ns

CLKOUT

A0–A13

DMS, PMS,
BMS, CMS,

IOMS

WR

RD

t

ASW

t

CWR

D

t

WDE

t

WP

t

AW

– 7 + w ns

CK

– 2 ns

CK

– 6 ns

CK

– 5 0.25 tCK + 7 ns

CK

– 9 + w ns

CK

– 3 ns

CK

t

WRA

t

WWR

t

DH

t

DW

t

DDR

Figure 23. Memory Write

–22–

REV. A

ADSP-2185L

Parameter Min Max Unit

Serial Ports

Timing Requirements:
t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics:
t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

TDE

t

TDV

t

SCDD

t

RDV

SCLK Period 50 ns
DR/TFS/RFS Setup before SCLK Low 4 ns
DR/TFS/RFS Hold after SCLK Low 8 ns
SCLK

CLKOUT High to SCLK

Width 15 ns

IN

OUT

0.25t

CK

0.25t

+ 10 ns

CK

SCLK High to DT Enable 0 ns
SCLK High to DT Valid 15 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 15 ns

OUT

DT Hold after SCLK High 0 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 14 ns
SCLK High to DT Disable 15 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 15 ns

CLKOUT

SCLK

DR

TFS

RFS

RFS

OUT

TFS

OUT

DT

TFS

OUT

ALTERNATE

FRAME MODE

RFS

MULTICHANNEL MODE,

MULTICHANNEL MODE,

OUT

FRAME DELAY 0

(MFD = 0)

TFS

ALTERNATE

FRAME MODE

RFS

FRAME DELAY 0

(MFD = 0)

t

CC

IN
IN

IN

IN

t

SCDE

t

t

RH

t

t

TDE

t

TDE

RD

SCDV

t

TDV

t

RDV

t

TDV

t

RDV

t

t

CC

SCS

t

SCK

t

SCP

t

SCH

t

t

SCDH

SCDD

t

SCP

REV. A

Figure 24. Serial Ports

–23–

ADSP-2185L

Parameter Min Max Unit

IDMA Address Latch

Timing Requirements:
t

IALP

t

IASU

t

IAH

t

IKA

t

IALS

t

IALD

NOTES

1

Start of Address Latch = IS Low and IAL High.

2

End of Address Latch = IS High or IAL Low.

3

Start of Write or Read = IS Low and IWR Low or IRD Low.

Duration of Address Latch
IAD15–0 Address Setup before Address Latch End
IAD15–0 Address Hold after Address Latch End
IACK Low before Start of Address Latch
Start of Write or Read after Address Latch End
Address Latch Start after Address Latch End

IACK

IAL

IS

IAD15–0

RD OR WR

1, 2

2

2

2, 3

2, 3

1, 2

t

IKA

t

IALP

t

IASU

t

IALD

t

IAH

Figure 25. IDMA Address Latch

10 ns
5ns
3ns
0ns
3ns
2ns

t

IALP

t

IASU

t

IAH

t

IALS

–24–

REV. A

ADSP-2185L

Parameter Min Max Unit

IDMA Write, Short Write Cycle

Timing Requirements:
t

IKW

t

IWP

t

IDSU

t

IDH

IACK Low before Start of Write
Duration of Write

1, 2

IAD15–0 Data Setup before End of Write
IAD15–0 Data Hold after End of Write

Switching Characteristic:
t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

End of Write = IS High or IWR High.

3

If Write Pulse ends before IACK Low, use specifications t

4

If Write Pulse ends after IACK Low, use specifications t

Start of Write to IACK High 4 15 ns

IACK

IS

IWR

IAD15–0

IDSU

IKSU

1

2, 3, 4

2, 3, 4

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

t

IWP

t

IDSU

DATA

0ns
15 ns
5ns
2ns

t

IDH

Figure 26. IDMA Write, Short Write Cycle

REV. A

–25–

ADSP-2185L

Parameter Min Max Unit

IDMA Write, Long Write Cycle

Timing Requirements:
t

IKW

t

IKSU

t

IKH

IACK Low before Start of Write
IAD15–0 Data Setup before IACK Low
IAD15–0 Data Hold after IACK Low

Switching Characteristics:
t

IKLW

t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

If Write Pulse ends before IACK Low, use specifications t

3

If Write Pulse ends after IACK Low, use specifications t

4

This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual , Third Edition.

Start of Write to IACK Low
Start of Write to IACK High 4 15 ns

IACK

IS

IWR

IAD15–0

4

IKSU

IDSU

1

2, 3, 4

2, 3, 4

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

t

0ns

0.5tCK + 10 ns
2ns

IKSU

t

IKLW

DATA

1.5t

CK

t

IKH

ns

Figure 27. IDMA Write, Long Write Cycle

–26–

REV. A

ADSP-2185L

Parameter Min Max Unit

IDMA Read, Long Read Cycle

Timing Requirements:
t
t

IKR

IRK

IACK Low before Start of Read
End of Read after IACK Low

Switching Characteristics:
t

IKHR

t

IKDS

t

IKDH

t

IKDD

t

IRDE

t

IRDV

t

IRDH1

t

IRDH2

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

3

DM read or first half of PM read.

4

Second half of PM read.

IACK High after Start of Read
IAD15–0 Data Setup before IACK Low 0.5tCK – 7 ns
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)32tCK – 5 ns
IAD15–0 Previous Data Hold after Start of Read (PM2)

IACK

IRD

1

2

1

2

2

4

t

t

IKR

IS

t

IRDE

IKHR

t

IKDS

0ns
2ns

415ns

0ns

10 ns

tCK – 5 ns

t

IRK

t

IKDH

IAD15–0

t

IRDV

PREVIOUS

DATA

t

IRDH

READ
DATA

Figure 28. IDMA Read, Long Read Cycle

t

IKDD

REV. A

–27–

ADSP-2185L

Parameter Min Max Unit

IDMA Read, Short Read Cycle

Timing Requirements:
t
t

IKR

IRP

IACK Low before Start of Read
Duration of Read 15 ns

Switching Characteristics:
t

IKHR

t

IKDH

t

IKDD

t

IRDE

t

IRDV

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

IACK High after Start of Read
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns

IACK

IRD

1

1

2

2

t

IKR

t

IS

IKHR

t

IRP

0ns

415ns
0ns

10 ns

t

IRDE

IRDV

PREVIOUS

DATA

IAD15–0

t

Figure 29. IDMA Read, Short Read Cycle

t

IKDH

t

IKDD

–28–

REV. A

A4/IAD3
A5/IAD4

GND

A6/IAD5
A7/IAD6

A8/IAD7
A9/IAD8

A10/IAD9

A11/IAD10
A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

VDD

CLKOUT

GND
VDD

WR

RD
BMS
DMS

PMS

IOMS

CMS

ADSP-2185L

100-Lead LQFP Package Pinout

D16

D17

D18

A1/IAD0

A0

A2/IAD1

A3/IAD2

9998979695

100

1

PIN 1

2

IDENTIFIER

3
4

5
6

7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

BGH

PWDACK

PWD

PF1 [MODE B]

PF0 [MODE A]

GND

9493929190

ADSP-2185L

(Not to Scale)

VDD

PF2 [MODE C]

PF3

8988878685

TOP VIEW

FL0

FL1

D22

D23

FL2

8483828180

D21

D20

GND

D19
797877

76

75

D15

74

D14

73

D13

72

D12

71

GND

70

D11

69

D10

68

D9

67

VDD

66

GND

65

D8
D7/IWR

64

D6/IRD

63

D5/IAL

62

D4/IS

61
60

GND

59

VDD
D3/IACK

58

D2/IAD15

57
56

D1/IAD14

55

D0/IAD13

BG

54

EBG

53

BR

52

EBR

51

26

IRQE+PF4

27

IRQL0+PF5

28

GND

29

IRQL1+PF6

30

IRQ2+PF7

31

DT0

32

TFS0

33

RFS0

34

DR0

35

36

VDD

SCLK0

37

DT1

38

TFS1

39

RFS1

40

DR1

41

GND

43

42

SCLK1

ERESET

45

44

EMS

RESET

50

48

46

47

49

EE

ECLK

ELIN

ELOUT

EINT

REV. A

–29–

ADSP-2185L

The ADSP-2185L package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [␣ ] are state bits latched from the value of the pin at the deassertion of RESET.

LQFP Pin Configurations

LQFP Pin LQFP Pin LQFP Pin LQFP Pin
Number Name Number Name Number Name Number Name

1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16
2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17
3GND28GND53EBG 78 D18
4 A6/IAD5 29 IRQL1 + PF6 54 BG 79 D19
5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND
6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22
9 A11/IAD10 34 DR0 59 VDD 84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 VDD 61 D4/IS 86 FL1
12 GND 37 DT1 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1 63 D6/IRD 88 PF3
14 XTAL 39 RFS1 64 D7/IWR 89 PF2 [Mode C]
15 VDD 40 DR1 65 D8 90 VDD
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 VDD 92 GND
18 VDD 43 ERESET 68 D9 93 PF1 [Mode B]
19 WR 44 RESET 69 D10 94 PF0 [Mode A]
20 RD 45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS 47 ECLK 72 D12 97 A0
23 PMS 48 ELOUT 73 D13 98 A1/IAD0
24 IOMS 49 ELIN 74 D14 99 A2/IAD1
25 CMS 50 EINT 75 D15 100 A3/IAD2

–30–

REV. A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

ADSP-2185L

0.640 (16.25)

0.630 (16.00)

0.620 (15.75)

0.553 (14.05)

0.551 (14.00)

0.549 (13.95)

0.063 (1.60) MAX

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)
SEATING

PLANE

0.004

(0.102)

MAX LEAD

COPLANARITY

0° – 7°

NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)

0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

0.007 (0.177)

0.005 (0.127) TYP

0.003 (0.077)

100 76

12°

1

TYP

25

6° ± 4°

26

0.472 (12.00) BSC

TOP VIEW

(PINS DOWN)

0.020 (0.50)
BSC

LEAD PITCH

TYP SQ

TYP SQ

0.011 (0.27)

0.009 (0.22) TYP

0.007 (0.17)

LEAD WIDTH

C3189a–3–11/98

75

51

50

ORDERING GUIDE

Ambient Instruction
Temperature Rate Package Package

Part Number Range (MHz) Description Option*

ADSP-2185LKST-115 0°C to +70°C 28.8 100-Lead LQFP ST-100
ADSP-2185LBST-115 –40°C to +85°C 28.8 100-Lead LQFP ST-100
ADSP-2185LKST-133 0°C to +70°C 33.3 100-Lead LQFP ST-100
ADSP-2185LBST-133 –40°C to +85°C 33.3 100-Lead LQFP ST-100
ADSP-2185LBST-160 –40°C to +85°C 40 100-Lead LQFP ST-100
ADSP-2185LKST-210 0°C to +70°C 52 100-Lead LQFP ST-100
ADSP-2185LBST-210 –40°C to +85°C 52 100-Lead LQFP ST-100

*ST = Plastic Thin Quad Flatpack (LQFP).

PRINTED IN U.S.A.

REV. A

–31–