Datasheet ADSP-2183 Datasheet (Analog Devices)

a

DSP Microcomputer

ADSP-2183

FEATURES
PERFORMANCE
19 ns Instruction Cycle Time from 26.32 MHz Crystal

@ 3.3 Volts
52 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 300 Cycle Recovery from

Power-Down Condition
Low Power Dissipation in Idle Mode

INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction

Set Extensions
80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Memory RAM

16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction

and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides

Zero Overhead Looping

Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead LQFP, 144-Ball Mini-BGA

SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables

and Program Overlays
8-Bit DMA to Byte Memory for Transparent

Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals
Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System

Signaling
ICE-Port™ Emulator Interface Supports Debugging

in Final Systems

ICE-Port is a trademark of Analog Devices, Inc.

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

DATA ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTERMACALU

POWERDOWN

CONTROL

MEMORY

PROGRAM

MEMORY

SERIAL PORTS

SPORT 1SPORT 0

MEMORY

DATA

PROGRAMMABLE

CONTROLLER

TIMER

I/O

FLAGS

BYTE DMA

INTERNAL

DMA

PORT

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

DMA
BUS

GENERAL DESCRIPTION

The ADSP-2183 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.

The ADSP-2183 combines the ADSP-2100 family base architec­ture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and
data memory.

The ADSP-2183 integrates 80K bytes of on-chip memory con­figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equipment.
The ADSP-2183 is available in 128-lead LQFP, and 144-Ball
Mini-BGA packages.

In addition, the ADSP-2183 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans­fers and global interrupt masking, for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2183 operates with a 19 ns instruction cycle
time. Every instruction can execute in a single processor cycle.

The ADSP-2183’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera­tions in parallel. In one processor cycle the ADSP-2183 can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADSP-2183

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Development System

The ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2183. The assembler has an algebraic syntax
that is easy to program and debug. The linker combines object
files into an executable file. The simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment.

The EZ-KIT Lite is a hardware/software kit offering a com­plete development environment for the ADSP-21xx family:
an ADSP-2189M evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-2189M evaluation board is a low-cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite include the
following features:

• 35.7 MHz ADSP-2189M

• Full 16-bit Stereo Audio I/O with AD73322

CODEC

• RS-232 Interface

• EZ-ICE Connector for Emulator Control

• DSP Demo Programs

• Evaluation Suite of VisualDSP

®

The ADSP-218x EZ-ICE

Emulator aids in the hardware debug­ging of ADSP-218x systems. The ADSP-218x integrates on-chip
emulation support with a 14-pin ICE-Port interface. This inter­face provides a simpler target board connection requiring fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-218x device need not be removed
from the target system when using the EZ-ICE, nor are any
adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

(See Designing An EZ-ICE-Compatible Target System section
of this data sheet for exact specifications of the EZ-ICE target
board connector.)

Additional Information

This data sheet provides a general overview of ADSP-2183
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2183 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro­cessor cycle. The ADSP-2183 assembly language uses an alge­braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2183. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi­sions to support multiprecision computations. The ALU per­forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith­metic shifts, normalization, denormalization and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.

The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.

The ADSP-21xx family DSPs contain a shadow register that is
useful for single cycle context switching of the processor.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu­tational units. The sequencer supports conditional jumps, sub­routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2183 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.

Efficient data transfer is achieved with the use of five internal
buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus
The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit­ting the ADSP-2183 to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2183 can fetch an operand from program memory and
the next instruction in the same cycle.

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

–2– REV. C

ADSP-2183

In addition to the address and data bus for external memory
connection, the ADSP-2183 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro­grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2183 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.

The ADSP-2183 can respond to thirteen possible interrupts,
eleven of which are accessible at any given time. There can be
up to six external interrupts (one edge-sensitive, two level­sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal.

The two serial ports provide a complete synchronous serial inter­face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.

The ADSP-2183 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro­cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2183 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2183
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.

• SPORTs are bidirectional and have a separate, double­buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their
own serial clock internally.

• SPORTs have independent framing for the receive and trans­mit sections. Sections run in a frameless mode or with frame
synchronization signals, internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.

DATA

ADDRESS

GENERATOR

#1

INPUT REGS INPUT REGS

INPUT REGS

ALU

ALU

OUTPUT REGS

OUTPUT REGS

DATA

ADDRESS

GENERATOR

#2

PMA BUS

DMA BUS

PMD BUS

DMD BUS

INPUT REGS

OUTPUT REGS

MAC

MAC

OUTPUT REGS

16

INSTRUCTION

R BUS

REGISTER

PROGRAM

SEQUENCER

INPUT REGS

OUTPUT REGS

14

14

24

BUS

EXCHANGE

16

SHIFTER

PROGRAM

SRAM

16kⴛ24

TRANSMIT REG

RECEIVE REG

ADSP-2183 INTEGRATION 21xx CORE

DATA
SRAM

16kⴛ16

COMPANDING

CIRCUITRY

SERIAL
PORT 0

5 5

TRANSMIT REG

RECEIVE REG

SERIAL
PORT 0

BYTE

DMA

CONTROLLER

TIMER

POWER

DOWN

CONTROL

LOGIC

PROGRAMMABLE

I/O

FLAGS

PMA BUS

DMA BUS

PMD BUS

DMD
BUS

INTERRUPTS

MUX

EXTERNAL

EXTERNAL

MUX

INTERNAL

DMA

PORT

2

8

3

14

ADDRESS

BUS

DATA

BUS

16

4

24

REV. C

Figure 1. Block Diagram

–3–

ADSP-2183

• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.

• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.

Pin Descriptions

The ADSP-2183 is available in a 128-lead LQFP package, and
Mini-BGA.

PIN FUNCTION DESCRIPTIONS

#
Pin of Input/
Name(s) Pins Output Function

Address 14 O Address Output Pins for Program,

Data, Byte, & I/O Spaces

Data 24 I/O Data I/O Pins for Program and

Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)

RESET 1 I Processor Reset Input
IRQ2 1 I Edge- or Level-Sensitive

Interrupt Request

IRQL0,
IRQL1 2 I Level-Sensitive Interrupt

Requests

IRQE 1 I Edge-Sensitive Interrupt

Request

BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
PMS 1 O Program Memory Select Output
DMS 1 O Data Memory Select Output
BMS 1 O Byte Memory Select Output
IOMS 1 O I/O Space Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output

MMAP 1 I Memory Map Select Input
BMODE 1 I Boot Option Control Input
CLKIN,

XTAL 2 I Clock or Quartz Crystal Input

#
Pin of Input/
Name(s) Pins Output Function

CLKOUT 1 O Processor Clock Output.
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port 1 or Two External

IRQs, Flag In and Flag Out
IRD, IWR 2 I IDMA Port Read/Write Inputs
IS 1 I IDMA Port Select

IAL 1 I IDMA Port Address Latch

Enable
IAD 16 I/O IDMA Port Address/Data Bus
IACK 1 O IDMA Port Access Ready

Acknowledge
PWD 1 I Power-Down Control
PWDACK 1 O Power-Down Control
FL0, FL1,

FL2 3 O Output Flags
PF7:0 8 I/O Programmable I/O Pins
EE 1 * (Emulator Only*)

EBR 1 * (Emulator Only*)
EBG 1 * (Emulator Only*)
ERESET 1 * (Emulator Only*)
EMS 1 * (Emulator Only*)
EINT 1 * (Emulator Only*)

ECLK 1 * (Emulator Only*)
ELIN 1 * (Emulator Only*)
ELOUT 1 * (Emulator Only*)
GND 11 Ground Pins (LQFP)
VDD 6 Power Supply Pins (LQFP)
GND 22 Ground Pins (Mini-BGA)
VDD 11 Power Supply Pins (Mini-BGA)

*These ADSP-2183 pins must be connected only to the EZ-ICE connector in

the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.

Interrupts

The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2183 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP­2183 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power-down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level­sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.

–4– REV. C

ADSP-2183

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt Address (Hex)

Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable) 002C

IRQ2 0004
IRQL1 0008
IRQL0 000C

SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter­rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.

The ADSP-2183 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest­ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear
interrupts.

On-chip stacks preserve the processor status and are automati­cally maintained during interrupt handling. The stacks are
twelve levels deep to allow interrupt, loop and subroutine nesting.

The following instructions allow global enable or disable servic­ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.

ENA INTS;
DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2183 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external
power dissipation.

Power-Down

The ADSP-2183 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power­down features. Refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter for detailed
information about the power-down feature.

• Quick recovery from power-down. The processor begins
executing instructions in as few as 300 CLKIN cycles.

• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 300 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscil­lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi­lize), and letting the oscillator run to allow 300 CLKIN
cycle start-up.

• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit.

• Interrupt support allows an unlimited number of instruc­tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non­maskable, edge-sensitive interrupt.

• Context clear/save control allows the processor to con­tinue where it left off or start with a clean context when
leaving the power-down state.

•The RESET pin also can be used to terminate
power-down.

• Power-down acknowledge pin indicates when the
processor has entered power-down.

Idle

When the ADSP-2183 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2183 to
let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency,
a programmable fraction of the normal clock rate, is speci­fied by a selectable divisor given in the IDLE instruction.
The format of the instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.

REV. C

–5–

ADSP-2183

When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock, and thus its response time, to
incoming interrupts. The one-cycle response time of the stan­dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-2183 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64 or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems with an exter­nally generated serial clock (SCLK), the serial clock rate may be
faster than the processor’s reduced internal clock rate. Under
these conditions, interrupts must not be generated at a faster
rate than can be serviced, due to the additional time the processor
takes to come out of the idle state (a maximum of n processor
cycles).

SYSTEM INTERFACE

Figure 2 shows a typical basic system configuration with the
ADSP-2183, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories. Program­mable wait state generation allows the processor to connect
easily to slow peripheral devices. The ADSP-2183 also provides
four external interrupts and two serial ports or six external inter­rupts and one serial port.

ADSP-2183

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

SYSTEM

INTERFACE

OR

␮CONTROLLER

16

CLKIN

XTAL

FL0-2
PF0-7

IRQ2
IRQE
IRQL0
IRQL1

SPORT1

SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

IDMA PORT

IRD
IWR
IS

IAL

IACK

IAD15-0

ADDR13-0

DATA23-0

BMS

WR

IOMS

PMS
DMS
CMS

BGH
PWD

PWDACK

A

14

24

RD

BR
BG

13-0

A0-A21

D

23-16

D

A

D

A

D

15-8

10-0

23-8

13-0

23-0

BYTE

MEMORY

DATA

CS

ADDR

I/O

DATA

SPACE

(PERIPHERALS)

CS

2048 LOCATIONS

ADDR

OVERLAY

MEMORY

DATA

TWO 8K

PM SEGMENTS

TWO 8K

DM SEGMENTS

Figure 2. ADSP-2183 Basic System Configuration

Clock Signals

The ADSP-2183 can be clocked by either a crystal or a TTL­compatible clock signal.

The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera­tion. The only exception is while the processor is in the power­down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.

If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con­nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.

The ADSP-2183 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.

Because the ADSP-2183 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.

A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.

CLKIN CLKOUT

XTAL

DSP

Figure 3. External Crystal Connections

Reset

The RESET signal initiates a master reset of the ADSP-2183.
The RESET signal must be asserted during the power-up se­quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

DD

is ap­plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini­mum pulsewidth specification, t

RSP

.

The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.

–6– REV. C

ADSP-2183

INTERNAL 8K

(PMOVLAY = 0,

MMAP = 1)

0x3FFF

0x2000
0x1FFF

8K EXTERNAL

0x0000

PROGRAM MEMORY

ADDRESS

Memory Architecture

The ADSP-2183 provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O.

Program Memory is a 24-bit-wide space for storing both
instruction opcodes and data. The ADSP-2183 has 16K words
of Program Memory RAM on chip and the capability of access­ing up to two 8K external memory overlay spaces using the
external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.

Data Memory is a 16-bit-wide space used for the storage of
data variables and for memory-mapped control registers. The
ADSP-2183 has 16K words on Data Memory RAM on chip,
consisting of 16,352 user-accessible locations and 32 memory­mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus.

Byte Memory provides access to an 8-bit-wide memory space
through the Byte DMA (BDMA) port. The Byte Memory inter­face provides access to 4 MBytes of memory by utilizing eight
data lines as additional address lines. This gives the BDMA Port
an effective 22-bit address range. On power-up, the DSP can
automatically load bootstrap code from byte memory.

I/O Space allows access to 2048 locations of 16-bit-wide data.
It is intended to be used to communicate with parallel periph­eral devices such as data converters and external registers or
latches.

Program Memory

The ADSP-2183 contains a 16K × 24 on-chip program RAM.
The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2183 allows the use of 8K
external memory overlays.

The program memory space organization is controlled by the
MMAP pin and the PMOVLAY register. Normally, the ADSP­2183 is configured with MMAP = 0 and program memory orga­nized as shown in Figure 4.

Table II.

PMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable

1 External 0 13 LSBs of Address

Overlay 1 Between 0x2000

and 0x3FFF

2 External 1 13 LSBs of Address

Overlay 2 Between 0x2000

and 0x3FFF

This organization provides for two external 8K overlay segments
using only the normal 14 address bits. This allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space because the processor core (i.e., the sequencer)
does not take the PMOVLAY register value into account. For
example, if a loop operation were occurring on one of the exter­nal overlays, and the program changes to another external over­lay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.

For ADSP-2100 Family compatibility, MMAP = 1 is allowed.
In this mode, booting is disabled and overlay memory is dis­abled (PMOVLAY must be 0). Figure 5 shows the memory map
in this configuration.

There are 16K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to
something other than 0, external accesses occur at addresses
0x2000 through 0x3FFF. The external address is generated as
shown in Table II.

REV. C

PROGRAM MEMORY

8K INTERNAL

(PMOVLAY = 0,

MMAP = 0)

OR

EXTERNAL 8K

(PMOVLAY = 1 or 2,

MMAP = 0)

8K INTERNAL

ADDRESS

0x3FFF

0x2000

0x1FFF

0x0000

Figure 4. Program Memory (MMAP = 0)

Figure 5. Program Memory (MMAP = 1)

Data Memory

The ADSP-2183 has 16,352 16-bit words of internal data
memory. In addition, the ADSP-2183 allows the use of 8K
external memory overlays. Figure 6 shows the organization of
the data memory.

DATA MEMORY

32 MEMORY–

MAPPED REGISTERS

INTERNAL

8160 WORDS

8K INTERNAL

(DMOVLAY = 0)

OR

EXTERNAL 8K

(DMOVLAY = 1, 2)

ADDRESS

0x3FFF

0x3FEO

0x3FDF

0x2000

0x1FFF

0x0000

Figure 6. Data Memory

–7–

ADSP-2183

There are 16,352 words of memory accessible internally when
the DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.

Table III.

DMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable

1 External 0 13 LSBs of Address

Overlay 1 Between 0x0000

and 0x1FFF

2 External 1 13 LSBs of Address

Overlay 2 Between 0x0000

and 0x1FFF

This organization allows for two external 8K overlays using only
the normal 14 address bits.

All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register.

I/O Space

The ADSP-2183 supports an additional external memory space
called I/O space. This space is designed to support simple con­nections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper 3 bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space.
The I/O space also has four dedicated 3-bit wait state regis­ters, IOWAIT0-3, which specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table IV.

Table IV.

Address Range Wait State Register

0x000–0x1FF IOWAIT0
0x200–0x3FF IOWAIT1
0x400–0x5FF IOWAIT2
0x600–0x7FF IOWAIT3

Composite Memory Select (CMS)

The ADSP-2183 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.

When set, each bit in the CMSSEL register causes the CMS
signal to be asserted when the selected memory select is as­serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip
select of the memory; use either DMS or PMS as the additional
address bit.

The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2183 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.

Byte Memory DMA (BDMA)

The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space,
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.

The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num­ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table V shows the data formats
supported by the BDMA circuit.

Table V.

Internal

BTYPE Memory Space Word Size Alignment

00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start­ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener­ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
MMAP, PMOVLAY or DMOVLAY.

–8– REV. C

ADSP-2183

When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to create
a destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera­tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port)

The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2183. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory­mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2183 is operating at full speed.

The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in­creases throughput as the address does not have to be sent for
each memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14­bit address and 1-bit destination type can be driven onto the bus
by an external device. The address specifies an on-chip memory
location; the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.

Once the address is stored, data can either be read from or
written to the ADSP-2183’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2183 that a particular
transaction is required. In either case, there is a one-processor­cycle delay for synchronization. The memory access consumes
one additional processor cycle.

Once an access has occurred, the latched address is automati­cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.

Bootstrap Loading (Booting)

The ADSP-2183 has two mechanisms to allow automatic load­ing of the on-chip program memory after reset. The method for
booting after reset is controlled by the MMAP and BMODE
pins as shown in Table VI.

Table VI. Boot Summary Table

MMAP BMODE Booting Method

0 0 BDMA feature is used in default mode

to load the first 32 program memory
words from the byte memory space.
Program execution is held off until all
32 words have been loaded.

0 1 IDMA feature is used to load any inter-

nal memory as desired. Program execu­tion is held off until internal program
memory location 0 is written to.

1 X Bootstrap features disabled. Program

execution immediately starts from
location 0.

BDMA Booting

When the BMODE and MMAP pins specify BDMA booting
(MMAP = 0, BMODE = 0), the ADSP-2183 initiates a BDMA
boot sequence when reset is released. The BDMA interface is
set up during reset to the following defaults when BDMA boot­ing is specified: the BDIR, BMPAGE, BIAD and BEAD regis­ters are set to 0, the BTYPE register is set to 0 to specify
program memory 24 bit words, and the BWCOUNT register is
set to 32. This causes 32 words of on-chip program memory to
be loaded from byte memory. These 32 words are used to set up
the BDMA to load in the remaining program code. The BCR
bit is also set to 1, which causes program execution to be held
off until all 32 words are loaded into on-chip program memory.
Execution then begins at address 0.

The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface.

IDMA Booting

The ADSP-2183 can also boot programs through its Internal
DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2183
boots from the IDMA port. IDMA feature can load as much on­chip memory as desired. Program execution is held off until on­chip program memory location 0 is written to.

The ADSP-2100 Family Development Software (Revision 5.02
and later) can generate IDMA compatible boot code.

Bus Request and Bus Grant

The ADSP-2183 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2183 is not performing an external memory access, then
it responds to the active BR input in the following processor
cycle by:

• three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,

• asserting the bus grant (BG) signal, and

• halting program execution.

REV. C

–9–

ADSP-2183

If Go Mode is enabled, the ADSP-2183 will not halt program
execution until it encounters an instruction that requires an
external memory access.

If the ADSP-2183 is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.

When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.

The bus request feature operates at all times, including when
the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2183 is ready to
execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can re­lease the bus by deasserting bus request. Once the bus is re­leased, the ADSP-2183 deasserts BG and BGH and executes
the external memory access.

Flag I/O Pins

The ADSP-2183 has eight general purpose programmable in­put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc­tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2183’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2183 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2.
FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
are available as an alternate configuration of SPORT1.

INSTRUCTION SET DESCRIPTION

The ADSP-2183 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read­ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.

• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan­guage and is completely source and object code compatible
with other family members. Programs may need to be relo­cated to utilize on-chip memory and conform to the ADSP­2183’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.

• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2183 has on-chip emulation support and an ICE­Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

The ICE-Port interface consists of the following ADSP-2183 pins:

EBR EBG ERESET
EMS EINT ECLK

ELIN ELOUT EE

These ADSP-2183 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull­down resistors. The traces for these signals between the ADSP­2183 and the connector must be kept as short as possible, no
longer than three inches.

The following pins are also used by the EZ-ICE:

BR BG
RESET GND

The EZ-ICE uses the EE (emulator enable) signal to take con­trol of the ADSP-2183 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.

The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.

–10– REV. C

ADSP-2183

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.

12

GND

EBG

EBR

KEY (NO PIN)

ELOUT

EE

RESET

34

56

78

910

11 12

13 14

TOP VIEW

BG

BR

EINT

ELIN

ECLK

EMS

ERESET

Figure 7. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca­tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac­ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie, and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emu­lator, it must comply with the memory interface guidelines
listed below.

PM, DM, BM, IOM and CM

Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.

Note: If your target does not meet the worst case chip specifica­tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De­pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require­ments within published limits.

Restriction: All memory strobe signals on the ADSP-2183
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected
when the EZ-ICE is being used. The pull-up resistors are nec­essary because there are no internal pull-ups to guarantee their
state during prolonged three-state conditions resulting from
typical EZ-ICE debugging sessions. These resistors may be
removed at your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced
by the EZ-ICE board:

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the RESET
signal.

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the BR signal.

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

• EZ-ICE emulation ignores RESET and BR when in Emula-

tor Space (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.

Target Architecture File

The EZ-ICE software lets you load your program in its linked
(executable) form. The EZ-ICE PC program can not load
sections of your executable located in boot pages (by the
linker). With the exception of boot page 0 (loaded into PM
RAM), all sections of your executable mapped into boot pages
are not loaded.

Write your target architecture file to indicate that only PM
RAM is available for program storage, when using the EZ-ICE
software’s loading feature. Data can be loaded to PM RAM or
DM RAM.

REV. C

–11–

ADSP-2183–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade B Grade

Parameter Min Max Min Max Unit

V

DD

T

AMB

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Typ Max Unit

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

I

OZH

I

OZL

I

DD

I

DD

C

I

C

O

NOTES

1

Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.

12

Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.

13

Input only pins: CLKIN, RESET, IRQ2, BR , MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.

14

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A13, DT0, DT1, CLKOUT, FL2-0.

15

Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

16

Guaranteed but not tested.

17

Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–IAD15, PF0–PF7.

18

0 V on BR, CLKIN Active (to force three-state condition).

19

Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

10

Current reflects device operating with no output loads.

11

VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section.

12

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are

1

type 2 and type 6, and 20% are idle instructions.

13

Applies to LQFP package type and Mini-BGA.

14

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

Supply Voltage 3.0 3.6 3.0 3.6 V
Ambient Operating Temperature 0 +70 –40 +85 °C

K/B Grades

Hi-Level Input Voltage
Lo-Level Input Voltage
Hi-Level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

Three-State Leakage Current

Three-State Leakage Current

Supply Current (Idle)

Supply Current (Dynamic)

Input Pin Capacitance

Output Pin Capacitance

1, 2

1, 3

1, 4, 5

1, 4, 5

3

3

9, 10

3, 6, 13

6, 7, 13, 14

7

7

10, 12

@ V

= max 2.0 V

DD

@ VDD = min 0.4 V
@ VDD = min
I

= –0.5 mA 2.4 V

OH

= min

@ V

DD

I

= –100 µA

OH

6

VDD – 0.3 V

@ VDD = min

= 2 mA 0.4 V

I

OL

@ VDD = max
V

= V

IN

max 10 µA

DD

@ VDD = max
V

= 0 V 10 µA

IN

@ VDD = max

= V

V

IN

@ VDD = max
V

= 0 V

IN

DD

max

8

8

10 µA

8 µA
@ VDD = 3.3
T

= +25°C

AMB

t

= 19 ns

CK

= 25 ns

t

CK

t

= 30 ns

CK

t

= 34.7 ns

CK

11

11

11

11

10 mA
9mA
8mA

6mA
@ VDD = 3.3
T

= +25°C

AMB

t

= 19 ns

CK

= 25 ns

t

CK

t

= 30 ns

CK

t

= 34.7 ns

CK

11

11

11

11

44 mA

35 mA

30 mA

26 mA
@ VIN = 2.5 V
f

= 1.0 MHz

IN

T

= +25°C8pF

AMB

@ VIN = 2.5 V
f

= 1.0 MHz

IN

T

= +25°C8pF

AMB

or GND.

DD

–12–

REV. C

ADSP-2183

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

DD

+ 0.5 V

DD

Operating Temperature Range (Ambient) . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch­ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir­cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications
and the corresponding ADSP-2183 timing parameters, for your
convenience.

Memory ADSP-2183 Timing
Device Timing Parameter
Specification Parameter Definition

Address Setup to t

ASW

Write Start WR Low

Address Setup to t

AW

Write End WR Deasserted

Address Hold Time t

Data Setup Time t

Data Hold Time t
OE to Data Valid t
Address Access Time t

xMS = PMS, DMS, BMS, CMS , IOMS.

WRA

DW

DH

RDD

AA

A0–A13, xMS Setup before

A0–A13, xMS Setup before

A0–A13, xMS Hold after
WR Deasserted
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Valid

REV. C

FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS

tCK is defined as 0.5t

. The ADSP-2183 uses an input clock

CKI

with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces­sor cycle (equivalent to 33 MHz). t

period should be substituted for all relevant timing pa-

0.5t

CKI

values within the range of

CK

rameters to obtain the specification value.

Example: t

= 0.5tCK – 7 ns = 0.5 (34.7 ns) – 7 ns = 10.35 ns

CKH

–13–

ADSP-2183

Parameter Min Max Unit

Clock Signals and Reset

Timing Requirements:
t

CKI

t

CKIL

t

CKIH

Switching Characteristics:
t

CKL

t

CKH

t

CKOH

Control Signals

Timing Requirement:
t

RSP

NOTE

1

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).

CLKIN Period 38 100 ns
CLKIN Width Low 15 ns
CLKIN Width High 15 ns

CLKOUT Width Low 0.5t
CLKOUT Width High 0.5t

– 7 ns

CK

– 7 ns

CK

CLKIN High to CLKOUT High 0 20 ns

RESET Width Low 5t

t

CKI

CLKIN

t

CKIL

CK

t

CKOH

t

CKH

1

t

CKIH

ns

CLKOUT

t

CKL

Figure 8. Clock Signals

Parameter Min Max Unit

Interrupts and Flag

Timing Requirements:
t

IFS

t

IFH

Switching Characteristics:
t

FOH

t

FOD

NOTES

1

If IRQx and FI inputs meet t
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

2

Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

4

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5

Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.

IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High

Flag Output Hold after CLKOUT Low

5

Flag Output Delay from CLKOUT Low

and t

IFS

setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

IFH

CLKOUT

FLAG

OUTPUTS

IRQx

FI

PFx

1, 2, 3, 4

1, 2, 3, 4

5

t

FOD

t

FOH

0.25tCK + 15 ns

0.25t

CK

0.5tCK – 7 ns

0.5t

+ 6 ns

CK

t

IFH

t

IFS

ns

Figure 9. Interrupts and Flags

–14– REV. C

ADSP-2183

Parameter Min Max Unit

Bus Request–Bus Grant

Timing Requirements:
t

BH

t

BS

BR Hold after CLKOUT High
BR Setup before CLKOUT Low

1

1

0.25tCK + 2 ns

0.25tCK + 17 ns

Switching Characteristics:
t

SD

CLKOUT High to xMS, 0.25tCK + 10 ns
RD, WR Disable

t

SDB

xMS, RD, WR
Disable to BG Low 0 ns

t

SE

BG High to xMS,
RD, WR Enable 0 ns

t

SEC

t

SDBH

t

SEH

NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.

1

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.

2

BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

xMS, RD, WR

Enable to CLKOUT High 0.25t
xMS, RD, WR
Disable to BGH Low

BGH High to xMS,
RD, WR Enable

CLKOUT

2

2

t

BH

0ns

0ns

– 4 ns

CK

BR

CLKOUT

PMS, DMS

BMS, RD

WR

BG

BGH

t

BS

t

SD

t

SDB

t

SDBH

Figure 10. Bus Request–Bus Grant

t

SEC

t

SE

t

SEH

REV. C

–15–

ADSP-2183

Parameter Min Max Unit

Memory Read

Timing Requirements:
t

RDD

t

AA

t

RDH

Switching Characteristics:
t

RP

t

CRD

t

ASR

t

RDA

t

RWR

w = wait states × tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

RD Low to Data Valid 0.5tCK – 8 + w ns

A0–A13, xMS to Data Valid 0.75tCK – 10.5 + w ns
Data Hold from RD High 0 ns

RD Pulsewidth 0.5tCK – 5 + w ns
CLKOUT High to RD Low 0.25tCK – 2 0.25tCK + 7 ns
A0–A13, xMS Setup before RD Low 0.25tCK – 4 ns
A0–A13, xMS Hold after RD Deasserted 0.25tCK – 3 ns
RD High to RD or WR Low 0.5t

CLKOUT

A0 – A13

– 5 ns

CK

DMS, PMS,

BMS, IOMS,

CMS

RD

WR

t

RDA

t

ASR

t

CRD

D

t

AA

t

RDD

t

RP

t

RDH

t

RWR

Figure 11. Memory Read

–16– REV. C

ADSP-2183

Parameter Min Max Unit

Memory Write

Switching Characteristics:
t

DW

t

DH

t

WP

t

WDE

t

ASW

t

DDR

t

CWR

t

AW

t

WRA

t

WWR

w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.

Data Setup before WR High 0.5t
Data Hold after WR High 0.25t

WR Pulsewidth 0.5tCK – 5 + w ns
WR Low to Data Enabled 0 ns

A0–A13, xMS Setup before WR Low 0.25t
Data Disable before WR or RD Low 0.25tCK – 4 ns
CLKOUT High to WR Low 0.25t
A0–A13, xMS, Setup before WR Deasserted 0.75t
A0–A13, xMS Hold after WR Deasserted 0.25t
WR High to RD or WR Low 0.5tCK – 5 ns

CLKOUT

A0–A13

DMS, PMS,
BMS, CMS,

IOMS

WR

RD

t

ASW

t

D

CWR

t

WDE

t

AW

– 7 + w ns

CK

– 2 ns

CK

– 4 ns

CK

– 2 0.25 tCK + 7 ns

CK

– 9 + w ns

CK

– 3 ns

CK

t

WRA

t

WP

t

DW

t

WWR

t

DH

t

DDR

Figure 12. Memory Write

REV. C

–17–

ADSP-2183

Parameter Min Max Unit

Serial Ports

Timing Requirements:
t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics:
t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

TDE

t

TDV

t

SCDD

t

RDV

SCLK Period 38 ns
DR/TFS/RFS Setup before SCLK Low 4 ns
DR/TFS/RFS Hold after SCLK Low 7 ns
SCLK

CLKOUT High to SCLK

Width 15 ns

IN

OUT

0.25t

CK

0.25t

+ 10 ns

CK

SCLK High to DT Enable 0 ns
SCLK High to DT Valid 15 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 15 ns

OUT

DT Hold after SCLK High 0 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 14 ns
SCLK High to DT Disable 15 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 15 ns

CLKOUT

SCLK

DR

TFS

RFS

RFS

OUT

TFS

OUT

DT

TFS

ALTERNATE

FRAME MODE

MULTICHANNEL MODE,

RFS

FRAME DELAY 0

(MFD = 0)

t

CC

IN
IN

t

SCDE

t

t

RH

t

t

TDE

RD

SCDV

t

TDV

t

RDV

t

CC

t

SCStSCH

t

SCDH

t

SCDD

t

SCP

t

SCK

t

SCP

Figure 13. Serial Ports

–18– REV. C

ADSP-2183

Parameter Min Max Unit

IDMA Address Latch

Timing Requirements:
t

IALP

t

IASU

t

IAH

t

IKA

t

IALS

NOTES

1

Start of Address Latch = IS Low and IAL High.

2

End of Address Latch = IS High or IAL Low.

3

Start of Write or Read = IS Low and IWR Low or IRD Low.

Duration of Address Latch
IAD15–0 Address Setup before Address Latch End
IAD15–0 Address Hold after Address Latch End
IACK Low before Start of Address Latch
Start of Write or Read after Address Latch End

IACK

IAL

IS

IAD15–0

IRD OR

IWR

1, 2

2

2

1

2, 3

t

IKA

t

IALP

t

IASU

t

t

10 ns
5ns
2ns
0ns
3ns

IAH

IALS

Figure 14. IDMA Address Latch

REV. C

–19–

ADSP-2183

Parameter Min Max Unit

IDMA Write, Short Write Cycle

Timing Requirements:
t

IKW

t

IWP

t

IDSU

t

IDH

IACK Low before Start of Write
Duration of Write

1, 2

IAD15–0 Data Setup before End of Write
IAD15–0 Data Hold after End of Write

Switching Characteristic:
t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

End of Write = IS High or IWR High.

3

If Write Pulse ends before IACK Low, use specifications t

4

If Write Pulse ends after IACK Low, use specifications t

Start of Write to IACK High 15 ns

IACK

IS

IWR

IAD15–0

IDSU

IKSU

1

2, 3, 4

2, 3, 4

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

t

IWP

t

IDSU

DATA

0ns
15 ns
5ns
2ns

t

IDH

Figure 15. IDMA Write, Short Write Cycle

–20– REV. C

ADSP-2183

Parameter Min Max Unit

IDMA Write, Long Write Cycle

Timing Requirements:
t

IKW

t

IKSU

t

IKH

IACK Low before Start of Write
IAD15–0 Data Setup before IACK Low
IAD15–0 Data Hold after IACK Low

Switching Characteristics:
t

IKLW

t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

If Write Pulse ends before IACK Low, use specifications t

3

If Write Pulse ends after IACK Low, use specifications t

4

This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User’s Manual, Third Edition.

Start of Write to IACK Low
Start of Write to IACK High 15 ns

IACK

IS

IWR

IAD15–0

4

IDSU

IKSU

1

2, 3

2, 3

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

0ns

0.5tCK + 10 ns
2ns

t

t

IKSU

IKLW

1.5t

DATA

CK

t

IKH

ns

Figure 16. IDMA Write, Long Write Cycle

REV. C

–21–

ADSP-2183

Parameter Min Max Unit

IDMA Read, Long Read Cycle

Timing Requirements:
t
t

IKR

IRP

IACK Low before Start of Read
Duration of Read 15 ns

Switching Characteristics:
t

IKHR

t

IKDS

t

IKDH

t

IKDD

t

IRDE

t

IRDV

t

IRDH1

t

IRDH2

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

3

DM read or first half of PM read.

4

Second half of PM read.

IACK High after Start of Read
IAD15–0 Data Setup before IACK Low 0.5tCK – 7 ns
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)32tCK – 5 ns
IAD15–0 Previous Data Hold after Start of Read (PM2)

IACK

IRD

1

1

2

2

4

t

t

IKR

IS

t

IRDE

IKHR

t

IRP

t

IKDS

0ns

15 ns

0ns

10 ns

tCK – 5 ns

t

IKDH

IAD15–0

t

IRDV

PREVIOUS

DATA

t

IRDH

READ
DATA

Figure 17. IDMA Read, Long Read Cycle

t

IKDD

–22– REV. C

ADSP-2183

Parameter Min Max Unit

IDMA Read, Short Read Cycle

Timing Requirements:
t
t

IKR

IRP

IACK Low before Start of Read
Duration of Read 15 ns

Switching Characteristics:
t

IKHR

t

IKDH

t

IKDD

t

IRDE

t

IRDV

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

IACK High after Start of Read
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns

IACK

IRD

IAD15–0

1

1

2

2

t

IKR

t

IS

t

IRDE

IKHR

t

IRDV

t

IRP

PREVIOUS

0ns

15 ns

0ns

10 ns

t

IKDH

DATA

t

IKDD

Figure 18. IDMA Read, Short Read Cycle

REV. C

–23–

ADSP-2183

OUTPUT DRIVE CURRENTS

Figure 19 shows typical I-V characteristics for the output drivers
of the ADSP-2183. The curves represent the current drive
capability of the output drivers as a function of output voltage.

100

75

50

25

0

–25

–50

–75

–100

SOURCE CURRENT – mA

–125

–150

–175

–200

0 5.25

3.6V, –40°C

0.75 1.50 2.25 3.00 3.75 4.50

3.3V, +25°C

3.0V, +85°C

3.0V, +85°C

3.3V, +25°C

SOURCE VOLTAGE – V

3.6V, –40°C

Figure 19. Typical Drive Currents

1000

V

= 3.6V

DD

V

= 3.3V

100

10

CURRENT (LOG SCALE) – ␮A

0

08525 55

NOTES:

1. REFLECTS ADSP-2183 OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
USER'S MANUAL FOR DETAILS.)

2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS.

TEMPERATURE – °C

DD

V

= 3.0V

DD

Figure 20. Power-Down Supply Current (Typical)

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

DD

2

× f

C × V

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:

Assumptions:

•

External data memory is accessed every cycle with 50% of the
address pins switching.

•

External data memory writes occur every other cycle with
50% of the data pins switching.

•

Each address and data pin has a 10 pF total load at the pin.

•

The application operates at V

Total Power Dissipation = P

= 3.3 V and t

DD

+ (C × V

INT

= 30.0 ns.

CK

2

× f )

DD

–24– REV. C

P

= internal power dissipation from Power vs. Frequency

INT

graph (Figure 20).

2

(C × V

Address, DMS 8 × 10 pF × 3.32 V × 33.3 MHz = 29.0 mW
Data Output, WR 9 × 10 pF × 3.3
RD 1 × 10 pF × 3.3

× f ) is calculated for each output:

DD

# of
Pins × C × V

2

DD

2

V × 16.67 MHz = 16.3 mW

2

V × 16.67 MHz = 1.8 mW

× f

CLKOUT 1 × 10 pF × 3.32 V × 33.3 MHz = 3.6 mW

50.7 mW

Total power dissipation for this example is P

2183 POWER, INTERNAL

220

205

190

175

160

145

130

110mW

115

90mW

100

85

72mW

70

28 5232 36 40 44 48

50

45

40

35

27mW

30

25

20mW

20

15

15mW

10

5

0

28

32

30

28

26

24

22

20

20mW

18

16

14

11mW

12

10

10.6mW

8

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

3

TYPICAL POWER DISSIPATION AT 3.3V VDD AND 25ⴗC EXCEPT WHERE SPECIFIED.

4

IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

VDD = 3.6V

VDD = 3.3V

VDD = 3.0V

1/tCK – MHz

POWER, IDLE

VDD = 3.6V

VDD = 3.3V

VDD = 3.0V

36 40 44 48

1/tCK – MHz

POWER, IDLE n MODES

1/tCK – MHz

1, 3, 4

1, 2, 3

4428 32 36 40

INT

184mW

150mW

120mW

38mW

30mW

24mW

3

30mW

13.8mW

13mW

48 52

+ 50.7 mW.

5232

IDLE

IDLE (16)
IDLE (128)

OR GND.

DD

Figure 21. Power vs. Frequency

ADSP-2183

1.5V

INPUT

OR

OUTPUT

1.5V

CAPACITIVE LOADING

Figures 22 and 23 show the capacitive loading characteristics of
the ADSP-2183.

25

T = +85ⴗC

V

= 3.0V

DD

20

15

10

RISE TIME (0.4V – 2.4V) – ns

5

0

0 16020 40 60 80 100 120 140

CL – pF

180 200

Figure 22. Typical Output Rise Time vs. Load Capacitance,

(at Maximum Ambient Operating Temperature)

C

L

18

16

14

12

10

8

6

4

OR HOLD – ns

2

VALID OUTPUT DELAY

NOMINAL

–2

–4

–6

0 20040 80 120 160

CL – pF

is calculated. If multiple pins (such as the data bus) are dis­abled, the measurement value is that of the last pin to stop
driving.

Figure 24. Voltage Reference Levels for AC Measure­ments (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

) is the interval from when

ENA

a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.

REFERENCE

SIGNAL

t

(MEASURED)

OUTPUT

(MEASURED)

MEASURED

t

V

DIS

OH

V

OL

OUTPUT STOPS

DRIVING

V

(MEASURED) – 0.5V

OH

(MEASURED) +0.5V

V

OL

t

DECAY

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

t

ENA

V

OH

(MEASURED)

2.0V

1.0V

OUTPUT STARTS

DRIVING

V

OL

(MEASURED)

Figure 25. Output Enable/Disable

I

OL

Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating

L

Temperature)

TEST CONDITIONS
Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out­put disable time (t

) is the difference of t

DIS

MEASURED

and t

DECAY

,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,

, is dependent on the capacitive load, CL, and the current

t

DECAY

load, i

, on the output pin. It can be approximated by the fol-

L

lowing equation:

•0.5V

C

t

DECAY

L

=

i

L

from which

t

REV. C

= t

DIS

MEASURED

– t

DECAY

–25–

TO

OUTPUT

PIN

50pF

I

OH

+1.5V

Figure 26. Equivalent Device Loading for AC Measure­ments (Including All Fixtures)

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

T

= T

AMB

T

= Case Temperature in °C

CASE

– (PD × θCA)

CASE

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

θ

CA

θ

= Thermal Resistance (Junction-to-Ambient)

JA

= Thermal Resistance (Junction-to-Case)

θ

JC

Package ␪

JA

␪

JC

␪

CA

LQFP 50°C/W 2°C/W 48°C/W
Mini-BGA 70.7°C/W 7.4°C/W 63.3°C/W

ADSP-2183

128-Lead LQFP Package Pinout

IAL

PF3

PF2

PF1

PF0

WR

RD

IOMS

BMS
DMS
CMS

GND

V

PMS

A0

A1

A2

A3

A4

A5

A6

A7

XTAL

CLKIN

GND

CLKOUT

GND

V

A8

A9

A10

A11

A12

A13

IRQE

MMAP

PWD
IRQ2

IS

PF4

PF6

PF5

GND

128

127

126

125

124

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

DD

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DD

29

30

31

32

33

34

35

36

37

38

39

BMODE

41

40

42

IACK

PWDACK

BGH

43

DD

V

PF7

123

44

GND

IAD0

122

45

IRQL0

IAD1

121

46

IRQL1

IAD2

120

47

FL0

IAD4

IAD3

118

119

ADSP-2183

48

49

FL1

FL2

DD

V

GND

IAD5

115

116

117

TOP VIEW

(Not to Scale)

51

50

52

DT0

TFS0

RFS0

IAD6

114

53

DR0

IAD7

112

113

55

54

SCLK0

IAD9

IAD8

111

56

DT1/F0

TFS1/ IRQ1

IAD11

IAD10

110

109

57

58

GND

RFS1/IRQ0

IAD12

IAD13

108

107

59

60

DR1/FI

SCLK1

IAD15

IAD14

106

105

61

62

RESET

ERESET

IRD

104

63

EMS

IWR

103

64

EE

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

GND

D23

D22

D21

D20

D19

D18

D17

D16

D15

GND

V

DD

GND

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

GND

D4

D3

D2

D1

D0

V

DD

BG
EBG
BR
EBR
EINT

ELIN

ELOUT

ECLK

–26– REV. C

ADSP-2183

LQFP Pin Configurations

LQFP Pin LQFP Pin LQFP Pin LQFP Pin
Number Name Number Name Number Name Number Name

1 IAL 33 A12 65 ECLK 97 D19
2 PF3 34 A13 66 ELOUT 98 D20
3 PF2 35 IRQE 67 ELIN 99 D21
4 PF1 36 MMAP 68 EINT 100 D22
5 PF0 37 PWD 69 EBR 101 D23
6 WR 38 IRQ2 70 BR 102 GND
7 RD 39 BMODE 71 EBG 103 IWR
8 IOMS 40 PWDACK 72 BG 104 IRD
9 BMS 41 IACK 73 VDD 105 IAD15
10 DMS 42 BGH 74 D0 106 IAD14
11 CMS 43 VDD 75 D1 107 IAD13
12 GND 44 GND 76 D2 108 IAD12
13 VDD 45 IRQL0 77 D3 109 IAD11
14 PMS 46 IRQL1 78 D4 110 IAD10
15 A0 47 FL0 79 GND 111 IAD9
16 A1 48 FL1 80 D5 112 IAD8
17 A2 49 FL2 81 D6 113 IAD7
18 A3 50 DT0 82 D7 114 IAD6
19 A4 51 TFS0 83 D8 115 VDD
20 A5 52 RFS0 84 D9 116 GND
21 A6 53 DR0 85 D10 117 IAD5
22 A7 54 SCLK0 86 D11 118 IAD4
23 XTAL 55 DT1/F0 87 D12 119 IAD3
24 CLKIN 56 TFS1/IRQ1 88 D13 120 IAD2
25 GND 57 RFS1/IRQ0 89 D14 121 IAD1
26 CLKOUT 58 GND 90 GND 122 IAD0
27 GND 59 DR1/FI 91 VDD 123 PF7
28 VDD 60 SCLK1 92 GND 124 PF6
29 A8 61 ERESET 93 D15 125 PF5
30 A9 62 RESET 94 D16 126 PF4
31 A10 63 EMS 95 D17 127 GND
32 A11 64 EE 96 D18 128 IS

REV. C

–27–

ADSP-2183

144-Lead Mini-BGA Package Pinout

(Bottom View)

12 11 10 9 8 7 6 5 4

GND GND

D21 D23 IAD15 IAD11 VDD GND IAD1 PF5 GND PF3 PF1

D17 D20 D22 IAD13 IAD8 VDD IAD0 PF4 PF2 PF0

GND D15 D18 D19 D16 IAD9 IAD5 PF7 GND GND

D14 GND VDD GND GND IAD7 IAD3 A0 VDD VDD

D10 D11 D13 D12 IAD12 D8 IAD4 A3 A4 A1 A2

D6 D5 D9 D4 D7 DT0 A7 A8 A6 GND A5 XTAL

GND D2 GND D0 D3 DT1 VDD GND GND GND CLKIN

VDD D1 BG RFS1 SCLK0 VDD VDD A10 VDD CLKOUTVDD

IWR IS

IAD14 IAD10 IAD6 GND IAD2 PF6 GND IAL

IRD

IOMS DMS

CMS BMS

PMS

IRQL0

IRQL1

3

WR RD

21

A

B

C

D

E

F

G

H

J

EBG BR EBR ERESET

EINT RESET IACK IRQE

ECLK EE DR1 GND RFS0 FL1 GND BMODE

ELOUT ELIN GND DR0 FL0 GND MMAP A13

EMS BGH IRQ2 PWD

SCLK1 TFS1 TFS0 FL2 PWDACK A11 A12 A9

K

L

M

–28– REV. C

ADSP-2183

Mini-BGA Pin Configurations

Ball # Name Ball # Name Ball # Name Ball # Name

A01 IAL D01 GND G01 XTAL K01 A9
A02 IS D02 DMS G02 A5 K02 A12
A03 GND D03 GND G03 GND K03 A11
A04 PF6 D04 IOMS G04 A6 K04 PWDACK
A05 IAD2 D05 PF7 G05 A8 K05 FL2
A06 GND D06 IAD5 G06 A7 K06 TFS0
A07 IAD6 D07 IAD9 G07 DT0 K07 TFS1
A08 IAD10 D08 D16 G08 D7 K08 SCLK1
A09 IAD14 D09 D19 G09 D4 K09 ERESET
A10 IWR D10 D18 G10 D9 K10 EBR
A11 GND D11 D15 G11 D5 K11 BR
A12 GND D12 GND G12 D6 K12 EBG
B01 PF1 E01 VDD H01 CLKIN L01 A13
B02 PF3 E02 VDD H02 GND L02 MMAP
B03 GND E03 A0 H03 GND L03 IRQE
B04 PF5 E04 BMS H04 GND L04 IACK
B05 IAD1 E05 IAD3 H05 VDD L05 GND
B06 GND E06 CMS H06 IRQL0 L06 FL0
B07 VDD E07 IAD7 H07 DT1 L07 DR0
B08 IAD11 E08 GND H08 D3 L08 GND
B09 IAD15 E09 GND H09 D0 L09 RESET
B10 IRD E10 VDD H10 GND L10 ELIN
B11 D23 E11 GND H11 D2 L11 ELOUT
B12 D21 E12 D14 H12 GND L12 EINT
C01 RD F01 A2 J01 CLKOUT M01 PWD
C02 PF0 F02 A1 J02 VDD M02 IRQ2
C03 WR F03 A4 J03 A10 M03 BMODE
C04 PF2 F04 A3 J04 VDD M04 BGH
C05 PF4 F05 PMS J05 VDD M05 GND
C06 IAD0 F06 IAD4 J06 IRQL1 M06 FL1
C07 VDD F07 D8 J07 SCLK0 M07 RFS0
C08 IAD8 F08 IAD12 J08 RFS1 M08 GND
C09 IAD13 F09 D12 J09 BG M09 DR1
C10 D22 F10 D13 J10 D1 M10 EMS
C11 D20 F11 D11 J11 VDD M11 EE
C12 D17 F12 D10 J12 VDD M12 ECLK

REV. C

–29–

ADSP-2183

OUTLINE DIMENSIONS

Dimensions given in mm and (inches).

128-Lead Metric Plastic Thin Quad Flatpack (LQFP)

(ST-128)

16.20 (0.638)

16.00 (0.630)

15.80 (0.622)

TOP VIEW

(PINS DOWN)

103

102

0.75 (0.030)

0.60 (0.024)

0.50 (0.020)

SEATING

PLANE

1.60 (0.063)
MAX

128
1

22.20 (0.874)

22.00 (0.866)

20.10 (0.792)

20.00 (0.787)

19.90 (0.783)

21.80 (0.858)

0.08 (0.003)
MAX LEAD

COPLANARITY

0.15 (0.006)

0.05 (0.002)

38

39

0.50 (0.020)
BSC

1.45 (0.057)

1.40 (0.055)

1.35 (0.053)

NOTES:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08
(0.0032) FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

LEAD PITCH

0.27 (0.011)

0.22 (0.009)

0.17 (0.007)

LEAD WIDTH

14.10 (0.555)

14.00 (0.551)

13.90 (0.547)

64

65

–30– REV. C

OUTLINE DIMENSIONS

Dimensions given in mm and (inches).

144-Lead Mini-BGA Package Pinout

0.404 (10.25)

0.394 (10.00) SQ

0.384 (9.75)

0.404 (10.25)

TOP VIEW

0.067 (1.70) MAX

NOTE
THE ACTUAL POSITION OF THE BALL POPULATION
IS WITHIN 0.006 (0.150) OF ITS IDEAL POSITION
RELATIVE TO THE PACKAGE EDGES. THE ACTUAL
POSITION OF EACH BALL IS WITHIN 0.003 (0.08) OF
ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION.

0.394 (10.00) SQ

0.384 (9.75)

DETAIL A

(CA-144)

0.010 (0.25) MIN

0.346

(8.80)

BSC

12 11 10 9 8 7 6 5 4 3 2 1

0.031

(0.80)

BSC

0.346 (8.80) BSC

0.010
(0.25)

NOM

0.022 (0.55)

0.020 (0.50)

0.018 (0.45)

BALL DIAMETER

0.031 (0.80) BSC

DETAIL A

0.005

(0.12)

MAX

A
B
C
D
E
F
G
H
J
K
L
M

0.034 (0.85) MIN

SEATING
PLANE

ADSP-2183

C00184b–0–7/00 (rev. C)

ORDERING GUIDE

Ambient Instruction
Temperature Rate Package Package

Part Number Range (MHz) Description Option

ADSP-2183KST-115 0°C to +70°C 28.8 128-Lead LQFP ST-128
ADSP-2183BST-115 –40°C to +85°C 28.8 128-Lead LQFP ST-128
ADSP-2183KST-133 0°C to +70°C 33.3 128-Lead LQFP ST-128
ADSP-2183BST-133 –40°C to +85°C 33.3 128-Lead LQFP ST-128
ADSP-2183KST-160 0°C to +70°C 40 128-Lead LQFP ST-128
ADSP-2183BST-160 –40°C to +85°C 40 128-Lead LQFP ST-128
ADSP-2183KST-210 0°C to +70°C 52 128-Lead LQFP ST-128
ADSP-2183KCA-210 0°C to +70°C 52 144-Lead Mini-BGA CA-144

PRINTED IN U.S.A.

REV. C

–31–