Datasheet ADSP-21371, ADSP-21375 Datasheet (ANALOG DEVICES)

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Page 1

SHARC Processor

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 stage

Sequencer

PEx PEy

PMD 64-BIT

IODO 32-BIT

EPD BUS 48-BIT

Core Bus

Cross Bar

DAI Routing/Pins

PCG A

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI

SDRAM

External Port Pin MUX

TIMER

SPORT

PWM

DAG1/2 Timer

IDP/

PDAP

TWI

IOD0 BUS

MTM/

PCG C

PERIPHERAL BUS

32-BIT

CORE

FLAGS

FLAGx/IRQx/ TMREXP

JTAG

Internal Memory

DMD 64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1 32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals

External Port

SIMD Core

DTCP

S/PDIF Tx/Rx

DMD 64-BIT

ADSP-21371/ADSP-21375

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory, ADSP-21371—1M bits of on-chip SRAM

and 4M bits of on-chip mask-programmable ROM

On-chip memory, ADSP-21375—0.5M bits of on-chip

SRAM and 2M bits of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21371/ADSP-21375 processors are available with a

200/266 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, precision clock generators, and more. For complete ordering information, see Order-

ing Guide on Page 52.

DEDICATED AUDIO COMPONENTS

ADSP-21371—S/PDIF-compatible digital audio

receiver/transmitter

ADSP-21371—8 dual data line serial ports that operate at up

to 50 Mbps on each data line — each has a clock, frame sync, and two data lines that can be configured as either a

receiver or transmitter pair 16 PWM outputs configured as four groups of four outputs ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios Available in a 208-lead LQFP_EP package

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

Figure 1. Functional Block Diagram

Page 2

ADSP-21371/ADSP-21375

Summary ............................................................... 1

Dedicated Audio Components .................................... 1

Revision History ...................................................... 2

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 6

I/O Processor Features ......................................... 10

System Design .................................................... 11

Development Tools ............................................. 11

Additional Information ........................................ 12

Pin Function Descriptions ....................................... 13

ADSP-21371/ADSP-21375 Specifications .. . ................. 16

Operating Conditions .......................................... 16

Electrical Characteristics ....................................... 16

Package Information ........................................... 17

REVISION HISTORY

9/09—Rev. B to Rev. C

Corrected all outstanding document errata. Also replaced core clock references (CCLK) in the timing specifications with peripheral clock references (PCLK).

Added operating conditions and electrical characteristics for the 1.0 V, 200 MHz parts.

For this revision the following sections have been removed. For information see the ADSP-2137x SHARC Processor Hardware Reference: “Address Data Pins as Flags”, “Address/Data Modes”, Core Instruction Rate to CLKIN Ratio Modes.”

Revised Figure 1, Functional Block Diagram ....................1

Added Table 2, ADSP-21371/ADSP-21375 Features ..........3

Added Figure 2, SHARC Core Block Diagram ..................4

Added Context Switch ...............................................5

Added Universal Registers ..........................................5

Added Timer ...........................................................5

Maximum Power Dissipation ................................. 17

Absolute Maximum Ratings ................................... 17

ESD Sensitivity ................................................... 17

Timing Specifications ........................................... 17

Output Drive Currents ......................................... 45

Test Conditions .................................................. 45

Capacitive Loading .............................................. 45

Thermal Characteristics ........................................ 46

208-Lead LQFP_EP Pinout ....................................... 47

Package Dimensions ............................................... 51

Automotive Products .............................................. 52

Ordering Guide ..................................................... 52

Added On-Chip Memory Bandwidth ............................ 5

Added External Port Throughput ................................. 8

Added Input Data Port (IDP) ...................................... 9

Added Precision Clock Generator (PCG) ....................... 9

Added Scatter/Gather DMA .......................................11

Clarified VCO operations in

Voltage Controlled Oscillator .....................................18

Corrected the pins names for the DAI and DPI in 208-Lead

LQFP_EP Pinout .....................................................47

Added Automotive Products ......................................52

Rev. C | Page 2 of 52 | September 2009

Page 3

GENERAL DESCRIPTION

ADSP-21371/ADSP-21375

The ADSP-21371/ADSP-21375 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio applications with their large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).

As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processors achieve an instruction cycle time of 3.75 ns at 266 MHz. With its SIMD computational hardware, the processors can perform 1.596 GFLOPS running at 266 MHz.

Table 1 shows performance benchmarks for these devices. Table 2 shows the features of the individual product offerings.

Table 1. Processor Benchmarks (at 266 MHz)

Speed

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, With Reversal) 34.5 μs FIR Filter (per Tap) IIR Filter (per Biquad) Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1] [4 × 4] × [4 × 1]

Divide (y/x) 13.1 ns Inverse Square Root 20.4 ns

Assumes two files in multichannel SIMD mode

(at 266 MHz)

1.88 ns

7.5 ns

16.91 ns

30.07 ns

Table 2. ADSP-21371/ADSP-21375 Features

Feature ADSP-21371 ADSP-21375

Frequency 266 MHz

(3.75 ns)

RAM 1M bit 0.5M bit

ROM 4M bits 2M bits

Pulse-Width Modulation

Serial Ports 8 4

UART 1 1

Digital Application Interface (DAI)

Ye s N o

Ye s Ye s

266 MHz (3.75 ns)

Table 2. ADSP-21371/ADSP-21375 Features (Continued)

Feature ADSP-21371 ADSP-21375

Digital Peripheral Interface (DPI)

S/PDIF Transceiver Yes No

SPI 2 2

TWI Yes Yes

Package 208-Lead LQFP_EP 208-Lead LQFP_EP

Ye s Ye s

The diagram on Page 1 shows the two clock domains that make up the ADSP-2137x processors. The core clock domain contains the following features:

• Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle

• One periodic interval timer with pinout

• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit, ADSP-21375)

• On-chip mask-programmable ROM (4M bit, ADSP-21371; 2M bit, ADSP-21375)

• JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints which allow flexible exception handling.

The diagram on Page 1 also shows the peripheral clock domains (also known as the I/O processor) and contains the following features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers

• Peripheral and external port bus for core connection

• Digital applications interface that includes four precision clock generators (PCG), an S/PDIF-compatible digital audio receiver/transmitter, an input data port (IDP), eight serial ports, eight serial interfaces, a 20-bit parallel input port (PDAP), and a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, one UART, two serial peripheral interfaces (SPI), a 2-wire interface (TWI), and a flexible signal routing unit (DPI SRU).

• External port with AMI and SDRAM controller

• Four units for PWM control

• One MTM for internal to internal memory transfers

Rev. C | Page 3 of 52 | September 2009

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ADSP-21371/ADSP-21375

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1 16x32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

US TAT

4x32-BIT

64-BIT

DAG2 16x32

ALU

MULTIPLIER

SHIFTER

DATA SWAP

PM ADDRESS 24

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21371/ADSP-21375 processors are code compatible at the assembly level with the ADSP-2136x, ADSP-2126x, ADSP-21160x, and ADSP-21161N, and with the first generation ADSP-2106x SHARC processors. The ADSP-21371/ ADSP-21375 processors share architectural features with the ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections.

SIMD Computational Engine

The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY, and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.

Figure 2. SHARC Core Block Diagram

Rev. C | Page 4 of 52 | September 2009

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ADSP-21371/ADSP-21375

Data Register File

Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the SHARC’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result register all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.

Universal Registers

Universal registers can be used for general purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all system registers (control/status) of the core.

The data bus exchange register PX permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM data bus. These registers contain hardware to handle the data width difference.

Tim er

The processors contain a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal.

Single-Cycle Fetch of an Instruction and Four Operands

The processors feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2). With the processor’s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

Instruction Cache

The processors include an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The processors’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.

On-Chip Memory

The ADSP-21371 processor contains 1 megabit of internal RAM and four megabits of internal mask-programmable ROM (see

Table 3 on Page 6) and the ADSP-21375 processor contains 0.5

megabits of internal RAM and two megabits of internal maskprogrammable ROM (see Table 4 on Page 7). Each block can be configured for different combinations of code and data storage. Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle.

The ADSP-21371 processor’s SRAM can be configured as a maximum of 32k words of 32-bit data, 64k words of 16-bit data,

21.3k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 1 megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

On-Chip Memory Bandwidth

The internal memory architecture allows four accesses at the same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses (2 × 64-bits, core CLK) and the IOD0/1 buses (2 × 32-bit, PCLK).

ROM-Based Security

The processors have a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the processor does not boot-load any

Rev. C | Page 5 of 52 | September 2009

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ADSP-21371/ADSP-21375

Table 3. ADSP-21371 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

BLOCK 0 ROM 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 BFFF

BLOCK 0 RAM 0x0004 C000–0x0004 CFFF

Reserved 0x0004 D000–0x0004 FFFF

BLOCK 1 ROM 0x0005 0000–0x0005 7FFF

Reserved 0x0005 8000–0x0005 BFFF

BLOCK 1 RAM 0x0005 C000–0x0005 CFFF

Reserved 0x0005 D000–0x0005 FFFF

BLOCK 2 RAM 0x0006 0000–0x0006 0FFF

Reserved 0x0006 1000–0x0006 FFFF

BLOCK 3 RAM 0x0007 0000–0x0007 0FFF

Reserved 0x0007 1000–0x0007 FFFF

Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM 0x0008 0000–0x0008 AAA9

Reserved 0x0008 AAAA–0x0008 FFFF

BLOCK 0 RAM 0x0009 0000–0x0009 1554

Reserved 0x0009 1555–0x0009 FFFF

BLOCK 1 ROM 0x000A 0000–0x000A AAA9

Reserved 0x000A AAAA–0x000A FFFF

BLOCK 1 RAM 0x000B 0000–0x000B 1554

Reserved 0x000B 1555–0x000B FFFF

BLOCK 2 RAM 0x000C 0000–0x000C 1554

Reserved 0x000C 1555–0x000D FFFF

BLOCK 3 RAM 0x000E 0000–0x000E 1554

Reserved 0x000E 1555–0x000F FFFF

BLOCK 0 ROM 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 7FFF

BLOCK 0 RAM 0x0009 8000–0x0009 9FFF

Reserved 0x0009 A000–0x0009 FFFF

BLOCK 1 ROM 0x000A 0000–0x000A FFFF

Reserved 0x000B 0000–0x000B 7FFF

BLOCK 1 RAM 0x000B 8000–0x000B 9FFF

Reserved 0x000B A000–0x000B FFFF

BLOCK 2 RAM 0x000C 0000–0x000C 1FFF

Reserved 0x000C 2000–0x000D FFFF

BLOCK 3 RAM 0x000E 0000–0x000E 1FFF

Reserved 0x000E 2000–0x000F FFFF

BLOCK 0 ROM 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 FFFF

BLOCK 0 RAM 0x0013 0000–0x0013 3FFF

Reserved 0x0013 4000–0x0013 FFFF

BLOCK 1 ROM 0x0014 0000–0x0015 FFFF

Reserved 0x0016 0000–0x0016 FFFF

BLOCK 1 RAM 0x0017 0000–0x0017 3FFF

Reserved 0x0017 4000–0x0017 FFFF

BLOCK 2 RAM 0x0018 0000–0x0018 3FFF

Reserved 0x0018 4000–0x001B FFFF

BLOCK 3 RAM 0x001C 0000–0x001C 3FFF

Reserved 0x001C 4000–0x001F FFFF

external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-21371/ADSP-21375 family contains a rich set of peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, monitor control, imaging, and other applications.

Rev. C | Page 6 of 52 | September 2009

External Port

The external port on the ADSP-21371/ADSP-21375 SHARC processors provide a high performance, glueless interface to a wide variety of industry-standard memory devices. The 32-bit wide bus (ADSP-21371) may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers: the first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs (dual inline memory module), while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types.

Page 7

Table 4. ADSP-21375 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

BLOCK 0 ROM 0x0004 0000–0x0004 3FFF

Reserved 0x0004 4000–0x0004 BFFF

BLOCK 0 RAM 0x0004 C000–0x0004 C7FF

Reserved 0x0004 C800–0x0004 FFFF

BLOCK 1 ROM 0x0005 0000–0x0005 3FFF

Reserved 0x0005 4000–0x0005 BFFF

BLOCK 1 RAM 0x0005 C000–0x0005 C7FF

Reserved 0x0005 C800–0x0005 FFFF

BLOCK 2 RAM 0x0006 0000–0x0006 07FF

Reserved 0x0006 0800–0x0006 FFFF

BLOCK 3 RAM 0x0007 0000–0x0007 07FF

Reserved 0x0007 0800–0x0007 FFFF

Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM 0x0008 0000–0x0008 5554

Reserved 0x0008 5555–0x0008 FFFF

BLOCK 0 RAM 0x0009 0000–0x0009 0AAA

Reserved 0x0009 0AAB–0x0009 FFFF

BLOCK 1 ROM 0x000A 0000–0x000A 5554

Reserved 0x000A 5555–0x000A FFFF

BLOCK 1 RAM 0x000B 0000–0x000B 0AAA

Reserved 0x000B 0AAB–0x000B FFFF

BLOCK 2 RAM 0x000C 0000–0x000C 0AAA

Reserved 0x000C 0AAB–0x000D FFFF

BLOCK 3 RAM 0x000E 0000–0x000E 0AAA

Reserved 0x000E 0AAB–0x000F FFFF

ADSP-21371/ADSP-21375

BLOCK 0 ROM 0x0008 0000–0x0008 7FFF

Reserved 0x0008 8000–0x0009 7FFF

BLOCK 0 RAM 0x0009 8000–0x0009 8FFF

Reserved 0x0009 9000–0x0009 FFFF

BLOCK 1 ROM 0x000A 0000–0x000A 7FFF

Reserved 0x000A 8000–0x000B 7FFF

BLOCK 1 RAM 0x000B 8000–0x000B 8FFF

Reserved 0x000B 9000–0x000B FFFF

BLOCK 2 RAM 0x000C 0000–0x000C 0FFF

Reserved 0x000C 1000–0x000D FFFF

BLOCK 3 RAM 0x000E 0000–0x000E 0FFF

Reserved 0x000E 1000–0x000F FFFF

BLOCK 0 ROM 0x0010 0000–0x0010 FFFF

Reserved 0x0011 0000–0x0012 FFFF

BLOCK 0 RAM 0x0013 0000–0x0013 1FFF

Reserved 0x0013 2000–0x0013 FFFF

BLOCK 1 ROM 0x0014 0000–0x0014 FFFF

Reserved 0x0015 0000–0x0016 FFFF

BLOCK 1 RAM 0x0017 0000–0x0017 1FFF

Reserved 0x0017 2000–0x0017 FFFF

BLOCK 2 RAM 0x0018 0000–0x0018 1FFF

Reserved 0x0018 2000–0x001B FFFF

BLOCK 3 RAM 0x001C 0000–0x001C 1FFF

Reserved 0x001C 2000–0x001F FFFF

Rev. C | Page 7 of 52 | September 2009

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ADSP-21371/ADSP-21375

SDRAM Controller

The SDRAM controller provides an interface to up to four separate banks of industry-standard SDRAM devices or DIMMs. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0 contain between 16M bytes and 256M bytes of memory. SDRAM external memory address space is shown in Table 5.

The controller maintains all of the banks as a contiguous address space so that the processor sees this as a single address space, even if different size devices are used in the different banks.

A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The memory banks can be configured as 16 bits wide or as 32 bits wide. The SDRAM controller address, data, clock, and command pins can drive loads up to 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be sel ect ed a nd e xte rna l bu ffe rin g sh ould be pro vid ed s o th at t he load on the SDRAM controller pins does not exceed 30 pF.

Table 5. External Memory for SDRAM Addresses

Bank Size in Words Address Range

Bank 0 62M 0x0020 0000–0x03FF FFFF Bank 1 64M 0x0400 0000–0x07FF FFFF Bank 2 64M 0x0800 0000–0x0BFF FFFF Bank 3 64M 0x0C00 0000–0x0FFF FFFF

Note that the external memory bank addresses shown in Table 5 are for normal word accesses. If 48-bit instructions are placed in any such bank (with two instructions packed into three 32-bit locations), then care must be taken to map data buffers in the same bank. For example, if 2k instructions are placed starting at the bank 0 base address (0x0020 0000), then the data buffers can be placed starting at an address that is offset by 3k words (0x0020 0C00).

–MS3), and can be configured to

External Memory Code Execution

The program sequencer can execute code directly from external memory bank 0 (SRAM, SDRAM) over the 48-bit external port data bus (EPD). This allows a reduction in internal memory size, thereby reducing the die area. With external execution, programs run at slower speeds since 48-bit instructions are fetched in parts from a 16-bit external bus coupled with the inherent latency of fetching instructions from SDRAM. Fetching instructions from external memory generally takes 1.5 peripheral clock cycles per instruction. Non SDRAM external memory address space is shown in Table 6.

Table 6. External Memory for Non SDRAM Addresses

Bank Size in Words Address Range

Bank 0 14M 0x0020 0000–0x00FF FFFF Bank 1 16M 0x0400 0000–0x04FF FFFF Bank 2 16M 0x0800 0000–0x08FF FFFF Bank 3 16M 0x0C00 0000–0x0CFF FFFF

External Port Throughput

The throughput for the external port, based on 133 MHz clock and 32-bit data bus, is 177M bytes/s for the AMI and 532M bytes/s for SDRAM.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14.7M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The banks can also be configured as 8-bit or 16-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to high performance or to low cost and power.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms).

The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs.

The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the mid-point of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to connect various peripherals to any of the processor’s DAI pins (DAI_P1 to DAI_P20).

Programs make these connections using the signal routing unit (SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI

Rev. C | Page 8 of 52 | September 2009

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ADSP-21371/ADSP-21375

associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths.

In the ADSP-21371, the DAI includes eight serial ports, four precision clock generators (PCG), and an input data port (IDP). For the ADSP-21375, the DAI includes four serial ports, four precision clock generators (PCG) and an input data port (IDP).

The IDP provides an additional input path to the core of the processor, configurable as either eight channels of I

S serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports.

Serial Ports

The processors feature eight synchronous serial ports on the ADSP-21371 and four on the ADSP-21375. The SPORTs provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.

For the ADSP-21371, serial ports are enabled via 16 programmable pins and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight SPORTs are enabled, or eight duplex TDM streams of 128 channels per frame.

For the ADSP-21375, serial ports are enabled via eight programmable pins and simultaneous receive or transmit pins that support up to 16 transmit or 16 receive channels of audio data when all four SPORTs are enabled, or four duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of 50 Mbps. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

•Multichannel (TDM) mode with support for packed I

mode

•I

S mode

•Packed I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I

S protocols (I2S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I devices) per serial port, with a maximum of up to 32 I

S channels (using two stereo

S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I

S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated.

The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The ADSP-21371 S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I

S or right justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), and are controlled by the SRU control registers.

The ADSP-21375 does not have an S/PDIF-compatible digital receiver/transmitter.

Input Data Port (IDP)

The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I

S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, one-half of a frame at a time). The processor supports 24- and 32-bit I

S, 24and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats.

Precision Clock Generator (PCG)

The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.

Rev. C | Page 9 of 52 | September 2009

Page 10

ADSP-21371/ADSP-21375

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two serial peripheral interface (SPI) ports, one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), and two general-purpose timers.

Serial Peripheral (Compatible) Interface

The ADSP-21371/ADSP-21375 SHARC processors contain two serial peripheral interface ports (SPIs). The SPI is an industrystandard synchronous serial link, enabling the SPI-compatible ports of the processors to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device.

The SPI-compatible peripheral implementation also features programmable baud rates and clock phases and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable. The port:

• Supports bit rates ranging from (f (f

/16) bits per second.

PCLK

/1,048,576) to

PCLK

• Supports data formats from 7 to 12 bits per frame.

• Can be configured to generate maskable interrupts for both transmit and receive operations.

In conjunction with the general-purpose timer functions, autobaud detection is supported.

Peripheral Timers

Two general-purpose timers can generate periodic interrupts and be independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

Each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables the general-purpose timers independently.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the I

C bus protocol.

The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration

• Digital filtering and timed event processing

• 7-bit addressing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

I/O PROCESSOR FEATURES

The I/O processor provides many channels of DMA and controls the extensive set of peripherals described in the previous sections.

DMA Controller

The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-2137x processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART (see Table 7).

Table 7. DMA Channels

Peripheral ADSP-21371 ADSP-21375

SPORT 16 8 PDAP 8 8 SPI 2 2 UART 2 2 EP 2 2 MTM/DTCP 2 2 Total DMA Channels 32 24

Rev. C | Page 10 of 52 | September 2009

Page 11

ADSP-21371/ADSP-21375

Delay Line DMA

The processors provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction.

Scatter/Gather DMA

The ADSP-2137x processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from noncontiguous memory blocks.

SYSTEM DESIGN

The following sections provide an introduction to system design options and power supply issues. For complete system design information, see the ADSP-2137x SHARC Processor Hardware Reference.

Program Booting

The internal memory of the processor boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an SPI slave. Booting is determined by the boot configuration (BOOT_CFG1–0) pins in Table 8. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.

Table 8. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot 01 SPI Master Boot 10 EPROM/FLASH Boot 11 Reserved

The “Running Reset” feature allows programs to perform a reset of the processor core and peripherals, but without resetting the PLL and SDRAM controller, or performing a boot. The RESETOUT

Power Supplies

The processors have separate power supply connections for the internal (V internal supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide”.

pin acts as the input for initiating a running reset.

), and external (V

DDINT

) power supplies. The

DDEXT

DEVELOPMENT TOOLS

The processors are supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21371/ADSP-21375.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC processor has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

software and hardware development tools,

devel-

Rev. C | Page 11 of 52 | September 2009

Page 12

ADSP-21371/ADSP-21375

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK.

Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with the existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the processor’s architecture and functionality. For detailed information on the core architecture and instruction set, refer to the ADSP-2137x SHARC Processor Hardware Reference.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices

Rev. C | Page 12 of 52 | September 2009

Page 13

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

Table 9. Pin Descriptions

State During and After

Name Type

Reset Description

ADSP-21371/ADSP-21375

ADDR

DATA

DAI _P

DPI _P

23–0

31–0

20–1

14–1

O/T (pu) Pulled high/

driven low

I/O (pu) Pulled high/

pulled high

I/O with programmable

(pu)

I/O with programmable

(pu)

Pulled high/ pulled high

External Address.

erals on these pins.

External Data.

interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port data pins for parallel input data. PDAP over 16-bit external port DATA is not supported on the ADSP-21375 processor.

Digital Applications Interface Pins

DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in th e DA I SR U may be r ou ted to a ny of t hes e pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module (ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled via the DAI_PIN_PULLUP register.

Digital Peripheral Interface.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and generalpurpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP register.

The processor outputs addresses for external memory and periph-

The data pins can be multiplexed to support the external memory

. These pins provide the physical interface to the

These pins provide the physical interface to the DPI SRU.

ACK I (pu)

SDRAS

SDCAS

SDWE

O/T (pu) Pulled high/

driven high

Memory Acknowledge.

an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access.

External Port Read Enable.

external memory. RD

External Port Write Enable.

external memory. WR

SDRAM Row Address Strobe.

SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Column Address Select.

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Write Enable.

Rev. C | Page 13 of 52 | September 2009

External devices can deassert ACK (low) to add wait states to

RD is asserted whenever the processor reads a word from

has a 22.5 kΩ internal pull-up resistor.

WR is asserted when the processor writes a word to

has a 22.5 kΩ internal pull-up resistor.

Connect to SDRAM’s RAS pin. In conjunction with other

Connect to SDRAM’s WE or W buffer pin.

Connect to SDRAM's CAS pin. In conjunction with

Page 14

ADSP-21371/ADSP-21375

Table 9. Pin Descriptions (Continued)

State During and After

Name Type

Reset Description

SDCKE O/T (pu) Pulled high/

driven high

SDA10 O/T (pu) Pulled high/

driven low

SDCLK O/T High-Z/driving

0–1

O/T (pu) Pulled high/

driven high

FLAG[0]/IRQ0 I/O FLAG[0] INPUT

FLAG[1]/IRQ1 I/O FLAG[1] INPUT

FLAG[2]/IRQ2/ MS2

I/O with programmable pu

FLAG[2] INPUT

(for MS mode)

FLAG[3]/ TMREXP/ MS3

I/O with programmable pu

FLAG[3] INPUT

(for MS mode)

TDI I (pu)

SDRAM Clock Enable.

Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDRAM A10 Pin.

Enables applications to refresh an SDRAM in parallel with a non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDRAM Clock.

Memory Select Lines 0–1.

sponding banks of external memory. The MS

These lines are asserted (low) as chip selects for the corre-

lines are decoded memory address lines

3-0

that change at the same time as the other address lines. When no external memory access is occurring the MS

lines are inactive; they are active however when a condi-

3-0

tional memory access instruction is executed, whether or not the condition is true.

pin can be used in EPORT/FLASH boot mode. For more information, see the

The MS1

ADSP-2137x SHARC Processor Hardware Reference.

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG2/Interrupt Request/Memory Select2.

FLAG3/Timer Expired/Memory Select3.

Test Data Input (JTAG).

Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

TDO O/T

TMS I (pu)

TCK I

TRST

EMU

CLK_CFG

BOOT_CFG

1–0

I (pu)

O/T (pu)

Test Data Output (JTAG).

Test Mode Select (JTAG).

Serial scan output of the boundary scan path.

Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

Test Clock (JTAG).

Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processor.

Test Reset (JTAG).

Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. TRST internal pull-up resistor.

Emulation Status.

Must be connected to the processor. Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU pull-up resistor.

Core to CLKIN Ratio Control.

These pins set the start up clock frequency. See the

ADSP-2137x SHARC Processor Hardware Reference

ration modes. Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

Boot Configuration Select.

These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before reset is asserted. See the

Processor Hardware Reference

Rev. C | Page 14 of 52 | September 2009

for information about boot modes.

has a 22.5 kΩ

has a 22.5 kΩ internal

for a description of the clock configu-

ADSP-2137x SHARC

Page 15

Table 9. Pin Descriptions (Continued)

Name Type

ADSP-21371/ADSP-21375

State During and After Reset Description

RESET I

XTAL O

CLKIN I

RESETOUT RUNRSTIN

Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

I/O (pu)

Processor Reset.

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET (low) at power-up.

Crystal Oscillator Terminal.

Local Clock In.

configures the processor to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use the external clock source such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.

Reset Out/Running Reset In.

function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the

Resets the processor to a known state. Upon deassertion, there is a

input must be asserted

Used in conjunction with CLKIN to drive an external crystal.

Used in conjunction with XTAL. CLKIN is the processor clock input. It

The default setting is reset out. This pin also has a second

ADSP-2137x SHARC Processor Hardware Reference

Rev. C | Page 15 of 52 | September 2009

Page 16

ADSP-21371/ADSP-21375

ADSP-21371/ADSP-21375 SPECIFICATIONS

OPERATING CONDITIONS

1.0 V, 200 MHz 1.2 V, 266 MHz

Parameter

DDINT

DDEXT

IH_CLKIN

IL_CLKIN

JUNCTION

AMBIENT

Specifications subject to change without notice.

Applies to input and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOT_CFGx, CLKCFGx, RUNRSTIN ,

RESET, TCK, TMS, TDI, TRST.

Applies to input pin CLKIN.

ELECTRICAL CHARACTERISTICS

Description

Internal (Core) Supply Voltage 0.95 1.05 1.14 1.26 V External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V High Level Input Voltage @ V

Low Level Input Voltage @ V

High Level Input Voltage @ V

Low Level Input Voltage @ V Junction Temperature 208-Lead LQFP_EP @ T Ambient Temperature 208-Lead LQFP_EP @ T

= max 2.0 V

DDEXT

= min –0.5 +0.8 –0.5 +0.8 V

DDEXT

= max 1.74 V

DDEXT

= min –0.5 +1.10 –0.5 +1.10 V

DDEXT

0ºC to +70ºC 0 115 0 115 ºC

AMBIENT

0ºC to +70ºC –40 105 –40 105 ºC

AMBIENT

+ 0.5 2.0 V

DDEXT

+ 0.5 1.74 V

DDEXT

UnitMin Max Min Max

+ 0.5 V

1.0 V, 200 MHz 1.2 V, 266 MHz

Parameter

4, 5

ILPU

Description Test Conditions Min Typ Max Min Typ Max Unit

High Level Output Voltage @ V Low Level Output Voltage @ V High Level Input Current @ V Low Level Input Current @ V Low Level Input Current

@ V

= min, IOH = –1.0 mA

DDEXT

= min, IOL = 1.0 mA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 10 μA

DDEXT

= max, VIN = 0 V 200 200 μA

DDEXT

max 10 10 μA

DDEXT

2.4 2.4 V

0.4 0.4 V

Pull-up

OZH

OZL

OZLPU

6, 7

Three-State Leakage Current @ V Three-State Leakage Current @ V Three-State Leakage Current

@ V

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 10 μA

DDEXT

= max, VIN = 0 V 200 200 μA

DDEXT

max 10 10 μA

DDEXT

Pull-up

8, 9

DD-INTYP

10, 11

Specifications subject to change without notice.

Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE,

SDCKE, SDA10, and SDCLK.

See Output Drive Currents on Page 45 for typical drive current capabilities.

Applies to input pins: BOOT_CFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: FLAG3–0.

Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information.

Applies to all signal pins.

Guaranteed, but not tested.

Supply Current (Internal) 1.0V, 200 MHz: t

= 1.0 V, 25ºC

DDINT

1.2V, 266 MHz: t V

= 1.2 V, 25ºC

DDINT

Input Capacitance fIN = 1 MHz, T

CASE

= 5.00 ns,

CCLK

= 3.75 ns,

CCLK

400

600

= 25°C, VIN= 1.2 V 4.7 4.7 pF

Rev. C | Page 16 of 52 | September 2009

Page 17

ADSP-21371/ADSP-21375

vvvvvv.x n.n

tppZ-cc

ADSP-2137x

yyww country_of_origin

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 3 provides details about the package branding for the ADSP-21371/ADSP-21375 processor. For a complete listing of product availability, see Ordering

Guide on Page 52.

Figure 3. Typical Package Brand

Table 10. Package Brand Information

Brand Key Field Description

t Temperature Range pp Package Type Z RoHS Compliant Part ccc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision yyww Date Code

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see

Thermal Characteristics on Page 46.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 11 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 11. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V External (I/O) Supply Voltage (V Input Voltage –0.5 V to V Output Voltage Swing –0.5 V to V

DDEXT

) –0.3 V to +1.5 V

DDINT

) –0.3 V to +4.6 V

DDEXT

+0.5 V

DDEXT

+0.5 V

Table 11. Absolute Maximum Ratings (Continued)

Parameter Rating

Load Capacitance 200 pF Storage Temperature Range –65°C to +150°C Junction Temperature under Bias 125°C

ESD SENSITIVITY

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See

Figure 37 on Page 45 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 4). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock.

Rev. C | Page 17 of 52 | September 2009

Page 18

ADSP-21371/ADSP-21375

LOOP

FILTER

CLKIN

PCLK

SDCLK

SDRAM

DIVIDER

PMCTL

(PLLBP)

DIVIDE

BY 2

PMCTL

(SDCKR)

CCLK

PLL

XTAL

CLKIN

DIVIDER

RESETOUT

RESET

PLL

MULTIPLIER

BUF

VCO

BUF

PMCTL (INDIV)

PLL

DIVIDER

CLK_CFGx/PMCTL (2xPLLM)

RESETOUT

CLKOUT (TESTONLY)

DELAY OF

4096 CLKIN

CYCLES

CORERST

CCLK

PCLK

PMCTL

(PLLBP)

PMCTL

(2xPLLD)

VCO

CCLK

INPUT

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds f

specified in Table 14.

VCO

• The product of CLKIN and PLLM must never exceed 1/2 f

(max) in Table 14 if the input divider is not enabled

VCO

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 14 if the input divider is enabled (INDIV = 1).

The VCO frequency is calculated as follows:

= 2 × PLLM × f

VCO

= (2 × PLLM × f

CCLK

INPUT

) ÷ (2 × PLLD)

where:

= VCO output

VCO

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware.

PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the PMCTL register. During reset this value is 1.

= Input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled or

INPUT

= CLKIN ÷ 2 when the input divider is enabled

INPUT

Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 12. All of the timing specifications for the ADSP-2137x peripherals are defined in relation to t

. See the peripheral specific section

PCLK

for each peripheral’s timing information.

Table 12. Clock Periods

Timing Requirements Description

t t t

CCLK

PCLK

CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × t

CCLK

Figure 4 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-2137x SHARC Processor Hard- ware Reference.

Figure 4. Core Clock and System Clock Relationship to CLKIN

Rev. C | Page 18 of 52 | September 2009

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ADSP-21371/ADSP-21375

RSTVDD

CLKVDD

CLKRST

CORERST

PLLRST

DDEXT

DDINT

CLKIN

CLK_CFG1–0

RESET

RESETOUT

IVDDEVDD

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Note that during power-up, a leakage current of approximately 200 μA may be observed on the RESET results from the weak internal pull-up resistor on this pin being enabled during power-up.

Table 13. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

IVDDEVDD

CLKVDD

CLKRST

PLLRST

RESET Low Before V V

on Before V

DDINT

CLKIN Valid After V CLKIN Valid Before RESET Deasserted 10 PLL Control Setup Before RESET Deasserted 20

Switching Characteristic

CORERST

Valid V

DDINT/VDDEXT

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

cycles maximum.

Core Reset Deasserted After RESET Deasserted 4096 × tCK + 2 × t

assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

SRST

pin. This leakage current

DDINT/VDDEXT

DDEXT

DDINT/VDDEXT

specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

On 0 ns

–50 +200 ms

Valid 0 200 ms

CCLK

μs μs

Figure 5. Power-Up Sequencing

Rev. C | Page 19 of 52 | September 2009

Page 20

ADSP-21371/ADSP-21375

CLKIN

CKL

CKH

22pF

R1 1M⍀*

XTAL

CLKIN

22pF

16.67 MHz

47⍀*

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’SSPECIFICATIONS

*TYPICAL VALUES

ADSP-2137x

Clock Input

Table 14. Clock Input

Parameter

Timing Requirements

CKL

CKH

CKRF

CCLK

VCO

Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CLKIN Period 22.5 CLKIN Width Low 11.25 CLKIN Width High 11.25 CLKIN Rise/Fall (0.4 V to 2.0 V) 6 ns CCLK Period 3.75 10 ns VCO Frequency 200 800 MHz

CCLK

Min Max

266 MHz

Unit

100 ns 45 ns 45 ns

Figure 6. Clock Input

Clock Signals

The processor can use an external clock or a crystal. See the CLKIN pin description in Table 9. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 7 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register.

Figure 7. 266 MHz Operation (Fundamental Mode Crystal)

Rev. C | Page 20 of 52 | September 2009

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ADSP-21371/ADSP-21375

CLKIN

RESET

SRST

WRST

Reset

Table 15. Reset

Parameter Min Max Unit

Timing Requirements

WRST

SRST

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

Running Reset

The following timing specification applies to RESETOUT/RUNRSTIN RUNRSTIN

RESET Pulse Width Low 4 × t

RESET Setup Before CLKIN Low 8 ns

Figure 8. Reset

pin when it is configured as

Table 16. Running Reset

Parameter Min Max Unit

Timing Requirements

WRUNRST

SRUNRST

Running RESET Pulse Width Low 4 × t

Running RESET Setup Before CLKIN High 8 ns

CLKIN

RUNRSTIN

WRUNRST

Figure 9. Running Reset

SRUNRST

Rev. C | Page 21 of 52 | September 2009

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ADSP-21371/ADSP-21375

FLAG3

(TMREXP)

WCTIM

DAI_P20–1 DPI_P14–1

FLAG2–0

(IRQ2–0)

IPW

Core Timer

The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin).

Table 17. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

Interrupts

The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0

, and IRQ2 interrupts as well as the DAI_P20–1 and

IRQ1 DPI_P14

–1 pins when they are configured as interrupts.

TMREXP Pulse Width 4 × t

Figure 10. Core Timer

– 1 ns

PCLK

Table 18. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

Figure 11. Interrupts

+2 ns

PCLK

Rev. C | Page 22 of 52 | September 2009

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ADSP-21371/ADSP-21375

DPI_P14–1

(TIMER1–0)

PWMO

DPI_P14–1

(TIMER1–0)

PWI

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0 and Timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specifications provided below are valid at the DPI_P14–1 pins.

Table 19. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer W DTH_CAP Timing

The following timing specification applies to Timer0 and Timer1 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the specifications provided below are valid at the DPI_P14–1 pins.

Timer Pulse Width Output 2 × t

Figure 12. Timer PWM_OUT Timing

– 2 2 × (231 – 1) × t

PCLK

Table 20. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 × t

Figure 13. Timer Width Capture Timing

PCLK

2 × (231– 1) × t

PCLK

Rev. C | Page 23 of 52 | September 2009

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ADSP-21371/ADSP-21375

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O).

Table 21. DAI/DPI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 10 ns

DAI_Pn DPI_Pn

DAI_Pm

DPI_Pm

DPIO

Figure 14. DAI/DPI Pin to Pin Direct Routing

Rev. C | Page 24 of 52 | September 2009

Page 25

ADSP-21371/ADSP-21375

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py DPI_Py

PCG_CLKx_O

DAI_Pz DPI_Pz

PCG_FSx_O

DTRIGFS

DTRIGCLK

DPCGIO

STRIG

HTRIG

PCGOW

DPCGIO

PCGIW

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs

inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 through DAI_P20).

directly to the DAI pins. For the other cases, where the PCG’s

Table 22. Precision Clock Generator (Direct Pin Routing)

1.2 V, 266 MHz

Parameter Min Max Unit

Timing Requirements t t

PCGIP

STRIG

Input Clock Period t PCG Trigger Setup Before Falling Edge of P CG

× 4 ns

PCLK

4.5 ns

Input Clock

HTRIG

PCG Trigger Hold After Falling Edge of PCG

3ns

Input Clock

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock 2.5 10 ns

DTRIGCLK

DTRIGFS

PCGOW

PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5) × t

) 10 + ((2.5) × t

PCGIW

PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × t Output Clock Period 2 × t

– 1 ns

PCGIW

) 10 + ((2.5 + D – PH) × t

PCGIW

)ns

PCGIW

)ns

PCGIW

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.

Normal mode of operation.

Figure 15. Precision Clock Generator (Direct Pin Routing)

Rev. C | Page 25 of 52 | September 2009

Page 26

ADSP-21371/ADSP-21375

Flags

The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the DATA31–0 pins. See Table 9 on

Page 13 for more information on flag use.

Table 23. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

Switching Characteristic

FOPW

DPI_P14–1, DATA31–0, FLAG3–0 IN Pulse Width 2 × t

DPI_P14–1, DATA31–0, FLAG3–0

DPI_P14–1

(FLAG3–0 (DATA31–0)

DPI_P14–1

(FLAG3–0

(DATA31–0)

OUT

)

Pulse Width 2 × t

OUT

FIPW

FOPW

+ 3 ns

PCLK

– 2 ns

PCLK

Figure 16. Flags

Rev. C | Page 26 of 52 | September 2009

Page 27

SDRAM Interface Timing

Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.

ADSP-21371/ADSP-21375

Table 24. SDRAM Interface Timing

1.2 V, 266 MHz

Parameter Min Max Unit

Timing Requirements

SSDAT

HSDAT

DATA Setup Before SDCLK 0.58 ns

DATA Hold After SDCLK 2.2 ns Switching Characteristics t

SDCLK

SDCLKH

SDCLKL

DCAD

HCAD

DSDAT

ENSDAT

For F

Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.

= 133 MHz (SDCLK ratio = 1:2).

CCLK

SDCLK Period 7.5 ns

SDCLK Width High 3 ns

SDCLK Width Low 3 ns

Command, ADDR, Data Delay After SDCLK

Command, ADDR, Data Hold After SDCLK

1.3 ns

5.3 ns

Data Disable After SDCLK 5.3 ns

Data Enable After SDCLK 1.6 ns

SDCLKH

SDCLK

SSDAT

SDCLK

HSDAT

SDCLKL

DATA (IN)

DATA (OUT)

CMND ADDR

(OUT)

DCAD

ENSDAT

DCAD

HCAD

Figure 17. SDRAM Interface Timing for 133 MHz SDCLK

HCAD

DSDAT

Rev. C | Page 27 of 52 | September 2009

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ADSP-21371/ADSP-21375

ACK

DATA

DRHA

HDRH

RWR

DAD

DARL

DRLD

SDS

DSAK

DAAK

ADDR

MSx

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD timing parameters only apply to asynchronous access mode.

Table 25. Memory Read—Bus Master

Parameter Min Max Unit

Timing Requirements

DAD

DRLD

SDS

HDRH

DAAK

DSAK

Address, Selects Delay to Data Valid

RD Low to Data Valid

Data Setup to RD High 2.2 ns

Data Hold from RD High3,

ACK Delay from Address, Selects

ACK Delay from RD Low

Switching Characteristics

DRHA

DARL

RWR

Address Selects Hold After RD High RHC + 0.38 ns

Address Selects to RD Low

RD Pulse Width W – 1.4 ns

RD High to WR, RD, Low HI + t

W = (number of wait states specified in AMICTLx register) × t HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × t

IC = (number of idle cycles specified in AMICTLx register) × t H = (number of hold cycles specified in AMICTLx register) × t

Data delay/setup: System must meet t

The falling edge of MSx, is referenced.

Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

Data hold: User must meet t

ACK delay/setup: User must meet t

HDRH

, t

DAD

in asynchronous access mode. See Test Conditions on Page 45 for the calculation of hold times given capacitive and dc loads.

, or t

DAAK

, WR, and strobe

1.2 V, 266 MHz

1, 2

2, 5

SDCLK

)

SDCLK

, or t

DRLD

SDS.

, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t

DSAK

0ns

– 3.3 ns

SDCLK

– 0.8 ns

SDCLK

W + t

W – 3 ns

SCDCLK

W – 7.0 ns

– 5.12 ns

SDCLK

– 10. + W ns

or t

DSAK

DAAK

Figure 18. Memory Read—Bus Master

Rev. C | Page 28 of 52 | September 2009

Page 29

ADSP-21371/ADSP-21375

ACK

DATA

DAWH

DWHA

WWR

DATRWH

DWHD

DDWR

DDWH

DAWL

WDE

DSAK

DAAK

ADDR

MSx

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD timing parameters only apply to asynchronous access mode.

Table 26. Memory Write—Bus Master

Parameter Min Max Unit

Timing Requirements

t t

DAAK

DSAK

ACK Delay from Address, Selects ACK Delay from WR Low

Switching Characteristics

DAWH

DAWL

DDWH

DWHA

DWHD

DATRWH

WWR

DDWR

WDE

Address, Selects to WR Deasserted Address, Selects to WR Low WR Pulse Width W – 1.3 ns Data Setup Before WR High t Address Hold After WR Deasserted H + 0.15 ns Data Hold After WR Deasserted H + 0.02 ns Data Disable After WR Deasserted WR High to WR, RD Low t Data Disable Before RD Low 2t WR Low to Data Enabled t

W = (number of wait states specified in AMICTLx register) × t

ACK delay/setup: System must meet t

The falling edge of MSx is referenced.

Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

See Test Conditions on Page 45 for calculation of hold times given capacitive and dc loads.

DAAK

, or t

, WR, and strobe

1.2 V, 266 MHz

1, 2

1, 3

, H = (number of hold cycles specified in AMICTLx register) × t

SDCLK

, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t

DSAK

–3.6 + W ns

SDCLK

– 2.7 ns

SDCLK

– 3.0 + W ns

SDCLK

– 1.37 + H t

SDCLK

– 1.5+ H ns

SDCLK

– 5.1 ns

SDCLK

– 4.1 ns

SDCLK

W – 7.1 ns

SDCLK

– 10.1 + W ns

+ 4.9+ H ns

or t

DAAK

DSAK

SDCLK

Figure 19. Memory Write—Bus Master

Rev. C | Page 29 of 52 | September 2009

Page 30

ADSP-21371/ADSP-21375

Serial Ports

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) serial clock (SCLK) width.

Table 27. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

Frame Sync Setup Before SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 2.5 ns

HFSE

Frame Sync Hold After SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 2.5 ns

SDRE

HDRE

SCLKW

SCLK

Receive Data Setup Before Receive SCLK 2.5 ns Receive Data Hold After SCLK 2.5 ns SCLK Width (t SCLK Period t

Switching Characteristics

DFSE

Frame Sync Delay After SCLK (Internally Generated Frame Sync in either Transmit or Receive Mode) 10.5 ns

HOFSE

Frame Sync Hold After SCLK (Internally Generated Frame Sync in either Transmit or Receive Mode) 2 ns

DDTE

HDTE

Referenced to sample edge.

Referenced to drive edge.

Transmit Data Delay After Transmit SCLK 11 ns Transmit Data Hold After Transmit SCLK 2 ns

Serial port signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

1.2 V, 266 MHz

× 4) ÷ 2 – 0.5 ns

PCLK

× 4 ns

PCLK

Table 28. Serial Ports—Internal Clock

1.2 V, 266 MHz

Parameter Min Max Unit

Timing Requirements

SFSI

Frame Sync Setup Before SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 7 ns

HFSI

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode) 2.5 ns t t

SDRI

HDRI

Receive Data Setup Before SCLK 7 ns

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

HOFSI

DFSIR

HOFSIR

DDTI

HDTI

SCKLIW

Referenced to the sample edge.

Referenced to drive edge.

Minimum SPORT divisor register value.

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 4 ns

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0 ns

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 10.7 ns

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0 ns

Transmit Data Delay After SCLK 3.6 ns

Transmit Data Hold After SCLK –1.0 ns

Transmit or Receive SCLK Width 0.5t

– 2 0.5t

PCLK

+ 2 ns

PCLK

Rev. C | Page 30 of 52 | September 2009

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ADSP-21371/ADSP-21375

Table 29. Serial Ports—Enable and Three-State

1.2 V, 266 MHz

Parameter Min Max Unit

Switching Characteristics

DDTEN

DDTTE

DDTIN

Referenced to drive edge.

Table 30. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

DDTENFS

The t

DDTLFSE

Data Enable from External Transmit SCLK 2 ns Data Disable from External Transmit SCLK 10 ns Data Enable from Internal Transmit SCLK –1 ns

1.2 V, 266 MHz

Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 0

Data Enable for MCE = 1, MFD = 0 0.5 ns

and t

parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

DDTENFS

10 ns

Rev. C | Page 31 of 52 | September 2009

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ADSP-21371/ADSP-21375

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA CHANNEL

A/B)

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE SAMPLE

SFSE/I

DDTENFS

DDTLFSE

DRIVE SAMPLE

SFSE/I

DDTENFS

HFSE/I

DRIVE

HDTE/I

1ST BIT

LATE EXTERNAL TRANSMIT FS

DRIVE

HDTE/I

1ST BIT

DDTE/I

2ND BIT

DDTLFSE

NOTES

1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS. THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.

Figure 20. External Late Frame Sync

This figure reflects changes made to support left-justified sample pair mode.

Rev. C | Page 32 of 52 | September 2009

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ADSP-21371/ADSP-21375

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

HOFSIR

NOTES

1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

HOFSI

HDTI

SCLKIW

DFSIR

SFSI

SDRI

DATA TRANSMIT—INTERNAL CLOCK

DDTI

SAMPLE EDGE

SFSI

DFSI

SCLKIW

HFSI

HDRI

HFSI

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA

CHANNEL A/B)

DRIVE EDGE SAMPLE EDGE

HOFSE

DRIVE EDGE SAMPLE EDGE

HOFSE

HDTE

DATA RECEIVE—EXTERNAL CLOCK

SCLKW

DFSE

SFSE

SDRE

DATA TRANSMIT—EXTERNAL CLOCK

SCLKW

DFSE

SFSE

DDTE

HFSE

HDRE

HFSE

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA

CHANNEL A/B)

NOTES

1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DDTIN

DDTEN

SCLK

DRIVE EDGE

DDTTE

Figure 21. Serial Ports

Rev. C | Page 33 of 52 | September 2009

Page 34

ADSP-21371/ADSP-21375

DAI_P20–1

(SERIAL CLOCK)

SAMPLE EDGE

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA)

IPDCLK

IPDCLKW

SISFS

SIHFS

SIHD

SISD

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 31. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 31. Input Data Port (IDP)

1.2 V, 266 MHz

Parameter Min Max Unit

Timing Requirements

SISFS

SIHFS

SISD

SIHD

IDPCLKW

IDPCLK

The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either

CLKIN or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge 3.8 ns Frame Sync Hold After Serial Clock Rising Edge 2.5 ns Data Setup Before Serial Clock Rising Edge 2.5 ns Data Hold After Serial Clock Rising Edge 2.5 ns Clock Width (t Clock Period t

× 4) ÷ 2 – 1 ns

PCLK

× 4 ns

PCLK

Figure 22. IDP Master Timing

Rev. C | Page 34 of 52 | September 2009

Page 35

ADSP-21371/ADSP-21375

DATA

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_CLKEN)

DAI_P20–1

(PDAP_STROBE)

PDSTRB

PDHLDD

PDHD

PDSD

SPCLKEN

HPCLKEN

PDCLK

PDCLKW

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 32. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the PDAP chapter of the ADSP-2137x SHARC Processor Hardware

Note that the 20-bits of external PDAP data can be provided through the external port DATA31–12 pins. On the ADSP-21375 processors, PDAP can not be multiplexed on the external port (since only DATA15–0). Use the SRU DAI instead.

Reference.

Table 32. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPCLKEN

HPCLKEN

PDSD

PDHD

PDCLKW

PDCLK

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge 3.85 ns PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge 2.5 ns Clock Width (t Clock Period t

× 4) ÷ 2 – 3 ns

PCLK

× 4 ns

PCLK

Switching Characteristics

PDHLDD

PDSTRIB

Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t PDAP Strobe Pulse Width 2 × t

+ 3 ns

PCLK

– 1 ns

PCLK

Rev. C | Page 35 of 52 | September 2009

Figure 23. PDAP Timing

Page 36

ADSP-21371/ADSP-21375

PWM

OUTPUTS

PWMW

PWMP

Pulse-Width Modulation Generators (PWM)

For the ADSP-21371, the following timing specifications apply

Pulse-width modulation generator information does not apply to the ADSP-21375.

when the DATA31–16 pins are configured as PWM.

Table 33. Pulse-Width Modulation (PWM) Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWMP

PWM Output Pulse Width t

PCLK

PWM Output Period 2 × t

Figure 24. PWM Timing

– 2.5 (216 – 2) × t

– 2.5 (216 – 1) × t

PCLK

– 2.5 ns

PCLK

– 2.5 ns

PCLK

Rev. C | Page 36 of 52 | September 2009

Page 37

ADSP-21371/ADSP-21375

MSB

LEFT CHANNEL

RIGHT CHANNEL

LSB LSB

MSB – 1

MSB – 2

MSB

MSB – 1

MSB – 2

LSB + 2

LSB + 1

LSB

LSB + 2

LSB + 1

DAI_P20–1

LRCLK

DAI_P20–1

SCLK

DAI_P20–1

SDATA

LEFT CHANNEL

RIGHT CHANNEL

LSB

MSB – 1

MSB – 2

LSB + 2

LSB + 1

MSBMSBLSB

MSB – 1

MSB – 2

LSB + 2

LSB + 1

DAI_P20–1

LRCLK

DAI_P20–1

SCLK

DAI_P20–1

SDATA

MSB

LEFT CHANNEL

RIGHT CHANNEL

MSB LSB

MSB – 1

MSB – 2

MSB

MSB – 1

MSB

MSB + 1

MSB – 2

LSB + 2

LSB + 1

LSB

LSB + 2

LSB + 1

DAI_P20–1

LRCLK

DAI_P20–1

SCLK

DAI_P20–1

SDATA

S/PDIF Transmitter

For the ADSP-21371, serial data input to the S/PDIF transmitter can be formatted as left-justified, I

S, or right-justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 25 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit

Figure 25. Right-Justified Mode

output mode) from an LRCLK transition, so that when there are 64 serial clock periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.

S/PDIF transmitter information does not apply to the ADSP-21375.

Figure 26 shows the default I

S-justified mode. LRCLK is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to an LRCLK transition but with a single serial clock period delay.

Figure 27 shows the left-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to an LRCLK transition with no MSB delay.

Figure 26. I

S-Justified Mode

Figure 27. Left-Justified Mode

Rev. C | Page 37 of 52 | September 2009

Page 38

ADSP-21371/ADSP-21375

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SERIAL CLOCK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA)

SITXCLKW

SITXCLK

SISCLKW

SISCLK

SISFS

SIHFS

SISD

SIHD

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given in Table 34. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 34. S/PDIF Transmitter Input Data Timing

1.2 V, 266 MHz

Parameter Min Max Unit

Timing Requirements

SISFS

SIHRS

SISD

SIHD

SITXCLKW

SITXCLK

SISCLKW

SISCLK

The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN

or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge 3 ns Frame Sync Hold After Serial Clock Rising Edge 3 ns Data Setup Before Serial Clock Rising Edge 3 ns Data Hold After Serial Clock Rising Edge 3 ns Transmit Clock Width 9 ns Transmit Clock Period 20 ns Clock Width 36 ns Clock Period 80 ns

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock.

Table 35. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Max Unit

TxCLK Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync <= 1/t TxCLK Frequency for TxCLK = 256 × Frame Sync 49.2 MHz Frame Rate (FS) 192.0 kHz

Figure 28. S/PDIF Transmitter Input Timing

Rev. C | Page 38 of 52 | September 2009

SITXCLK

MHz

Page 39

ADSP-21371/ADSP-21375

DAI_P20–1

(SERIAL CLOCK)

SAMPLE EDGE

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

SCLKIW

DFSI

HOFSI

DDTI

HDTI

S/PDIF Receiver

For the ADSP-21371, the following section describes timing as it relates to the S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × Frame Sync clock. The S/PDIF receiver information does not apply to the ADSP-21375.

Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing

1.2 V, 266 MHz

Parameter Min Max Unit

Switching Characteristics

DFSI

HOFSI

DDTI

HDTI

SCLKIW

Serial lock frequency is 64 × Frame Sync where FS = the frequency of LRCLK.

LRCLK Delay After Serial Clock 5 ns LRCLK Hold After Serial Clock –2 ns Transmit Data Delay After Serial Clock 5 ns Transmit Data Hold After Serial Clock –2 ns Transmit Serial Clock Width 38.5 ns

Figure 29. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. C | Page 39 of 52 | September 2009

Page 40

ADSP-21371/ADSP-21375

SPICHM

SDSCIM

SPICLM

SPICLKM

HDSM

SPITDM

SPICLM

SPICHM

MSB

VALID

LSB VALIDMSB VALID

LSB

LSBMSB

MSB

DDSPIDM

HSPIDM

SSPIDM

LSB VALID

FLAG3–0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

HDSPIDM

HSPIDM

SSPIDM

DDSPIDM

HDSPIDM

SPI Interface—Master

The processor contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in

Table 37 and Table 38 applies to both.

Table 37. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SSPIDM

HSPIDM

Switching Characteristics

SPICLKM

SPICHM

SPICLM

DDSPIDM

HDSPIDM

SDSCIM

HDSM

SPITDM

Data Input Valid To SPICLK Edge (Data Input Setup Time) 8.2 ns SPICLK Last Sampling Edge To Data Input Not Valid 2 ns

Serial Clock Cycle 8 × t Serial Clock High Period 4 × t Serial Clock Low Period 4 × t

– 2 ns

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t FLAG3–0IN (SPI device select) Low to First SPICLK Edge 4 × t Last SPICLK Edge to FLAG3–0IN High 4 × t Sequential Transfer Delay 4 × t

– 2 ns

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

– 1 ns

PCLK

Figure 30. SPI Master Timing

Rev. C | Page 40 of 52 | September 2009

Page 41

ADSP-21371/ADSP-21375

SPICHS

SPICLS

SPICLKS

HDS

SDPPW

SDSCO

SPICLS

SPICHS

DSOE

DDSPIDS

DSDHI

HDSPIDS

HSPIDS

SSPIDS

MSB VALID

LSB VALIDMSB VALID

SSPIDS

LSB

MSB

DSDHI

DDSPIDS

DSOV

HSPIDS

SSPIDS

HDSPIDS

LSB VALID

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

SPI Interface—Slave

Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications

1.2 V, 266 MHz

Parameter Min Max Unit

Timing Requirements

SPICLKS

SPICHS

SPICLS

SDSCO

HDS

SSPIDS

HSPIDS

SDPPW

Switching Characteristics

DSOE

DSDHI

DDSPIDS

HDSPIDS

DSOV

Serial Clock Cycle 4 × t Serial Clock High Period 2 × t Serial Clock Low Period 2 × t SPIDS Assertion to First SPICLK Edge

CPHASE = 0 CPHASE = 1

Last SPICLK Edge to SPIDS Not Asserted (CPHASE=0) 2 × t

– 2 ns

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

2 × t

PCLK

2 × t

PCLK

ns Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 ns SPICLK Last Sampling Edge to Data Input Not Valid 2 ns SPIDS Deassertion Pulse Width (CPHASE=0) 2 × t

PCLK

SPIDS Assertion to Data Out Active 0 6.8 ns SPIDS Deassertion to Data High Impedance 0 6.8 ns SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

Figure 31. SPI Slave Timing

Rev. C | Page 41 of 52 | September 2009

Page 42

ADSP-21371/ADSP-21375

DPI_P14–1

[RxD]

DPI_P14–1

[TxD]

DATA (5–8)

INTERNAL

UART RECEIVE

INTERRUPT

INTERNAL

UART TRANSMIT

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

START

STOP

STOP (1–2)

RXD

TXD

RECEIVE

TRANSMIT

Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing

Figure 32 describes UART port receive and transmit operations.

The maximum baud rate is PCLK/16 where PCLK = 1/t

PCLK

. As

generation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.

shown in Figure 32 there is some latency between the

Table 39. UART Port

Parameter Min Max Unit

Timing Requirement

TXD

Incoming Data Pulse Width 16t

–1 ns

PCLK

Switching Characteristic

RXD

UART signals TXD and RXD are routed through DPI P14-1 pins using the SRU.

Incoming Data Pulse Width 16t

–1 ns

PCLK

Figure 32. UART Port—Receive and Transmit Timing

Rev. C | Page 42 of 52 | September 2009

Page 43

TWI Controller Timing

Table 40 and Figure 33 provide timing information for the TWI

interface. Input signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins.

ADSP-21371/ADSP-21375

Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices

Standard Mode Fast Mode

Parameter

SCL

Hold Time (repeated) Start Condition. After This

HDSTA

SCL Clock Frequency 0 100 0 400 kHz

Min Max Min Max Unit

Period, the First Clock Pulse is Generated. 4.0 0.6 μs

Low Period of the SCL Clock 4.7 1.3 μs

LOW

HIGH

Setup Time for a Repeated Start Condition 4.7 0.6 μs

SUSTA

Data Hold Time for TWI-Bus Devices 0 0 μs

HDDAT

Data Setup Time 250 100 ns

SUDAT

SUSTO

BUF

Pulse Width of Spikes Suppressed By the Input Filter n/a n/a 0 50 ns

All values referred to V

High Period of the SCL Clock 4.0 0.6 μs

Setup Time for Stop Condition 4.0 0.6 μs Bus Free Time Between a Stop and Start Condition 4.7 1.3 μs

IHmin

and V

DPI_P14–1

levels. For more information, see Electrical Characteristics on page 16.

ILmax

SDA

HIGH

SUDAT

SUSTA

SCL

LOW

HDSTA

HDDAT

HDSTA

SUSTO

BUF

PSS Sr

Figure 33. Fast and Standard Mode Timing on the TWI Bus

Rev. C | Page 43 of 52 | September 2009

Page 44

ADSP-21371/ADSP-21375

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

STAP

HTAP

DTDO

SSYS

HSYS

DSYS

JTAG Test Access Port and Emulation

Table 41. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

STAP

HTAP

SSYS

HSYS

TRSTW

Switching Characteristics

DTDO

DSYS

System Inputs = ADDR15–0, CLKCFG1–0, RESET, BOOT_CFG1–0, DAI_Px, and FLAG3–0.

System Outputs = DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.

TCK Period t

ns TDI, TMS Setup Before TCK High 5 ns TDI, TMS Hold After TCK High 6 ns System Inputs Setup Before TCK High 7 ns System Inputs Hold After TCK High 18 ns TRST Pulse Width 4 × t

TDO Delay from TCK Low 7 ns System Outputs Delay After TCK Low t

÷ 2 + 7 ns

Figure 34. IEEE 1149.1 JTAG Test Access Port

Rev. C | Page 44 of 52 | September 2009

Page 45

ADSP-21371/ADSP-21375

SWEEP ( V

DDEXT

)VOLTAGE(V)

0 3.50.5 1.0 1.5 2.0 2.5 3.0

3.11V, 125°C

3.3V, 25°C

3.47V,-45°C

3.11V, 125°C

3.3V, 25°C

3.47V,-45°C

OUTPUT

ȍ

LOAD

30pF

INPUT

OUTPUT

1.5V 1.5V

LOAD CAPACITANCE (pF)

100 250

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISE

FALL

y = 0.049x + 1.5105

y=0.0482x + 1.4604

OUTPUT DRIVE CURRENTS

Figure 35 shows typical I-V characteristics for the output driv-

ers of the processors. The curves represent the current drive capability of the output drivers as a function of output voltage.

) A m

( T N

E R R U C )

( E

C R U O

Figure 35. Typical Drive at Junction Temperature

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 15 on Page 21 through Table 41 on Page 44. These include

output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 36.

Timing is measured on signals when they cross the 1.5 V level as described in Figure 37. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 36). Figure 40 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 38, Figure 39, and Figure 40 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance.

)

(

E M

I T

L L A F

D N A

I R

Figure 38. Typical Output Rise/Fall Time (20% to 80%,

= Max)

DDEXT

)

(

E M

I T

L L A F

D N A E

I R

Figure 36. Equivalent Device Loading for AC Measurements

Figure 37. Voltage Reference Levels for AC Measurements

(Includes All Fixtures)

Figure 39. Typical Output Rise/Fall Time (20% to 80%,

Rev. C | Page 45 of 52 | September 2009

DDEXT

= Min)

Page 46

ADSP-21371/ADSP-21375

LOAD CAPACITANCE (pF)

0 20050 100 150

-4

-2

Y=0.0488X - 1.5923

TJT

CASE

×()+=

TJT

AθJAPD

×()+=

)

( D

L O H

R O

Y A L E D

T U P T U O

Figure 40. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

THERMAL CHARACTERISTICS

The processor is rated for performance over the temperature range specified in Operating Conditions on Page 16.

Table 42 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with JEDEC standard JESD51-7 (LQFP_EP). The junction-to-case measurement complies with MIL- STD-883. All measurements use a 2S2P JEDEC test board.

To determine the junction temperature of the device while on the application PCB, use

Values of θ

are provided for package comparison and PCB

design considerations. Note that the thermal characteristics values provided in Table 42 are modeled values.

Table 42. Thermal Characteristics for 208-Lead LQFP E_PAD (With Exposed Pad Soldered to PCB)

Parameter Condition Typical Unit

JMA

JMT

JMB

Airflow = 0 m/s 17.1 °C/W Airflow = 1 m/s 14.7 °C/W Airflow = 2 m/s 14.0 °C/W

9.6 °C/W Airflow = 0 m/s 0.23 °C/W Airflow = 1 m/s 0.39 °C/W Airflow = 2 m/s 0.45 °C/W Airflow = 0 m/s 11.5 °C/W Airflow = 1 m/s 11.2 °C/W Airflow = 2 m/s 11.0 °C/W

where:

= junction temperature °C

= case temperature (°C) measured at the top center of the

CASE

package

= junction-to-top (of package) characterization parameter

is the Typical value from Table 42.

= power dissipation

Values of θ design considerations. θ mation of T

where:

= ambient temperature °C

Values of θ design considerations when an external heatsink is required.

are provided for package comparison and PCB

by the equation

are provided for package comparison and PCB

can be used for a first order approxi-

Rev. C | Page 46 of 52 | September 2009

Page 47

ADSP-21371/ADSP-21375

208-LEAD LQFP_EP PINOUT

Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

DDINT

2 DATA28 54 GND 106 GND 158 V 3DATA27 55 V 4 GND 56 ADDR0 108 SDCAS 5V

DDEXT

6 DATA26 58 ADDR1 110 SDCKE 162 V 7 DATA25 59 ADDR4 111 SDWE 163 TDI 8 DATA24 60 ADDR3 112 WR 9 DATA23 61 ADDR5 113 SDA10 165 TCK 10 GND 62 GND 114 GND 166 GND 11 V

DDINT

12 DATA22 64 GND 116 SDCLK 168 TMS 13 DATA21 65 V 14 DATA20 66 ADDR6 118 V 15 V

DDEXT

16 GND 68 ADDR8 120 ACK 172 EMU 17 DATA19 69 ADDR9 121 FLAG3 173 BOOT_CFG1 18 DATA18 70 ADDR10 122 FLAG2 174 TDO 19 V

DDINT

20 GND 72 V 21 DATA17 73 GND 125 DAI_P20 (SFS5) 177 DAI_P3 (SCLK0) 22 V

DDINT

23 GND 75 ADDR11 127 V 24 V

DDINT

25 GND 77 ADDR13 129 V 26 DATA16 78 GND 130 DAI_P19 (SCLK5) 182 GND 27 DATA15 79 V 28 DATA14 80 NC 132 DAI_P17 (SD5A) 184 DPI_P13 (TIMER0) 29 DATA13 81 NC 133 DAI_P16 (SD4B) 185 DPI_P12 (TWI_CLK) 30 DATA12 82 GND 134 DAI_P15 (SD4A) 186 DPI_P11 (TWI_DATA) 31 V

DDEXT

32 GND 84 XTAL 136 DAI_P13 (SCLK3) 188 DPI_P09 (UART0TX) 33 V

DDINT

34 GND 86 GND 138 V 35 DATA11 87 V 36 DATA10 88 ADDR14 140 GND 192 GND 37 DATA9 89 GND 141 V 38 DATA8 90 V 39 DATA7 91 ADDR15 143 DAI_P11 (SD3A) 195 DPI_P06 (SPIFLG1) 40 DATA6 92 ADDR16 144 DAI_P10 (SD2B) 196 DPI_P05 (SPIFLG0) 41 V

DDEXT

42 GND 94 ADDR18 146 DAI_P9 (SD2A) 198 DPI_P03 (SPICLK) 43 V

DDINT

44 DATA4 96 V

53 V

DDINT

DDEXT

57 ADDR2 109 SDRAS 161 V

105 V

107 V

DDINT

DDEXT

157 V

DDINT

159 GND 160 V

DDINT

164 TRST

63 V

DDINT

DDEXT

115 V

DDEXT

167 V

DDINT

117 GND 169 CLK_CFG0

DDINT

170 BOOT_CFG0

67 ADDR7 119 RD 171 CLK_CFG1

71 GND 123 FLAG1 175 DAI_P4 (SFS0)

124 FLAG0 176 DAI_P2 (SD0B)

126 GND 178 DAI_P1 (SD0A)

DDINT

179 V

DDEXT

74 V

DDINT

DDEXT

76 ADDR12 128 GND 180 GND

181 V

DDINT

DDEXT

131 DAI_P18 (SD5B) 183 DPI_P14 (TIMER1)

83 CLKIN 135 DAI_P14 (SFS3) 187 DPI_P10 (UART0RX)

85 V

DDEXT

DDINT

DDEXT

137 DAI_P12 (SD3B) 189 DPI_P08 (SPIFLG3)

190 DPI_P07 (SPIFLG2) 191 V

193 V

DDEXT

DDINT

139 V

DDINT

DDEXT

DDINT

142 GND 194 GND

93 ADDR17 145 DAI_P8 (SFS1) 197 DPI_P04 (SPIDS)

95 GND 147 DAI_P6 (SD1B) 199 DPI_P01 (SPIMOSI)

DDEXT

148 DAI_P7 (SCLK1) 200 DPI_P02 (SPIMISO)

Rev. C | Page 47 of 52 | September 2009

Page 48

ADSP-21371/ADSP-21375

Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

45 DATA5 97 ADDR19 149 DAI_P5 (SD1A) 201 RESETOUT/

RUNRSTIN

46 DATA2 98 ADDR20 150 V

DDEXT

47 DATA3 99 ADDR21 151 GND 203 V 48 DATA0 100 ADDR23 152 V

DDINT

49 DATA1 101 ADDR22 153 GND 205 DATA30 50 V

DDEXT

51 GND 103 MS0 52 V

DDINT

102 MS1 154 V

155 GND 207 DATA29

104 V

DDINT

156 V

DDINT

202 RESET

DDEXT

204 GND

206 DATA31

208 V

DDINT

Rev. C | Page 48 of 52 | September 2009

Page 49

ADSP-21371/ADSP-21375

Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

DDINT

2NC 54GND 106GND 158V 3NC 55V 4 GND 56 ADDR0 108 SDCAS 5V

DDEXT

6NC 58ADDR1 110SDCKE 162V 7NC 59ADDR4 111SDWE 163 TDI 8NC 60ADDR3 112WR 9 NC 61 ADDR5 113 SDA10 165 TCK 10 GND 62 GND 114 GND 166 GND 11 V

DDINT

12 NC 64 GND 116 SDCLK 168 TMS 13 NC 65 V 14 NC 66 ADDR6 118 V 15 NC 67 ADDR7 119 RD 16 NC 68 ADDR8 120 ACK 172 EMU 17 NC 69 ADDR9 121 FLAG3 173 BOOT_CFG1 18 NC 70 ADDR10 122 FLAG2 174 TDO 19 NC 71 GND 123 FLAG1 175 DAI_P4 (SFS0) 20 NC 72 V 21 NC 73 GND 125 DAI_P20 (SFS5) 177 DAI_P3 (SCLK0) 22 V

DDINT

23 GND 75 ADDR11 127 V 24 V

DDINT

25 GND 77 ADDR13 129 V 26 NC 78 GND 130 DAI_P19 (SCLK5) 182 GND 27 DATA15 79 V 28 DATA14 80 NC 132 DAI_P17 (SD5A) 184 DPI_P13 (TIMER0) 29 DATA13 81 NC 133 DAI_P16 (SD4B) 185 DPI_P12 (TWI_CLK) 30 DATA12 82 GND 134 DAI_P15 (SD4A) 186 DPI_P11 (TWI_DATA) 31 V

DDEXT

32 GND 84 XTAL 136 DAI_P13 (SCLK3) 188 DPI_P09 (UART0TX) 33 V

DDINT

DDEXT

42 GND 94 ADDR18 146 DAI_P9 (SD2A) 198 DPI_P03 (SPICLK) 43 V

DDINT

44 DATA4 96 V

53 V

DDINT

DDEXT

57 ADDR2 109 SDRAS 161 V

105 V

107 V

DDINT

DDEXT

157 V

DDINT

159 GND 160 V

DDINT

164 TRST

63 V

DDINT

DDEXT

115 V

DDEXT

167 V

DDINT

117 GND 169 CLK_CFG0

DDINT

170 BOOT_CFG0 171 CLK_CFG1

124 FLAG0 176 DAI_P2 (SD0B)

126 GND 178 DAI_P1 (SD0A)

DDINT

179 V

DDEXT

74 V

DDINT

DDEXT

76 ADDR12 128 GND 180 GND

181 V

DDINT

DDEXT

131 DAI_P18 (SD5B) 183 DPI_P14 (TIMER1)

83 CLKIN 135 DAI_P14 (SFS3) 187 DPI_P10 (UART0RX)

85 V

DDEXT

DDINT

DDEXT

137 DAI_P12 (SD3B) 189 DPI_P08 (SPIFLG3)

190 DPI_P07 (SPIFLG2) 191 V

193 V

DDEXT

DDINT

139 V

DDINT

DDEXT

DDINT

142 GND 194 GND

93 ADDR17 145 DAI_P8 (SFS1) 197 DPI_P04 (SPIDS)

95 GND 147 DAI_P6 (SD1B) 199 DPI_P01 (SPIMOSI)

DDEXT

148 DAI_P7 (SCLK1) 200 DPI_P02 (SPIMISO)

Rev. C | Page 49 of 52 | September 2009

Page 50

ADSP-21371/ADSP-21375

Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

45 DATA5 97 ADDR19 149 DAI_P5 (SD1A) 201 RESETOUT/

RUNRSTIN

46 DATA2 98 ADDR20 150 V

DDEXT

47 DATA3 99 ADDR21 151 GND 203 V 48 DATA0 100 ADDR23 152 V

DDINT

49 DATA1 101 ADDR22 153 GND 205 DATA30 50 V

DDEXT

51 GND 103 MS0 52 V

DDINT

102 MS1 154 V

155 GND 207 DATA29

104 V

DDINT

156 V

DDINT

202 RESET

DDEXT

204 GND

206 DATA31

208 V

DDINT

Rev. C | Page 50 of 52 | September 2009

Page 51

PACKAGE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD

NOTE:

THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO GND.

THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS THE SAME SIZE

AS THE EXPOSED PAD. THE GND PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN THE PCB WITH AN ARRAY OF THERMAL V

IAS FOR BEST PERFORMANCE.

0.15

0.10

0.05

0.08

COPLANARITY

0.20

0.15

0.09

1.45

1.40

1.35

7°

3.5°

0°

VIEW A

ROTATED 90° CCW

0.27

0.22

0.17

0.75

0.60

0.45

0.50 BSC

LEAD PITCH

28.10

28.00 SQ

27.90

30.20

30.00 SQ

29.80

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

105

104

105

104

156

208

157

156

157

PIN 1

1.60 MAX

1.00 REF

SEATING

PLANE

VIEW A

8.890 REF

8.712 REF

25.50 REF

The processors are available in a 208-lead RoHS compliant LQFP_EP package.

ADSP-21371/ADSP-21375

Figure 41. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-208-1)

Dimensions shown in millimeters

Rev. C | Page 51 of 52 | September 2009

Page 52

ADSP-21371/ADSP-21375

AUTOMOTIVE PRODUCTS

Some ADSP-21371/ADSP-21375 models are available for automotive applications with controlled manufacturing. Note that this special model may have specifications that differ from the general release models.

Table 45. Automotive Products

The automotive grade products shown in Table 45 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant.

Model

Tem p er at u re

Range

Instruction Rate

On-Chip SRAM ROM Package Description Package Option

AD21371WBSWZ2xx –40ºC to 85ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1

AD21371WYSWZ1xx –40ºC to 105ºC 200 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1

AD21375WBSWZ2xx –40ºC to 85ºC 266 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1

AD21375WYSWZ1xx –40ºC to 105ºC 200 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1

Referenced temperature is ambient temperature.

ORDERING GUIDE

Tem p er at u re

Model

ADSP-21371KSWZ-2A ADSP-21371KSWZ-2B ADSP-21371BSWZ-2B ADSP-21375KSWZ-2B ADSP-21375BSWZ-2B

Referenced temperature is ambient temperature.

Z = RoHS Compliant Part

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software.

For a complete list, visit our website at www.analog.com/SHARC

2, 3

Range

0ºC to +70ºC 200 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1 0ºC to +70ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1

-40ºC to +85ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1 0ºC to +70ºC 266 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1

-40ºC to +85ºC 266 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1

Instruction Rate

On-Chip SRAM ROM Package Description Package Option

D07170-0-9/09(C)

Rev. C | Page 52 of 52 | September 2009

Datasheet ADSP-21371, ADSP-21375 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

SUMMARY

DEDICATED AUDIO COMPONENTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SHARC FAMILY CORE ARCHITECTURE

SIMD Computational Engine

Independent, Parallel Computation Units

Data Register File

Context Switch

Universal Registers

Tim er

Single-Cycle Fetch of an Instruction and Four Operands

Instruction Cache

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

Flexible Instruction Set

On-Chip Memory

On-Chip Memory Bandwidth

ROM-Based Security

FAMILY PERIPHERAL ARCHITECTURE

External Port

SDRAM Controller

External Memory Code Execution

External Port Throughput

Asynchronous Memory Controller

Pulse-Width Modulation

Digital Applications Interface (DAI)

Serial Ports

S/PDIF-Compatible Digital Audio Receiver/Transmitter

Input Data Port (IDP)

Precision Clock Generator (PCG)

Digital Peripheral Interface (DPI)

Serial Peripheral (Compatible) Interface

UART Port

Peripheral Timers

2-Wire Interface Port (TWI)

I/O PROCESSOR FEATURES

DMA Controller

Delay Line DMA

Scatter/Gather DMA

SYSTEM DESIGN

Program Booting

Power Supplies

Target Board JTAG Emulator Connector

DEVELOPMENT TOOLS

Evaluation Kit

ADDITIONAL INFORMATION

Designing an Emulator-Compatible DSP Board (Target)

PIN FUNCTION DESCRIPTIONS

ADSP-21371/ADSP-21375 SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PACKAGE INFORMATION

MAXIMUM POWER DISSIPATION

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

Core Clock Requirements

Voltage Controlled Oscillator

Power-Up Sequencing

Clock Input

Clock Signals

RESET

Running Reset

Core Timer

Interrupts

Timer PWM_OUT Cycle Timing

Timer W DTH_CAP Timing

Pin to Pin Direct Routing (DAI and DPI)

Precision Clock Generator (Direct Pin Routing)

Flags

SDRAM Interface Timing

Serial Ports

Input Data Port (IDP)

Parallel Data Acquisition Port (PDAP)

Pulse-Width Modulation Generators (PWM)