Datasheet ADSP-21367 Datasheet (Analog Devices)

a

SHARC® Processor

Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance automotive audio
processing

Audio decoder and post processor-algorithm support with

32-bit floating-point implementations
Non-volatile memory may be configured to support audio

decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby
headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,
MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and Multi­channel encoder. Functions like Bass management, Delay,
Speaker equalization, Graphic equalization, Decoder/post-

COREPROCESSOR

INSTRUCTION

CACHE

32 X48-BIT

PROGRAM

SE QUENCER

DAG1

8X4X32

PROC ESSING

EL EMEN T

(P EX)

DAG2

8X 4X32

PROC ESSI NG

ELEMENT

(P EY)

TIMER

P X REG ISTER

ADSP-21367

processor algorithm combination support will vary
depending upon the chip version and the system configu­rations. Please visit www.analog.com

Single-Instruction Multiple-Data (SIMD) computational

architecture

On-chip memory—2M bit of on-chip SRAM and a dedicated

6M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367 is available with a 400 MHz core instruction

rate with unique audio centric peripherals such as the Digi-

tal Audio Interface, S/PDIF transceiver, serial ports, 8-

channel asynchronous sample rate converter, precision

clock generators and more. For complete ordering infor-

mation, see Ordering Guide on page 47

JTAG TEST & EMULATIO N

4 BLOCKS OF

ON-CHIPMEMORY

2 M B IT R AM , 6 M BI T ROM

ADDR DATA

IOA(24)

IOP REGISTER ( MEMORY MAP PED )

CO NTROL, STATUS, & DATA BUFFERS

IOD(32)

EXTERNAL PORT

SDRAM

CONTROLLER

ASYNCHRONOUS

ME MO RY

INTERFACE

DMA

CONTROLLER

34 CHANNE LS

S

8

N

I
P

L
O
R

3

T
N
O
C

32 PM ADDRESS BUS

32

DMADDRESS BUS

64

PM DATA BUS

64

DM DATA BUS

ME M ORY -T O-

ME M ORY DM A (2 )

24

ADDRE SS

11

CONTROL

32

DATA

PWM (16)

4

GPI O FLAGS/

IRQ/TIMEXP

S

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

PREC ISI ON CL OCK

GENERATORS(4)

SRC (8 CHANNELS)

SPDIF(RX/TX)

DIGITAL AUDIO INTERFACE

DAI ROUTINGUNIT

SERIAL PORTS (8)

INPUT DATA PORT/

PDAP

DA I PIN S

20

Figure 1. Functional Block Diagram – Processor Core

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:[phone] www.analog.com
Fax:[phone] © 2004 Analog Devices, Inc. All rights reserved.

SPIPORT(2)

TWO WIRE

INTERFACE

DPI PINS

DI GI TAL PER IP HE RAL I NTE RF ACE

14

DPI ROUTING UNIT

I/O PROCESSOR

UART (2)

TIMERS (3)

ADSP-21367 Preliminary Technical Data

KEY FEATURES – PROCESSOR CORE

At 400 MHz (2.5 ns) core instruction rate, the ADSP-21367

performs 2.4 GFLOPS/800 MMACS

2M bit on-chip SRAM (0.75M Bit in blocks 0 and 1, and 250K

Bit in blocks 2 and 3) for simultaneous access by the core
processor and DMA

6M bit on-chip mask-programmable ROM (3M bit in block 0

and 3M bit in block 1)

Dual Data Address Generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at

the assembly level

Parallelism in busses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch

Transfers between memory and core at a sustained 6.0G

bytes/s bandwidth at 400 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA Controller supports:

34 zero-overhead DMA channels for transfers between

ADSP-21367 internal memory and a variety of
peripherals

32-bit DMA transfers at core clock speed, in parallel with

full-speed processor execution

32-Bit Wide External Port Provides Glueless Connection to

both Synchronous (SDRAM) and Asynchronous Memory
Devices

Programmable wait state options: 2 to 31 SCLK cycles
Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 166MHz and Asynchronous accesses at

66MHz

4 Memory Select lines allows multiple external memory

devices

Digital Audio Interface (DAI) includes eight serial ports, four

Precision Clock Generators, an Input Data Port, an S/PDIF
transceiver, an 8-channel asynchronous sample rate con­verter, and a Signal Routing Unit

Digital Peripheral Interface (DPI) includes, three timers, two

UARTs, two SPI ports, and a two wire interface port
Outputs of PCG's C and D can be driven on to DPI pins

Eight dual data line serial ports that operate at up to 50M

bits/s on each data line — each has a clock, frame sync and
two data lines that can be configured as either a receiver or
transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces
such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per

frame
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data

or seven channels of serial data and a single channel of up

to a 20-bit wide parallel data
Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components
2 Muxed Flag/IRQ
1 Muxed Flag/Timer expired line /MS
1 Muxed Flag/IRQ

lines

pin

/MS pin

DEDICATED AUDIO COMPONENTS

S/PDIF Compatible Digital Audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I

16, 18, 20 or 24-bit word widths (transmitter)
Sample Rate Converter (SRC) contains a Serial Input Port, De-

emphasis Filter, Sample Rate Converter (SRC) and Serial

Output Port providing up to -128db SNR performance.

Supports Left Justified, I

18 and 16-bit serial formats (input)
Pulse Width Modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms
ROM Based Security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios
Dual voltage: 3.3 V I/O, 1.3 V core
Available in 256-ball BGA and 208-lead LQFP Packages (see

Ordering Guide on page 47)

2

S or right-justified serial data input with

2

S, TDM and Right Justified 24, 20,

Rev. PrA | Page 2 of 48 | November 2004

TABLE OF CONTENTS

ADSP-21367Preliminary Technical Data

Summary ............................................................... 1

Key Features – Processor Core ................................. 2

Input/Output Features ........................................... 2

Dedicated Audio Components ................................. 2

General Description ................................................. 4

ADSP-21367 Family Core Architecture ...................... 4

SIMD Computational Engine ............................... 4

Independent, Parallel Computation Units ................ 4

Data Register File ............................................... 5

Single-Cycle Fetch of Instruction and Four Operands . 5

Instruction Cache .............................................. 5

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support .................................... 5

Flexible Instruction Set ....................................... 6

ADSP-21367 Memory ............................................ 6

On-Chip Memory .............................................. 6

External Memory .................................................. 6

SDRAM Controller ............................................ 7

Asynchronous Controller .................................... 7

ADSP-21367 Input/Output Features .......................... 7

DMA Controller ................................................ 7

Digital Audio Interface (DAI) ............................... 7

Serial Ports ....................................................... 8

S/PDIF Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample

Rate Converter ............................................... 8

Digital Peripheral Interface (DPI) .......................... 8

Serial Peripheral (Compatible) Interface .................. 8

UART Port ...................................................... 8

Timers ............................................................ 9

Two Wire Interface Port (TWI) ............................. 9

Pulse Width Modulation ..................................... 9

ROM Based Security ........................................... 9

System Design ...................................................... 9

Program Booting .............................................. 10

Power Supplies ................................................. 10

Target Board JTAG Emulator Connector ................ 10

Development Tools .............................................. 10

Designing an Emulator-Compatible DSP

Board(Target) .............................................. 11

Evaluation Kit .................................................. 11

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Address Data Modes ............................................ 14

Boot Modes ....................................................... 14

Core Instruction Rate to CLKIN Ratio Modes ............ 14

ADSP-21367 Specifications ....................................... 15

Recommended Operating Conditions ...................... 15

Electrical Characteristics ....................................... 15

Absolute Maximum Ratings ................................... 16

ESD Sensitivity ................................................... 16

Timing Specifications ........................................... 16

Power-Up Sequencing ....................................... 18

Clock Input .................................................... 19

Clock Signals ................................................... 19

Reset ............................................................. 20

Interrupts ....................................................... 20

Core Timer ..................................................... 21

Timer PWM_OUT Cycle Timing ......................... 21

Timer WDTH_CAP Timing ............................... 22

DAI and DPI Pin to Pin Direct Routing ................. 22

Precision Clock Generator (Direct Pin Routing) ...... 23

Flags ............................................................. 24

SDRAM Interface Timing .................................. 25

External Port Bus Request and Grant Cycle Timing .. 26

Serial Ports ..................................................... 27

Input Data Port ............................................... 30

Parallel Data Acquisition Port (PDAP) .................. 31

Sample Rate Converter—Serial Input Port .............. 32

Sample Rate Converter—Serial Output Port ........... 33

SPDIF Transmitter ........................................... 34

SPDIF Receiver ................................................ 36

SPI Interface—Master ....................................... 38

SPI Interface—Slave .......................................... 39

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 40

JTAG Test Access Port and Emulation .................. 41

Output Drive Currents ......................................... 42

Test Conditions .................................................. 42

Capacitive Loading .............................................. 42

Thermal Characteristics ........................................ 43

Ordering Guide ..................................................... 45

Rev. PrA | Page 3 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-21367 SHARC processor is a members of the SIMD
SHARC family of DSPs that feature Analog Devices' Super Har­vard Architecture. The ADSP-21367 is source code compatible
with the ADSP-2126x, and ADSP-2116x, DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin­gle-Instruction, Single-Data) mode. The ADSP-21367 is a 32­bit/40-bit floating point processors optimized for high perfor­mance automotive audio applications with its large on-chip
SRAM and mask-programmable ROM, multiple internal buses
to eliminate I/O bottlenecks, and an innovative Digital Audio
Interface (DAI).

As shown in the functional block diagram on page 1, the
ADSP-21367 uses two computational units to deliver a signifi­cant performance increase over the previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21367 processor achieves
an instruction cycle time of 2.5 ns at 400 MHz. With its SIMD
computational hardware, the ADSP-21367 can perform 2.4
GFLOPS running at 400 MHz.

Table 1 shows performance benchmarks for the ADSP-21367.

Table 1. ADSP-21367 Benchmarks (at 400 MHz)

Benchmark Algorithm Speed

(at 400 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 23.25 µs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)

[3x3] × [3x1]
[4x4] × [4x1]

Divide (y/×) 8.75 ns
Inverse Square Root 13.5 ns

1

Assumes two files in multichannel SIMD mode

1

1

1.25 ns

5.0 ns

11.25 ns

20.0 ns

The ADSP-21367 continues SHARC’s industry leading stan­dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21367 on page 1, illustrates the
following architectural features:

• Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

• Three Programmable Interval Timers with PWM Genera­tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities

•On-Chip SRAM (2M bit)

• On-Chip mask-programmable ROM (6M bit)

• JTAG test access port

The block diagram of the ADSP-21367 on page 1 also illustrates
the following architectural features:

• DMA controller

• Eight full duplex serial ports

• Two SPI-compatible interface ports

• Digital Audio Interface that includes four precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, eight serial ports, eight serial interfaces, a
20-bit parallel input port, a flexible signal routing unit
(SRU), and a Digital Peripheral Interface (DPI)

ADSP-21367 FAMILY CORE ARCHITECTURE

The ADSP-21367 is code compatible at the assembly level with
the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The ADSP­21367 shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC processors, as detailed in the fol­lowing sections.

SIMD Computational Engine

The ADSP-21367 contains two computational processing ele­ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg­ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro­cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is trans­ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-

Rev. PrA | Page 4 of 48 | November 2004

ADSP-21367Preliminary Technical Data

ments. These computation units support IEEE 32-bit single­precision floating-point, 40-bit extended precision floating­point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro­cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har­vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21367 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 1 on page 1). With the ADSP-21367’s separate pro­gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin­gle cycle.

Instruction Cache

The ADSP-21367 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

The ADSP-21367’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program­ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21367 contain

sufficient registers to allow the creation of up to 32 circular buff­ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over­head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21367 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch­ing up to four 32-bit values from memory—all in a single
instruction.

ADSP-21367 MEMORY

The ADSP-21367 adds the following architectural features to
the SIMD SHARC family core.

On-Chip Memory

The ADSP-21367 contains two megabits of internal RAM and
six megabits of internal mask-programmable ROM. Each block
can be configured for different combinations of code and data
storage (see Table 2). Each memory block supports single-cycle,
independent accesses by the core processor and I/O processor.
The ADSP-21367 memory architecture, in combination with its
separate on-chip buses, allow two data transfers from the core
and one from the I/O processor, in a single cycle.

The ADSP-21367’s, SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ­ent word sizes up to three megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float­ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for­mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Table 2. ADSP-21367 Internal Memory Space

IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits) Extended Precision Normal or

Instruction Word (48 bits)

BLOCK 0 ROM
0x0004 0000–0x0004 BFFF

Reserved
0x0004 F000–0x0004 FFFF

BLOCK 0 RAM
0x0004 C000–0x0004 EFFF

BLOCK 1 ROM
0x0005 0000–0x0005 BFFF

BLOCK 0 ROM
0x0008 0000–0x0008 FFFF

Reserved
0x0009 4000–0x0009 FFFF

BLOCK 0 RAM
0x0009 0000–0x0009 3FFF

BLOCK 1 ROM
0x000A 0000–0x000A FFFF

Rev. PrA | Page 5 of 48 | November 2004

Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM
0x0008 0000–0x0009 7FFF

Reserved
0x0009 E0000–0x0009 FFFF

BLOCK 0 RAM
0x0009 8000–0x0009 DFFF

BLOCK 1 ROM
0x000A 0000– 0x000B 7FFF

BLOCK 0 ROM
0x0010 0000–0x0012 FFFF

Reserved
0x0013 C000–0x0013 FFFF

BLOCK 0 RAM
0x0013 0000–0x0013 BFFF

BLOCK 1 ROM
0x0014 0000–0x0016 FFFF

ADSP-21367 Preliminary Technical Data

Table 2. ADSP-21367 Internal Memory Space (Continued)

IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits) Extended Precision Normal or

Instruction Word (48 bits)

Reserved
0x0005 F000–0x0005 FFFF

BLOCK 1 RAM
0x0005 C000–0x0005 EFFF

BLOCK 2 RAM
0x0006 0000–0x0006 0FFF

Reserved
0x0006 1000– 0x0006 FFFF

BLOCK 3 RAM
0x0007 0000–0x0007 0FFF

Reserved
0x0007 1000– 0x0007 FFFF

Reserved
0x000B 4000–0x000B FFFF

BLOCK 1 RAM
0x000B 0000–0x000B 3FFF

BLOCK 2 RAM
0x000C 0000–0x000C 1554

Reserved
0x000C 1555–0x000C 3FFF

BLOCK 3 RAM
0x000E 0000–0x000E 1554

Reserved
0x000E 1555–0x000F FFFF

Normal Word (32 bits) Short Word (16 bits)

Reserved
0x000B E000– 0x000B FFFF

BLOCK 1 RAM
0x000B 8000–0x000B DFFF

BLOCK 2 RAM
0x000C 0000–0x000C 1FFF

Reserved
0x000C 2000–0x000D FFFF

BLOCK 3 RAM
0x000E 0000–0x000E 1FFF

Reserved
0x000E 2000–0x000F FFFF

Reserved
0x0017 C000–0x0017 FFFF

BLOCK 1 RAM
0x0017 0000–0x0017 BFFF

BLOCK 2 RAM
0x0018 0000–0x0018 3FFF

Reserved
0x0018 4000–0x001B FFFF

BLOCK 3 RAM
0x001C 0000–0x001C 3FFF

Reserved
0x001C 4000–0x001F FFFF

Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.

EXTERNAL MEMORY

The External Port on the ADSP-21367 SHARC provides a high
performance, glueless interface to a wide variety of industry­standard memory devices. The 32-bit wide bus may be used to
interface to synchronous and/or asynchronous memory devices
through the use of it's separate internal memory controllers: the
first is an SDRAM controller for connection of industry-stan­dard synchronous DRAM devices and DIMMs (Dual Inline
Memory Module), while the second is an asynchronous mem­ory controller intended to interface to a variety of memory
devices. Four memory select pins enable up to four separate
devices to coexist, supporting any desired combination of syn­chronous and asynchronous device types.

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa­rate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to f
each bank can has it's own memory select line (MS0
can be configured to contain between 16M bytes and
128M bytes of memory.

The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the different
banks.

A set of programmable timing parameters is available to config­ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as either 32 bits wide for max­imum performance and bandwidth or 16 bits wide for
minimum device count and lower system cost.

. Fully compliant with the SDRAM standard,

SCLK

–MS3), and

The SDRAM controller address, data, clock, and command pins
can drive loads up to 30 pF. For larger memory systems, the
SDRAM controller external buffer timing should be selected
and external buffering should be provided so that the load on
the SDRAM controller pins does not exceed 30 pF.

Asynchronous Controller

The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif­ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, and flash EPROM,
as well as I/O devices that interface with standard memory con­trol lines. Bank0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of
interfacing to a range of memories and I/O devices tailored
either to high performance or to low cost and power.

The asynchronous memory controller is capable of a maximum
throughput of 267M bytes/sec using a 66MHz external bus
speed. Other features include 8 to 32-bit and 16 to 32-bit pack­ing and unpacking, booting from Bank Select 1, and support for
delay line DMA.

ADSP-21367 INPUT/OUTPUT FEATURES

The ADSP-21367 I/O processor provides 34 channels of DMA,
as well as an extensive set of peripherals. These include a 20 pin
Digital Audio Interface which controls:

• Eight Serial ports

• S/PDIF Receiver/Transmitter

• Four Precision Clock generators

Rev. PrA | Page 6 of 48 | November 2004

ADSP-21367Preliminary Technical Data

• Four Sample Rate Converters

• Internal Data port/Parallel Data Acquisition port

The ADSP-21367 processor also contains a 14 pin Digital
Peripheral Interface which controls:

• Three general-purpose timers

• Two Serial Peripheral Interfaces

•Two Universal Asynchronous Receiver/Transmitters
(UARTs)

2

• A Two Wire Interface/I

C

DMA Controller

The ADSP-21367’s on-chip DMA controller allows data trans­fers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta­neously executing its program instructions. DMA transfers can
occur between the ADSP-21367’s internal memory and its serial
ports, the SPI-compatible (Serial Peripheral Interface) ports, the
IDP (Input Data Port), the Parallel Data Acquisition Port
(PDAP) or the UART. Thirty-four channels of DMA are avail­able on the ADSP-21367—sixteen via the serial ports, eight via
the Input Data Port, four for the UARTs, two for the SPI inter­face, two for the external port, and two for memory-to-memory
transfers. Programs can be downloaded to the ADSP-21367
using DMA transfers. Other DMA features include interrupt
generation upon completion of DMA transfers, and DMA
chaining for automatic linked DMA transfers.

Delay Line DMA

The ADSP-21367 processor provides Delay Line DMA func­tionality. This allows processor reads and writes to external
Delay Line Buffers (and hence to external memory) with limited
core interaction.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con­nect various peripherals to any of the DSPs DAI pins
(DAI_P20–1).

Programs make these connections using the Signal Routing
Unit (SRU, shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non con­figurable signal paths.

The DAI also includes eight serial ports, an S/PDIF
receiver/transmitter, four precision clock generators (PCG),
eight channels of synchronous sample rate converters, and an
input data port (IDP). The IDP provides an additional input
path to the ADSP-21367 core, configurable as either eight chan­nels of I

2

S serial data or as seven channels plus a single 20-bit
wide synchronous parallel data acquisition port. Each data
channel has its own DMA channel that is independent from the
ADSP-21367's serial ports.

For complete information on using the DAI, see the ADSP-
2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-21367 features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog devices AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has a dedicated DMA channel.

Serial ports are enabled via 16 programmable and simultaneous
receive or transmit pins that support up to 32 transmit or 32
receive channels of audio data when all eight SPORTS are
enabled, or eight full duplex TDM streams of 128 channels per
frame.

The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig­nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

2

•Multichannel (TDM) mode with support for Packed I

S

mode

2

S mode

•I

2

•Packed I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var­ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

2

S protocols (I2S is an industry standard interface com-

and I
monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I

2

S channels (using two stereo

2

S chan­nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I

2

S modes, data­word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional µ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter­nally or externally generated.

The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep­tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.

Rev. PrA | Page 7 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

S/PDIF Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left justified, I

2

S or right justified with word

widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the Signal Routing Unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.

The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz Stereo
Asynchronous Sample Rate Converter and provides up to
128dB SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to con­vert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.

Digital Peripheral Interface (DPI)

The Digital Peripheral Interface provides connections to two
serial peripheral interface ports, two universal asynchronous
receiver-transmitters (UARTs), a Two Wire Interface (TWI), 12
Flags, and three general-purpose timers.

Serial Peripheral (Compatible) Interface

The ADSP-21367 SHARC processor contains two Serial Periph­eral Interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21367 SPI compati­ble port to communicate with other SPI compatible devices. The
SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, sup­porting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI compatible devices, either acting as a master or slave
device. The ADSP-21367 SPI compatible peripheral implemen­tation also features programmable baud rate and clock phase
and polarities. The ADSP-21367 SPI compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.

UART Port

The ADSP-21367 processor provides a full-duplex Universal
Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART also has multiprocessor com­munication capability using 9-bit address detection. This allows
it to be used in multidrop networks through the RS-485 data

interface standard. The UART port also includes support for 5
to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:

• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.

• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen­eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f
(f

/16) bits per second.

SCLK

/ 1,048,576) to

SCLK

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

f

UART Clock Rate

---------------------------------------- ---------=
16 UART_Divisor×

SCLK

Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8bits).

In conjunction with the general-purpose timer functions, auto­baud detection is supported.

Timers

The ADSP-21367 has a total of four timers: a core timer that can
generate periodic software interrupts and three general purpose
timers that can generate periodic interrupts and be indepen­dently set to operate in one of three modes:

• Pulse Waveform Generation mode

• Pulse Width Count /Capture mode

• External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general purpose timer has one bidirec­tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin­gle control and status register enables or disables all three
general purpose timers independently.

Rev. PrA | Page 8 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Two Wire Interface Port (TWI)

The TWI is a bi-directional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI Master incorporates the following features:

• Simultaneous Master and Slave operation on multiple
device systems with support for multi master data
arbitration

• Digital filtering and timed event processing

• 7 and 10 bit addressing

• 100K bits/s and 400K bits/s data rates

• Low interrupt rate

Pulse Width Modulation

The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave­forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non
paired mode (applicable to a single group of four PWM
waveforms).

The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.

The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a sec­ond updating of the PWM registers is implemented at the mid­point of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis­tortion in three-phase PWM inverters.

ROM Based Security

The ADSP-21367 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation fea­tures and external boot modes are only available after the
correct key is scanned.

SYSTEM DESIGN

The following sections provide an introduction to system design
options and power supply issues.

Program Booting

The internal memory of the ADSP-21367 boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins (see Table 4 on

page 14). Selection of the boot source is controlled via the SPI as

either a master or slave device, or it can immediately begin exe­cuting from ROM.

Power Supplies

The ADSP-21367 has separate power supply connections for the
internal (V

DDINT

), external (V

power supplies. The internal and analog supplies must meet the

1.3V requirement. The external supply must meet the 3.3V
requirement. All external supply pins must be connected to the
same power supply.

Note that the analog supply (A
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the A

pin. Place the filter as close as possible to the pin. For

VDD

an example circuit, see Figure 2. To prevent noise coupling, use
a wide trace for the analog ground (A
decoupling capacitor as close as possible to the pin. Note that
the A

VSS

and A

pins specified in Figure 2 are inputs to the

VDD

processor and not the analog ground plane on the board. For

more information, see Electrical Characteristics on page 15.

10⍀

V

DDINT

Figure 2. Analog Power (A

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21367 pro­cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces­sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro­priate “Emulator Hardware User's Guide”.

), and analog (A

DDEXT

) powers the ADSP-21367’s

VDD

) signal and install a

VSS

0.01␮F0.1␮F

A

VSS

) Filter Circuit

VDD

VDD/AVSS

A

VDD

)

Rev. PrA | Page 9 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

DEVELOPMENT TOOLS

The ADSP-21367 is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel­opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21367.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,
and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel­opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and
generate outputs

• Maintain a one-to-one correspondence with the tool’s
command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen­eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica­tions. Download components from the Web and drop them into
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi­nition File (LDF), allowing the developer to move between the
graphical and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard­ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

Rev. PrA | Page 10 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in­circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com­mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter­mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat­forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standal­one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, non­intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21367
architecture and functionality. For detailed information on the
ADSP-2136x Family core architecture and instruction set, refer
to the ADSP-2136x SHARC Processor Hardware Reference and
the ADSP-2136x SHARC Processor Programming Reference.

Rev. PrA | Page 11 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of TBD:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State, (pd) = pull-down
resistor, (pu) = pull-up resistor.

Table 3. Pin List

Name Type State During

and After
Reset

ADDR

DATA

23–0

31–0

I/O with programmable

1

PUP

I/O with programmable

Three-state

Three-state

PUP

DAI _P

20–1

DPI _P

14–1

ACK Input with programma-

RD

I/O with programma-

2

PUP

ble

I/O with programma-

3

PUP

ble

1

ble PUP

I/O with programmable

1

PUP

Three-state

Three-state

Description

External Address Bus.

External Data Bus.

Digital Audio Interface Pins

. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any
input or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock gen­erators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins

Ω

have internal 22.5 k

pull-up resistors which are enabled on reset. These pull-ups can

be disabled in the DAI_PIN_PULLUP register.

Digital Peripheral Interface.

Memory Acknowledge.

External devices can deassert ACK (low) to add wait states
to an external memory access. ACK is used by I/O devices, memory controllers, or
other peripherals to hold off completion of an external memory access.

External Port Read Enable.

RD is asserted low whenever the processor reads 8-bit
or 16-bit data from an external memory device. When AD15–0 are flags, this pin
remains deasserted. RD

has a 22.5 kΩ internal pull-up resistor.

WR

SDRAS

SDCAS

SDWE

SDCKE Output with program-

SDA10 Output with program-

Output with program­mable PUP

Output with program­mable PUP

Output with program­mable PUP

Output with program­mable PUP

mable PUP

mable PUP

1

1

1

1

1

1

SDCLK0 I/O

External Port Write Enable.

WR is asserted low whenever the processor writes 8-bit
or 16-bit data to an external memory devi ce. When AD15–0 are flags, this pin remains
deasserted. WR

has a 22.5 kΩ internal pull-up resistor.

SDRAM Row Address Strobe.

SDRAM column address select.

SDRAM Write Enable.

SDRAM Clock Enable.

SDRAM A10.

SDRAM Clock Configure.

Rev. PrA | Page 12 of 48 | November 2004

Connect to SDRAM’s WE or W buffer pin.

Connect to SDRAM’s CKE pin.

Connect to SDRAM’s RAS pin.

Connect to SDRAM’s CAS pin.

Table 3. Pin List

ADSP-21367Preliminary Technical Data

Name Type State During

and After
Reset

MS

0–1

FLAG[0]/IRQ0

I/O with programmable

1

PUP

I/O

FLAG[1]/IRQ1 I/O

FLAG[2]/IRQ2/
MS2

I/O with
programmable

1

pull-

up (for MS mode)

FLAG[3]/TIMEX
P/MS3

I/O with
programmable

1

pull-

up (for MS mode)

TDI Input with pull-up

TDO Output

Description

Memory Select Lines 0–1.

These lines are asserted (low) as chip selects for the cor­responding banks of external memory. Memory bank size must be defined in the
ADSP-21062’s system control register (SYSCON) . The MS

lines are decoded memory

3-0

address lines that change at the same time as the other address lines. When no
external memory access is occurring the MS3-0 lines are inactive; they are active
however when a conditional memory access instruction is executed, whether or not
the condition is true. In a multiprocessing system the MS

lines are output by the

3-0

bus master.

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG2/Interrupt Request/Memory Select2.

FLAG3/Timer Expired/Memory Select3.

Test Data Input (JTAG).

Ω

internal pull-up resistor.

22.5 k

Test Data Output (JTAG).

Provides serial data for the boundary scan logic. TDI has a

Serial scan output of the boundary scan path.

TMS Input with pull-up

TCK Input

TRST

EMU

CLK_CFG

BOOT_CFG

RESET

1–0

Input with pull-up

Output with pull-up

Input

Input

1–0

Input

Test Mode S elec t ( JTAG) .

Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

Test Clock ( JTAG).

Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21367.

Te st Re se t (J TAG ).

after power-up or held low for proper operation of the ADSP-21367. TRST

Ω

internal pull-up resistor.

k

Emulation Status.

product line of JTAG emulators target board connector only. EMU

Resets the test state machine. TRST must be asserted (pulsed low)

has a 22.5

Must be connected to the ADSP-21367 Analog Devices DSP Tools

has a 22.5 kΩ

internal pull-up resistor.

Core/CLKIN Ratio Control.

These pins set the start up clock frequency. See Table5

for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi­plier and divider in the PMCTL register at any time after the core comes out of reset.

Boot Configuration Select.

These pins select the boot mode for the processor. The
BOOTCFG pins must be valid before reset is asserted. See Tab le 4 for a description of
the boot modes.

Processor Reset.

Resets the ADSP-21367 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program exe cution from the h ardware reset vect or address. The RES ET

input must be

asserted (low) at power-up.

Rev. PrA | Page 13 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Table 3. Pin List

Name Type State During

and After
Reset

XTAL Output

CLKIN

CLKOUT Output

1

Pull-up is always enabled for ID - 000 in uniprocessor mode and ID- 001 in Multiprocessing mode.

2

Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

3

OP is three-statable

Description

Crystal Oscillator Terminal.

crystal.

Local Clock In.

It configures the ADSP-21367 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21367 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.

Local Clock O ut.

can be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTREG register. The default is reset out.

Used in conjunction with XTAL. CLKIN is the ADSP-21367 clock input.

CL KOUT c an als o be c onfig ured as a reset out pin.The functionality

ADDRESS/DATA MODES

TBD

BOOT MODES

Used in conjunction with CLKIN to drive an external

Table 4. Boot Mode Selection

BOOTCFG1–0 Booting Mode

00 SPI Slave Boot
01 SPI Master Boot
10 AMI boot via EPROM

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 3 on page 17.

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0 Core to CLKIN Ratio

00 6:1
01 32:1
10 16:1

Rev. PrA | Page 14 of 48 | November 2004

ADSP-21367 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ADSP-21367Preliminary Technical Data

K Grade

Parameter

V

DDINT

A

VDD

V

DDEXT

2

V

IH

2

V

IL

V

IH_CLKIN

V

IL_CLKIN

T

AMB

1

Specifications subject to change without notice.

2

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

3

Applies to input pin CLKIN.

4

See Thermal Characteristics on page 41 for information on thermal specifications.

5

See Engineer-to-Engineer Note (No. TBD) for further information.

1

Internal (Core) Supply Voltage 1.235 1.365 V

Analog (PLL) Supply Voltage 1.235 1.365 V

External (I/O) Supply Voltage 3.13 3.47 V

High Level Input Voltage @ V

Low Level Input Voltage @ V

3

High Level Input Voltage @ V

Low Level Input Voltage @ V

4, 5

Ambient Operating Temperature 0 +70 °C

= max 2.0 V

DDEXT

= min –0.5 +0.8 V

DDEXT

= max 1.74 V

DDEXT

= min –0.5 +1.19 V

DDEXT

Min Max Unit

+ 0.5 V

DDEXT

+ 0.5 V

DDEXT

ELECTRICAL CHARACTERISTICS

Parameter

V

OH

V

OL

4, 5

I

IH

4

I

IL

I

ILPU

I

OZH

I

OZL

I

OZLPU

I

DD-INTYP

AI

DD

11, 12

C

IN

1

Specifications subject to change without notice.

2

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

3

See Output Drive Currents on page 41 for typical drive current capabilities.

4

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

5

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

6

Applies to three-statable pins: FLAG3–0.

7

Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.

8

Typical internal current data reflects nominal operating conditions.

9

See Engineer-to-Engineer Note (No. TBD) for further information.

10

Characterized, but not tested.

11

Applies to all signal pins.

12

Guaranteed, but not tested.

1

2

2

High Level Output Voltage @ V
Low Level Output Voltage @ V
High Level Input Current @ V
Low Level Input Current @ V

5

6, 7

6

7

8, 9

10

Low Level Input Current Pull-up @ V
Three-State Leakage Current @ V
Three-State Leakage Current @ V
Three-State Leakage Current Pull-up @ V
Supply Current (Internal) t
Supply Current (Analog) A
Input Capacitance fIN=1 MHz, T

Test Conditions Min Max Unit

= min, IOH = –1.0 mA

DDEXT

= min, IOL = 1.0 mA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 µA

DDEXT

= max, VIN = 0 V 200 µA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 µA

DDEXT

= max, VIN = 0 V 200 µA

DDEXT

= 5.0 ns, V

CCLK

= max 10 mA

VDD

= 1.3 500 mA

DDINT

=25°C, VIN=1.3V 4.7 pF

CASE

3

3

max 10 µA

DDEXT

max 10 µA

DDEXT

2.4 V

0.4 V

Rev. PrA | Page 15 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Parameter Rating

Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage–0.5 V to V

DDEXT

1

Output Voltage Swing–0.5 V to V
Load Capacitance
Storage Temperature Range

1

1

–65°C to +150°C

DDINT

VDD

DDEXT

DDEXT

1

)

1

)

1

)

–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+ 0.5 V

1

+ 0.5 V
200 pF

Junction Temperature under Bias 125°C

1

Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;

functional operation of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21367 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS

The ADSP-21367’s internal clock (a multiple of CLKIN) pro­vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG1–0 pins
(see Table 5 on page 14). To determine switching frequencies
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the serial
ports).

The ADSP-21367’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys­tem clock (CLKIN) signal and the processor’s internal clock (the
clock source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (Table 6).

Table 6. ADSP-21367 CLKOUT and CCLK Clock
Generation Operation

Timing
Requirements

CLKIN Input Clock 1/t
CCLK Core Clock 1/t

Description Calculation

CK

CCLK

Table 7. Clock Periods

Timing
Requirements

t

CK

t

CCLK

t

PCLK

t

SCLK

t

SDCLK

t

SPICLK

1

where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT

CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock

Figure 3 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with

external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP-
2136x SHARC Processor Programming Reference.

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See

Figure 34 on page 41 under Test Conditions for voltage refer-

ence levels.

Description

1

CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
Serial Port Clock Period = (t

PCLK

SDRAM Clock Period = (TBD)
SPI Clock Period = (t

PCLK

) × SPIR

CCLK

) × SR

Rev. PrA | Page 16 of 48 | November 2004

ADSP-21367Preliminary Technical Data

CLKIN

XTAL

XTAL

OSC

PLLILCLK

PLL

6:1, 16:1,

32:1

CLK-CFG [1: 0]

Figure 3. Core Clock and System Clock Relationship to CLKIN

CLKOUT

CCLK
(CORE CLOCK)

SDCLK
(SDRAM CLOCK)

Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char­acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir­cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

Rev. PrA | Page 17 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 8.

Table 8. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

t

RSTVDD

t

IVDDEVDD

t

CLKVDD

t

CLKRST

t

PLLRST

1

RESET Low Before V
V

on Before V

DDINT

CLKIN Valid After V

DDINT/VDDEXT

DDEXT

DDINT/VDDEXT

on 0 ns

–50 200 ms

Valid 0 200 ms
CLKIN Valid Before RESET Deasserted 10
PLL Control Setup Before RESET Deasserted 20

2

3

µs
µs

Switching Characteristic

t

CORERST

1

Valid V

DDINT/VDDEXT

depending on the design of the power supply subsystem.

2

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3

Based on CLKIN cycles

4

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

5

The 4096 cycle count depends on t

cycles maximum.

Core Reset Deasserted After RESET Deasserted 4096tCK + 2 t

assumes that the supplies are fully ramped to their 1.3 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

specification in Table 10. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

SRST

RESET

t

RSTVDD

V

DDINT

V

DDEXT

CLKIN

CLK_CFG1-0

t

IVDDEVDD

t

CLKVDD

t

CLKRST

CCLK

4,

5

RSTOUT

t

PLLRST

Figure 4. Power-Up Sequencing

Rev. PrA | Page 18 of 48 | November 2004

t

CORERST

Clock Input

Table 9. Clock Input

Parameter 400 MHz Unit

Min Max

Timing Requirements

t

CK

t

CKL

t

CKH

t

CKRF

3

t

CCLK

1

Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

2

Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

3

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CLKIN

CLKIN Period 15
CLKIN Width Low 6
CLKIN Width High 6

1

1

CLKIN Rise/Fall (0.4V–2.0V) TBD ns
CCLK Period 2.5

t

CK

t

CKH

t

CKL

1

1

.

CCLK

2

320
150
150

2

2

ns
ns
ns

10 ns

ADSP-21367Preliminary Technical Data

Figure 5. Clock Input

Clock Signals

The ADSP-21367 can use an external clock or a crystal. See the
CLKIN pin description in TBD. The programmer can configure
the ADSP-21367 to use its internal clock generator by connect­ing the necessary components to CLKIN and XTAL. Figure 6
shows the component connections used for a crystal operating
in fundamental mode. Note that the clock rate is achieved using
a 16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi­plier bits in the PMCTL register.

CLKIN XTAL

C1 C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 6. 400 MHz Operation (Fundamental Mode Crystal)

1M⍀

X1

Rev. PrA | Page 19 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Reset

Table 10. Reset

Parameter Min Max Unit

Timing Requirements

1

t

WRST

t

SRST

1

Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

Interrupts

The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0

, and IRQ2 interrupts.

IRQ1

RESET Pulse Width Low 4t

CK

ns

RESET Setup Before CLKIN Low 8 ns

CLKIN

t

SRST

RESET

t

WRST

Figure 7. Reset

,

Table 11. Interrupts

Parameter Min Max Unit

Timing Requirement

t

IPW

IRQx Pulse Width 2 × t

DPI14-1

FLAG2-0

(IRQ2-0)

t

IPW

Figure 8. Interrupts

+2 ns

PCLK

Rev. PrA | Page 20 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Core Timer

The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).

Table 12. Core Timer

Parameter Min Max Unit

Switching Characteristic

t

WCTIM

CTIMER Pulse width 4 × t

– 1 ns

PCLK

FLAG3

(CTIM ER)

Figure 9. Core Timer

t

WCTIM

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.

Table 13. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

t

PWMO

Timer Pulse Width Output 2 t

DPI14-0

(TIMER2-0)

Figure 10. Timer PWM_OUT Timing

– 1 2(231 – 1) t

PCLK

t

PWMO

PCLK

ns

Rev. PrA | Page 21 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DAI_P20–1 pins.

Table 14. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

t

PWI

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).

Timer Pulse Width 2 t

DPI14-0

(TIMER2-0)

Figure 11. Timer Width Capture Timing

PCLK

2(231– 1) t

t

PWI

PCLK

ns

Table 15. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

t

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

DAI_Pn
DPI_Pn

DAI_pm
DPI_Pm

t

DPIO

Figure 12. DAI Pin to Pin Direct Routing

Rev. PrA | Page 22 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that
the Precision Clock Generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs

inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All Timing Param­eters and Switching Characteristics apply to external DAI pins
(DAI_P07 – DAI_P20).

directly to the DAI pins. For the other cases, where the PCG’s

Table 16. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements
t

PCGIW

t

STRIG

t

HTRIG

Input Clock Period 24
PCG Trigger Setup Before Falling Edge of PCG Input Clock 2 ns
PCG Trigger Hold After Falling Edge of PCG Input Clock 2 ns

Switching Characteristics

t

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After
PCG Input Clock 2.5 10 ns

t

DTRIG

t

PCGOW

PCG Output Clock and Frame Sync Delay After PCG Trigger 2.5 + 2.5 × t
Output Clock Period 48

t

STRI G

DAI_Pn
DPI_Pn

PCG_TRIGx_I

t

PCGIW

t

PCGOW

DAI _Pm
DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py
DPI_Py

PCG_CLKx_O

t

HTRIG

t

DPCGIO

PCGOW

10 + 2.5 × t

PCGOW

ns

DAI_Pz
DPI_Pz

PCG_FSx_O

t

DTRIG

Figure 13. Precision Clock Generator (Direct Pin Routing)

Rev. PrA | Page 23 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Flags

The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, the parallel port, and the serial peripheral
interface (SPI). See TBD for more information on flag use.

Table 17. Flags

Parameter Min Max Unit

Timing Requirement

t

FIPW

FLAG3–0 IN Pulse Width 2 × t

Switching Characteristic

t

FOPW

FLAG3–0 OUT Pulse Width 2 × t

DPI_P140-1
(FLAG3-0

(DATA31-0)

)

IN

t

FIPW

+ 3 ns

PCLK

– 1 ns

PCLK

DPI_P14-1

(FLAG3-0

(DATA31-0)

OUT

)

t

FOPW

Figure 14. Flags

Rev. PrA | Page 24 of 48 | November 2004

SDRAM Interface Timing

ADSP-21367Preliminary Technical Data

Table 18. SDRAM Interface Timing

1

Parameter Minimum Maximum Unit

Timing Requirement

t

SSDAT

t

HSDAT

DATA Setup Before CLKOUT TBD ns
DATA Hold After CLKOUT TBD ns

Switching Characteristic

t

SCLK

t

SCLKH

t

SCLKL

t

DCAD

t

HCAD

t

DSDAT

t

ENSDAT

1

For V

2

Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

DDINT

= 1.3 V.

CLKOUT Period TBD ns
CLKOUT Width High TBD ns
CLKOUT Width Low TBD ns
Command, ADDR, Data Delay After CLKOUT
Command, ADDR, Data Hold After CLKOUT

2

1

TBD ns

TBD ns

Data Disable After CLKOUT TBD ns
Data Enable After CLKOUT TBD ns

t

SCLKH

SDCLK

DATA (IN)

t

SSDAT

t

SCLK

t

HSDAT

t

SCLKL

DATA(OUT)

CMND ADDR

(OUT)

t

DCAD

t

ENSDAT

t

DCAD

t

HCAD

NOTE: COMMAND = SRAS, SCAS, SWE,SDQM,SMS, SA10, SCKE.

Figure 15. SDRAM Interface Timing

t

DSDAT

t

HCAD

Rev. PrA | Page 25 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Serial Ports

To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 19. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

1

t

SFSE

FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns

1

t

HFSE

FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns

1

t

SDRE

t

HDRE

t

SCLKW

t

SCLK

1

Receive Data Setup Before Receive SCLK 2.5 ns
Receive Data Hold After SCLK 2.5 ns
SCLK Width 24 ns
SCLK Period 48 ns

Switching Characteristics

2

t

DFSE

FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 7 ns

2

t

HOFSE

FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 2 ns

2

t

DDTE

2

t

HDTE

1

Referenced to sample edge.

2

Referenced to drive edge.

Transmit Data Delay After Transmit SCLK 7 ns
Transmit Data Hold After Transmit SCLK 2 ns

Serial port signals (SCLK, FS, data channel A,/data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.

Table 20. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

t

SFSI

1

FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode) 7 ns

t

HFSI

1

FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns

1

t

SDRI

t

HDRI

1

Receive Data Setup Before SCLK 7 ns
Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

2

t

DFSI

2

t

HOFSI

2

t

DFSI

2

t

HOFSI

2

t

DDTI

2

t

HDTI

t

SCLKIW

1

Referenced to the sample edge.

2

Referenced to drive edge.

FS Delay After SCLK (Internally Generated FS in Transmit Mode) 3 ns
FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns
FS Delay After SCLK (Internally Generated FS in Receive or Mode) 3 ns
FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns
Transmit Data Delay After SCLK 3 ns
Transmit Data Hold After SCLK –1.0 ns
Transmit or Receive SCLK Width 0.5t

– 2 0.5t

SCLK

+ 2 ns

SCLK

Rev. PrA | Page 26 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Table 21. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

1

t

DDTEN

1

t

DDTTE

1

t

DDTIN

1

Referenced to drive edge.

Table 22. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

1

t

DDTLFSE

1

t

DDTENFS

1

The t

DDTLFSE

Data Enable from External Transmit SCLK 2 ns
Data Disable from External Transmit SCLK 7 ns
Data Enable from Internal Transmit SCLK –1 ns

Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0 7 ns

Data Enable for MCE = 1, MFD = 0 0.5 ns

and t

parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.

DDTENFS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

NOTE
SERIAL PORTSIGNALS (SCLK, FS,DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

DRIVE SAMPLE DRIVE

t

SFSE/I

t

DDTENFS

1ST BIT 2ND BIT

t

DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE SAMPLE DRIVE

t

SFSE/I

t

t

DDTLFSE

DDTENFS

t

HDTE/I

1ST BIT 2ND BIT

t

HDTE/I

t

HFSE/I

t

HFSE/I

t

t

DDTE/I

DDTE/I

Figure 16. External Late Frame Sync

1

This figure reflects changes made to support Left-justified Sample Pair mode.

Rev. PrA | Page 27 of 48 | November 2004

1

ADSP-21367 Preliminary Technical Data

—EX

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE

DRIVE EDGE SAMPL EEDGE

t

HOFSI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t

HOFSI

t

HDTI

t

DFSI

t

DFSI

t

SCLKIW

t

SCLKIW

t

DDTI

t

t

SDRI

t

SFSI

SFSI

t

t

t

HFSI

HFSI

HDRI

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE EDGE SAMPLE EDGE

t

t

HOFSE

DRIVE EDGE SAMPLE EDGE

t

HOFSE

t

HDTE

DFSE

DATA TRANSMIT — EXTERNAL CLOCK

t

DFSE

TERNAL CLOCK

t

SCLKW

t

SCLK W

t

DDTE

t

t

SFSE

SDRE

t

SFSE

t

t

HFSE

t

HFSE

HDRE

SCLK (EXT)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1
SCLK (INT)

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK ( INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING E DGE.

DRIVE EDGE DRIVE EDGE

SCLKDAI_P20-1

DRIVEEDGE

t

DDTIN

t

DDTEN

t

DDTTE

Figure 17. Serial Ports

Rev. PrA | Page 28 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Input Data Port

The timing requirements for the IDP are given in Table 23.IDP
Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.

Table 23. IDP

Parameter Min Max Unit

Timing Requirements

1

t

SISFS

1

t

SIHFS

1

t

SISD

1

t

SIHD

t

IDPCLKW

t

IDPCLK

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

FS Setup Before SCLK Rising Edge 2.5 ns
FS Hold After SCLK Rising Edge 2.5 ns
SData Setup Before SCLK Rising Edge 2.5 ns
SData Hold After SCLK Rising Edge 2.5 ns
Clock Width 9 ns
Clock Period 24 ns

SAMPLE EDGE
t

IPDCLK

DAI_P20-1

(SCLK)

t

IPDCLKW

DAI_P20-1

(FS)

DAI_P20- 1

(SDATA)

t

SISFS

t

SISD

t

Figure 18. IDP Master Timing

SIHFS

t

SIHD

Rev. PrA | Page 29 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 24. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2136x SHARC Processor Hardware Refer-

ence. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD15–0 or
the DAI_P20–5 pins. The remaining 4 bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.

Table 24. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

1

t

SPCLKEN

t

HPCLKEN

t

PDSD

t

PDHD

t

PDCLKW

t

PDCLK

1

1

1

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns
PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 2.5 ns
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns
Clock Width 7 ns
Clock Period 24 ns

Switching Characteristics

t

PDHLDD

t

PDSTRB

1

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t
PDAP Strobe Pulse Width 1 × t

SAMPLE EDGE

t

PDCLK

DAI_P20-1

(PDAP_CLK)

t

PDCLKW

CCLK

– 1 ns

CCLK

ns

DAI_P20-1

(PDAP_CLKEN)

DATA

DAI_P20-1

(PDAP_STROBE)

t

SPCLKEN

t

PDSD

t

PDHLDD

Figure 19. PDAP Timing

t

HPCLKEN

t

PDHD

t

PDSTRB

Rev. PrA | Page 30 of 48 | November 2004

ADSP-21367Preliminary Technical Data

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec­ifications provided in Table 25 are valid at the DAI_P20–1 pins.

Table 25. SRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

1

t

SRCSFS

1

t

SRCHFS

1

t

SRCSD

1

t

SRCHD

t

SRCCLKW

t

SRCCLK

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

FS Setup Before SCLK Rising Edge 4 ns
FS Hold After SCLK Rising Edge 5.5 ns
SData Setup Before SCLK Rising Edge 4 ns
SData Hold After SCLK Rising Edge 5.5 ns
Clock Width 9 ns
Clock Period 20 ns

SAMPLE EDGE

t

SRCCLK

DAI_P20-1

(SCLK)

t

SRCCLKW

DAI_P20-1

(FS)

DAI_P20-1

(SDATA)

t

SRCSFS

t

SRCSD

t

SRCHFS

t

SRCH D

Figure 20. SRC Serial Input Port Timing

Rev. PrA | Page 31 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the

and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive
edge.

output port. The serial data output, SDATA, has a hold time

Table 26. SRC, Serial Output Port

Parameter Min Max Unit

Timing Requirements

t

SRCSFS

t

SRCHFS

1

1

FS Setup Before SCLK Rising Edge 4 ns
FS Hold Before SCLK Rising Edge 5.5 ns

Switching Characteristics

1

t

SRCTDD

1

t

SRCTDH

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Transmit Data Delay After SCLK Falling Edge 7 ns
Transmit Data Hold After SCLK Falling Edge 2 ns

DAI_P20-1

(SCLK)

t

SRCCLKW

SAMPLE E DGE

t

SRCSFS

t

SRCCLK

t

SRCHFS

DAI_P20-1

(FS)

DAI_P20-1

(SDATA)

t

SRCT DH

t

SRCTDD

Figure 21. SRC Serial Output Port Timing

Rev. PrA | Page 32 of 48 | November 2004

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as
left justified, I

2

S or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.

SPDIF Transmitter—Serial Input Waveforms

Figure 22 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

ADSP-21367Preliminary Technical Data

mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.

LRCLK

SCLK

SDATA

LSB

LEFT CHANNEL

MSB

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB M SB-1 MSB- 2 LSB+2 LSB+1 LS B

Figure 22. Right-Justified Mode

Figure 23 shows the default I2S-justified mode. LRCLK is LO

for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.

LRCLK

SCLK

SDATA

MSB

MSB-1 MSB-2 LSB+2 LSB+1 LSB

LEFT CHANNEL

Figure 23. I2S-Justified Mode

Figure 24 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.

RIGHT CHANNEL

RIGHT CH ANNEL

MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB

MSB

LRCLK

SCLK

SDATA

MSB

MSB-1 MSB-2

LEFT CHANNEL

LSB+2 LSB+1 LSB

Rev. PrA | Page 33 of 48 | November 2004

MSB MSB-1 MSB-2

Figure 24. Left-Justified Mode

RIGHT CHANNEL

LSB+2 LSB+1 LSB

MSB MSB+1

ADSP-21367 Preliminary Technical Data

SPDIF Transmitter Input Data Timing

The timing requirements for the Input port are given in

Table 27. Input Signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica­tions provided below are valid at the DAI_P20–1 pins.

Table 27. SPDIF Transmitter Input Data Timing

Parameter Min Max Unit

Timing Requirements

1

t

SIFS

1

t

SIHFS

1

t

SISD

1

t

SIHD

t

SISCLKW

t

SISCLK

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

FS Setup Before SCLK Rising Edge 4 ns
FS Hold After SCLK Rising Edge 5.5 ns
SData Setup Before SCLK Rising Edge 4 ns
SData Hold After SCLK Rising Edge 5.5 ns
Clock Width 9 ns
Clock Period 20 ns

SAMPLE EDGE

t

DAI_P20-1

(SCLK)

SISCLKW

t

SIHFS

t

SIHD

DAI_P20-1

(FS)

DAI_P20-1

(SDATA)

t

SISFS

t

SISD

Figure 25. SPDIF Transmitter Input Timing

Over Sampling Clock (TXCLK) Switching Characteristics

SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the Biphase Clock.

Table 28. Over Sampling Clock (TXCLK) Switching Characteristics

Parameter Min Max Unit

TXCLK Frequency for TXCLK = 768 × FS 147.5 MHz
TXCLK Frequency for TXCLK = 512 × FS 98.4 MHz
TXCLK Frequency for TXCLK = 384 × FS 73.8 MHz
TXCLK Frequency for TXCLK = 256 × FS 49.2 MHz
Frame Rate 192.0 MHz

Rev. PrA | Page 34 of 48 | November 2004

SPDIF Receiver

The following sections describe timing as it relates to the SPDIF
receiver.

Internal Digital PLL Mode

In internal Digital Phase-locked Loop mode the internal PLL
(Digital PLL) generates the 512 × Fs clock.

Table 29. SPDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit

Switching Characteristics

t

DFSI

t

HOFSI

t

DDTI

t

HDTI

1

t

SCLKIW

t

CCLK

1

SCLK frequency is 64 x FS where FS = the frequency of LRCLK.

LRCLK Delay After SCLK 5 ns
LRCLK Hold After SCLK –2 ns
Transmit Data Delay After SCLK 5 ns
Transmit Data Hold After SCLK –2 ns
Transmit SCLK Width 40 ns
Core Clock Period 5 ns

ADSP-21367Preliminary Technical Data

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

Figure 26. SPDIF Receiver Internal Digital PLL Mode Timing

DRIVE EDGE SAMPLE EDGE

t

SCLKIW

t

t

HOFSI

t

HDTI

DFSI

t

DDTI

t

SFSI

t

HFSI

Rev. PrA | Page 35 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

External PLL Mode

In External PLL Mode internal Digital PLL is disabled and the
receiver runs on the PLL that is connected to the processor
externally. This external PLL generates the 512 x Fs clock
(MCLK) from the reference clock (LRCLK) and gives it to
SPDIF receiver.

Table 30. SPDIF Receiver External PLL Mode Timing

Parameter Min Max Unit

Timing Requirements

t

MCP

FMCLK MCLK Frequency (1/t
t

BDM

t

LDM

t

DDP

t

DDS

t

DDH

MCLK INP UT

(NOT TO SCAL E)

MCLK Period 10 ns

)100MHz

MCP

SCLK Propagation Delay from MCLK to the Falling Edge 30 ns
LRCLK Propagation Delay From MCLK 30 ns
Data Propagation Delay From MCLK 30 ns
Data Output Setup To SCLK 1/2 SCLK Period ns
Data Output Hold From SCLK 1/2 SCLK Period ns

BCLK OUTPUT

LRCLK

OUTPUT

SDATA OUTPUT

I2S-JUSTIFIED

MODE

SDATA OUTPUT

RIGHT-J USTIFIED

MODE

t

BDM

t

LDM

t

DDS

MSB

t

DDH

t

DDP

t

DDS

MSB LSB

t

DDH

t

DDP

Figure 27. SPDIF Receiver External PLL Mode Timing

t

DDS

t

DDH

Rev. PrA | Page 36 of 48 | November 2004

ADSP-21367Preliminary Technical Data

SPI Interface—Master

The ADSP-21367 contains two SPI ports. The primary has dedi­cated pins and the secondary is available through the DPI. The
timing provided in Table 31 and Table 32 on page 38 applies to
both.

Table 31. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

t

SSPIDM

t

HSPIDM

Switching Characteristics

t

SPICLKM

t

SPICHM

t

SPICLM

t

DDSPIDM

t

HDSPIDM

t

SDSCIM

t

HDSM

t

SPITDM

Data Input Valid To SPICLK Edge (Data Input Set-up Time) 8 ns
SPICLK Last Sampling Edge To Data Input Not Valid 2 ns

Serial Clock Cycle 8 × t
SErial Clock High Period 4 × t
Serial Clock Low Period 4 × t

PCLK

PCLK

– 2 ns

PCLK

ns
ns

SPICLK Edge to Data Out Valid (Data Out Delay Time) 0
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 ns
FLAG3–0IN (SPI device select) Low to First SPICLK Edge 4 × t
Last SPICLK Edge to FLAG3–0IN High 4 × t
Sequential Transfer Delay 4 × t

– 2 ns

PCLK

– 1 ns

PCLK

– 1 ns

PCLK

FLAG3-0

(OUTPUT)

SPICLK
(CP = 0)

(OUTPUT)

SPICLK
(CP = 1)

(OUTPUT)

(OUTPUT)

CPHASE=1

(OUTPUT)

CPHASE=0

MOS I

MIS O

(INPUT)

MOS I

MIS O

(INPUT)

t

SSPIDM

t

SDSCIM

t

SPICHMtSPICLM

t

SPICLM

MSB

VALID

t

MSB

VALID

HSPIDM

t

SPICHM

t

DDSPIDM

t

SSPIDM

t

HSSPIDM

t

DDSPIDM

t

HDSPIDM

t

SSPIDM

t

HDSPIDM

t

SPICLKM

LSB

VALID

LSBMSB

LSB

VALID

t

HDSM

t

SPITDM

LSBMSB

t

HSPIDM

Figure 28. SPI Master Timing

Rev. PrA | Page 37 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

SPI Interface—Slave

Table 32. SPI Interface Protocol —Slave Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

t

SPICLKS

t

SPICHS

t

SPICLS

t

SDSCO

t

HDS

t

SSPIDS

t

HSPIDS

t

SDPPW

Switching Characteristics

t

DSOE

t

DSDHI

t

DDSPIDS

t

HDSPIDS

t

DSOV

Serial Clock Cycle 4 × t
Serial Clock High Period 2 × t
Serial Clock Low Period 2 × t
SPIDS Assertion to First SPICLK Edge

CPHASE = 0
CPHASE = 1

2 × t
2 × t

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

PCLK

– 2 ns

PCLK

PCLK
PCLK

PCLK

ns
ns

ns

ns
Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 ns
SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
SPIDS Deassertion Pulse Width (CPHASE=0) 2 × t

PCLK

ns

SPIDS Assertion to Data Out Active 0 4 ns
SPIDS Deassertion to Data High Impedance 0 4 ns
SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.4 ns
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

SPIDS Assertion to Data Out Valid (CPHASE=0) 5 × t

PCLK

ns

ns

SPID S

(INPUT)

SPICLK
(CP = 0)
(INPUT)

SPICLK

(CP = 1)

(INPUT)

MISO

(OUTPUT)

CPHASE=1

(INPUT)

MISO

(OUTPUT)

CPHASE=0

(INPUT)

MOSI

MOSI

t

SDSCO

t

DSOE

t

DSOV

t

DSOE

t

SPICHS

t

SSPIDS

t

SPICLS

t

DDSPIDS

MSB

VALID

MSB

VALID

MSB

t

DDSPIDS

t

SPICLS

t

SPICHS

t

SSPIDS

t

DDSPIDS

VALID

t

SPICLKS

t

SSPIDS

LSB

VALID

t

HDLSBS

LSB

t

HSPIDS

LSB

t

HDS

LSBMSB

t

HSPIDS

t

SDPPW

t

DSDHI

t

HDLSBS

t

DSDHI

Figure 29. SPI Slave Timing

Rev. PrA | Page 38 of 48 | November 2004

Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing

Figure 30 describes UART port receive and transmit operations.

The maximum baud rate is SCLK/16. As shown in Figure 30
there is some latency between the generation internal UART

CLKOUT

(SAMPLE CLOCK)

ADSP-21367Preliminary Technical Data

interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.

RXD

RECEIVE

UART RECEIVE

TXD

TRANSMIT

UART TRANSMIT

INTERNAL

INTERRUPT

INTERNAL

INTERRUPT

DATA(5–8)

START

DATA(5–8)

Figure 30. UART Port—Receive and Transmit Timing

STOP

STOP ( 1–2)

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Rev. PrA | Page 39 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

JTAG Test Access Port and Emulation

Table 33. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

t

TCK

t

STAP

t

HTAP

1

t

SSYS

1

t

HSYS

t

TRSTW

Switching Characteristics

t

DTDO

2

t

DSYS

1

System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

2

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

TCK Period t

CK

ns
TDI, TMS Setup Before TCK High 5 ns
TDI, TMS Hold After TCK High 6 ns
System Inputs Setup Before TCK Low 7 ns
System Inputs Hold After TCK Low 18 ns
TRST Pulse Width 4t

CK

ns

TDO Delay from TCK Low 7 ns
System Outputs Delay After TCK Low 10 ns

t

TCK

TCK

TMS
TDI

TDO

SYSTEM
INPUTS

SYSTEM
OUTPUTS

t

DTDO

t

DSYS

t

STAP

t

HTAP

Figure 31. IEEE 1149.1 JTAG Test Access Port

t

SSYS

t

HSYS

Rev. PrA | Page 40 of 48 | November 2004

ADSP-21367Preliminary Technical Data

OUTPUT DRIVE CURRENTS

Figure 32 shows typical I-V characteristics for the output driv-

ers of the ADSP-21367. The curves represent the current drive
capability of the output drivers as a function of output voltage.

TBD

Figure 32. ADSP-21367 Typical Drive

TEST CONDITIONS

The ac signal specifications (timing parameters) appear

Table 10 on page 20 through Table 33 on page 40. These include

output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 33.

Timing is measured on signals when they cross the 1.5 V level as
described in Figure 34. All delays (in nanoseconds) are mea­sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 33). Figure 37 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 35, Figure 36, and Figure 37 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20%-80%, V=Min)
vs. Load Capacitance.

TBD

Figure 35. Typical Output Rise/Fall Time (20%-80%,

= Max)

V

DDEXT

TO

OUTPUT

PIN

30pF

Figure 33. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

INPUT

1.5V 1.5V

OR

OUTPUT

Figure 34. Voltage Reference Levels for AC Measurements

50⍀

1.5V

THERMAL CHARACTERISTICS

The ADSP-21367 processor is rated for performance over the

Rev. PrA | Page 41 of 48 | November 2004

TBD

Figure 36. Typical Output Rise/Fall Time (20%-80%,

V

=Min)

DDEXT

TBD

Figure 37. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

commercial temperature range, T

= –40°C to 85°C.

AMB

ADSP-21367 Preliminary Technical Data

Table 34 through Table 36 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to­board measurement complies with JESD51-8. Test board and
thermal via design comply with JEDEC standards JESD51-9
(BGA). The junction-to-case measurement complies with MIL­STD-883. All measurements use a 2S2P JEDEC test board.

To determine the Junction Temperature of the device while on
the application PCB, use:

TJT

CASE

Ψ

P

×()+=

JT

D

where:

= Junction temperature °C

T

J

= Case temperature (°C) measured at the top center of

T

CASE

the package

= Junction-to-Top (of package) characterization parameter

Ψ

JT

is the Typical value from Table 34 and Table 36.
P

= Power dissipation (see EE Note #TBD)

D

Values of θ
design considerations. θ
mation of T

are provided for package comparison and PCB

JA

by the equation:

J

can be used for a first order approxi-

JA

T

JTAθJAPD

×()+=

where:

= Ambient Temperature °C

T

A

Values of θ

are provided for package comparison and PCB

JC

design considerations when an external heatsink is required.
Values of θ

are provided for package comparison and PCB

JB

design considerations. Note that the thermal characteristics val­ues provided in Table 34 through Table 36 are modeled values.

Table 35. Thermal Characteristics for 256 Ball SBGA (Ther­mal vias in PCB)

Parameter Condition Typical Unit

Ψ

JT

Ψ

JMT

Ψ

JMT

Airflow = 0 m/s TBD °C/W
Airflow = 1 m/s TBD °C/W
Airflow = 2 m/s TBD °C/W

Table 36. Thermal Characteristics for 208-Lead MQFP

Parameter Condition Typical Unit

θ

JA

θ

JMA

θ

JMA

θ

JC

Ψ

JT

Ψ

JMT

Ψ

JMT

Airflow = 0 m/s TBD °C/W
Airflow = 1 m/s TBD °C/W
Airflow = 2 m/s TBD °C/W

TBD °C/W
Airflow = 0 m/s TBD °C/W
Airflow = 1 m/s TBD °C/W
Airflow = 2 m/s TBD °C/W

Table 34. Thermal Characteristics for 256 Ball SBGA (No
thermal vias in PCB)

Parameter Condition Typical Unit

θ

JA

θ

JMA

θ

JMA

θ

JC

Ψ

JT

Ψ

JMT

Ψ

JMT

Airflow = 0 m/s TBD °C/W
Airflow = 1 m/s TBD °C/W
Airflow = 2 m/s TBD °C/W

TBD °C/W
Airflow = 0 m/s TBD °C/W
Airflow = 1 m/s TBD °C/W
Airflow = 2 m/s TBD °C/W

Table 35. Thermal Characteristics for 256 Ball SBGA (Ther­mal vias in PCB)

Parameter Condition Typical Unit

θ

JA

θ

JMA

θ

JMA

θ

JC

Airflow = 0 m/s TBD °C/W
Airflow = 1 m/s TBD °C/W
Airflow = 2 m/s TBD °C/W

TBD °C/W

Rev. PrA | Page 42 of 48 | November 2004

ADSP-21367Preliminary Technical Data

256-BALL SBGA PINOUT

Table 37. 256-Ball SBGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

A01 NC B01 DAI5 C01 DAI9 D01 DAI10
A02 TDI B02 SDCLK1 C02 DAI7 D02 DAI6
A03 TMS B03 TRST
A04 CLK_CFG0 B04 TCK C04 IOVDD D04 IOVDD
A05 CLK_CFG1 B05 BOOTCFG_0 C05 GND D05 GND
A06 EMU
A07 DAI4 B07 TDO C07 VDD D07 VDD
A08 DAI1 B08 DAI3 C08 GND D08 GND
A09 DPI14 B09 DAI2 C09 GND D09 IOVDD
A10 DPI12 B10 DPI13 C10 VDD D10 VDD
A11 DPI10 B11 DPI11 C11 GND D11 GND
A12 DPI9 B12 DPI8 C12 GND D12 IOVDD
A13 DPI7 B13 DPI5 C13 VDD D13 VDD
A14 DPI6 B14 DPI4 C14 GND D14 GND
A15 DPI3 B15 DPI1 C15 GND D15 IOVDD
A16 DPI2 B16 RESET
A17 CLKOUT B17 DATA30 C17 VDD D17 IOVDD
A18 DATA31 B18 DATA29 C18 VDD D18 GND
A19 NC B19 DATA28 C19 DATA27 D19 DATA26
A20 NC B20 NC C20 RPBA D20 DATA24
E01 DAI11 F01 DAI14 G01 DAI15 H01 DAI17
E02 DAI8 F02 DAI12 G02 DAI13 H02 DAI16
E03 VDD F03 GND G03 GND H03 VDD
E04 VDD F04 GND G04 IOVDD H04 VDD
E17 GND F17 IOVDD G17 VDD H17 IOVDD
E18 GND F18 GND G18 VDD H18 GND
E19 DATA25 F19 ID2 G19 DATA22 H19 DATA19
E20 DATA23 F20 DATA21 G20 DATA20 H20 DATA18
J01 DAI19 K01 FLAG0 L01 FLAG2 M01 ACK
J02 DAI18 K02 DAI20 L02 FLAG1 M02 FLAG3
J03 GND K03 GND L03 VDD M03 GND
J04 GND K04 IOVDD L04 VDD M04 GND

B06 BOOTCFG_1 C06 GND D06 IOVDD

C03 GND D03 GND

C16 VDD D16 GND

Rev. PrA | Page 43 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Table 37. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

J17 GND K17 VDD L17 VDD M17 IOVDD
J18 GND K18 VDD L18 VDD M18 GND
J19 ID1 K19 ID0 L19 DATA15 M19 DATA12
J20 DATA17 K20 DATA16 L20 DATA14 M20 DATA13
N01 RD
N02 SDCLK0 P02 WR
N03 GND P03 VDD R03 GND T03 GND
N04 IOVDD P04 VDD R04 GND T04 IOVDD
N17 GND P17 VDD R17 IOVDD T17 GND
N18 GND P18 VDD R18 GND T18 GND
N19 DATA11 P19 DATA8 R19 DATA6 T19 DATA5
N20 DATA10 P20 DATA9 R20 DATA7 T20 DATA4
U01 MS0
U02 MS1
U03 VDD V03 VDD W03 ADDR19 Y03 NC
U04 GND V04 GND W04 ADDR20 Y04 ADDR18
U05 IOVDD V05 GND W05 ADDR17 Y05 BR1
U06 GND V06 GND W06 ADDR16 Y06 BR2
U07 IOVDD V07 GND W07 ADDR15 Y07 XTAL2
U08 VDD V08 VDD W08 ADDR14 Y08 CLKIN
U09 IOVDD V09 GND W09 AVDD Y09 NC
U10 GND V10 GND W10 AVSS Y10 NC
U11 IOVDD V11 GND W11 ADDR13 Y11 BR3
U12 VDD V12 VDD W12 ADDR12 Y12 BR4
U13 IOVDD V13 GND W13 ADDR10 Y13 ADDR11
U14 IOVDD V14 IOVDD W14 ADDR8 Y14 ADDR9
U15 VDD V15 VDD W15 ADDR5 Y15 ADDR7
U16 IOVDD V16 GND W16 ADDR4 Y16 ADDR6
U17 VDD V17 GND W17 ADDR1 Y17 ADDR3
U18 VDD V18 GND W18 ADDR2 Y18 GND
U19 DATA0 V19 DATA1 W19 ADDR0 Y19 GND
U2 0 D ATA2 V 20 D ATA3 W2 0 N C Y2 0 NC

P01 SDA10 R01 SDWE T01 SDCKE

R02 SDRAS T02 SDCAS

V01 ADDR22 W01 GND Y01 GND
V02 ADDR23 W02 ADDR21 Y02 NC

Rev. PrA | Page 44 of 48 | November 2004

208-LEAD MQFP PINOUT

Table 38. 208-Lead MQFP Pin Assignment (Numerically by Lead Number)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

1 VDD 53 VDD 105 VDD 157 VDD
2 DATA28 54 GND 106 GND 158 VDD
3 DATA27 55 IOVDD 107 IOVDD 159 GND
4 GND 56 ADDR0 108 SDCAS
5 IOVDD 57 ADDR2 109 SDRAS
6 DATA26 58 ADDR1 110 SDCKE 162 VDD
7 DATA25 59 ADDR4 111 SDWE
8DATA24 60ADDR3 112WR
9 DATA23 61 ADDR5 113 SDA10 165 TCK
10 GND 62 GND 114 GND 166 GND
11 VDD 63 VDD 115 IOVDD 167 VDD
12 DATA22 64 GND 116 SDCLK0 168 TMS
13 DATA21 65 IOVDD 117 GND 169 CLK_CFG0
14 DATA20 66 ADDR6 118 VDD 170 BOOTCFG0
15 IOVDD 67 ADDR7 119 RD
16 GND 68 ADDR8 120 ACK 172 EMU
17 DATA19 69 ADDR9 121 FLAG3 173 BOOTCFG1
18 DATA18 70 ADDR10 122 FLAG2 174 TDO
19 VDD 71 GND 123 FLAG1 175 DAI4
20 GND 72 VDD 124 FLAG0 176 DAI2
21 DATA17 73 GND 125 DAI20 177 DAI3
22 VDD 74 IOVDD 126 GND 178 DAI1
23 GND 75 ADDR11 127 VDD 179 IOVDD
24 VDD 76 ADDR12 128 GND 180 GND
25 GND 77 ADDR13 129 IOVDD 181 VDD
26 DATA16 78 GND 130 DAI19 182 GND
27 DATA15 79 VDD 131 DAI18 183 DPI14
28 DATA14 80 AVSS 132 DAI17 184 DPI13
29 DATA13 81 AVDD 133 DAI16 185 DPI12
30 DATA12 82 GND 134 DAI15 186 DPI11
31 IOVDD 83 CLKIN 135 DAI14 187 DPI10
32 GND 84 XTAL2 136 DAI13 188 DPI9
33 VDD 85 IOVDD 137 DAI12 189 DPI8
34 GND 86 GND 138 VDD 190 DPI7
35 DATA11 87 VDD 139 IOVDD 191 IOVDD
36 DATA10 88 ADDR14 140 GND 192 GND
37 DATA9 89 GND 141 VDD 193 VDD
38 DATA8 90 IOVDD 142 GND 194 GND
39 DATA7 91 ADDR15 143 DAI11 195 DPI6
40 DATA6 92 ADDR16 144 DAI10 196 DPI5
41 IOVDD 93 ADDR17 145 DAI8 197 DPI4
42 GND 94 ADDR18 146 DAI9 198 DPI3
43 VDD 95 GND 147 DAI6 199 DPI1
44 DATA4 96 IOVDD 148 DAI7 200 DPI2

160 VDD
161 VDD

163 TDI
164 TRST

171 CLK_CFG1

ADSP-21367Preliminary Technical Data

Rev. PrA | Page 45 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

Table 38. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

45 DATA5 97 ADDR19 149 DAI5 201 CLKOUT
46 DATA2 98 ADDR20 150 IOVDD 202 RESET
47 DATA3 99 ADDR21 151 GND 203 IOVDD
48 DATA0 100 ADDR23 152 VDD 204 GND
49 DATA1 101 ADDR22 153 GND 205 DATA30
50 IOVDD 102 MS1
51 GND 103 MS0
52 VDD 104 VDD 156 VDD 208 VDD

PACKAGE DIMENSIONS

The ADSP-21367 is available in a 208-lead-free MQFP package
and 256-ball lead-free and leaded SBGA packages

A1 BALL
INDICATOR

TOP VIEW

1.27

NOM

27.0 0

BSC SQ

0.70

0.60

0.50

154 VDD 206 DATA31
155 GND 207 DATA29

A1 CORNER

INDEX AREA

1214

16

1.00

0.80

0.60

20 18

15 13

1719

BOTTOM

VIEW

24.13

REF SQ

1234567891011

A
B
C
D
E

F
G
H

J
K

L
M
N
P
R

T
U
V
W

Y

1.70 MAX

0.10
MIN

COPLANARITY

DIMENSIONS ARE IN MILLIMETERS AND COMPLY
WITH JEDEC STANDARDS MO-192-BAL-2.

0.20

Figure 38. 256-Lead SBGA, Thermally Enhanced (BP-256)

Rev. PrA | Page 46 of 48 | November 2004

BALL

DIAMETER

0.90

0.75

0.60

0.25 MIN 4X

SEATING

PLANE

0.75

0.60

0.45

SEATING

PLANE

4.10

MAX

30.85

30.60 SQ

30.35

208 157

1

PIN 1 INDICATOR

TOP VIEW

(PINS DOWN)

156

28.2 0

28.00 SQ

27.8 0

ADSP-21367Preliminary Technical Data

3.60

3.40

3.20

0.50

0.25

ROTATED 90° CCW

VIEW A

VIEW A

0.20

0.09

0.08 MAX

(LEAD COPLANARITY)

1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

2. CENTER DIMENSIONS ARE TYPICAL UNLESS OTHERWISE NOTED.

52

0.50

BSC

(LEAD PITCH)

NOTES:

3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH
JEDEC STANDARD MS-029, FA-1.

(LEAD WIDTH)

0.27

0.17

105

10453

Figure 39. 208-Lead MQFP (S-208-2)

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and
combinations to run on the ADSP-21367 processor. These
products are sold as part of a chip set, bundled with necessary
application software under special part numbers. For a complete
list, visit our web site at www.analog.com/SHARC.

Part Number1,

2

Ambient Temperature
Range

Instruction
Rate

ADSP-21367SKSZ-ENG 0°C to + 70°C 266 MHz 2M bit 6M bit 1.2 INT/3.3 EXT V 208-Lead MQFP,

ADSP-21367SKBP-ENG 0°C to +70°C 400 MHz 2M bit 6M bit 1.3 INT/3.3 EXT V 256-Ball SBGA, Pb-

ADSP-21367SKBPZENG 0°C to +70°C 400 MHz 2M bit 6M bit 1.3 INT/3.3 EXT V 256-Ball SBGA, Pb-

1

B indicates Ball Grid Array package.

2

Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.

These product also may contain 3rd party IPs that may require
users to have authorization from the respective IP holders to
receive them. Royalty for use of the 3rd party IPs may also be
payable by users.

On-Chip

ROM Operating Voltage Packages

SRAM

Pb-Free

Bearing

Free

Rev. PrA | Page 47 of 48 | November 2004

ADSP-21367 Preliminary Technical Data

PR05267-0-11/04(PrA)

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

Rev. PrA | Page 48 of 48 | November 2004