Datasheet ADSP-21262 Datasheet (ANALOG DEVICES)

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Page 1

SUMMARY

ADDR

DATA

PX REGISTER

JTAG TEST & EMULATION

SER IAL PORTS ( 6)

INPUT DATA PORTS (8) PARALLEL DATA

ACQUISIT ION POR T

PER IPHERA L

TI ME R S (3 )

SI GNAL

RO UTI NG

UNIT

PRECISI ON CLOCK

GENERATORS (2)

DIGITAL AUDIO INTERFACE

ADDRESS/

DATA BUS/ GPIO

CONTROL/GPIO

PARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

CONTROL,

STATUS,

DATA BUFFERS

SPI PORT ( 1)

DMA CONTROLLER

22 CHANNELS

GPIO FLAGS/

IRQ /TIM EXP

PROCESSING

ELEMEN T

(PEY)

PROCES SING

ELEM ENT

(PEX)

TIMER

INSTRUCTION

CACHE

32  48-B IT

DAG1

8  4  32

DAG2

8  4  32

32PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

CORE PROCESS OR

PROGRAM

SEQ UENCE R

ADDR DATA

SRAM 1M BIT ROM

2M BIT

DUAL PORTED MEMORY

BLOCK 0

SRAM 1M BIT ROM

2M B IT

DUAL PORTED MEMORY

BLO C K 1

IOD (32)

IOA (19)

I/O PROCESSOR

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High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Code compatibility—at assembly level, uses the same

instruction set as other SHARC DSPs

Processes high performance audio while enabling low

system costs

Audio decoders and postprocessor algorithms support

nonvolatile memory that can be configured to contain a combination of PCM 96 kHz, Dolby Surround EX DTS® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMAPRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6

Various multichannel surround sound decoders are con-

tained in ROM. For configurations of decoder algorithms, see Table 3 on Page 6.

, DTS-ES

Discrete 6.1, DTS-ES Matrix 6.1,

Digital, Dolby Digital

SHARC

Embedded Processor

ADSP-21261/ADSP-21262/ADSP-21266

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI port, 6 serial

ports, a digital audio interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisition port (PDAP), and 3 programmable timers, all under software control by the signal routing unit (SRU)

On-chip memory—up to 2M bits on-chip SRAM and a dedi-

cated 4M bits on-chip mask-programmable ROM

The ADSP-2126x processors are available with a 150 MHz or a

200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page 47.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Functional Block Diagram

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KEY FEATURES

Serial ports offer left-justified sample-pair and I2S support

via 12 programmable and simultaneous receive or transmit pins, which support up to 24 transmit or 24 receive I channels of audio when all 6 serial ports (SPORTs) are enabled or 6 full duplex TDM streams of up to 128 channels per frame

At 200 MHz (5 ns) core instruction rate, the ADSP-2126x oper-

ates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed- or floating-point data; 400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—3 independent buses for dual

data fetch, instruction fetch, and nonintrusive, zero-overhead I/O

Up to 2M bits on-chip dual-ported SRAM (1M bit block 0, 1M

Up to 4M bits on-chip dual-ported mask-programmable ROM

Dual data address generators (DAGs) with modulo and bit-

Zero-overhead looping with single-cycle loop setup,

Single instruction multiple data (SIMD) architecture provides

Transfers between memory and core at up to four 32-bit

Accelerated FFT butterfly computation through a multiply

DMA controller supports

IEEE 1149.1 JTAG standard test access port and on-chip

Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages; avail-

Digital audio interface includes 6 serial ports, 2 precision

bit block 1) for simultaneous access by core processor and DMA

(2M bits in block 0 and 2M bits in block 1)

reverse addressing

providing efficient program sequencing

2 computational processing elements Concurrent execution—each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows single

cycle executions (with or without SIMD) of a multiply operation; an ALU operation; a dual memory read or write; and an instruction fetch

floating- or fixed-point words per cycle, sustained

2.4 GBps bandwidth at 200 MHz core instruction rate; 900 Mbps is available via DMA

with add and subtract instruction

Up to 22 zero-overhead DMA channels for transfers

between the ADSP-2126x internal memory and serial ports (12), the input data ports (IDP) (8), the SPI-compatible port (1), and the parallel port (1)

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

emulation

able in RoHS compliant packages

clock generators, an input data port, 3 programmable timers, and a signal routing unit

Asynchronous parallel/external port provides

Access to asynchronous external memory 16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data 66M byte/sec transfer rate for 200 MHz core rate 50M byte/sec transfer rate for 150 MHz core rate 256 word page boundaries External memory access in a dedicated DMA channel 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLKs

Serial ports provide

50M bits/sec for a 200 MHz core and up to 37.5M bits/sec

for a 150 MHz core on each data line—each has a clock,

frame sync, and 2 data lines that can be configured as

either a receiver or transmitter pair Left-justified sample-pair and I

direction for up to 24 simultaneous receive or transmit

channels (16 channels on the ADSP-21261) using 2 I

compatible stereo devices per serial port TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-

faces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels

per frame Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core configurable as either 8 channels of I serial data or as 7 channels plus a single 20-bit wide synchronous parallel data acquisition port

Supports receive audio channel data in I

sample pair, or right-justified mode

Signal routing unit (SRU) provides configurable and flexible

connections between all DAI components, 6 serial ports, two precision clock generators, 3 timers, an input data port/parallel data acquisition port, 10 interrupts, 6 flag inputs, 6 flag outputs, and 20 SRU I/O pins (DAI_Px)

Serial peripheral interface (SPI)

Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open-drain outputs Programmable baud rates, clock polarities, and phases

3 muxed flag/IRQ lines 1 muxed flag/timer expired line ROM-based security features:

JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

S support, programmable

S, left-justified

S-

S or

Rev. E | Page 2 of 48 | July 2008

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ADSP-21261/ADSP-21262/ADSP-21266

Summary ............................................................... 1

Key Features ........................................................... 2

Table of Contents .................................................... 3

Revision History ...................................................... 3

General Description ................................................. 4

Family Core Architecture ....................................... 5

Memory and I/O Interface Features ........................... 6

Target Board JTAG Emulator Connector .................... 9

Development Tools ............................................... 9

Evaluation Kit ..................................................... 10

Designing an Emulator-Compatible DSP Board (Target) 11

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Address Data Pins as Flags ..................................... 15

Core Instruction Rate to CLKIN Ratio Modes ............. 15

Address Data Modes ............................................. 15

Product Specifications .............................................. 16

Operating Conditions ........................................... 16

Electrical Characteristics ........................................ 16

Package Information ............................................ 17

ESD Caution ...................................................... 17

Maximum Power Dissipation ................................. 17

Absolute Maximum Ratings ................................... 17

Timing Specifications ........................................... 17

Output Drive Currents .......................................... 39

Test Conditions ................................................... 39

Capacitive Loading ............................................... 39

Environmental Conditions ..................................... 40

Thermal Characteristics ........................................ 40

144-Lead LQFP Pin Configurations ............................. 41

136-Ball BGA Pin Configurations .. ............................. 42

Outline Dimensions ................................................ 45

Surface-Mount Design .......................................... 45

Ordering Guide ...................................................... 47

REVISION HISTORY

7/08—Rev. D to Rev. E

This revision of the data sheet combines the ADSP-21261 and

ADSP-21262 into the ADSP-21266 data sheet.

Corrected all outstanding document errata.

Corrected block diagram............................................. 1

Added Extended Precision Normal or Instruction Word (48

Bits) to Table 4 and Table 5 ......................................... 7

Revised VCO specification in Clock Input .....................20

Rev. E | Page 3 of 48 | July 2008

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GENERAL DESCRIPTION

The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs are members of the SIMD SHARC family of DSPs featuring Analog Devices Inc., Super Harvard Architecture. The ADSP-2126x is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP2106x SHARC processors in SISD (single-instruction, singledata) mode. Like other SHARC DSPs, the ADSP-2126x are 32-bit/40-bit floating-point processors optimized for high performance audio applications with dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface.

Table 1 shows performance benchmarks for the processors run-

ning at 200 MHz. Table 2 shows the features of the individual product offerings.

Table 1. Processor Benchmarks (at 200 MHz)

Speed

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap) IIR Filter (per biquad) Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1] Divide (y/x) Inverse Square Root

Assumes two files in multichannel SIMD mode.

(at 200 MHz)

61.3 μs

3.3 ns

13.3 ns

30 ns

53.3 ns 20 ns

30 ns

As shown in the functional block diagram in Figure 1 on Page 1, the ADSP-2126x uses two computational units to deliver a 5 to 10 times performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-theart, high speed, CMOS process, the ADSP-2126x DSPs achieve an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at 150 MHz. With its SIMD computational hardware, the ADSP-2126x can perform 1200 MFLOPS running at 200 MHz, or 900 MFLOPS running at 150 MHz.

Table 2. ADSP-2126x SHARC Processor Features

Feature ADSP-21261 ADSP-21262 ADSP-21266

RAM 1M bit 2M bit 2M bit

ROM 3M bit 4M bit 4M bit

Audio Decoders

in ROM

DMA Channels 18 22 22

SPORTs 4 6 6

Package 136-ball BGA

For information on available audio decoding algorithms, see Table 3 on Page 6.

No No Yes

144-lead LQFP

136-ball BGA 144-lead LQFP

The ADSP-2126x continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include 2M bit dual-ported SRAM memory, 4M bit dual-ported ROM, an I/O processor that supports 22 DMA channels, six serial ports, an SPI interface, external parallel bus, and digital audio interface.

The block diagram of the ADSP-2126x on Page 1 illustrates the following architectural features:

• Two processing elements, each containing an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle

• Three programmable interval timers with PWM generation, PWM capture/pulse width measurement, and external event counter capabilities

• On-chip dual-ported SRAM (up to 2M bit)

• On-chip dual-ported, mask-programmable ROM (up to 4M bit)

• JTAG test access port

• 8- or 16-bit parallel port that supports interfaces to off-chip memory peripherals

• DMA controller

• Six full-duplex serial ports (four on the ADSP-21261)

• SPI-compatible interface

• Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), six serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three programmable timers, and a flexible signal routing unit (SRU)

Figure 2 shows one sample configuration of a SPORT using the

precision clock generator to interface with an I

S DAC with a much lower jitter clock than the serial port

I would generate itself. Many other SRU configurations are

S ADC and an

possible.

FAMILY CORE ARCHITECTURE

The ADSP-2126x is code compatible at the assembly level with the ADSP-2136x and ADSP-2116x, and with the first generation ADSP-2106x SHARC DSPs. The ADSP-2126x shares architectural features with the ADSP-2136x and ADSP-2116x SIMD SHARC family of DSPs, as detailed in the following sections.

SIMD Computational Engine

The ADSP-2126x contain two computational processing elements that operate as a single-instruction multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY

Rev. E | Page 4 of 48 | July 2008

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ADSP-21261/ADSP-21262/ADSP-21266

DAI

SPORT 5

SPO RT4

SPORT3

SPO RT2

SP ORT 1

SPORT0

SCL K0

SD0A

SFS0

SD0B

SRU

DA I_ P 1 DAI_P2 DAI_P3

DA I_ P1 8

DA I_ P19

DA I_P 20

CLOCK

2 2

CLKIN XTA L

CLK_CFG1–0 BOOTCFG1–0

FLAG 3–1

ADDR

PARALLEL

PO RT

RA M , R O M

BOOT ROM

I/O D EVIC E

DA TA

CLKOUT

ALE

AD15–0

LATCH

RESE T JTAG

ADSP-21266

ADDRESS

DATA

CONTROL

FL A G0

PCGB

PCG A

CLK FS

ADC

(OPTIONAL)

CLK

SDAT

DAC

(OPTIONAL)

CLK

SDAT

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Figure 2. ADSP-21266 System Sample Configuration

and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive audio algorithms.

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing

Rev. E | Page 5 of 48 | July 2008

elements. These computation units support IEEE 32-bit single precision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2126x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2126x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With the ADSP-2126x’s separate pro- gram and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

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Instruction Cache

The ADSP-2126x includes an on-chip instruction cache that enables three-bus operation to fetch an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The ADSP-2126x’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-2126x contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-2126x can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-2126x adds the following architectural features to the SIMD SHARC family core:

Dual-Ported On-Chip Memory

The ADSP-21262 and ADSP-21266 contain two megabits of internal SRAM and four megabits of internal mask-programmable ROM. The ADSP-21261 contain one megabit of internal SRAM and three megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see memory maps, Table 4 and

Table 5). Each memory block is dual-ported for single-cycle,

independent accesses by the core processor and I/O processor. The dual-ported memory, in combination with three separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle.

The ADSP-2126x is available with a variety of multichannel surround sound decoders, preprogrammed in ROM memory.

Table 3 shows the configuration of decoder algorithms.

Table 3. Multichannel Surround Sound Decoder Algorithms in On-Chip ROM

Algorithms B ROM C ROM D ROM

PCM Yes Yes Yes AC-3 Yes Yes Yes DTS 96/24 v2.2 v2.3 v2.3 AAC (LC) Yes Yes Coefficients only WMAPRO 7.1 96 KHz No No Yes MPEG2 BC 2ch Yes Yes No Noise Yes Yes Yes DPL2x/EX DPL2 Yes Yes Neo:6/ES (v2.5046) Yes Yes Yes

The ADSP-2126x’s SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.

Using the DM bus and PM buses, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

Rev. E | Page 6 of 48 | July 2008

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Table 4. Internal Memory Space (ADSP-21261)

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Block 0 SRAM 0x0004 0000–0x0004 1FFF

Reserved 0x0004 2000–0x0005 7FFF

Block 0 ROM 0x0005 8000–0x0002 FFFF

Reserved 0x0005 3000–0x0005 FFFF

Block 1 SRAM 0x0006 0000–0x0006 1FFF

Reserved 0x0006 2000–0x0007 7FFF

Block 1 ROM 0x0007 8000–0x0007 DFFF

Reserved 0x0007 E000–0x0007 FFFF

Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 SRAM 0x0008 0000–0x0008 2AAA

Reserved Reserved

Block 0 ROM 0x000A 0000–0x000A 7FFF

Reserved Reserved

Block 1 SRAM 0x000C 0000–0x000C 2AAA

Reserved Reserved

Block 1 ROM 0x000E 0000–0x000E 7FFF

Reserved Reserved

Table 5. Internal Memory Space (ADSP-21262/ADSP-21266)

Block 0 SRAM 0x0008 0000–0x0008 3FFF

0x0008 4000–0x000A FFFF

Block 0 ROM 0x000B 0000–0x000B BFFF

0x000B C000–0x000B FFFF

Block 1 SRAM 0x000C 0000–0x000C 3FFF

0x000C 4000–0x000E FFFF

Block 1 ROM 0x000F 0000–0x000F BFFF

0x000F C000–0x000F FFFF

Block 0 SRAM 0x0010 0000–0x0010 7FFF

Reserved 0x0010 8000–0x0015 FFFF

Block 0 ROM 0x0016 0000–0x0017 7FFF

Reserved 0x0017 8FFF–0x0017 FFFF

Block 1 SRAM 0x0018 0000–0x0018 7FFF

Reserved 0x0018 8000–0x001D FFFF

Block 1 ROM 0x001E 0000–0x001F 7FFF

Reserved 0x0000

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Block 0 SRAM 0x0004 0000–0x0004 3FFF

Reserved 0x0004 4000–0x0005 7FFF

Block 0 ROM 0x0005 8000–0x0005 FFFF

Block 1 SRAM 0x0006 0000–0x0006 3FFF

Reserved 0x0006 4000–0x0007 7FFF

Block 1 ROM 0x0007 8000–0x0007 FFFF

Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 SRAM 0x0008 0000–0x0008 5555

Reserved Reserved

Block 0 ROM 0x000A 0000–0x000A AAAA

Block 1 SRAM 0x000C 0000–0x000C 5555

Reserved Reserved

Block 1 ROM 0x000E 0000–0x000E AAAA

DMA Controller

The ADSP-2126x’s on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-2126x’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) port, the IDP (input data port), parallel data acquisition port (PDAP), or the parallel port. Up to 22 channels of DMA are available on the ADSP-2126x—one for the SPI interface, 12 via

Block 0 SRAM 0x0008 0000–0x0008 7FFF

0x0008 8000–0x000A FFFF

Block 0 ROM 0x000B 0000–0x000B FFFF

Block 1 SRAM 0x000C 0000–0x000C 7FFF

0x000C 8000–0x000E FFFF

Block 1 ROM 0x000F 0000–0x000F FFFF

the serial ports, eight via the input data port, and one via the processor’s parallel port. Programs can be downloaded to the ADSP-2126x using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The digital audio interface provides the ability to connect various peripherals to any of the SHARC DSP’s DAI pins (DAI_P20–1).

Block 0 SRAM 0x0010 0000–0x0010 FFFF

Reserved 0x0011 0000–0x0015 FFFF

Block 0 ROM 0x0016 0000–0x0017 FFFF

Block 1 SRAM 0x0018 0000–0x0018 FFFF

Reserved 0x0019 0000–0x001D FFFF

Block 1 ROM 0x001E 0000–0x001F FFFF

Rev. E | Page 7 of 48 | July 2008

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Connections are made using the signal routing unit (SRU, shown in the block diagram on Page 1).

The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths.

The DAI also includes six serial ports, two precision clock generators (PCGs), an input data port (IDP), six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-2126x core, configurable as either eight channels of I 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-2126x’s serial ports.

For complete information on using the DAI, see the ADSP-2126x SHARC DSP Peripherals Manual.

S or serial data, or as seven channels plus a single

Serial Ports

The ADSP-2126x features six full duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the Analog Devices AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has its own dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTs are enabled, or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of 50M bits/sec for a 200 MHz core and 37.5M bits/sec for a 150 MHz core. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides two receive signals. The frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame sync cycle, two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode.

Each of the serial ports supports the left-justified sample-pair and I monly used by audio codecs, ADCs, and DACs) with two data pins, allowing four left-justified sample-pair or I

S protocols (I2S is an industry-standard interface com-

S channels

(using two stereo devices) per serial port with a maximum of up to 24 audio channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated.

Serial Peripheral (Compatible) Interface

The serial peripheral interface is an industry-standard synchronous serial link, enabling the ADSP-2126x SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2126x SPI-compatible peripheral implementation also features programmable baud rates at up to 50 MHz for a core clock of 200 MHz and up to 37.5 MHz for a core clock of 150 MHz, clock phases, and polarities. The ADSP-2126x SPI-compatible port uses open-drain drivers to support a multimaster configuration and to avoid data contention.

Parallel Port

The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is one-third the core clock speed. As an example, a clock rate of 200 MHz is equivalent to 66M byte/sec, and a clock rate of 150 MHz is equivalent to 50M byte/sec.

DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port.

Tim er s

The ADSP-2126x has a total of four timers: a core timer able to generate periodic software interrupts, and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register,

Rev. E | Page 8 of 48 | July 2008

Page 9

a 32-bit period register, and a 32-bit pulse width register. A sin-

DDINT

HIGH-Z FERRITE

BEAD CHIP

VDD

VSS

100nF 10 nF 1nF

ADSP-212xx

LOCATE ALL COMPONENTS

CLOSE TO A

VDD

AND A

VSS

PINS

www.BDTIC.com/ADI

gle control and status register enables or disables all three general-purpose timers independently.

ROM-Based Security

The ADSP-2126x has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port, will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.

Program Booting

The internal memory of the ADSP-2126x boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins.

Phase-Locked Loop

The ADSP-2126x uses an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLK_CFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 2, 4, 8, and 16.

Power Supplies

The ADSP-2126x has separate power supply connections for the internal (V

), external (V

DDINT

), and analog (A

DDEXT

VDD/AVSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply.

Note that the analog supply pin (A

) powers the

VDD

ADSP-2126x’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the A possible to the A

Figure 3. (A recommended ferrite chip is the muRata

pin. Place the filter components as close as

VDD

VDD/AVSS

pins. For an example circuit, see

BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for

and GND. Use wide traces to connect the bypass capac-

DDINT

itors to the analog power (A that the A

VDD

and A

pins specified in Figure 3 are inputs to

VSS

the processor and not the analog ground plane on the board— the A

pin should connect directly to digital ground (GND) at

VSS

) and ground (A

VDD

VSS

) pins. Note

the chip.

ADSP-21261/ADSP-21262/ADSP-21266

Figure 3. Analog Power Filter Circuit

emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.

For complete information on Analog Devices SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The ADSP-2126x is supported by a complete automotive reference design and development board as well as by a complete home audio reference design board available from Analog Devices. These boards implement complete audio decoding and postprocessing algorithms that are factory programmed into the ROM space of the ADSP-2126x. SIMD optimized libraries consume less processing resources, which results in more available processing power for custom proprietary features.

The nonvolatile memory of the ADSP-2126x can be configured to contain a combination of Dolby Digital, Dolby Pro Logic, Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24, and Neo:6. Multiple S/PDIF and analog I/Os are provided to maximize end system flexibility.

The ADSP-2126x is also supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2126x.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The ADSP-2126x SHARC DSP has architectural features that improve the efficiency of compiled C/C++ code.

†

software and hardware development tools,

‡

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2126x processor to monitor and control the target board processor during

Rev. E | Page 9 of 48 | July 2008

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

Page 10

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tools’ command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It also is used for downloading components from the Web, dropping them into the application, and publishing component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, and examine run-time stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range o ware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

f tools supporting the SHARC processor family. Hard-

EVALUATION KIT

Analog Devices offers a range of EZ-KIT Lite forms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

†

EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

†

evaluation plat-

Rev. E | Page 10 of 48 | July 2008

Page 11

DESIGNING AN EMULATOR-COMPATIBLE DSP

www.BDTIC.com/ADI

BOARD (TARGET)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

ADSP-21261/ADSP-21262/ADSP-21266

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2126x architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x SHARC DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference.

Rev. E | Page 11 of 48 | July 2008

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ADSP-21261/ADSP-21262/ADSP-21266

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PIN FUNCTION DESCRIPTIONS

The ADSP-2126x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to V

or GND, except for the following:

DDEXT

DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI and AD15–0 (NOTE: These pins have internal pull-up resistors.)

The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open-drain, and T = three-state.

Table 6. Pin Descriptions

State During and

Pin Type

AD15–0 I/O/T Rev. 0.1 silicon—

ALE O Output only, driven

FLAG3–0 I/O/A Three-state Flag Pins. Each FLAG pin is configured via control bits as either an input or output. As an

DAI_P20–1 I/O/T Three-state with

O Output only, driven

After Reset Function

Parallel Port Address/Data. The parallel port and its corresponding DMA unit output

AD15–0 pins are driven low both during and after reset.

Rev. 0.2 silicon— AD15–0 pins are three-stated and pulled high both during and after reset.

high

low

programmable pull-up

addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address Data Modes on Page 15 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, A23–8; ALE is used in conjunction with an external latch to retain the values of the A23–8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A15–0; ALE is used in conjunction with an external latch to retain the values of the A15–0. To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the SYSCTL register and disable the parallel port. See Table 7 on Page 15 for a list of how the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL register, the IDP Channel 0 can use these pins for parallel input data.

Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or 16-bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted.

Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains deasserted.

Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a new address on the parallel port address pin. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted.

input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set (= 1) in the SYSCTL register, FLAG0 is configured as IRQ0. When Bit 17 is set (= 1) in the SYSCTL register, FLAG1 is configured as IRQ1. When Bit 18 is set (= 1) in the SYSCTL register, FLAG2 is configured as IRQ2. When Bit 19 is set (= 1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which indicates that the system timer has expired.

Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU can be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators, and timers to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register.

and the TIMEXP signals.

Rev. E | Page 12 of 48 | July 2008

Page 13

Table 6. Pin Descriptions (Continued)

www.BDTIC.com/ADI

State During and

Pin Type

SPICLK

SPIDS

MOSI

MISO

BOOT_CFG1–0

CLKIN

XTAL

I/O

I/O (O/D)

After Reset Function

Three-state with pull-up enabled, driven high in SPImaster boot mode

Input only

Three-state with pull-up enabled, driven low in SPImaster boot mode

Three-state with pull-up enabled

Input only

Output only

ADSP-21261/ADSP-21262/ADSP-21266

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode.

Serial Peripheral Inter face Slave Device Select. An active low signal used to select the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode, the DSP’s SPIDS signal can be dri ven by a s lav e de vic e to sig nal t o th e DSP (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high

on the master device. For ADSP-2126x to ADSP-2126x SPI interaction, any of the

to V

DDEXT

master ADSP-2126x’s flag pins can be used to drive the SPIDS signal on the ADSP-2126x SPI slave device.

SPI Master Out Slave In. If the ADSP-2126x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-2126x is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-2126x SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode.

SPI Master In Slave Out. If the ADSP-2126x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-2126x is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-2126x SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the DSP’s MISO pin can be disabled by setting (=1) Bit 5 (DMISO) of the SPICTL register.

Boot Configuration Select. Selects the boot mode for the DSP. The BOOT_CFG pins must be valid before reset is asserted. See Table 8 on Page 15 for a description of the boot modes.

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2126x clock input. It configures the ADSP-2126x to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-2126x to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated below the specified frequency.

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

Rev. E | Page 13 of 48 | July 2008

Page 14

ADSP-21261/ADSP-21262/ADSP-21266

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Table 6. Pin Descriptions (Continued)

State During and

Pin Type

CLK_CFG1–0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Tabl e 9 for a

RESETOUT/ O Output only Reset Out/Local Clock Out. Drives out the core reset signal to an external device. CLKOUT CLKOUT can also be configured as a reset out pin (RESETOUT). The functionality can be

RESET I/A Input only Processor Reset. Resets the ADSP-2126x to a known state. Upon deassertion, there is a

TCK I Input only

TMS I/S Three-state with

TDI I/S Three-state with

TDO O Three-state TRST I/A Three-state with

EMU O (O/D) Three-state with

DDINT

DDEXT

VDD

VSS

P Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

P I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP

P Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL (clock

G Analog Power Supply Return.

GND G Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver, with both output path and pull-up disabled.

Three-state is a three-state driver, with pull-up disabled.

After Reset Function

description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out.

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2126x.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a

pull-up enabled

22.5 kΩ internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5

kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path. Te st R es e t ( J TAG ) . Resets the test state machine. TRST must be asserted (pulsed low) after

pull-up enabled

power-up or held low for proper operation of the ADSP-2126x. TRST has a 22.5 kΩ internal pull-up resistor.

Emulation Status. Must be connected to the ADSP-2126x Analog Devices DSP Tools

pull-up enabled

product line of JTAG emulators target board connector only. EMU has a

22.5 kΩ internal pull-up resistor.

(13 pins on the BGA package, 32 pins on the LQFP package).

package).

generator). This pin has the same specifications as V circuitry is required. For more information, see Power Supplies on Page 9.

, except that added filtering

DDINT

Rev. E | Page 14 of 48 | July 2008

Page 15

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the SYSCTL register and disable the parallel port.

Table 7. AD15–0 to FLAG Pin Mapping

AD Pin Flag Pin

AD0 FLAG8 AD8 AD1 FLAG9 AD9 AD2 FLAG10 AD10 AD3 FLAG11 AD11 AD4 FLAG12 AD12 AD5 FLAG13 AD13 AD6 FLAG14 AD14 AD7 FLAG15 AD15

Boot Modes

Table 8. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot 01 SPI Master Boot 10 Parallel Port Boot via EPROM 11 Reserved

AD Pin Flag Pin

FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7

ADDRESS DATA MODES

Table 10 shows the functionality of the AD pins for 8-bit and

16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15–A0 when asserted, followed by data bits D15–D0 when deasserted.

Table 10. Address/Data Mode Selection

EP Data AD7–0 AD15–8 Mode ALE Function Function

8-bit Asserted A15–8 A23–16 8-bit Deasserted D7–0 A7–0 16-bit Asserted A7–0 A15–8 16-bit Deasserted D7–0 D15–8

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 9. Core Instruction Rate/CLKIN Ratio Selection

CLK_CFG1–0 Core to CLKIN Ratio

00 3:1 01 16:1 10 8:1 11 Reserved

Rev. E | Page 15 of 48 | July 2008

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ADSP-21261/ADSP-21262/ADSP-21266

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PRODUCT SPECIFICATIONS

OPERATING CONDITIONS

Parameter

DDINT

VDD

DDEXT

IH_CLKIN

IL_CLKIN

AMB

Specifications subject to change without notice.

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

Applies to input pin CLKIN.

See Thermal Characteristics on Page 40 for information on thermal specifications.

See Engineer-to-Engineer Note (No. EE-216) for further information.

Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage Low Level Input Voltage

K Grade

High Level Input Voltage Low Level Input Voltage @ V Ambient Operating Temperature

@ V

= Max

DDEXT

@ V

DDEXT

= Min

= Max

= Min

4, 5

Min Max Unit

1.14

3.13

2.0 –0.5

1.74 –0.5 0

1.26

3.47 V

+ 0.5

DDEXT

+0.8 V

+ 0.5

DDEXT

+1.19 +70

ELECTRICAL CHARACTERISTICS

Parameter

ILPU

OZH

OZL

OZLPU

DD-INTYP

AVDD

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See Output Drive Currents on Page 39 for typical drive current capabilities.

Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: FLAG3–0.

Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, MISO, MOSI.

Applies to open-drain output pins: EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note (EE-216) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current Pull-Up Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Pull-Up Supply Current (Internal) Supply Current (Analog) Input Capacitance

12, 13

4, 5

6, 7, 8

9, 10, 11

@ V

= Min, IOH = –1.0 mA

DDEXT

@ V

= Min, IOL = 1.0 mA

DDEXT

@ V

= Max, VIN = V

DDEXT

@ V

= Max, VIN = 0 V 10 µA

DDEXT

@ V

= Max, VIN = 0 V 200 µA

DDEXT

@ V

= Max, VIN = V

DDEXT

@ V

= Max, VIN = 0 V 10 µA

DDEXT

@ V

= Max, VIN = 0 V 200 µA

DDEXT

= 5.0 ns, V

CCLK

= Max 10 mA

VDD

fIN = 1 MHz, T

= 1.2 V, T

DDINT

= 25°C, VIN = 1.2 V 4.7 pF

CASE

Max 10 µA

DDEXT

Max 10 µA

DDEXT

= +25°C 500 mA

AMB

2.4 V

0.4 V

Test Conditions Min Max Unit

V V V V V V V °C

Rev. E | Page 16 of 48 | July 2008

Page 17

ADSP-21261/ADSP-21262/ADSP-21266

vvvvvv.x n.n

tppZ-cc

ADSP-2126x

#yyww country_o f_origin

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

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PACKAGE INFORMATION

The information presented in Figure 4 provides details about the package branding for the ADSP-21266 processors. For a complete listing of product availability, see Ordering Guide on

Page 47.

Figure 4. Typical Package Brand

Table 11. Package Brand Information

Brand Key Field Description

t Temperature Range pp Package Type Z RoHS Compliant Option (optional) cc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision # RoHS Compliant Designation yyww Date Code

ESD CAUTION

Table 12. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V Analog (PLL) Supply Voltage (A External (I/O) Supply Voltage (V Input Voltage –0.5 V to V Output Voltage Swing –0.5 V to V Load Capacitance 200 pF Storage Temperature Range –65°C to +150°C Junction Temperature Under Bias 125°C

VDD

DDEXT

+0.5 V

DDEXT

) –0.3 V to +1.4 V

DDINT

) –0.3 V to +1.4 V

) –0.3 V to +3.8 V

+0.5 V

DDEXT

TIMING SPECIFICATIONS

The ADSP-2126x’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports).

The ADSP-2126x’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 13 and Table 14.

In Table 13, CCLK is defined as

= (2 × PLLM × f

CCLK

INPUT

) ÷ (2 × PLLN)

where:

= CCLK frequency

CCLK

PLLM = Multiplier value programmed

PLLN = Divider value programmed.

MAXIMUM POWER DISSIPATION

See Estimating Power for the ADSP-21262 SHARC Processors (EE-216) for detailed thermal and power information regarding

maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 40.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 12 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. E | Page 17 of 48 | July 2008

Table 13. CLKOUT and CCLK Clock Generation Operation

Timing Requirements Description Calculation

CLKIN Input Clock 1/t CCLK Core Clock Variable, see equation

Note the definitions of various clock periods shown in Table 14

which are a function of CLKIN and the appropriate ratio control shown in Table 13.

Page 18

ADSP-21261/ADSP-21262/ADSP-21266

MCLK

XTAL

BUF

CLK_CFGx/

LOOP

FILTER

CLKIN

PLL

CLKIN

DIVIDER

DELAY OF

4096 CLKIN

CYCLES

PLL

MULTIPLIER

VCO

BUF

PLLI CLK

PMCTL

PLL

DIVIDER

CLK_CFGx/PMCTL

MUX

DIVIDE

BY 2

RESETOUT

CLKOUT

CCLK

PMCTL

RESETOUT

CLKOUT

RESET

CORERST

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Table 14. Clock Periods

Timing Requirements Description

CCLK

MCLK

SCLK

SPICLK

where: SR = serial port-to-core clock ratio (wide range, determined by SPORT

CLKDIV) SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register) SCLK = serial port clock SPICLK = SPI clock

Figure 5 shows core to CLKIN relationships with external oscil-

CLKIN Clock Period (Processor) Core Clock Period Internal memory clock = 1/2 t Serial Port Clock Period = (t SPI Clock Period = (t

CCLK

) × SR

CCLK

) × SPIR

CCLK

lator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-2126x SHARC Processor

Peripherals Reference and Managing the Core PLL on ThirdGeneration SHARC Processors (EE-290).

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times.

See Figure 30 on Page 39 under Test Conditions for voltage reference levels.

Note that in the user application, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds f

specified in Table 16. The VCO frequency is calcu-

VCO

lated as follows:

VCO

INPUT

= 2 × PLLM × f

where:

is the VCO frequency.

VCO

PLLM is the multiplier value programmed.

is the input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled and

INPUT

= CLKIN ÷ 2 when the input divider is enabled.

INPUT

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

Switching characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Figure 5. Core Clock and System Clock Relationship to CLKIN

Rev. E | Page 18 of 48 | July 2008

Page 19

ADSP-21261/ADSP-21262/ADSP-21266

CLKIN

RESET

RSTVDD

RESETOUT

(MULTIPLEXEDWITHCLKOUT)

DDEXT

DDINT

PLLRST

CLKRST

CLKVDD

IVDDEVDD

CLK_CFG1–0

CORERST

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Power-Up Sequencing

The timing requirements for DSP startup are given in Table 15 and Figure 6.

Table 15. Power-Up Sequencing (DSP Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

IVDDEVDD

CLKVDD

CLKRST

PLLRST

RESET Low Before V

On Before V

DDINT

V CLKIN Valid After V

DDINT/VDDEXT

DDEXT

DDINT/VDDEXT

CLKIN Valid Before RESET Deasserted PLL Control Setup Before RESET Deasserted

Valid

0 –50 0 10 20

ns +200 200

µs

Switching Characteristics

4, 5

CORERST

Valid V

DDINT/VDDEXT

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

4097 cycles maximum.

DSP Core Reset Deasserted After RESET Deasserted

assumes that the supplies are fully ramped to their 1.2 V and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

specification in Table 17. If setup time is not met, one additional CLKIN cycle can be added to the core reset time, resulting in

SRST

4096 × t

Figure 6. Power-Up Sequencing

Rev. E | Page 19 of 48 | July 2008

Page 20

ADSP-21261/ADSP-21262/ADSP-21266

CLKIN

CKH

CKL

CLKIN XTAL

1M 

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FO R DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKC FG1-0 = 10 OR = 01.

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Clock Input

See Table 16 and Figure 7.

Table 16. Clock Input

150 MHz

Parameter

Timing Requirements

CKL

CKH

CKRF

vco

CCLK

Applies to all 150 MHz models. See Ordering Guide on Page 47.

Applies to all 200 MHz models. See Ordering Guide on Page 47.

Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.

See Figure 5 on Page 18 for VCO diagram.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CLKIN Period 20 CLKIN Width Low 7.5 CLKIN Width High 7.5 CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 ns VCO Frequency 200 800 200 800 MHz CCLK Period

Min

Max Min

160

6.66 10 5 10 ns

15 6 6

200 MHz

Max

160

Unit

ns ns ns

CCLK

Figure 7. Clock Input

Clock Signals

The ADSP-2126x can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-2126x to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode. Note that the 200 MHz clock rate is achieved using a 12.5 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN).

Figure 8. 150 MHz or 200 MHz Operation with a 12.5 MHz

Fundamental Mode Crystal

Rev. E | Page 20 of 48 | July 2008

Page 21

ADSP-21261/ADSP-21262/ADSP-21266

CLKIN

RESET

WRST

SRST

DAI_P20–1

(FLAG2–0)

(IRQ2–0)

IPW

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Reset

See Table 17 and Figure 9.

Table 17. Reset

Parameter Min Max Unit

Timing Requirements

WRST

SRST

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

RESET Pulse Width Low RESET Setup Before CLKIN Low

Interrupts

The timing specification in Table 18 and Figure 10 applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins when configured as interrupts.

4 × t

Figure 9. Reset

ns ns

Table 18. Interrupts

Parameter Min Max Unit

Timing Requirements

IPW

IRQx Pulse Width 2 t

Figure 10. Interrupts

+2 ns

CCLK

Rev. E | Page 21 of 48 | July 2008

Page 22

ADSP-21261/ADSP-21262/ADSP-21266

FLG 3

(C T I M ER)

WC T IM

DAI_P20–1

(TIM ER)

PWMO

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Core Timer

The timing specification in Table 19 and Figure 11 applies to FLAG3 when it is configured as the core timer (CTIMER).

Table 19. Core Timer

Parameter Min Max Unit

Switching Characteristics

WCTIM

CTIMER Pulse Width 4 × t

Timer PWM_OUT Cycle Timing

The timing specification in Table 20 and Figure 12 applies to Timer in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Figure 11. Core Timer

– 1 ns

CCLK

Table 20. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristics

PWMO

Timer Pulse Width Output 2 × t

Figure 12. Timer PWM_OUT Timing

– 1 2(231 – 1) × t

CCLK

Rev. E | Page 22 of 48 | July 2008

Page 23

ADSP-21261/ADSP-21262/ADSP-21266

DAI_P20–1

(TIM ER)

PWI

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Timer WDTH_CAP Timing

The timing specification in Table 21 and Figure 13 applies to Timer in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 21. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirements

PWI

Timer Pulse Width 2 × t

CCLK

2(231 – 1) × t

CCLK

Figure 13. Timer Width Capture Timing

Rev. E | Page 23 of 48 | July 2008

Page 24

ADSP-21261/ADSP-21262/ADSP-21266

DAI _Pn

DAI_Pm

DPIO

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DAI Pin-to-Pin Direct Routing

See Table 22 and Figure 14 for direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O).

Table 22. DAI Pin-to-Pin Routing

Parameter Min Max Unit

Timing Requirements

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

Figure 14. DAI Pin-to-Pin Direct Routing

Rev. E | Page 24 of 48 | July 2008

Page 25

ADSP-21261/ADSP-21262/ADSP-21266

STRI G

DAI_Pn

PCG_TRIGx_I

DAI_Pm

PCG

_EXTx_I

(CLKIN)

DAI_Py

PCG

_CLKx_O

DAI_P z

PCG

_FSx_O

HTRIG

DPCGIO

DTRIG

PCGOW

PCGIW

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Precision Clock Generator (Direct Pin Routing)

The timing in Table 23 and Figure 15 is valid only when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buff-

cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P07–DAI_P20).

ers) and sends its outputs directly to the DAI pins. For the other

Table 23. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements t

PCGIW

STRIG

HTRIG

Input Clock Pulse Width PCG Trigger Setup Before Falling Edge of PCG Input Clock PCG Trigger Hold After Falling Edge of PCG Input Clock

20 2 2

ns ns

Switching Characteristics

DPCGIO

DTRIG

PCGOW

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock Falling Edge

PCG Output Clock and Frame Sync Delay After PCG Trigger Output Clock Pulse Width

2.5

2.5 + 2.5 × t 40

PCGOW

10 10 + 2.5 × t

PCGOW

ns ns ns

Figure 15. Precision Clock Generator (Direct Pin Routing)

Rev. E | Page 25 of 48 | July 2008

Page 26

ADSP-21261/ADSP-21262/ADSP-21266

DAI_P20–1

(FLAG3–0

)

(AD15–0)

DAI_P20–1

(FLAG3–0

OUT

)

(AD15–0)

FOPW

FIPW

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Flags

The timing specifications in Table 24 and Figure 16 apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 6 on Page 12 for more information on flag use.

Table 24. Flags

Parameter Min Max Unit

Timing Requirements

FIPW

FLAG3–0 IN Pulse Width

Switching Characteristics

FOPW

FLAG3–0 OUT Pulse Width

2 × t

CCLK

+ 3

– 1

Figure 16. Flags

Rev. E | Page 26 of 48 | July 2008

Page 27

ADSP-21261/ADSP-21262/ADSP-21266

ALE

AD15

AD7

VALID DATA

VALID ADDRESS VALID ADDRESS

ADAS

VALID ADDRESS

ALEW

ADAH

ADRH

ALEHZ

DRS

DRH

DAD

ALERW

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Memory Read—Parallel Port

The specifications in Table 25, Table 26, Figure 17, and

Figure 18 are for asynchronous interfacing to memories (and

memory-mapped peripherals) when the ADSP-2126x is accessing external memory space.

Table 25. 8-Bit Memory Read Cycle

Parameter Min Max Unit

Timing Requirements

DRS

DRH

DAD

Switching Characteristics

ALEW

ALERW

ADAS

1 Address/Data 15–0 Hold After ALE Deasserted

ADAH

ALEHZ

ADRH

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

Address/Data 7–0 Setup Before RD High Address/Data 7–0 Hold After RD High Address 15–8 to Data Valid

ALE Pulse Width ALE Deasserted to Read/Write Asserted Address/Data 15–0 Setup Before ALE Deasserted

ALE Deasserted to Address/Data7–0 in High-Z RD Pulse Width Address/Data 15–8 Hold After RD High

CCLK

3.3 0

2 × t 1 × t

2.5 × t

0.5 × t

0.5 × t D – 2

0.5 × t

– 2

CCLK

– 0.5

CCLK

– 2.0

CCLK

– 0.8

CCLK

– 0.8 0.5 × t

CCLK

– 1 + H

CCLK

D + 0.5 × t

CCLK

+ 2.0

– 3.5

ns ns ns

ns ns ns ns ns ns ns

Figure 17. 8-Bit Memory Read Cycle

Rev. E | Page 27 of 48 | July 2008

Page 28

ADSP-21261/ADSP-21262/ADSP-21266

VALID ADDRESS

VALID DATA

ADAS

ADAH

AD15-0

ALEHZ

DRS tDRH

ALEW

ALE

ALERW

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Table 26. 16-Bit Memory Read Cycle

Parameter Min Max Unit

Timing Requirements

t t

DRS

DRH

Address/Data 15–0 Setup Before RD high Address/Data 15–0 Hold After RD high

3.3 0

ns ns

Switching Characteristics

ALEW

ALERW

ADAS

1 Address/Data 15–0 Hold After ALE Deaserted

ADAH

ALEHZ

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE Pulse Width ALE Deasserted to Read/Write Asserted Address/Data 15–0 Setup Before ALE Deasserted

ALE Deasserted to Address/Data 15–0 in High-Z RD Pulse Width

CCLK

2 × t 1 × t

2.5 × t

0.5 × t

0.5 × t D – 2

– 2

CCLK

– 0.5

CCLK

– 2.0

CCLK

– 0.8

CCLK

– 0.8 0.5 × t

CCLK

+ 2.0

ns ns ns ns ns ns ns

Figure 18. 16-Bit Memory Read Cycle

Rev. E | Page 28 of 48 | July 2008

Page 29

ADSP-21261/ADSP-21262/ADSP-21266

ALE

AD15-8

AD7-0

VALID ADDRESS VA LID ADDRESS

ADAS

ALEW

ADAH

ADWH

ADWL

ALEHZ

VALID DA T A

DWS tDWH

VALID ADDRESS

DAWH

ALERW

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Memory Write—Parallel Port

Use the specifications in Table 27, Table 28, Figure 19, and

Figure 20 for asynchronous interfacing to memories (and

memory-mapped peripherals) when the ADSP-2126x is accessing external memory space.

Table 27. 8-Bit Memory Write Cycle

Parameter Min Max Unit

Switching Characteristics

ALEW

ALERW

ADAS

ADAH

ADWL

ADWH

ALEHZ

DWS

DWH

DAWH

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE Pulse Width ALE Deasserted to Read/Write Asserted Address/Data 15–0 Setup Before ALE Deasserted Address/Data 15–0 Hold After ALE Deasserted WR Pulse Width Address/Data 15–8 to WR Low Address/Data 15–8 Hold After WR High ALE Deasserted to Address/Data 15–0 in High-Z Address/Data 7–0 Setup Before WR High Address/Data 7–0 Hold After WR High Address/Data to WR High

2 × t

– 2

CCLK

1 × t

– 0.5

CCLK

2.5 × t

0.5 × t D – 2

0.5 × t

0.5 × t D

0.5 × t

– 2.0

CCLK

– 0.8

CCLK

– 1.5

CCLK

– 1 + H

CCLK

– 0.8 0.5 × t

CCLK

– 1.5 + H

CCLK

+ 2.0

CCLK

ns ns ns ns ns ns ns ns ns ns ns

Figure 19. 8-Bit Memory Write Cycle

Rev. E | Page 29 of 48 | July 2008

Page 30

ADSP-21261/ADSP-21262/ADSP-21266

VALID ADDRESS

VALID DATA

ADAS

AD15-0

ALEW

ALE

ADAH

DWH

DWS

ALERW

ALEH

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Table 28. 16-Bit Memory Write Cycle

Parameter Min Max Unit

Switching Characteristics

ALEW

ALERW

ADAS

ADAH

ALEHZ

DWS

DWH

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE Pulse Width ALE Deasserted to Read/Write Asserted Address/Data 15–0 Setup Before ALE Deasserted Address/Data 15–0 Hold After ALE Deasserted WR Pulse Width ALE Deasserted to Address/Data 15–0 in High-Z Address/Data 15–0 Setup Before WR High Address/Data 15–0 Hold After WR High

CCLK

2 × t 1 × t

2.5 × t

0.5 × t D – 2

0.5 × t D

0.5 × t

– 2

CCLK

– 0.5

CCLK

– 2.0

CCLK

– 0.8

CCLK

– 0.8 0.5 × t

CCLK

– 1.5 + H

CCLK

+ 2.0

ns ns ns ns ns ns ns ns

Figure 20. 16-Bit Memory Write Cycle

Rev. E | Page 30 of 48 | July 2008

Page 31

ADSP-21261/ADSP-21262/ADSP-21266

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Serial Ports

To determine whether communication is possible between two devices at a given clock speed, the specifications in Table 29,

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 30, Table 31, Table 32, Figure 21, and Figure 22 must be

confirmed: 1) frame sync delay and frame sync setup and hold;

2) data delay and data setup and hold; and 3) SCLK width.

Table 29. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

HFSE

SDRE

HDRE

SCLKW

SCLK

FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)

FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)

Receive Data Setup Before Receive SCLK Receive Data Hold After SCLK SCLK Width 7 ns SCLK Period

2.5 ns

20 ns

Switching Characteristics

DFSE

HOFSE

FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode)

FS Hold After SCLK

7 ns

(Internally Generated FS in Either Transmit or Receive Mode)2 2 ns

DDTE

HDTE

Referenced to sample edge.

Referenced to drive edge.

Transmit Data Delay After Transmit SCLK Transmit Data Hold After Transmit SCLK

2 ns

7 ns

Table 30. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

t t

SFSI

HFSI

SDRI

HDRI

FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)

FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)

Receive Data Setup Before SCLK Receive Data Hold After SCLK

6 ns

1.5 ns 6 ns

1.5 ns

Switching Characteristics

DFSI

HOFSI

DFSI

HOFSI

DDTI

HDTI

SCLKIW

Referenced to the sample edge.

Referenced to drive edge.

FS Delay After SCLK (Internally Generated FS in Transmit Mode) FS Hold After SCLK (Internally Generated FS in Transmit Mode) FS Delay After SCLK (Internally Generated FS in Receive Mode) FS Hold After SCLK (Internally Generated FS in Receive Mode) Transmit Data Delay After SCLK Transmit Data Hold After SCLK Transmit or Receive SCLK Width 0.5t

–1.0 ns

3 ns

–1.0 ns

– 2 0.5t

SCLK

+ 2 ns

SCLK

Rev. E | Page 31 of 48 | July 2008

Page 32

ADSP-21261/ADSP-21262/ADSP-21266

EXTERNAL RECEIVE F S WITH MCE = 1, MFD = 0

DAI_P20-1

(SCLK)

DAI_P20-1

(FS

)

DAI_P20- 1

(DATA

CHANNEL A/B)

DRIVE SA

MPLE DRIVE

1ST B IT 2ND BIT

HFSE/I

SFSE/I

DDTE/I

DDTENFS

DDTLFS E

HDTE/I

LATE EXTERNAL TRANSMIT FS

DRIVE SAMPLE DRIVE

DAI_P201

(SCLK)

DAI_P20-1

(FS

)

DAI_P20-1

(DATA CHANNEL A/ B)

1ST BIT 2ND BIT

SFSE/I

DDTE/I

DDTENFS

DDTLFSE

HDTE/I

HFSE/I

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/ B) ARE ROUTED TO THE DAI_P[20: 1] PINS USING THE SRU. THE TIMING SPECIFICATI ONS PROVI DED HERE ARE VALID AT THE DAI _P[20:1 ] PI NS.

www.BDTIC.com/ADI

Table 31. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

DDTTE

DDTIN

Referenced to drive edge.

Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK Data Enable from Internal Transmit SCLK

Table 32. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

DDTENFS

The t

DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 0

Data Enable for MCE = 1, MFD = 0

and t

parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.

DDTENFS

–1

0.5

ns ns

This figure reflects changes made to support left-justified sample pair mode.

Figure 21. External Late Frame Sync

Rev. E | Page 32 of 48 | July 2008

Page 33

ADSP-21261/ADSP-21262/ADSP-21266

XTE

DRIVE EDGE SAMPLE EDGE

DRIVE ED GE SA MPLE EDGE

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL A/B)

SDRI

HDRI

SFSI

HFSI

DFSI

HOFSI

SCLKIW

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL A/B)

SDRE

HDRE

SFSE

HFSE

DFSE

SCLKW

HOFSE

NOTE: EITHER T HE RISING EDGE OR FALLING EDGE OF S CLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACT IVE SAMPLING EDGE.

DATA TR ANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE E DGE D RIVE EDGE SAMP LE E DGE

DAI_P20–1

DDTI

SFSI

HFSI

DFSI

HOFSI

SCLKIW

HDTI

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNE

L A/B)

(DATA CHANNEL A

/B)

DDTE

SFSE

HFSE

DFSE

HOFSE

SCLKW

HDTE

NOTE: EITHER T HE RISING EDGE O R FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

SCLK

DAI_P20–1

SCLK (EXT)

DDTTE

DDTEN

DAI_P20–1

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20–1 SCLK (INT)

DDTIN

DAI_P20–1

(DATA CHANNEL A/B)

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DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—

RNAL CLOCK

Figure 22. Serial Ports

Rev. E | Page 33 of 48 | July 2008

Page 34

ADSP-21261/ADSP-21262/ADSP-21266

SAMPLE EDGE

DAI_P20–1

(SCLK)

DAI_P20

–1

(FS)

SISD

SIHD

SISFS

SIHFS

IDPCLKW

DAI_P20–1

(SDATA)

www.BDTIC.com/ADI

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 33 and

Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 33. Input Data Port (IDP)

Parameter Min Max Unit

Timing Requirements

SISFS

SIHFS

SISD

SIHD

IDPCLKW

IDPCLK

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either

CLKIN or any of the DAI pins.

FS Setup Before SCLK Rising Edge FS Hold After SCLK Rising Edge SDATA Setup Before SCLK Rising Edge SDATA Hold After SCLK Rising Edge Clock Width Clock Period

2.5

2.5 7 20

ns ns ns ns ns ns

Figure 23. Input Data Port (IDP)

Rev. E | Page 34 of 48 | July 2008

Page 35

ADSP-21261/ADSP-21262/ADSP-21266

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

PDSD

PDHD

SPCLKEN

HPCLKEN

PDCLKW

DATA

DAI_P20–1

(PDAP_CLKEN)

PDSTRB

PDHLDD

DAI_P20–1

(PDAP_STROBE)

PDCLK

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Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in Table 34 and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual.

Note that the most significant 16 bits of external PDAP data can be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins.

Table 34. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPCLKEN

HPCLKEN

PDSD

PDHD

PDCLKW

PDCLK

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge PDAP_CLKEN Hold After PDAP_CLK Sample Edge PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge Clock Width Clock Period

2.5

2.5 7 20

ns ns ns ns ns ns

Switching Characteristics

PDHLDD

PDSTRB

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word PDAP Strobe Pulse Width

2 × t 1 × t

CCLK

– 1

ns ns

Figure 24. Parallel Data Acquisition Port (PDAP)

Rev. E | Page 35 of 48 | July 2008

Page 36

ADSP-21261/ADSP-21262/ADSP-21266

FLG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP

= 1)

(OUTPUT)

MOSI

CPHASE = 1

(OUTPUT)

MISO

(INPUT)

MOSI

CPHASE = 0

(OUTPUT)

MISO

(INPUT)

LSB

VALID

MSB

VALID

SPICHM

SSPIDM

HSPIDM

HDSPIDM

LSB MSB

HSPIDM

DDSPIDM

SPICLM

SPICLKM

HDSM

SPITDM

SDSCIM

SPICLM tSPICHM

HDSPIDM

LSB

VALID

LSB MSB

MSB

VALID

HSPIDM

DDSPIDM

SSPIDM

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SPI Interface Protocol—Master

Table 35. SPI Interface Protocol—Master

Parameter Min Max Unit

Timing Requirements

SSPIDM

HSPIDM

Switching Characteristics

SPICLKM

SPICHM

SPICLM

DDSPIDM

HDSPIDM

SDSCIM

HDSM

SPITDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) SPICLK Last Sampling Edge to Data Input Not Valid

Serial Clock Cycle Serial Clock High Period Serial Clock Low Period SPICLK Edge to Data Out Valid (Data Out Delay Time) SPICLK Edge to Data Out Not Valid (Data Out Hold Time) FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge Last SPICLK Edge to FLAG3–0 OUT High Sequential Transfer Delay

5 2

8 × t 4 × t 4 × t

10 4 × t 4 × t 4 × t

CCLK

– 2 – 2

– 2 – 1 – 1

ns ns

ns ns ns ns ns ns ns ns

Figure 25. SPI Interface Protocol—Master

Rev. E | Page 36 of 48 | July 2008

Page 37

ADSP-21261/ADSP-21262/ADSP-21266

SPIDS

(INPUT)

SPICLK

(CP

= 0)

(INPUT)

SPICLK

(CP

= 1)

(INPUT)

MISO

MOSI

NPUT)

(OUTPUT)

CPHASE = 1

MISO

MOSI

(INPUT)

(OUTPUT)

CPHASE = 0

HSPIDS

DDSPIDS

DSDHI

LSB MSB

MSB VALID

DSOE

DDSPIDS

HDSPIDS

SSPIDS

SDSCO

SPICHS

SPICLS

SPICLKS

HDS

SPICHS

SSPIDS

HSPIDS

DSDHI

LSB VALID

MSB

MSB VALID

DSOE

DDSPIDS

SSPIDS

LSB VALID

LSB

SDPPW

DSOV

HDSPIDS

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SPI Interface Protocol—Slave

Table 36. SPI Interface Protocol—Slave

Parameter Min Max Unit

Timing Requirements

SPICLKS

SPICHS

SPICLS

SDSCO

HDS

SSPIDS

HSPIDS

SDPPW

Switching Characteristics

DSOE

DSDHI

DDSPIDS

HDSPIDS

DSOV

Serial Clock Cycle 4 × t Serial Clock High Period 2 × t Serial Clock Low Period 2 × t SPIDS Assertion to First SPICLK Edge

CPHASE = 0 2 × t CPHASE = 1 2 × t

Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0 2 × t Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns SPICLK Last Sampling Edge to Data Input Not Valid 2 ns SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

SPIDS Assertion to Data Out Active 0 5 ns SPIDS Deassertion to Data High Impedance 0 5 ns SPICLK Edge to Data Out Valid (Data Out Delay Time) 7.5 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

CCLK

– 2 ns

CCLK

– 2 ns

CCLK

+ 1 ns

CCLK

+ 1 ns

CCLK

– 2 ns

CCLK

+ 2 ns

CCLK

Figure 26. SPI Interface Protocol—Slave

Rev. E | Page 37 of 48 | July 2008

Page 38

ADSP-21261/ADSP-21262/ADSP-21266

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

STAP

TCK

HTAP

DTDO

SSYS

HSYS

DSYS

www.BDTIC.com/ADI

JTAG Test Access Port and Emulation

Table 37. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

STAP

HTAP

SSYS

HSYS

TRSTW

TCK Period TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

20 5 6

ns ns ns ns ns

4 × t

Switching Characteristics

DTDO

DSYS

System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

TDO Delay from TCK Low System Outputs Delay After TCK Low

7 10

ns ns

Figure 27. JTAG Test Access Port and Emulation

Rev. E | Page 38 of 48 | July 2008

Page 39

3.47V, –45°C

3.3V, 25°C

–10

–20

–30

–40

3.3V, 25°C

3.11V, 125°C

3.47V, –45°C

0 0.5 1 1.5 2 2.5 3 3.5

SWEEP (V

DDEXT

) V OLTAGE (V )

50

OUTPUT

1.5V

30pF

INPUT

OUTPUT

1.5V 1.5V

ADSP-21261/ADSP-21262/ADSP-21266

100

150 20 0

LOAD CAPACITANCE (pF)

y = 0.0467x + 1.6323

RIS

FALL

= 0

.045x + 1.524

0 50 100 150 200 250

RISE

y = 0.049x + 1.5105

FALL

y = 0

.0482x + 1.4604

LOAD CAPACITANCE (pF)

250

www.BDTIC.com/ADI

OUTPUT DRIVE CURRENTS

Figure 28 shows typical I-V characteristics for the output driv-

ers of the ADSP-2126x. The curves represent the current drive capability of the output drivers as a function of output voltage.

) A m

( T N

E R R U C )

( E

C R U O S

Figure 28. Typical Drive

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 16 on Page 20 through Table 37 on Page 38. These include

output disable time, output enable time, and capacitive loading.

Timing is measured on signals when they cross the 1.5 V level as described in Figure 30. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29). Figure 32 shows graphically how output delays and holds vary with load capacitance (note that this graph or derating does not apply to output disable delays). The graphs of Figure 31, Figure 32, and Figure 33 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance.

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 31. Typical Output Rise Time

(20% to 80%, V

DDEXT

= Max)

Figure 29. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 30. Voltage Reference Levels for AC Measurements

Rev. E | Page 39 of 48 | July 2008

) s n

( S

E M

I T

L L A F

D N A

E S

I R

Figure 32. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Min)

Page 40

y = 0.0488x – 1.5923

–2

–4

LOAD CAPACITANCE (pF)

= T

CASE

+ (

× PD)

ADSP-21261/ADSP-21262/ADSP-21266

0 50 100 150 200

= + ( × )T

J TA θJA PD

www.BDTIC.com/ADI

) s n

( D

L O H

R O

Y A L E D

T U P T U O

Figure 33. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

ENVIRONMENTAL CONDITIONS

The ADSP-2126x processor is rated for performance under T environmental conditions specified in the Operating Condi-

tions on Page 16.

AMB

THERMAL CHARACTERISTICS

Table 38 and Table 39 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board.

To determine the junction temperature of the device while on the application PCB, use

Values of θ design considerations (θ used for a first order approximation of T

are provided for package comparison and PCB

indicates moving air). θJA can be

JMA

by the equation

where:

= ambient temperature °C

Values of θ design considerations when an external heat sink is required.

Table 38. Thermal Characteristics for 136-Ball BGA

are provided for package comparison and PCB

Parameter Condition Typical Unit

JMA

JMT

Table 39. Thermal Characteristics for 144-Lead LQFP

Airflow = 0 m/s 31.0 °C/W Airflow = 1 m/s 27.3 °C/W Airflow = 2 m/s 26.0 °C/W

6.99 °C/W Airflow = 0 m/s 0.16 °C/W Airflow = 1 m/s 0.30 °C/W Airflow = 2 m/s 0.35 °C/W

Parameter Condition Typical Unit

JMA

JMT

Airflow = 0 m/s 32.5 °C/W Airflow = 1 m/s 28.9 °C/W Airflow = 2 m/s 27.8 °C/W

7.8 °C/W Airflow = 0 m/s 0.5 °C/W Airflow = 1 m/s 0.8 °C/W Airflow = 2 m/s 1.0 °C/W

where:

= junction temperature (°C)

= case temperature (°C) measured at the top center of the

CASE

package

= junction-to-top (of package) characterization parameter

is the typical value from Table 38 and Table 39 (Ψ

indicates

JMT

moving air).

= power dissipation. See Estimating Power Dissipation for

ADSP-21262 SHARC DSPs (EE-216) for more information.

Rev. E | Page 40 of 48 | July 2008

Page 41

144-LEAD LQFP PIN CONFIGURATIONS

www.BDTIC.com/ADI

Table 40 shows the ADSP-2126x’s pin names and their default

function after reset (in parentheses).

ADSP-21261/ADSP-21262/ADSP-21266

Table 40. 144-Lead LQFP Pin Assignments

LQFP LQFP LQFP LQFP

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

DDINT

CLK_CFG0 2 GND 38 GND 74 V CLK_CFG1 3 RD 39 V BOOT_CFG0 4 ALE 40 GND 76 V

1 V

DDINT

37 V

DDEXT

DDINT

73 GND 109

DDINT

110

75 GND 111

DDINT

112 BOOT_CFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113 GND 6 AD14 42 DAI_P11 (SD3A) 78 V V

DDEXT

7 AD13 43 DAI_P12 (SD3B) 79 GND 115 GND 8 GND 44 DAI_P13 (SCLK23) 80 V V

DDINT

9 V

DDEXT

45 DAI_P14 (SFS23) 81 GND 117 GND 10 AD12 46 DAI_P15 (SD4A) 82 V V

DDINT

11 V

DDINT

47 V

DDINT

83 GND 119 GND 12 GND 48 GND 84 V V

DDINT

13 AD11 49 GND 85 RESET 121

DDINT

DDEXT

DDINT

114

116

118

120

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122 FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123 FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V

DDINT

124 AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK45) 89 SPICLK 125 GND 18 V V

DDINT

19 GND 55 GND 91 MOSI 127

DDINT

54 V

DDINT

90 MISO 126

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128 V

DDEXT

GND 22 GND 58 DAI_P20 (SFS45) 94 V V

DDINT

AD6 24 V

21 DAI_P3 (SCLK0) 57 V

23 V

DDEXT

DDINT

59 GND 95 A 60 V

DDEXT

DDINT

93 V

96 A

DDINT

DDEXT

VDD

VSS

129

130

131

132 AD5 25 GND 61 FLAG2 97 GND 133 AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 RESETOUT V

DDINT

27 DAI_P5 (SD1A) 63 V

DDINT

99 EMU 135

/CLKOUT 134

GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136 AD3 29 DAI_P7 (SCLK1) 65 V AD2 30 V V

DDEXT

31 GND 67 V

GND 32 V

DDINT

66 GND 102 TRST 138

68 GND 104 TMS 140

AD1 33 GND 69 V

DDINT

101 TDI 137

103 TCK 139

105 GND 141 AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142 WR 35 DAI_P9 (SD2A) 71 V V

DDINT

36 V

DDINT

72 V

DDINT

107 XTAL 143

108 V

DDEXT

144

Rev. E | Page 41 of 48 | July 2008

Page 42

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

136-BALL BGA PIN CONFIGURATIONS

Table 41 shows the ADSP-2126x’s pin names and their default

function after reset (in parentheses). Figure 34 on Page 44 shows the BGA package pin assignments.

Table 41. 136-Ball BGA Pin Assignments

BGA Pin BGA Pin BGA Pin BGA Pin

Pin Name No. Pin Name No. Pin Name No. Pin Name No.

CLK_CFG0 A01 CLK_CFG1 B01 BOOT_CFG1 C01 V XTAL A02 GND B02 BOOT_CFG0 C02 GND D02 TMS A03 V TCK A04 CLKIN B04 GND C12 GND D05 TDI A05 TRST RESETOUT/CLKOUT A06 A TDO A07 A EMU A08 V MOSI A09 SPICLK B09 GND D13 MISO A10 RESET SPIDS A11 V V

DDINT

GND A13 GND B13 GND A14 GND B14 V

DDINT

GND E02 FLAG0 F02 V GND E04 GND F04 V GND E05 GND F05 DAI_P19 (SCLK45) G14 DAI_P17 (SD5A) H14 GND E06 GND F06 GND E09 GND F09 GND E10 GND F10 GND E11 GND F11 GND E13 FLAG2 F13 FLAG3 E14 DAI_P20 (SFS45) F14

A12 GND B12

E01 FLAG1 F01 AD7 G01 AD6 H01

DDEXT

VSS

VDD

DDEXT

DDINT

B03 GND C03 GND D04

B05 GND C13 GND D06 B06 V B07 GND D10 B08 GND D11

B10 V B11

DDINT

DDEXT

C14 GND D09

DDINT

G02 V G13 DAI_P18 (SD5B) H13

DDEXT

D01

D14

H02

Rev. E | Page 42 of 48 | July 2008

Page 43

Table 41. 136-Ball BGA Pin Assignments (Continued)

www.BDTIC.com/ADI

ADSP-21261/ADSP-21262/ADSP-21266

BGA Pin

Pin Name

AD5 J01 AD4 J02 GND J04 GND J05 GND J06 GND J09 GND J10 GND J11 V

DDINT

DAI_P16 (SD4B) J14 AD15 N01 AD14 P01 ALE N02 AD13 P02 RD V

DDINT

DDEXT

AD8 N06 AD9 P06 V

DDINT

DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08 V

DDEXT

DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10 V

DDINT

GND N13 DAI_P9 (SD2A) P13 DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14

No. Pin Name

AD3 K01 V

DDINT

GND K04 GND K05 GND K06 GND K09 GND K10 GND K11

J13

N03 AD12 P03 N04 AD11 P04 N05 AD10 P05

N07 DAI_P1 (SD0A) P07

N09 DAI_P5 (SD1A) P09

N11 DAI_P7 (SCLK1) P11 N12 DAI_P8 (SFS1) P12

GND K13 DAI_P15 (SD4A) K14

BGA Pin No. Pin Name

K02

BGA Pin No. Pin Name

AD2 L01 AD1 L02 GND L04 GND L05 GND L06 GND L09 GND L10 GND L11 GND L13 DAI_P14 (SFS23) L14

BGA Pin No.

AD0 M01 WR M02 GND M03 GND M12 DAI_P12 (SD3B) M13 DAI_P13 (SCLK23) M14

Rev. E | Page 43 of 48 | July 2008

Page 44

ADSP-21261/ADSP-21262/ADSP-21266

14 13 12 11 10 9 8 7 6 5 4 3 2 1

KEY

VSS

DDINT

DDEXT

I/O SIGNALS

VDD

GND

USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHW

AYS TO YOU R PRINTED

CIRCUIT BOARD’S GROUND PLANE.

www.BDTIC.com/ADI

Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary)

Rev. E | Page 44 of 48 | July 2008

Page 45

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

0.20

0.09

0.08 COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING PLANE

7°

3.5° 0°

22.20

0.75

0.60

0.45

0.27

0.22

0.17

108

LEAD PITCH

144

109

TOP VIEW

(PINS DOWN)

0.50

BSC

1.60 MAX

VIEW A

PIN 1

22.00 SQ

21.80

20.20

20.00 SQ

19.80

COMPLIANT TO JEDEC STANDARDS MS-026-BFB

www.BDTIC.com/ADI

The ADSP-2126x is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 36 and Figure 35.

ADSP-21261/ADSP-21262/ADSP-21266

Figure 35. 144-Lead Low Profile Flat Package [LQFP]

(ST-144)

Dimensions shown in millimeters

Rev. E | Page 45 of 48 | July 2008

Page 46

ADSP-21261/ADSP-21262/ADSP-21266

0.25 MIN

DETAIL A

0.50

0.45

0.40

BALL DIAMETER

0.12 MAX COPLANARITY

0.80 BSC

10.40

BSC SQ

A B C D E F G H J K L M

8 7 6

9 5

1.31

1.21

1.10

A1 CORNER

INDEX AREA

1.70 MAX

TOP VIEW

BALL A1 INDICATOR

DETAIL A

BOTTOM VIEW

N P

12.10

12.00 SQ

11.90

SEATING PLANE

COMPLIANT WITH JEDEC STANDARDS MO-205-AE

WITH EXCEPTION TO BALL DIAMETER.

www.BDTIC.com/ADI

Figure 36. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-136)

Dimensions shown in millimeters

SURFACE-MOUNT DESIGN

Table 42 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern Standard.

Table 42. BGA_ED Data for Use with Surface-Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size

136-Ball CSP_BGA (BC-136) Solder Mask Defined (SMD) 0.4 mm 0.53 mm

Rev. E | Page 46 of 48 | July 2008

Page 47

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21266 DSP. For a complete list, visit our website at www.analog.com/SHARC.

Model

Temperature

Range

Instruction Rate

ADSP-21261SKBC-150 0°C to +70°C 150 MHz 1M bit 3M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136

ADSP-21261SKBCZ150 ADSP-21261SKSTZ150

0°C to +70°C 150 MHz 1M bit 3M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136

0°C to +70°C 150 MHz 1M bit 3M bit 1.2 V/3.3 V 144-Lead LQFP ST-144 ADSP-21262SBBC-150 0°C to +70°C 150 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136 ADSP-21262SBBCZ150

0°C to +70°C 150 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136 ADSP-21262SKBC-200 0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136 ADSP-21262SKBCZ200 ADSP-21262SKSTZ200 ADSP-21266SKSTZ-1B ADSP-21266SKSTZ-2B ADSP-21266SKBCZ-2B ADSP-21266SKSTZ-1C ADSP-21266SKSTZ-2C ADSP-21266SKBCZ-2C ADSP-21266SKSTZ-1D ADSP-21266SKSTZ-2D ADSP-21266SKBCZ-2D

Referenced temperature is ambient temperature.

Z = RoHS Compliant Part.

B at end of part number indicates Rev. 0.1 silicon. See Table 3 on Page 6 for multichannel surround sound decoder algorithms in on-chip B ROM.

C and D at end of part number indicate Rev. 0.2 silicon. See Table 3 on Page 6 for multichannel surround sound decoder algorithms in on-chip C and D ROM.

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 3

0°C to +70°C 150 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 3

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 3

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136

2, 4

0°C to +70°C 150 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 4

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 4

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136

2, 4

0°C to +70°C 150 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 4

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 144-Lead LQFP ST-144

2, 4

0°C to +70°C 200 MHz 2M bit 4M bit 1.2 V/3.3 V 136-Ball CSP_BGA BC-136

On-Chip SRAM ROM

Operating Voltage Internal/ External

Package Description

Package Option

Rev. E | Page 47 of 48 | July 2008

Page 48

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

D04932-0-7/08(E)

Rev. E | Page 48 of 48 | July 2008

Datasheet ADSP-21262 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

SUMMARY

KEY FEATURES

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

FAMILY CORE ARCHITECTURE

SIMD Computational Engine

Independent, Parallel Computation Units

Data Register File

Single-Cycle Fetch of Instruction and Four Operands

Instruction Cache

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

Flexible Instruction Set

MEMORY AND I/O INTERFACE FEATURES

Dual-Ported On-Chip Memory

DMA Controller

Digital Audio Interface (DAI)

Serial Ports

Serial Peripheral (Compatible) Interface

Parallel Port

Tim er s

ROM-Based Security

Program Booting

Phase-Locked Loop

Power Supplies

DEVELOPMENT TOOLS

TARGET BOARD JTAG EMULATOR CONNECTOR

EVALUATION KIT

ADDITIONAL INFORMATION

PIN FUNCTION DESCRIPTIONS

ADDRESS DATA PINS AS FLAGS

Boot Modes

ADDRESS DATA MODES

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

PRODUCT SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PACKAGE INFORMATION

ESD CAUTION

TIMING SPECIFICATIONS

MAXIMUM POWER DISSIPATION

ABSOLUTE MAXIMUM RATINGS

Power-Up Sequencing

Clock Input

Clock Signals

RESET

Interrupts

Core Timer

Timer PWM_OUT Cycle Timing

Timer WDTH_CAP Timing

DAI Pin-to-Pin Direct Routing

Precision Clock Generator (Direct Pin Routing)

Flags

Serial Ports

Input Data Port (IDP)

Parallel Data Acquisition Port (PDAP)

JTAG Test Access Port and Emulation

OUTPUT DRIVE CURRENTS

TEST CONDITIONS

CAPACITIVE LOADING

ENVIRONMENTAL CONDITIONS

THERMAL CHARACTERISTICS

144-LEAD LQFP PIN CONFIGURATIONS

136-BALL BGA PIN CONFIGURATIONS

OUTLINE DIMENSIONS

SURFACE-MOUNT DESIGN

ORDERING GUIDE