Datasheet ADSP-21261 Datasheet (Analog Devices)

Download

Page 1

SHARC® Processor

Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high precision signal processing applications

The ADSP-21261 is available with a 150 MHz (6.67 ns) core

instruction rate.

The ADSP-21261 SHARC Processor is code compatible with

all other SHARC Processors

Single-Instruction Multiple-Data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixedpoint/40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file

CORE PROCESSOR

INSTRUCTION

32 ⴛ 48 -BIT

PROGR AM

SEQUENCER

CA CH E

DAG1

8 ⴛ 4 ⴛ 32

DAG 2

8 ⴛ 4 ⴛ 32

TIMER

ADSP-21261

High bandwidth I/O— A parallel port, SPI port, four serial

ports, digital audio interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) which includes the parallel data

acquisition port (PDAP), and three programmable timers, all under software control through the signal routing unit (SRU)

On-chip memory—1M bit of on-chip SRAM and a dedicated

3M bit of on-chip mask-programmable ROM

Six independent synchronous serial ports provide a variety

of serial communication protocols including TDM and I modes

For complete ordering information, see Ordering Guide on

Page 44.

DUALP ORTED MEMORY

SRAM

0.5MBIT ROM

ADDR DATA

BLOCK 0

1. 5M B IT

DUA L PORTED MEM ORY

BLO CK 1

SRA M

0.5 M BIT R OM

1. 5M B IT

ADDR

DATA

PROC ESSIN G

EL EMENT

(PEX)

PM ADDRESS BUS

DM ADDRESS BUS

PROC ESSIN G

ELEMENT

(P EY)

JTAG TEST & EMULATION

PX REGI STER

SI GNAL

RO UTI NG

UNIT

DIGITAL AUDIO INTERFACE

Figure 1. FUNCTIONAL BLOCK DIAGRAM

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PM DATABUS

DMDATA BUS

DMA CONTROLLER

18 CHANNELS

SP I PORT ( 1)

SERIAL PORTS(4)

INPUT DATA PORTS (8) PAR ALLEL DATA

ACQUISIT ION PORT

PREC ISION CLO CK

GENERATORS (2)

TIMERS(3)

I/O PROCESSOR

IOD (32)

(MEMORY MAPPED)

IOA (18)

IOP

REGISTE RS

CO N TRO L, STATUS, &

DATA BUFFERS

GPIO FLAGS/

IRQ/TIMEX P

ADDRESS/

DATA BUS / GPIO

CONTROL/GPIO

PARALLEL

PORT

Page 2

ADSP-21261 Preliminary Technical Data

KEY FEATURES

At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261

operates at 900 MFLOPS peak performance 300 MMACS sustained performance at 150 MHz Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O 1M bit on-chip dual-ported SRAM for simultaneous access by

core processor and DMA 3M bit on-chip dual-ported mask-programmable ROM Dual data address generators (DAGs) with modulo and bit-

reverse addressing Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution— Each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of: a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained

2.4G byte/s bandwidth at 150 MHz core instruction rate. In

addition, 600M byte/sec is available via DMA Accelerated FFT butterfly computation through a multiply

with add and subtract instruction DMA controller supports: 18 zero-overhead DMA channels for transfers between

ADSP-21261 internal memory and serial ports (12), the

input data port (IDP) (4), SPI-compatible port (1), and the

parallel port (1) 32-bit background DMA transfers at core clock speed, in par-

allel with full-speed processor execution Asynchronous parallel/external port provides: Access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address

external address range with 8-bit data or 16-bit address

external address range with 16-bit data

50M Byte per sec transfer rate for 150 MHz core rate External memory access in a dedicated DMA channel 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface (DAI) includes four serial ports, two

precision clock generators, an input data port, three pro-

grammable timers and a signal routing unit

Serial ports provide: Four dual data line serial ports that operate at up to

37.5M bit/s for a 150 MHz core on each data line — each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair

Left-justified sample pair and I

direction for up to 24 simultaneous receive or transmit channels using two I

S support, programmable

S compatible stereo devices per serial

port

TDM support for telecommunications interfaces including

128 TDM channel support for telephony interfaces such as

H.100/H.110 Up to four TDM streams, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP

core configurable as either eight channels of I

S or serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port

Supports receive audio channel data in I2S, left-justified

sample pair, or right-justified mode

Signal routing unit provides configurable and flexible

connections between all DAI components, four serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px)

Serial peripheral interface (SPI)provides:

Master or slave serial boot through Full-duplex operation Master-slave mode multi-master support Open drain outputs Programmable baud rates, clock polarities, and phases

3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features:

JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit

access under program control to sensitive code PLL has a wide variety of software multiplier ratios JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation Dual voltage: 3.3 V I/O, 1.2 V core Available pakages: 136-ball BGA, 136-ball lead-free BGA,

144-lead lead-free LQFP Code-compatible with all previous SHARC processors Pin-compatible with ADSP-2126x and ADSP-2136x

processors

Rev. PrB | Page 2 of 44 | June 2004

Page 3

ADSP-21261Preliminary Technical Data

General Description ................................................. 4

ADSP-21261 Family Core Architecture . . .................... 4

SIMD Computational Engine ............................... 4

Independent, Parallel Computation Units ................ 5

Data Register File ............................................... 5

Single-Cycle Fetch of Instruction and Four

Operands ...................................................... 5

Instruction Cache .............................................. 5

Data Address Generators With Zero-Overhead

Hardware Circular Buffer Support ...................... 5

Flexible Instruction Set ....................................... 6

ADSP-21261 Memory and I/O Interface Features ......... 6

Dual-Ported On-Chip Memory ............................. 6

DMA Controller ................................................ 6

Digital Audio Interface (DAI) ............................... 6

Serial Ports ....................................................... 6

Serial Peripheral (Compatible) Interface .................. 8

Parallel Port ..................................................... 8

Timers ............................................................ 8

ROM Based Security ........................................... 8

Program Booting ............................................... 8

Phase-Locked Loop ............................................ 8

Power Supplies .................................................. 8

Target Board JTAG Emulator Connector .................... 9

Development Tools ............................................... 9

Designing an Emulator-Compatible

DSP Board(Target) ........................................... 10

Additional Information ......................................... 10

Pin Function Descriptions ........................................ 11

Address Data Pins as FLAGs .................................. 14

Boot Modes ........................................................ 14

Core Instruction Rate to CLKIN Ratio Modes ............. 14

Address Data Modes ............................................. 14

ADSP-21261 Specifications ....................................... 15

Recommended Operating Conditions ....................... 15

Electrical Characteristics ........................................ 15

ABSOLUTE MAXIMUM RATINGS ........................ 15

ESD SENSITIVITY .............................................. 16

Timing Specifications ........................................... 16

Power-Up Sequencing ....................................... 18

Clock Input ..................................................... 19

Clock Signals ................................................... 19

Reset ............................................................. 20

Interrupts ....................................................... 20

Core Timer ..................................................... 20

Timer PWM_OUT Cycle Timing ......................... 21

Timer WDTH_CAP Timing ............................... 21

DAI Pin to Pin Direct Routing ............................ 22

Precision Clock Generator (Direct Pin Routing) ...... 23

Flags ............................................................. 24

Memory Read–Parallel Port ................................ 25

Memory Write—Parallel Port ............................. 27

Serial Ports ..................................................... 29

Input Data Port (IDP) ....................................... 32

Parallel Data Acquisition Port (PDAP) .................. 33

SPI Interface—Master ....................................... 34

SPI Interface—Slave .......................................... 35

JTAG Test Access Port and Emulation .................. 36

Output Drive Currents ......................................... 37

Test Conditions .................................................. 37

Capacitive Loading .............................................. 37

Environmental Conditions .................................... 38

Thermal Characteristics ........................................ 38

136-ball BGA Pin Configurations ............................... 39

144-Lead LQFP Pin Configurations .. .......................... 42

Package Dimensions ............................................... 43

Ordering Guide ..................................................... 44

Rev. PrB | Page 3 of 44 | June 2004

Page 4

ADSP-21261 Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-21261 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21261 is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP-21261 is a 32-bit/40-bit floating-point processor optimized for high precision signal processing applications with its dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).

As shown in the functional block diagram on Page 1, the ADSP21261 uses two computational units to deliver a 5 to 10 times performance increase over the ADSP-2106x on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21261 DSP achieves an instruction cycle time of 6.67 ns at 150 MHz. With its SIMD computational hardware, the ADSP-21261 can perform 900 MFLOPS running at 150 MHz.

Table 1 shows performance benchmarks for the ADSP-21261.

Table 1. ADSP-21261 Benchmarks (at 150 MHz)

Benchmark Algorithm Speed

(at 150 MHz)

1024 Point Complex FFT (Radix 4, with reversal)

FIR Filter (per tap) IIR Filter (per biquad) Matrix Multiply (pipelined)

[3×3] × [3×1] [4×4] × [4×1]

Divide (y/×) 20 ns Inverse Square Root 30 ns

Assumes two files in multichannel SIMD mode

61.3 µs

3.3 ns

13.3 ns

30 ns

53.3 ns

The ADSP-21261 continues SHARC’s industry leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include 1M bit dual-ported SRAM memory, 3M bit dual-ported ROM, an I/O processor that supports 22 DMA channels, six serial ports, an SPI interface, external parallel bus, and Digital Audio Interface (DAI).

The block diagram of the ADSP-21261 on Page 1 illustrates the following architectural features:

• Two processing elements, each containing an ALU, Multiplier, Shifter, and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle

• Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulse Width Measurement, and External Event Counter Capabilities

• On-Chip dual-ported SRAM (1M bit)

• On-Chip dual-ported mask-programmable ROM (3M bit)

• JTAG test access port

The block diagram of the ADSP-21261 on Page 1, illustrates the following architectural features:

• 8- or 16-bit Parallel port that supports interfaces to off-chip memory peripherals

• DMA controller

• Six full duplex serial ports

• SPI compatible interface

• Digital Audio Interface that includes two precision clock generators (PCG), an input data port (IDP), four serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU)

Figure 2 on Page 5 shows one sample configuration of a SPORT

using the precision clock generator to interface with an I and an I

S DAC with a much lower jitter clock than the serial

S ADC

port would generate itself. Many other SRU configurations are possible.

ADSP-21261 FAMILY CORE ARCHITECTURE

The ADSP-21261 is code compatible at the assembly level with the ADSP-21266, ADSP-21160 and ADSP-21161, and with the first generation ADSP-2106x SHARC DSPs. The ADSP-21261 shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC family of DSPs, as detailed in the following sections.

SIMD Computational Engine

The ADSP-21261 contains two computational processing elements that operate as a Single-Instruction Multiple-Data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.

Rev. PrB | Page 4 of 44 | June 2004

Page 5

ADSP-21261Preliminary Technical Data

CLOCK

ADC

(OPTIONAL)

CLK

SDAT

DAC

(OPTIONAL)

CLK

SDAT

ADSP -2 1261

SPORT0

SPO RT1

SPORT2

SPORT3

SPORT4

SPORT5

CLKO UT

AD15-0

ALE

FLAG0

CONTROL

LATCH

ADDR

PARALLEL

DATA

ADDRESS

PORT RAM, ROM BOOT R OM

I/O DE VICE

CLK IN XTAL

CLK_CFG1-0

BOO T CFG 1- 0

FL AG 3 -1

DAI_P 1

DAI_P2 DAI_P3

SRU

DA I_P 1 8

DA I_P 1 9 DAI_P20

CLK FS

DAI

RESE T JTAG

PCG A

PCGB

SCL K0 SFS0

SD0A SD0B

Figure 2. ADSP-21261 System Sample Configuration

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2126x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21261 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see the Figure 1 on Page 1). With the ADSP-21261’s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

Instruction Cache

The ADSP-21261 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

The ADSP-21261’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and

Rev. PrB | Page 5 of 44 | June 2004

Page 6

ADSP-21261 Preliminary Technical Data

Fourier transforms. The two DAGs of the ADSP-21261 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21261 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching, and fetching up to four 32-bit values from memory—all in a single instruction.

ADSP-21261 MEMORY AND I/O INTERFACE FEATURES

The ADSP-21261 adds the following architectural features to the SIMD SHARC family core.

Dual-Ported On-Chip Memory

The ADSP-21261 contains one megabit of internal SRAM and three megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see Figure 3 on Page 7). Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor. The dual-ported memory, in combination with three separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle.

The ADSP-21261’s SRAM can be configured as a maximum of 32K words of 32-bit data, 64K words of 16-bit data, 21.3K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.

Using the DM bus and PM buses, with one dedicated to each memory block assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

DMA Controller

The ADSP-21261’s on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21261’s internal memory and its serial ports, the SPI-compatible (Serial Peripheral Interface) port, the IDP (Input Data Port), Parallel Data Acquisition Port

(PDAP) or the parallel port. 18 channels of DMA are available on the ADSP-21261—one for the SPI interface, twelve via the serial ports, four via the Input Data Port and one via the processor’s parallel port. Programs can be downloaded to the ADSP21261 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to connect various peripherals to any of the DSPs 20 DAI pins (DAI_P[20:1]).

Programs make these connections using the Signal Routing Unit (SRU, shown in Figure 1).

The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This provides easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths.

The DAI also includes four serial ports, two precision clock generators (PCGs), an input data port (IDP), six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the DSP core configurable as either eight channels

S or serial data, or as seven channels plus a single 20-bit

of I wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21261's serial ports.

For complete information on using the DAI, see the ADSP- 2126x SHARC DSP Peripherals Manual.

Serial Ports

The ADSP-21261 features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices AD183x family of audio codecs, DACs, or ADCs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has its own dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of serial data when all four SPORTS are enabled, or four full duplex TDM streams of 128 channels per frame.

The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of

37.5M bit/s for a 150 MHz core. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared.

Rev. PrB | Page 6 of 44 | June 2004

Page 7

INTERNAL MEMORY

SPACE

ADSP-21261Preliminary Technical Data

LONG WORD

ADDRESSI NG

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0 .5 M BI T) 0x0004 0000 - 0x0004 1FFF

RESERVED

0x0004 2000 - 0x0005 7FFF

BLOCK 0 ROM (1.5M BIT)

0x00 05 800 0 - 0x 0002 FFFF

RESERVED

0x00 05 300 0 - 0x 0005 FFFF

BLOCK 1 SRAM (0 .5 M BI T) 0x0006 0000 - 0x0006 1FFF

RESERVED

0x0006 2000 - 0x0007 7FFF

BLOCK 1 ROM (1. 5M BI T)

0x0007 8000 - 0x0007 DFFF

NORMAL WORD

ADDRESSI NG

IOPREGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM(0.5MBIT) 0x0008 0000 - 0x0008 3FFF

RESERVED

0x0008 4000 - 0x000A FFFF

BLOCK 0 ROM ( 1. 5M BIT )

0x000B 0000 - 0x000B BFFF

RESERVED

0x000B C000 - 0x000B FFFF

BLOCK 1 SRAM ( 0.5 M BI T)

0x000C 0000 - 0x000C 3FFF

RESERV ED

0x000C 4000 - 0x000E FFFF

BLOCK 1 ROM (1.5M BIT)

0x000F 0000 - 0x000F BFFF

SHORT WORD

ADDRESSI NG

IOP REGISTERS

0x00 00 000 0 - 0x 0003 FFFF

BLOCK 0 SRAM (0 .5 M BI T) 0x0010 0000 - 0x0010 7FFF

RESERV ED

0x0010 8000 - 0x0015 FFFF

BLOCK 0 ROM (1 .5M BI T)

0x0016 0000 - 0x0017 7FFF

RESERVED

0x0017 8FFF - 0x0017 FFFF

BLOCK 1 SRAM ( 0. 5M BI T) 0x0018 0000 - 0x0018 7FFF

RESERVE D

0x00 18 800 0 - 0x 001D FFFF

BLOCK 1 ROM (1 .5M BI T)

0x001E 0000 - 0x001F 7FFF

RESERVED

0x0007 E000 - 0x0007 FFFF

RESERVED

0x000F C000 - 0x000F FFFF

EXTERNAL MEMORY

SPACE

RESERVED

0x0020 0000 - 0x00FF FFFF

EXTERNAL D MA

ADDRESS SP ACE

0x0100 0000 - 0x02FF FFFF

RESERVED

0x0300 0000 - 0x3FFF FFFF

Figure 3. ADSP-21261 Memory Map

RESERV ED

0x000

EXTE RNAL ME MORY IS NO T DI RECTLY AC CESSI BLE BY THE CORE. DMA MUST BE USED TO READ OR WRIT TO THI S MEMORY US ING THE SPI OR PARALL EL PORT .

BLOCK 0 ROM HAS A 4 8-BI T ADDRESS RANGE (0xA0000–0xA7 FFF).

BLOCK 1 ROM HAS A 4 8-BI T ADDRESS RANGE (0xE0000–0xE7 FFF).

Rev. PrB | Page 7 of 44 | June 2004

Page 8

ADSP-21261 Preliminary Technical Data

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

S mode

•I

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode.

Each of the serial ports supports the left-justified sample pair

S protocols (I2S is an industry standard interface com-

and I monly used by audio codecs, ADCs and DACs), with two data pins, allowing four left-justified Sample Pair or I

S channels (using two stereo devices) per serial port, with a maximum of up to 24 audio channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I

S modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard synchronous serial link, enabling the ADSP-21261 SPI compatible port to communicate with other SPI compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI compatible devices, either acting as a master or slave device. The ADSP-21261 SPI compatible peripheral implementation also features programmable baud rates up to

37.5 MHz, clock phases, and polarities. The ADSP-21261 SPI compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.

Parallel Port

The Parallel Port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15-0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is one-third the core clock speed. As an example, for a clock rate of 150 MHz, this is equivalent to 50M byte/sec.

DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (Address Latch Enable) pins are the control pins for the parallel port.

Timers

The ADSP-21261 has a total of four timers: a core timer able to generate periodic software interrupts and three general-purpose timers that can that can generate periodic interrupts and be independently set to operate in one of three modes:

• Pulse Waveform Generation mode

• Pulse Width Count/Capture mode

• External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer Expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently.

ROM Based Security

The ADSP-21261 has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.

Program Booting

The internal memory of the ADSP-21261 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave or an internal boot. Booting is determined by the Boot Configuration (BOOTCFG1-0) pins. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.

Phase-Locked Loop

The ADSP-21261 uses an on-chip Phase-Locked Loop (PLL) to generate the internal clock for the core. On power up, the CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 32 and software configurable divisor values of 1, 2, 4, 8, and 16.

Power Supplies

The ADSP-21261 has separate power supply connections for the internal (V

), external (V

DDINT

), and analog (A

DDEXT

VDD/AVSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply.

Note that the analog supply (A

) powers the ADSP-21261’s

VDD

clock generator PLL. To produce a stable clock, programs should provide an external circuit to filter the power input to

Rev. PrB | Page 8 of 44 | June 2004

Page 9

ADSP-21261Preliminary Technical Data

the A

pin. Place the filter as close as possible to the pin. For

VDD

an example circuit, see Figure 4. To prevent noise coupling, use a wide trace for the analog ground (A

) signal and install a

VSS

decoupling capacitor as close as possible to the pin. Note that the A

VSS

and A

pins specified in Figure 4 are inputs to the

VDD

SHARC and not the analog ground plane on the board.

10⍀

DDINT

Figure 4. Analog Power (A

VDD

0.01␮F0.1␮F

VSS

) Filter Circuit

VDD

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21261 processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The ADSP-21261 is supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21261.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique

software and hardware development tools,

devel-

to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into

Rev. PrB | Page 9 of 44 | June 2004

Page 10

ADSP-21261 Preliminary Technical Data

the application. Publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21261 architecture and functionality. For detailed information on the ADSP-2126x Family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference.

Rev. PrB | Page 10 of 44 | June 2004

Page 11

PIN FUNCTION DESCRIPTIONS

ADSP-21261Preliminary Technical Data

ADSP-21261 pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST

). Tie or pull unused inputs to

or GND, except for the following:

DDEXT

• DAI_Px, SPICLK, MISO, MOSI, EMU

, TMS,TRST, TDI,

and AD15-0 (NOTE: These pins have pull-up resistors.)

The following symbols appear in the Type column of Table 2: A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, and T = Three-State.

Table 2. Pin Descriptions

Pin Type State During and

After Reset

AD15-0 I/O/T Three-state with

pull-up enabled

ALE O Output only, driven

FLAG3-0 I/O/A Three-state Flag Pi ns. Each flag pin is configured via control bits as either an input or output. As

O Output only, driven

high

low

Function

Parallel Port Address/Data. The ADSP-21261 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address

Data Modes on Page 14 for details of the AD pin operation:

For 8-bit mode: ALE is automatically a sserted whenever a change occurs in the upper 16 external address bits, A23-8; ALE is used in conjunction with an external latch to retain the values of the A23-8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A15-0; ALE is used in conjunction with an external latch to retain the values of the A15-0. To use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. When used as an input, the IDP Channel 0 can use these pins for parallel input data.

Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or 16-bit data from an external memory device. When AD15-0 are flags, this pin remains deasserted.

Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or 16-bit data to an external memory device. When AD15-0 are flags, this pin remains deasserted.

Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15-0 are flags, this pin remains deasserted.

a n i np u t, i t c an b e t e st ed a s a co n di t io n. A s a n ou tp u t, i t c an b e u s ed to s ig na l ex t er n al peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0

When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1 When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2 When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which indicates that the system timer has expired.

and the TIMEXP signals.

. .

Rev. PrB | Page 11 of 44 | June 2004

Page 12

ADSP-21261 Preliminary Technical Data

Table 2. Pin Descriptions (Continued)

Pin Type State During and

After Reset

DAI_P20-1 I/O/T Three-state with

programmable pullup

SPICLK I/O Three-state with

pull-up enabled

SPIDS

MOSI I/O (O/D) Three-state with

MISO I/O (O/D) Three-state with

BOOTCFG1-0 I Input only Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins

I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select

pull-up enabled

Function

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators, and timer to the DAI_P20-1 pins. These pins have internal 22.5 kΩ pullup resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register.

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.

the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the DSPs

signal can be driven by a slave device to signal to the DSP (as SPI master) that

SPIDS an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to V 21261 SPI interaction, any of the master ADSP-21261's flag pins can be used to drive the SPIDS signal on the ADSP-21261 SPI slave device.

SPI Master Out Slave In. If the ADSP-21261 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21261 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21261 SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-up resistor.

SPI Master In Slave Out. If the ADSP-21261 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21261 is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21261 SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI-slaves, the DSP's MISO pin may be disabled by setting (=1) Bit 5 (DMISO) of the SPICTL register.

must be valid before reset is asserted. See Table 4 on Page 14 for a description of the boot modes.

on the master device. For ADSP-21261 to ADSP-

DDEXT

Rev. PrB | Page 12 of 44 | June 2004

Page 13

Table 2. Pin Descriptions (Continued)

ADSP-21261Preliminary Technical Data

Pin Type State During and

Function

After Reset

CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21261 clock input.

It configures the ADSP-21261 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21261 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency.

XTAL O Output only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

CLKCFG1-0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 5

on Page 14 for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT

/CLKOUT O Output only Reset Out/Local Clock Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin (RSTOUT)

. The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out.

RESET I/A Input only Processor Reset. Resets the ADSP-21261 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.

TCK I Input only

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21261.

TMS I/S Three-state with

pull-up enabled

TDI I/S Three-state with

pull-up enabled TDO O Three-state TRST

I/A Three-state with

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21261. TRST has a

22.5 kΩ internal pull-up resistor.

EMU

O (O/D) Three-state with

pull-up enabled

Emulation Status. Must be connected to the ADSP-21261 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU

has a 22.5 kΩ

internal pullup resistor.

DDINT

P Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

(13 pins on the BGA package, 32 pins on the LQFP package).

DDEXT

P I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the

LQFP package).

VDD

P Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL

(clock generator). This pin has the same specifications as V

, except that added

DDINT

filtering circuitry is required. For more information, see Power Supplies on Page 8.

VSS

G Analog Power Supply Return.

GND G Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver with both output paths and pull-up disabled.

Three-state is a three-state driver, with pull-up disabled

Rev. PrB | Page 13 of 44 | June 2004

Page 14

ADSP-21261 Preliminary Technical Data

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAGS15-0) set (=1) bit 20 of the SYSCTL register and disable the parallel port.

Table 3. AD[15:0] to Flag Pin Mapping

AD Pin Flag Pin

AD0 FLAG8 AD1 FLAG9 AD2 FLAG10 AD3 FLAG11 AD4 FLAG12 AD5 FLAG13 AD6 FLAG14 AD7 FLAG15 AD8 FLAG0 AD9 FLAG1 AD10 FLAG2 AD11 FLAG3 AD12 FLAG4 AD13 FLAG5 AD14 FLAG6 AD15 FLAG7

deasserted. For 16-bit data transfers, ALE latches address bits A15-A0 when asserted, followed by data bits D15-D0 when deasserted.

Table 6. Address/ Data Mode Selection

EP Data Mode

8-bit Asserted A15-8 A23-16 8-bit Deasserted D7-0 A7-0 16-bit Asserted A7-0 A15-8 16-bit Deasserted D7-0 D15-8

ALE AD7-0

Function

AD15-8 Function

BOOT MODES

Table 4. Boot Mode Selection

BOOTCFG1-0 Booting Mode

00 SPI Slave Boot 01 SPI Master Boot 10 Parallel Port boot via EPROM 11 Internal Boot Mode (ROM code only)

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1-0 Core to CLKIN Ratio

00 3:1 01 16:1 10 8:1 11 Reserved

ADDRESS DATA MODES

The following table shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23-A8 when asserted, followed by address bits A7-A0 and data bits D7-D0 when

Rev. PrB | Page 14 of 44 | June 2004

Page 15

ADSP-21261 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ADSP-21261Preliminary Technical Data

Parameter

DDINT

VDD

DDEXT

High Level Input Voltage2, @ V

Low Level Input Voltage2 @ V

IH_CLKIN

IL_CLKIN

AMB

Specifications subject to change without notice.

Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

Applies to input pin CLKIN.

See Thermal Characteristics on Page 38 for information on thermal specifications.

See Engineer-to-Engineer Note (No. 216) for further information.

Internal (Core) Supply Voltage 1.14 1.26 V Analog (PLL) Supply Voltage 1.14 1.26 V External (I/O) Supply Voltage 3.13 3.47 V

High Level Input Voltage3, @ V

Low Level Input Voltage, @ V

Ambient Operating Temperature

Min Max Unit

= max

DDEXT

= min –0.5 +0.8 V

DDEXT

= max

DDEXT

= min –0.5 +1.19 V

DDEXT

4, 5

2.0 V

1.74 V

+ 0.5 V

DDEXT

+ 0.5 V

DDEXT

0+70 °C

ELECTRICAL CHARACTERISTICS

Parameter

ILPU

OZH

OZL

OZLPU

DD-INTYP

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See Output Drive Currents on Page 37 for typical drive current capabilities.

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: FLAG3-0.

Applies to three-statable pins with 22.5 kΩ pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI.

Applies to open-drain output pins: EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note (No. 216) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current

4, 5

Low Level Input Current Pull-Up Three-State Leakage Current 6, 7, Three-State Leakage Current

Three-State Leakage Current Pull-Up7@ V Supply Current (Internal) Supply Current (Analog) Input Capacitance

9, 10, 11

13, 14

Test Conditions Min Max Unit

@ V @ V @ V @ V

@ V @ V @ V

t A fIN = 1 MHz, T

= min, IOH = –1.0 mA

DDEXT

= min, IOL = 1.0 mA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 µA

DDEXT

= max, VIN = 0 V 200 µA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 µA

DDEXT

= max, VIN = 0 V 200 µA

DDEXT

= 6.67 ns, V

CCLK

= max 10 mA

VDD

= 1.2 V, T

DDINT

= 25°C, VIN = 1.2 V 4.7 pF

CASE

max 10 µA

DDEXT

max 10 µA

DDEXT

= +25°C375mA

AMB

2.4 V

0.4 V

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage (V Analog (PLL) Supply Voltage (A External (I/O) Supply Voltage (V Input Voltage –0.5 V to V

)1 –0.3 V to +1.4 V

DDINT

)1 –0.3 V to +1.4 V

VDD

DDEXT

)

–0.3 V to +3.8 V

Rev. PrB | Page 15 of 44 | June 2004

DDEXT

+ 0.5 V

Page 16

ADSP-21261 Preliminary Technical Data

Output Voltage Swing –0.5 V to V Load Capacitance

Storage Temperature Range

–65°C to +150°C

200 pF

DDEXT

+ 0.5 V

Junction Temperature under Bias 125°C

Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings

only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21261 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS

The ADSP-21261’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1-0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports).

The ADSP-21261’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control (Table 7).

where: SR = serial port-to-core clock ratio (wide range, determined by

SPORT CLKDIV) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register) DAI_Px = Serial Port Clock SPICLK = SPI Clock

Figure 5 shows Core to CLKIN ratios of 3:1, 8:1, and 16:1 with

external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP- 2126x SHARC DSP Core Manual.

CLKIN

XTAL

OSC

PLLICLK

PLL

3:1, 8:1,

16:1

CLKOUT

CCLK (CORE CLOCK)

Table 7. ADSP-21261 CLKOUT and CCLK Clock Generation Operation

Timing

Description Calculation

Requirements

CLKIN Input Clock 1/t CCLK Core Clock 1/t

Timing

Description

CCLK

Requirements

CCLK

SCLK

SPICLK

CLKIN Clock Period (Processor) Core Clock Period Serial Port Clock Period = (t SPI Clock Period = (t

CCLK

) × SPIR

) × SR

Rev. PrB | Page 16 of 44 | June 2004

CLK-CFG [1:0]

Figure 5. Core Clock and System Clock Relationship to CLKIN

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times.

See Figure 30 on Page 37 under Test Conditions for voltage reference levels.

Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given

Page 17

circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

Note the following definitions of various clock periods that are a function of CLKIN and the appropriate ratio control.

ADSP-21261Preliminary Technical Data

Rev. PrB | Page 17 of 44 | June 2004

Page 18

ADSP-21261 Preliminary Technical Data

Power-Up Sequencing

The timing requirements for DSP startup are given in Table 8.

Table 8. Power-Up Sequencing Timing Requirements (DSP Startup)

Name Parameter Min Max Unit

Timing Requirements

RSTVDD

IVDDEVDD

CLKVDD

CLKRST

PLLRST

WRST

Switching Characteristic

4, 5

CORERST

Valid V

DDINT/VDDEXT

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

cycles maximum.

RESET low before V

on before V

DDINT

CLKIN valid after V

DDINT/VDDEXT

DDEXT

DDINT/VDDEXT

on 0 ns

-50 200 ms

valid 0 200 ms

CLKIN valid before RESET deasserted 10 µs

PLL control setup before RESET deasserted 20 µs

Subsequent RESET low pulse width 4t

DSP core reset deasserted after RESET deasserted 4096t

assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

specification in Table 10. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

SRST

RESET

DDINT

DDEXT

CLKIN

CLK_CFG1-0

RSTOUT*

RSTVDD

*MULTIPLEXED WITH CLKOUT

IVDDEVDD

CLKVDD

CLKRST

PLLRS T

Figure 6. Power-Up Sequencing

CORERST

Rev. PrB | Page 18 of 44 | June 2004

Page 19

Clock Input

Table 9. Clock Input

Parameter Min Max Unit

Timing Requirements

CKL

CKH

CKRF

CCLK

Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.

Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CLKIN

CLKIN Period 20 160 CLKIN Width Low 8.5 80 CLKIN Width High 8.5 80 CLKIN Rise/Fall (0.4 V – 2.0 V) 3 ns

CKH

CKL

6.67 10 ns

CCLK Period

Figure 7. Clock Input

CCLK

ns ns ns

ADSP-21261Preliminary Technical Data

Clock Signals

The ADSP-21261 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21261 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a

9.375 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN).

CLKIN XTAL

C1 C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 8. 150 MHz Operation with a 9.375 MHz Fundamental Mode

1M⍀

Crystal

Rev. PrB | Page 19 of 44 | June 2004

Page 20

ADSP-21261 Preliminary Technical Data

Reset

Table 10. Reset

Parameter Min Max Unit

Timing Requirements

WRST

SRST

Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

RESET Pulse Width Low RESET Setup Before CLKIN Low 8 ns

CLKIN

RESET

Interrupts

The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0 IRQ1

, and IRQ2 interrupts. Also applies to DAI_P[20:1] pins

when configured as interrupts.

WRST

Figure 9. Reset

SRST

Table 11. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

DAI_P20-1

(FLAG2-0)

(IRQ2-0)

IPW

Figure 10. Interrupts

+ 2 ns

CCLK

Core Timer

The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER).

Table 12. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

CTIMER Pulse Width 4 × t

FLAG3

(CTIMER)

– 1 ns

CCLK

WCTIM

Figure 11. Core Timer

Rev. PrB | Page 20 of 44 | June 2004

Page 21

ADSP-21261Preliminary Technical Data

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer[2:0] in PWM_OUT (pulse width modulation) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins.

Table 13. Timer[2:0] PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

DAI_P[20:1] (TIMER[2:0])

Timer WDTH_CAP Timing

The following timing specification applies to Timer[2:0] in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins.

Timer[2:0] Pulse Width Output 2 t

Figure 12. Timer[2:0] PWM_OUT Timing

– 1 2(231 – 1) t

CCLK

PWMO

CCLK

Table 14. Timer[2:0] Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

DAI_P[20:1] (TIMER[2:0])

Timer[2:0] Pulse Width 2 t

Figure 13. Timer[2:0] Width Capture Timing

CCLK

2(231 – 1) t

PWI

CCLK

Rev. PrB | Page 21 of 44 | June 2004

Page 22

ADSP-21261 Preliminary Technical Data

DAI Pin to Pin Direct Routing

For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O).

Table 15. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

DAI _Pn

DAI_Pm

DPIO

Figure 14. DAI Pin to Pin Direct Routing

Rev. PrB | Page 22 of 44 | June 2004

Page 23

ADSP-21261Preliminary Technical Data

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that the Precision Clock Generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs

inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is not timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P07 – DAI_P20).

directly to the DAI pins. For the other cases, where the PCG’s

Table 16. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirement

PCGIW

STRIG

HTRIG

Input Clock Period 20 PCG Trigger Setup Before Falling Edge of PCG Input Clock 2 ns PCG Trigger Hold After Falling Edge of PCG Input Clock 2 ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock 2.5 10 ns

DTRIG

PCGOW

PCG Output Clock and Frame Sync Delay After PCG Trigger 2.5 + 2.5 × t Output Clock Period 40

STRI G

PCGOW

10 + 2.5 × t

PCGOW

DAI_Pn

PCG_TRIGx_I

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

HTRIG

DTRIG

DPCGIO

PCGIW

Figure 15. Precision Clock Generator (Direct Pin Routing)

PCGOW

Rev. PrB | Page 23 of 44 | June 2004

Page 24

ADSP-21261 Preliminary Technical Data

Flags

The timing specifications provided below apply to the FLAG[3:0] and DAI_P[20:1] pins, the parallel port, and the serial peripheral interface (SPI). See Table 2 on Page 11 for more information on flag use.

Table 17. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

Switching Characteristic

FOPW

FLAG[3:0] IN Pulse Width 2 × t

FLAG[3:0] OUT Pulse Width 2 × t

DAI_P[20: 1]

(FLAG3-0IN)

(AD[15:0])

FIPW

+ 3 ns

CCLK

– 1 ns

CCLK

DAI_ P[20: 1]

(FLAG3- 0

(AD[15:0])

OUT

)

FOPW

Figure 16. Flags

Rev. PrB | Page 24 of 44 | June 2004

Page 25

ADSP-21261Preliminary Technical Data

Memory Read–Parallel Port

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is accessing external memory space.

Table 18. 8-Bit Memory Read Cycle

Parameter Min Max Unit

Timing Requirements

DRS

DRH

DAD

Switching Characteristics

ALEW

ALERW

ADAS

ADAH

ALE Deasserted1 to Address/Data[7:0] In High Z 0.5 × t

ALEHZ

ADRH

D = (Data Cycle Duration) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

Address/Data [7:0] Setup Before RD High 3.3 ns Address/Data [7:0] Hold After RD High 0 ns Address [15:8] to Data Valid D + 0.5 × t

ALE Pulse Width 2 × t ALE Deasserted to Read/Write Asserted 1 × t Address/Data [15:0] Setup Before ALE Deasserted Address/Data [15:0] Hold After ALE Deasserted

– 2 ns

CCLK

– 0.5 ns

CCLK

2.5 × t

0.5 × t

– 2.0 ns

CCLK

– 0.8 ns

CCLK

– 0.8 0.5 × t

CCLK

– 3.5 ns

CCLK

+ 2.0 ns

CCLK

RD Pulse Width D – 2 ns Address/Data [15:8] Hold After RD High 0.5 × t

CCLK

– 1 + H ns

CCLK

ALE

AD[15: 8]

AD[7:0]

ALEW

ALERW

ALEHZ

ADAS

VALID ADDRESS VALID ADDRESS

VALID ADDRESS

ADAH

DAD

DRS

VALID DATA

Figure 17. Read Cycle for 8-bit Memory Timing

DRH

ADRH

Rev. PrB | Page 25 of 44 | June 2004

Page 26

ADSP-21261 Preliminary Technical Data

Table 19. 16-bit Memory Read Cycle

Parameter Min Max Unit

Timing Requirements

DRS

DRH

Switching Characteristics ns t

ALEW

ALERW

ADAS

ADAH

ALEHZ

D = (Data Cycle Duration) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

Address/Data [15:0] Setup Before RD High 3.3 ns Address/Data [15:0] Hold After RD High 0 ns

ALE Pulse Width 2 × t ALE Deasserted to Read/Write Asserted 1 × t Address/Data [15:0] Setup Before ALE Deasserted Address/Data [15:0] Hold After ALE Deasserted

ALE Deasserted1 to Address/Data[15:0] In High Z 0.5 × t

– 2 ns

CCLK

– 0.5 ns

CCLK

2.5 × t

0.5 × t

– 2.0 ns

CCLK

– 0.8 ns

CCLK

– 0.8 0.5t

CCLK

+ 2.0 ns

CCLK

RD Pulse Width D – 2 ns

CCLK

ALE

AD[15:0]

ALEW

ALERW

ADAS

VALID ADDRESS

ADAH

ALEHZ

Figure 18. Read Cycle for 16-bit Memory Timing

DRStDRH

VALID DATA

Rev. PrB | Page 26 of 44 | June 2004

Page 27

ADSP-21261Preliminary Technical Data

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is accessing external memory space.

Table 20. 8-bit Memory Write Cycle

Parameter Min Max Unit

Switching Characteristics

ALEW

ALERW

ADAS

ADAH

ADWL

ADWH

ALEHZ

DWS

Address/Data [7:0] Hold After WR High 0.5 × t

DWH

DAWH

D = (Data Cycle Duration) × t H = t

(if a hold cycle is specified, else H = 0)

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE Pulse Width 2 × t ALE Deasserted to Read/Write Asserted 1 × t Address/Data [15:0] Setup Before ALE Deasserted Address/Data [15:0] Hold After ALE Deasserted

– 2 ns

CCLK

– 0.5 ns

CCLK

2.5 × t

0.5 × t

– 2.0 ns

CCLK

– 0.8 ns

CCLK

WR Pulse Width D – 2 ns Address/Data [15:8] to WR Low 0.5 × t Address/Data [15:8] Hold After WR High 0.5 × t ALE Deasserted1 to Address/Data[15:0] In High Z 0.5 × t

– 1.5 ns

CCLK

– 1 + H ns

CCLK

– 0.8 0.5t

CCLK

+ 2.0 ns

CCLK

Address/Data [7:0] Setup Before WR High D ns

– 1.5 + H ns

CCLK

Address/Data to WR High D ns

CCLK

ALE

AD[15:8]

AD[7:0]

ALERW

ALEW

ADAS

VALID ADDRESS VALID ADDRESS

VALID ADDRE SS

ADAH

ALEHZ

ADWL

DAWH

DWStDWH

VALID DATA

ADWH

Figure 19. Write Cycle for 8-bit Memory Timing

Rev. PrB | Page 27 of 44 | June 2004

Page 28

ADSP-21261 Preliminary Technical Data

Table 21. 16-bit Memory Write Cycle

Parameter Min Max Unit

Switching Characteristics

ALEW

ALERW

ADAS

ADAH

ALEHZ

DWS

DWH

D = (Data Cycle Duration) × t

(if a hold cycle is specified, else H = 0)

H = t

CCLK

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE Pulse Width 2 × t ALE Deasserted to Read/Write Asserted 1 × t Address/Data [15:0] Setup Before ALE Deasserted Address/Data [15:0] Hold After ALE Deasserted

– 2 ns

CCLK

– 0.5 ns

CCLK

2.5 × t

0.5 × t

– 2.0 ns

CCLK

– 0.8 ns

CCLK

WR Pulse Width D – 2 ns ALE Deasserted1 to Address/Data[15:0] In High Z 0.5 × t

–0.8 0.5t

CCLK

+ 2.0 ns

CCLK

Address/Data [15:0] Setup Before WR High D ns Address/Data [15:0] Hold After WR High 0.5 × t

CCLK

– 1.5 + H ns

CCLK

ALE

AD[15:0]

ALEW

ALERW

ALEHZ

ADAS

VALID ADDRESS

ADAH

DWS

VALID DATA

Figure 20. Write Cycle for 16-bit Memory Timing

DWH

Rev. PrB | Page 28 of 44 | June 2004

Page 29

ADSP-21261Preliminary Technical Data

Serial Ports

To determine whether communication is possible between two devices at clock speed n, the following specifications must be

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins.

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 22. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

HFSE

SDRE

HDRE

SCLKW

SCLK

FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)

FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)

Receive Data Setup Before Receive SCLK Receive Data Hold After SCLK

2.5 ns

2.5 ns SCLK Width 7 ns SCLK Period 20 ns

Switching Characteristics

DFSE

HOFSE

FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode)

FS Hold After SCLK

7ns

(Internally Generated FS in Either Transmit or Receive Mode)2 2ns

DDTE

HDTE

Referenced to sample edge.

Referenced to drive edge.

Transmit Data Delay After Transmit SCLK Transmit Data Hold After Transmit SCLK

2ns

7ns

Table 23. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

t t

SFSI

HFSI

SDRI

HDRI

FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)

FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive

Mode) Receive Data Setup Before SCLK Receive Data Hold After SCLK

6ns

1.5 ns

6ns

1.5 ns

Switching Characteristics

DFSI

HOFSI

DFSI

HOFSI

DDTI

HDTI

SCLKIW

Referenced to the sample edge.

Referenced to drive edge.

FS Delay After SCLK (Internally Generated FS in Transmit Mode) FS Hold After SCLK (Internally Generated FS in Transmit Mode) FS Delay After SCLK (Internally Generated FS in Receive or Mode) FS Hold After SCLK (Internally Generated FS in Receive Mode) Transmit Data Delay After SCLK Transmit Data Hold After SCLK Transmit or Receive SCLK Width 0.5t

–1.0 ns

3ns

–1.0 ns

– 2 0.5t

SCLK

+ 2 ns

SCLK

Rev. PrB | Page 29 of 44 | June 2004

Page 30

ADSP-21261 Preliminary Technical Data

Table 24. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

DDTTE

DDTIN

Referenced to drive edge.

Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK Data Enable from Internal Transmit SCLK

Table 25. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

DDTENFS

The t

DDTLFSE

and t

Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 0

Data Enable for MCE = 1, MFD = 0

parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.

DDTENFS

EXTERNAL RECEI VE F S WI TH MCE = 1, MFD = 0

2ns

7ns

–1 ns

7ns

0.5 ns

DAI_ P[2 0:1]

(SCL K)

DAI_P[20: 1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DAI_P[20: 1]

(SCLK)

DAI_P[20: 1]

(FS)

DAI_P[20: 1]

(DXA/DXB)

NOTE SERI AL PORT SI GNALS (SCLK, FS, DXA, / DXB) ARE ROUTE D TO THE DAI_P[ 20: 1] PI NS US ING THE S RU. THE TIMI NG SP ECIF ICATI ONS PROVIDED HERE AR E VAL ID AT TH E DAI _P[ 20 :1] PI NS.

DRIV E SAMPLE DRIV E

SFSE/I

DDTENFS

1ST BIT 2ND BIT

DDTLFSE

LATE EXTERNAL TRANSMI T F S

DRIV E SAMPLE DRIV E

SFSE/I

DDTENFS

1ST BIT 2NDBIT

DDTLFSE

HDTE/I

HFSE/I

DDTE/I

Figure 21. External Late Frame Sync

This figure reflects changes made to support left-justified sample pair mode.

Rev. PrB | Page 30 of 44 | June 2004

Page 31

DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE— EXTERNAL CLOCK

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DAI_P[20:1] (DXA/DXB)

DRIVE EDGE SAMPLE EDGE

HOFSI

DFSI

SCLKIW

SFSI

SDRI

HFSI

HDRI

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DRIVE EDGE SAMPLE EDGE

HOFSE

DFSE

SCLKW

SFSE

SDRE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

ADSP-21261Preliminary Technical Data

HFSE

HDRE

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

SCLKIW

HOFSI

DFSI

HDTI

DDTI

SFSI

DAI_P[20:1]

(SCLK)

HFSI

DAI_P[20:1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

SCLKW

HDTE

HOFSE

DFSE

DDTE

SFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

SCLK (EXT)

DAI_P[20:1]

DXA/DXB

DDTEN

SCLKDAI_P[20:1]

DDTTE

DRIVE EDGE

DAI_P[20:1]

SCLK (INT)

DDTIN

HFSE

DAI_P[20:1]

DXA/DXB

Figure 22. Serial Ports

Rev. PrB | Page 31 of 44 | June 2004

Page 32

ADSP-21261 Preliminary Technical Data

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 26. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins.

Table 26. Input Data Port

Parameter Min Max Unit

Timing Requirements

SISFS

SIHFS

SISD

SIHD

IDPCLKW

IDPCLK

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the Precision Clock Generators (PCG) or SPORTs. PCG's input can be either

CLKIN or any of the DAI pins.

FS Setup Before SCLK Rising Edge FS Hold After SCLK Rising Edge SData Setup Before SCLK Rising Edge SData Hold After SCLK Rising Edge Clock Width 7 ns Clock Period 20 ns

DAI_P[20:1]

(SCLK)

IDPCLKW

2.5 ns

SAMPLE EDGE

DAI_P[20:1]

(FS)

DAI_P[20:1]

(SDATA)

SISFS

SISD

Figure 23. IDP Master Timing

SIHFS

SIHD

Rev. PrB | Page 32 of 44 | June 2004

Page 33

ADSP-21261Preliminary Technical Data

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 27. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Note that the

most significant 16 bits of external PDAP data can be provided through either the parallel port AD[15:0] or the DAI_P[20:5] pins. The remaining 4 bits can only be sourced through DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins or at the AD[15:0] pins.

Table 27. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPCLKEN

HPCLKEN

PDSD

PDHD

PDCLKW

PDCLK

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge PDAP_CLKEN Hold After PDAP_CLK Sample Edge PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge Clock Width 7 ns Clock Period 20 ns

2.5 ns

Switching Characteristics

PDHLDD

PDSTRB

Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Delay of PDAP strobe after last PDAP_CLK capture edge for a word 2 × t PDAP Strobe Pulse Width 1 × t

CCLK

– 1 ns

CCLK

DAI_P[20:1]

(PDAP_CLK)

DAI_P[20:1]

(PDAP_CLKEN)

DATA

DAI_P[20:1]

(PDAP_STROBE)

PDCLKW

SPCLKEN

PDSD

Figure 24. PDAP Timing

SAMPLE EDGE

PDHLDD

HPCLKEN

PDHD

PDSTR B

Rev. PrB | Page 33 of 44 | June 2004

Page 34

ADSP-21261 Preliminary Technical Data

SPI Interface—Master

Table 28. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter Min Max Unit

Switching Characteristics

SPICLKM

SPICHM

SPICLM

DDSPIDM

HDSPIDM

SDSCIM

HDSM

SPITDM

Timing Requirements

SSPIDM

HSPIDM

FLAG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

MOSI

(OUTPUT)

CPHASE =1

MISO

(INPUT)

Serial Clock Cycle 8 × t Serial Clock High Period 4 × t Serial Clock Low Period 4 × t

CCLK

– 2 ns

CCLK

– 2 ns

CCLK

SPICLK Edge to Data Out Valid (Data Out Delay Time) 3 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 10 ns FLAG3-0 OUT (SPI device select) Low to First SPICLK Edge 4 × t Last SPICLK edge to FLAG3-0 OUT high 4 × t Sequential Transfer Delay 4 × t

– 2 ns

CCLK

– 1 ns

CCLK

– 1 ns

CCLK

Data Input Valid to SPICLK Edge (Data Input Setup Time) 5 ns SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDSCIM

SPICHMtSPICLM

SPICLM

MSB

VALID

SPICHM

DDSPIDM

SSPIDM

HSPIDM

HDSPIDM

SSPIDM

SPICLKM

LSB

VALID

HDSM

SPITDM

LSBMSB

HSPIDM

(OUTPUT)

CPHASE =0

MOSI

MISO

(INPUT)

SSPIDM

MSB

VALID

HSPIDM

DDSPIDM

HDSPIDM

LSB

VALID

LSBMSB

Figure 25. SPI Master Timing

Rev. PrB | Page 34 of 44 | June 2004

Page 35

ADSP-21261Preliminary Technical Data

SPI Interface—Slave

Table 29. SPI Interface Protocol —Slave Switching and Timing Specifications

Parameter Min Max Unit

Switching Characteristics

DSOE

DSDHI

DDSPIDS

HDSPIDS

DSOV

Timing Requirements

SPICLKS

SPICHS

SPICLS

SDSCO

HDS

SSPIDS

HSPIDS

SDPPW

SPIDS Assertion to Data Out Active 0 5 ns SPIDS Deassertion to Data High Impedance 0 5 ns SPICLK Edge to Data Out Valid (Data Out Delay Time) 7.5 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

Serial Clock Cycle 4 × t Serial Clock High Period 2 × t Serial Clock Low Period 2 × t

– 2 ns

CCLK

+ 2 ns

CCLK

– 2 ns

CCLK

– 2 ns

CCLK

SPIDS assertion to first SPICLK edge CPHASE = 0 CPHASE = 1

2 × t 2 × t

Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0 2 × t

CCLK

+ 1 + 1

ns ns

ns Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns SPICLK Last Sampling Edge to Data Input Not Valid 2 ns SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

CCLK

(INPUT)

SPICLK (CP = 0) (INPUT)

SPICLK (CP = 1) (INPUT)

MISO

(OUTPUT)

CPHASE = 1

(INPUT)

MISO

(OUTPUT)

CPHASE = 0

(INPUT)

SPIDS

MOSI

SDSCO

DSOE

DSOV

DSOE

SPICHS

SSPIDS

SPICLS

DDSPIDS

MSB

MSB VALID

DDSPIDS

SPICLS

SPICHS

SSPIDS

DDSPIDS

LSB VALID

SPICLKS

SSPIDS

LSB VALID

HDSPIDS

LSB

HSPIDS

HDS

LSBMSB

HSPIDS

SDPPW

DSDHI

HDSPIDS

DSDHI

Figure 26. SPI Slave Timing

Rev. PrB | Page 35 of 44 | June 2004

Page 36

ADSP-21261 Preliminary Technical Data

JTAG Test Access Port and Emulation

Table 30. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

STAP

HTAP

SSYS

HSYS

TRSTW

Switching Characteristics

DTDO

DSYS

System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE.

TCK Period 20 ns TDI, TMS Setup Before TCK High 5 ns TDI, TMS Hold After TCK High 6 ns System Inputs Setup Before TCK High

7ns System Inputs Hold After TCK High1 8ns TRST Pulse Width 4t

TDO Delay from TCK Low 7 ns

TCK

10 ns

System Outputs Delay After TCK Low

TCK

TMS TDI

TDO

SYSTEM INPUTS

SYSTEM OUTPUTS

DTDO

SSYS

DSYS

STAP

HTAP

HSYS

Figure 27. IEEE 11499.1 JTAG Test Access Port

Rev. PrB | Page 36 of 44 | June 2004

Page 37

ADSP-21261Preliminary Technical Data

OUTPUT DRIVE CURRENTS

Figure 28 shows typical I-V characteristics for the output driv-

ers of the ADSP-21261. The curves represent the current drive capability of the output drivers as a function of output voltage.

3.11V, 70° C

)VOLTAGE(V)

DDEXT

3.3V, 25° C

3.47V, 0° C

3.11V, 70° C

) A

( T N

R R U C

)

T X E

-10

D D

(

-20

E C R U O S

-30

-40

03.50.5 1 1.5 2 2.5 3

3.3V, 25° C

3.47V, 0° C

SWEEP (V

Figure 28. ADSP-21261 Typical Drive

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 9 on Page 19 through Table 30 on Page 36. These include

output disable time, output enable time, and capacitive loading.

Timing is measured on signals when they cross the 1.5 V level as described in Figure 30. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V.

OUTPUT

30pF

50⍀

1.5V

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29). Figure 33 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 31, Figure 32, and Figure 33 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% – 80%, V = Min) vs. Load Capacitance.

12.0

10.0

) s n

( S

8.0

E M

I T

L L

6.0

A F

D N A

4.0

E S

I R

2.0

y = 0.0904x + 1.9426

y = 0.0722x + 1.4042

0 12040 100

LOAD CAPACITANCE (pF)

Figure 31. Typical Output Rise/Fall Time

(20%-80%, V

)

s n

( S

I T

L L A

F D

N A

E S

I R

y = 0.0915x + 2.2207

RISE

806020

= Max)

DDEXT

RISE

y = 0.0728x +1.6336

FALL

Figure 29. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

INPUT

1.5V 1.5V

OUTPUT

Figure 30. Voltage Reference Levels for AC Measurements

Rev. PrB | Page 37 of 44 | June 2004

012020 40 60 80 100

LOAD CAPACITANCE (pF)

Figure 32. Typical Output Rise/Fall Time

(20%-80%, V

DDEXT

= Min)

Page 38

ADSP-21261 Preliminary Technical Data

7 6

) s

(

D L O

H R

O Y

A L E

D T

-1

P T

-2

U O

-3

-4

Figure 33. Typical Output Delay or Hold vs. Load Capacitance

y = 0.0904x - 2.712

012020 40 60 80 100

LOAD CAPACITANCE (pF)

(at Ambient Temperature)

ENVIRONMENTAL CONDITIONS

The ADSP-21261 processor is rated for performance over the commercial temperature range, T

= 0°C to 70°C.

AMB

THERMAL CHARACTERISTICS

Table 31 and Table 32 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board.

To determine the Junction Temperature of the device while on the application PCB, use:

Values of θ

are provided for package comparison and PCB

design considerations when an external heat sink is required. Values of θ

are provided for package comparison and PCB

design considerations.

Table 31. Thermal Characteristics for 136-Ball BGA

Parameter Condition Typical Unit

JMA

JMT

The thermal characteristics values provided in this table are modeled values.

Airflow = 0 m/s 28.2 °C/W Airflow = 1 m/s 24.4 °C/W Airflow = 2 m/s 23.3 °C/W

20.1 °C/W

7.0 °C/W Airflow = 0 m/s 0.1 °C/W Airflow = 1 m/s 0.3 °C/W Airflow = 2 m/s 0.4 °C/W

Table 32. Thermal Characteristics for 144-Lead LQFP1

Parameter Condition Typical Unit

JMA

JMT

The thermal characteristics values provided in this table are modeled values.

Airflow = 0 m/s 32.5 °C/W Airflow = 1 m/s 28.9 °C/W Airflow = 2 m/s 27.8 °C/W

7.8 °C/W Airflow = 0 m/s 0.5 °C/W Airflow = 1 m/s 0.8 °C/W Airflow = 2 m/s 1.0 °C/W

TJT

CASE

PD×()+=

where:

= Junction temperature 0C

= Case temperature (0C) measured at the top center of the

CASE

package

= Junction-to-Top (of package) characterization parameter

= Typical value from the tables below

= Power dissipation see EE Note #216

Values of θ design considerations. θ mation of T

are provided for package comparison and PCB

by the equation:

can be used for a first order approxi-

TJTAθ

PD×()+=

where:

= Ambient Temperature 0C

Rev. PrB | Page 38 of 44 | June 2004

Page 39

136-BALL BGA PIN CONFIGURATIONS

The following table shows the ADSP-21261’s pin names and their default function after reset (in parentheses).

Table 33. 136-Ball BGA Pin Assignments

ADSP-21261Preliminary Technical Data

Pin Name BGA Pin

No.

CLKCFG0 A01 CLKCFG1 B01 BOOTCFG1 C01 V

Pin Name BGA Pin

No.

Pin Name BGA Pin

No.

Pin Name BGA Pin

No.

DDINT

D01 XTAL A02 GND B02 BOOTCFG0 C02 GND D02 TMS A03 V

DDEXT

B03 GND C03 GND D04 TCK A04 CLKIN B04 GND C12 GND D05 TDI A05 TRST B05 GND C13 GND D06 CLKOUT A06 A TDO A07 A EMU

A08 V

VSS

VDD

DDEXT

B06 V

DDINT

C14 GND D09 B07 GND D10 B08 GND D11

MOSI A09 SPICLK B09 GND D13 MISO A10 RESET B10 V SPIDS V

DDINT

A11 V

DDINT

B11

A12 GND B12

DDINT

D14

GND A13 GND B13 GND A14 GND B14 V

DDINT

GND E02 FLAG0 F02 V GND E04 GND F04 V

E01 FLAG1 F01 AD7 G01 AD6 H01

DDINT

DDEXT

G02 V

DDEXT

G13 DAI_P18 (SD5B) H13

H02

GND E05 GND F05 DAI_P19 (SCLK45) G14 DAI_P17 (SD5A) H14 GND E06 GND F06 GND E09 GND F09 GND E10 GND F10 GND E11 GND F11 GND E13 FLAG2 F13 FLAG3 E14 DAI_P20 (SFS45) F14

Rev. PrB | Page 39 of 44 | June 2004

Page 40

ADSP-21261 Preliminary Technical Data

Table 33. 136-Ball BGA Pin Assignments (Continued)

Pin Name BGA Pin

No.

Pin Name BGA Pin

No.

Pin Name BGA Pin

No.

Pin Name BGA Pin

No.

AD5 J01 AD3 K01 AD2 L01 AD0 M01 AD4 J02 V

DDINT

K02 AD1 L02 WR M02 GND J04 GND K04 GND L04 GND M03 GND J05 GND K05 GND L05 GND M12 GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13 GND J09 GND K09 GND L09 DAI_P13 (SCLK23) M14 GND J10 GND K10 GND L10 GND J11 GND K11 GND L11 V

DDINT

J13 GND K13 GND L13 DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS23) L14 AD15 N01 AD14 P01 ALE N02 AD13 P02 RD V V

DDINT

DDEXT

N03 AD12 P03

N04 AD11 P04

N05 AD10 P05 AD8 N06 AD9 P06 V

DDINT

N07 DAI_P1 (SD0A) P07 DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08 V

DDEXT

N09 DAI_P5 (SD1A) P09 DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10 V V

DDINT

N11 DAI_P7 (SCLK1) P11

N12 DAI_P8 (SFS1) P12 GND N13 DAI_P9 (SD2A) P13 DAI_P10 SD2B) N14 DAI_P11 (SD3A) P14

Rev. PrB | Page 40 of 44 | June 2004

Page 41

KEY

DDINT

DDEXT

GND*

VSS

VDD

I/O SIGNALS

ADSP-21261Preliminary Technical Data

12345678910111214 13

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary)

Rev. PrB | Page 41 of 44 | June 2004

Page 42

ADSP-21261 Preliminary Technical Data

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-21261’s pin names and their default function after reset (in parentheses).

Table 34. 144-Lead LQFP Pin Assignments

Pin Name LQFP

Pin No.

DDINT

1V CLKCFG0 2 GND 38 GND 74 V CLKCFG1 3 RD BOOTCFG0 4 ALE 40 GND 76 V

Pin Name LQFP

Pin No.

DDINT

37 V

39 V

Pin Name LQFP

Pin No.

DDEXT

DDINT

73 GND 109

75 GND 111

Pin Name LQFP

Pin No.

DDINT

110

112 BOOTCFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113 GND 6 AD14 42 DAI_P11 (SD3A) 78 V V

DDEXT

7 AD13 43 DAI_P12 (SD3B) 79 GND 115 GND 8 GND 44 DAI_P13 (SCLK23) 80 V V

DDINT

DDEXT

45 DAI_P14 (SFS23) 81 GND 117 GND 10 AD12 46 DAI_P15 (SD4A) 82 V V

DDINT

11 V

DDINT

47 V

DDINT

83 GND 119 GND 12 GND 48 GND 84 V V

DDINT

13 AD11 49 GND 85 RESET 121

DDINT

DDEXT

DDINT

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS

114

116

118

120

122 FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123 FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V

DDINT

124 AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK45) 89 SPICLK 125 GND 18 V V

DDINT

19 GND 55 GND 91 MOSI 127

DDINT

54 V

DDINT

90 MISO 126

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128 V

DDEXT

GND 22 GND 58 DAI_P20 (SFS45) 94 V V

DDINT

AD6 24 V

21 DAI_P3 (SCLK0) 57 V

23 V

DDEXT

DDINT

59 GND 95 A 60 V

DDEXT

DDINT

93 V

96 A

DDINT

DDEXT

VDD

VSS

129

130

131

132 AD5 25 GND 61 FLAG2 97 GND 133 AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 CLKOUT 134 V

DDINT

27 DAI_P5 (SD1A) 63 V

DDINT

99 EMU 135 GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136 AD3 29 DAI_P7 (SCLK1) 65 V AD2 30 V V

DDEXT

31 GND 67 V

GND 32 V

DDINT

66 GND 102 TRST 138

68 GND 104 TMS 140

AD1 33 GND 69 V

DDINT

101 TDI 137

103 TCK 139

105 GND 141 AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142 WR V

DDINT

35 DAI_P9 (SD2A) 71 V 36 V

DDINT

72 V

DDINT

107 XTAL 143

108 V

DDEXT

144

Rev. PrB | Page 42 of 44 | June 2004

Page 43

PACKAGE DIMENSIONS

The ADSP-21261 is available in a 136-ball chip scale (miniBGA) package and a 144-lead low profile quad flat (LQFP) package, as shown in Figure 35 and Figure 36.

ADSP-21261Preliminary Technical Data

12.00 BSC SQ

PIN A1 INDICATOR

TOP VIEW

1.70 MAX

1. DIMENSIONS ARE IN MILIMETERS (MM).

2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.

3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 MM OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.

4. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR THE BALL DIAMETER.

5. CENTER DIMENSIONS ARE NOMINAL.

DETAIL A

0.80

BSC

TYP

0.25 MIN

A B C D

F G H

J K

L M N

0.50

0.46

0.40

(BALL

DIAMETER)

10.40 BSC SQ

109876543211314 1112

BOTTOM VIEW

DETAIL A

1.31

1.21

1.10

SEATING PLANE

0.12 MAX (BALL COPLANARITY)

0.80 BSC TYP

Figure 35. 136-Ball Chip Scale Package Mini-BGA (CSP_BGA) (BC-136)

Rev. PrB | Page 43 of 44 | June 2004

Page 44

ADSP-21261 Preliminary Technical Data

22.00 BSC SQ

20.00 BSC SQ

109

108

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB.

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OFITSIDEALPOSITION,WHENMEASUREDINTHE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

0.27 TYP

0.22

0.17

SEATING

PLANE

0.08 MAX (LEAD COPLANARITY)

0.15

0.05

0.75

0.60 TYP

0.45

1.45

1.40

1.35

1.60 MAX

DETAIL A

0.50 BSC TYP (LEAD PITCH)

144

DETAIL A

PIN 1 INDICATOR

TOP VIEW (PINS DOWN)

Figure 36. 144-lead LQFP (ST-144)

ORDERING GUIDE

Part Number Ambient Temperature

Range

Instruction Rate

On-Chip SRAM

ROM Operating Voltage Package

ADSP-21261SKBC-X 0°C to +70°C 150 MHz 1 Mbit 3 Mbit 1.2 INT/3.3 EXT V 136-ball BGA ADSP-21261SKBCZ-X ADSP-21261SKSTZ-X

BC indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package.

Z = Pb-free part. For more information about lead-free package offerings, please visit www.analog.com.

0°C to +70°C 150 MHz 1 Mbit 3 Mbit 1.2 INT/3.3 EXT V 136-ball BGA 0°C to +70°C 150 MHz 1 Mbit 3 Mbit 1.2 INT/3.3 EXT V 144-Lead LQFP

registered trademarks are the property of their respective owners.

Rev. PrB | Page 44 of 44 | June 2004

Datasheet ADSP-21261 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

SUMMARY

KEY FEATURES

TABLE OF CONTENTS

GENERAL DESCRIPTION

ADSP-21261 FAMILY CORE ARCHITECTURE

SIMD Computational Engine

Independent, Parallel Computation Units

Data Register File

Single-Cycle Fetch of Instruction and Four Operands

Instruction Cache

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

Flexible Instruction Set

ADSP-21261 MEMORY AND I/O INTERFACE FEATURES

Dual-Ported On-Chip Memory

DMA Controller

Serial Ports

Serial Peripheral (Compatible) Interface

Parallel Port

Timers

ROM Based Security

Program Booting

Phase-Locked Loop

Power Supplies

TARGET BOARD JTAG EMULATOR CONNECTOR

DEVELOPMENT TOOLS

ADDITIONAL INFORMATION

PIN FUNCTION DESCRIPTIONS

ADDRESS DATA PINS AS FLAGS

BOOT MODES

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

ADDRESS DATA MODES

ADSP-21261 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

Power-Up Sequencing

Clock Input

Clock Signals

Reset

Interrupts

Core Timer

Timer PWM_OUT Cycle Timing

Timer WDTH_CAP Timing

DAI Pin to Pin Direct Routing

Precision Clock Generator (Direct Pin Routing)

Flags

Memory Read–Parallel Port

Memory Write—Parallel Port

Serial Ports

Input Data Port (IDP)

Parallel Data Acquisition Port (PDAP)

SPI Interface—Master

SPI Interface—Slave

JTAG Test Access Port and Emulation

OUTPUT DRIVE CURRENTS

TEST CONDITIONS

CAPACITIVE LOADING

ENVIRONMENTAL CONDITIONS

THERMAL CHARACTERISTICS

136-BALL BGA PIN CONFIGURATIONS

144-LEAD LQFP PIN CONFIGURATIONS

PACKAGE DIMENSIONS

ORDERING GUIDE