The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, VisualDSP++, the VisualDSP++ logo, SHARC,
CROSSCORE, the CROSSCORE logo, and EZ-KIT Lite are registered
trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Page 3
Regulatory Compliance
The ADSP-21161N EZ-KIT Lite evaluation system has been certified to
comply with the essential requirements of the European EMC directive
89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE”
mark.
The ADSP-21161N EZ-KIT Lite evaluation system had been appended to
Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE
Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
Page 4
Page 5
CONTENTS
PREFACE
Purpose of This Manual ................................................................. xiv
Intended Audience ......................................................................... xiv
Manual Contents ............................................................................ xv
What’s New in This Manual ............................................................ xv
Technical or Customer Support ...................................................... xvi
Supported Processors ...................................................................... xvi
Product Information ..................................................................... xvii
MyAnalog.com ........................................................................ xvii
Processor Product Information ................................................. xvii
Related Documents ................................................................ xviii
Online Technical Documentation ............................................. xix
Accessing Documentation From VisualDSP++ ....................... xx
Accessing Documentation From Windows ............................. xx
Accessing Documentation From Web ................................... xxi
Printed Manuals ....................................................................... xxi
VisualDSP++ Documentation Set ......................................... xxi
Power Supply ........................................................................ 2-21
Board Current Measurements ................................................ 2-21
BILL OF MATERIALS
INDEX
viiiADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 9
CONTENTS
ADSP-21161N EZ-KIT Lite Evaluation System Manualix
Page 10
CONTENTS
xADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 11
PREFACE
Thank you for purchasing the ADSP-21161N EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for SHARC
(DSPs).
The SHARC processors are based on a 32-bit super Harvard architecture
that includes a unique memory architecture comprised of two large
on-chip, dual-ported SRAM blocks coupled with a sophisticated IO processor, which gives a SHARC processor the bandwidth for sustained
high-speed computations. SHARC processors represent today’s de facto
standard for floating-point processor targeted for premium audio
applications.
The evaluation system is designed to be used in conjunction with the
VisualDSP++
ADSP-21161N SHARC processors. The VisualDSP++ development environment gives you the ability to perform advanced application code
development and debug, such as:
•Create, compile, assemble, and link application programs written
in C++, C, and ADSP-21161N assembly
•Load, run, step, halt, and set breakpoints in application program
®
development environment to test the capabilities of the
®
digital signal processors
•Read and write data and program memory
•Read and write core and peripheral registers
•Plot memory
ADSP-21161N EZ-KIT Lite Evaluation System Manualxi
Page 12
Access to the ADSP-21161N processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface provides unrestricted access to the ADSP-21161N processor and
the evaluation board peripherals. Analog Devices JTAG emulators offer
faster communication between the host PC and target hardware. Analog
Devices carries a wide range of in-circuit emulation products. To learn
more about Analog Devices emulators and processor development tools,
go to
http://www.analog.com/dsp/tools/.
ADSP-21161N EZ-KIT Lite provides example programs to demonstrate
the capabilities of the evaluation board.
L
The board features:
The ADSP-21161N EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. Once
the initial unrestricted 90-day evaluation license expires:
•VisualDSP++ allows a connection to the ADSP-21161N
EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer
allowed.
•The linker restricts a users program to 5K words of internal
memory for code space with no restrictions for data space.
Refer to the VisualDSP++ Installation Quick Reference Card for
details.
•Analog Devices ADSP-21161N processor
D 100 MHz Core Clock Speed
D Core Clock Mode Jumper Configurable
•Analog Devices AD1836 96 kHz Audio Codec
D Jumper Selectable Line-In or Mic-In 3.5 mm Stereo Jack
xiiADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 13
D Line-Out 3.5 mm Stereo Jack
D 4 RCA Jacks for Audio Input
D 8 RCA Jacks for Audio Output
D 14-Pin Emulator Connector for JTAG Interface
D SPORT Connectors
D Link Port 0 and Link Port 1
D External Port Connectors (not populated)
Preface
•General-Purpose IO
D 4 Push Button Flags
D 3 Push Button Interrupts
D 6 LED Outputs
•Analog Devices ADP3338 and ADP3339 Voltage Regulators
•Breadboard area with typical SMT footprints
The EZ-KIT Lite board has a flash memory device that can be used to
store user-specific boot code. By configuring the jumpers for EPROM
boot, the board can run as a stand-alone unit. The ADSP-21161N
EZ-KIT Lite package contains a flash programmer utility, which allows
you to program the flash memory. The “Flash Programmer Utility” is
described on page 1-12.
ADSP-21161N EZ-KIT Lite Evaluation System Manualxiii
Page 14
Purpose of This Manual
SPORT0 and SPORT2 connect to the audio codec, facilitating creation of
audio-signal processing applications.
off-board connectors of other serial devices.
Additionally, the EZ-KIT Lite board provides un-installed expansion connector footprints to connect to the processor’s External Port (EP) and
Host Processor Interface (HPI).
SPORT1 and SPORT3 connect to
Purpose of This Manual
The ADSP-21161N EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board) and describes the
operation and configuration of the board components. The product software component is detailed in the VisualDSP++ Installation Quick Reference Card. The manual provides guidelines for running your own
code on the ADSP-21161N EZ-KIT Lite. Finally, a schematic and a bill
of materials are provided as a reference for future designs.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual but should supplement it with other texts
(such as the ADSP-21161 SHARC Processor Hardware Reference and ADSP-21160 SHARC Processor Instruction Set Reference) that describe your
target architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and the VisualDSP++ user’s or getting started
guides. For the locations of these documents, see “Related Documents” on
page -xviii.
xivADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 15
Manual Contents
The manual consists of:
•Chapter 1, “Using EZ-KIT Lite” on page 1-1
Provides information on the EZ-KIT Lite from a programmer’s
perspective and provides a simplified memory map.
•Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1
Provides information on the hardware aspects of the evaluation
system.
•Appendix A, “Bill Of Materials” on page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
•Appendix B, “Schematics” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
Preface
L
This appendix is not part of the online Help. The online Help
viewers should go to the PDF version of the ADSP-21161N
EZ-KIT Lite Evaluation System Manual located in the
Docs\EZ-KIT Lite Manuals folder on the installation CD to see the
schematics. Alternatively, the schematics can be found on the Analog Devices Web site,
www.analog.com/processors.
What’s New in This Manual
This revision of the ADSP-21161N EZ-KIT Lite Evaluation System Manual provides an updated listing of related documents and updated
licensing information.
ADSP-21161N EZ-KIT Lite Evaluation System Manualxv
Page 16
Technical or Customer Support
Technical or Customer Support
You can reach DSP Tools Support in the following ways.
•Visit the Embedded Processing and processor products Web site at
http://www.analog.com/processors/technicalSupport
•E-mail tools questions to
dsptools.support@analog.com
•E-mail processor questions to
dsp.support@analog.com
•Phone questions to 1-800-ANALOGD
•Contact your Analog Devices, Inc. local sales office or authorized
distributor
•Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
This EZ-KIT Lite evaluation system supports the Analog Devices
ADSP-21161N SHARC processors.
xviADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 17
Product Information
You can obtain product information from the Analog Devices website,
from the product CD-ROM, or from the printed publications (manuals).
Preface
Analog Devices is online at
mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
www.analog.com. Our website provides infor-
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
Registration:
Visit
www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and processors, visit our Web
site at www.analog.com/processors, which provides access to technical
publications, data sheets, application notes, product overviews, and product announcements.
ADSP-21161N EZ-KIT Lite Evaluation System Manualxvii
Page 18
Product Information
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
•E-mail questions or requests for information to
dsp.support@analog.com
•Fax questions or requests for information to
1-781-461-3010 (North America)
+49 (89) 76 903-557 (Europe)
•Access the FTP Web site at
ftp ftp.analog.com or ftp 137.71.23.21
ftp://ftp.analog.com
Related Documents
For information on product related development software, see the following publications.
Table 1. Related Processor Publications
TitleDescription
ADSP-21161N DSP Data Sheet General functional description, pinout, and
timing
ADSP-21161 SHARC Processor Hardware Reference
ADSP-21160 SHARC Processor Instruction Set
Reference
Description of internal processor architecture,
registers, and all peripheral functions
Description of all allowed processor assembly
instructions
Table 2. Related VisualDSP++ Publications
TitleDescription
VisualDSP++ User’s GuideDescription of VisualDSP++ features and usage
VisualDSP++ Assembler and Preprocessor Manual
Description of the assembler function and
commands
xviiiADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 19
Table 2. Related VisualDSP++ Publications (Cont’d)
TitleDescription
Preface
VisualDSP++ C/C++ Complier and Library
Manual for SHARC Processors
VisualDSP++ Linker and Utilities ManualDescription of the linker function and com-
VisualDSP++ Loader ManualDescription of the loader function and com-
Description of the complier function and commands for SHARC processors
mands
mands
The listed documents can be found through online Help or in the Docs
folder of your VisualDSP++ installation. Most documents are available in
printed form.
If you plan to use the EZ-KIT Lite board in conjunction with a
L
JTAG emulator, also refer to the documentation that accompanies
the emulator.
All documentation is available online. Most documentation is available in
printed form.
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary
Docs folder on the VisualDSP++ installation CD.
ADSP-21161N EZ-KIT Lite Evaluation System Manualxix
.PDF files of most manuals are provided in the
Page 20
Product Information
Each documentation file type is described as follows.
File Description
.CHMHelp system files and manuals in Help format
.HTM or
.HTML
.PDFVisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the
Internet Explorer 4.0 (or higher).
Viewing and printing the
Reader (4.0 or higher).
.PDF files requires a PDF reader, such as Adobe Acrobat
.HTML files requires a browser, such as
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows
®
Explorer, or the Analog Devices
Web site.
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
To view ADSP-21161N EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
xxADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 21
Preface
Help system files (.
located in the
The
Docs folder also contains the Dinkum Abridged C++ library and the
CHM) are located in the Help folder, and .PDF files are
Docs folder of your VisualDSP++ installation CD-ROM.
Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about
VisualDSP++ and the ADSP-21161N EZ-KIT Lite evaluation system.
Select a processor family and book title. Download archive (.ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
ADSP-21161N EZ-KIT Lite Evaluation System Manualxxi
Page 22
Notation Conventions
Hardware Tools Manuals
To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
L
xxiiADSP-21161N EZ-KIT Lite Evaluation System Manual
Additional conventions, which apply only to specific chapters, may
appear throughout this document.
Page 23
ExampleDescription
Preface
Close command
(File menu)
{this | that}Alternative required items in syntax descriptions appear within curly
[this | that]Optional items in syntax descriptions appear within brackets and sepa-
[this,…]Optional item lists in syntax descriptions appear within brackets
.SECTIONCommands, directives, keywords, and feature names are in text with
filenameNon-keyword placeholders appear in text with italic style format.
L
a
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close
command appears on the File menu).
brackets and separated by vertical bars; read the example as
that. One or the other is required.
rated by vertical bars; read the example as an optional
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of
letter gothic font.
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
this.
this or
this or that.
Warn in g: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
[
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Wa rn in g
appears instead of this symbol.
ADSP-21161N EZ-KIT Lite Evaluation System Manualxxiii
Page 24
Notation Conventions
xxivADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 25
1USING EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-21161N EZ-KIT Lite evaluation system.
The information appears in the following sections.
•“Package Contents” on page 1-2
Lists the items contained in the ADSP-21161N EZ-KIT Lite
package.
•“Default Configuration” on page 1-3
Shows the default configuration of the ADSP-21161N EZ-KIT
Lite.
•“Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing
ADSP-21161NEZ-KIT Lite session using VisualDSP++.
•“Evaluation License Restrictions” on page 1-6
Describes the restrictions of the VisualDSP++ license shipped with
the EZ-KIT Lite.
•“Memory Map” on page 1-6
Defines the ADSP-21161N EZ-KIT Lite’s memory map.
•“SDRAM Memory” on page 1-6·
Defines the register values to configure the on-board SDRAM.
•“FLAG Pins” on page 1-9
Describes the board’s FLAG pins.
ADSP-21161N EZ-KIT Lite Evaluation System Manual1-1
Page 26
Package Contents
•“Interrupt Pins” on page 1-10
Describes the board’s interrupt pins.
•“Audio Interface” on page 1-10
Describes the board’s audio interface.
•“Example Programs” on page 1-12
Provides information about example programs included in the
ADSP-21161N EZ-KIT Lite.
•“Flash Programmer Utility” on page 1-12
Provides information on the Flash Programmer utility included
with the EZ-KIT Lite software.
•“VisualDSP++ Interface” on page 1-13
Describes the boot loading, target options, and other facilities of
the EZ-KIT Lite system.
For detailed information on how to program the ADSP-21161N SHARC
processor, refer to the documents referenced in “Related Documents”.
Package Contents
Your ADSP-21161N EZ-KIT Lite evaluation system package contains the
following items.
•ADSP-21161N EZ-KIT Lite board
•VisualDSP++ Installation Quick Reference Card
1-2ADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 27
Using EZ-KIT Lite
•CD containing:
D VisualDSP++ software
D ADSP-21161N EZ-KIT Lite debug software
D USB driver files
D Example programs
D ADSP-21161N EZ-KIT Lite Evaluation System Manual (this
document)
•Universal 7V DC power supply
•USB 2.0 cable
•Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic
charges readily accumulate on the human body and
equipment and can discharge without detection. Permanent damage may occur on devices subjected to
high-energy discharges. Proper ESD precautions are
recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards
in the protective shipping package.
The ADSP-21161N EZ-KIT Lite board is designed to run outside your
personal computer as a stand-alone unit. You do not have to open your
computer case.
ADSP-21161N EZ-KIT Lite Evaluation System Manual1-3
Page 28
Default Configuration
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings, DIP
switch, connector locations, and LEDs used in installation. Confirm that
your board is set up in the default configuration before using the board.
USB Monitor: LED10
DSP Reset: LED8
Reset: LED1
Power: LED11
Figure 1-1. EZ-KIT Lite Hardware Setup
1-4ADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 29
Installation and Session Startup
Using EZ-KIT Lite
L
For correct operation, install the software and hardware in the
order presented in the VisualDSP++ Installation Quick Reference Card.
1. Verify that the yellow USB monitor LED (
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. From the Start menu, navigate to the VisualDSP++ environment
via the Programs menu.
If you are running VisualDSP++ for the first time, the New Session
dialog box appears on the screen (skip the rest of the procedure and
go to step 3).
If you have run VisualDSP++ previously, the last opened session
appears on the screen.
To switch to another session, via the Session List dialog box, hold
down the Ctrl key while starting VisualDSP++ (go to step 5).
3. In Debug target, select EZ-KIT Lite (ADSP-21xxx).
In Platform, select ADSP-21xxx EZ-KIT Lite.
In Processor, choose the appropriate processor, ADSP-21161.
In Session name, type a new name or accept the default.
LED10, located near the
4. Click OK to return to the Session List.
5. Highlight the session and click Activate.
ADSP-21161N EZ-KIT Lite Evaluation System Manual1-5
Page 30
Evaluation License Restrictions
Evaluation License Restrictions
The ADSP-21161N EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
•VisualDSP++ allows a connection to the ADSP-21161N EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
•The linker restricts a users program to 5K words of internal memory for code space with no restrictions for data space.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
Memory Map
The ADSP-21161N processors includes 1 Mbit of internal SRAM for program storage or data storage. The configuration of internal SRAM is
detailed in the ADSP-21161 SHARC Processor Hardware Reference.
The ADSP-21161N EZ-KIT Lite board contains 512K x 8-bits of external flash memory. The flash memory is connected to the processors’s
and
~BMS memory select pins. The flash memory can be accessed in either
the boot memory space or the external memory space. The external memory interface also connects to 1M x 48-bit SDRAM memory. The flash
memory connects to the
~MS0 pin.
~MS1
SDRAM Memory
To use the SDRAM memory, set the two SDRAM control registers to the
values shown in Listing 1-1.
1-6ADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 31
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start AddressEnd AddressContent
0x0000 00000x0001 FFFFIOP Registers (Internal)
0x0002 00000x0002 1FFFBlock 0 Long Word Addressing
Using EZ-KIT Lite
Internal
Memory
External
Memory
0x0002 80000x0002 9FFFBlock 1 Long Word Addressing
0x0004 00000x0004 3FFFBlock 0 Normal Word Addressing
0x0005 00000x0005 3FFFBlock 1 Normal Word Addressing
0x0008 00000x0008 7FFFBlock 0 Short Word Addressing
0x000A 00000x000A 7FFFBlock 1 Short Word Addressing
0x0010 00000x001F FFFFMulti-processor Memory Space
0x0020 00000x002F FFFFExternal Memory Space Bank 0 (SDRAM)
0x0400 00000x047F FFFFExternal Memory Space Bank 1 (FLASH)
0x0800 0000 0x0BFF FFFFExternal Memory Space Bank 2
0x0C00 00000x0FFF FFFFExternal Memory Space Bank 3
Listing 1-1. ADSP-21161N EZ-KIT Lite – SDRAM Settings
/* SDRAM Controller Setup for the ADSP-21161N EZ-KIT Lite*/
/* Assumes SDRAM part# Micron MT48LC16M16A1-7SE (1Mx16-bit,
2 banks)*/
/* Default Factory Hardware settings (rev2.3)*/
/* LK_CFG[1:0]= 10,~CLDBL=1*/
/* CLKIN=25 MHz, => CCLK=100 MHz*/
/* 3 SDRAMs by 16 bits wide total = 3x(1Mx16-bit) = 1M x 48-bit */
/* Mapped to MS0 addresses 0x00200000-0x002fffff */
/* Estimated SDCLK 50 MHz => SDCKR=0 */
/* Settings must be double counted for SDCKR-bit=0, except CAS
Latency) */
/* 50 MHz min @ CL=2 -> SDCL=2 [CAS Latency]*/
/* tRAS=42ns min-> SDTRAS=5*2=10 [precharge delay]*/
ADSP-21161N EZ-KIT Lite Evaluation System Manual1-7
/* Note: If you change any clock, you have to change all settings
for best performance */
init_21161_SDRAM_controller:
ustat1=dm(WAIT);
bit clr ustat1 0x000FFFFF;/* clear MS0 wait state count */
dm(WAIT)=ustat1;
ustat1=0x60D;/* refresh rate
dm(SDRDIV)=ustat1;
ustat1=0x040146A2;/* mask in SDRAM settings */
dm(SDCTL)=ustat1;
init_21161_SDRAM_controller.end:
rts;
*/
When you are in a VisualDSP++ session connected to the ADSP-21161N
EZ-KIT Lite board, the SDRAM registers are configured automatically
through the debugger each time the processor is reset. Clearing the Auto configure external memory check box on the Target Options dialog box,
which is accessible through the Settings pull-down menu, disables this
feature. For more information see “Target Options” on page 1-13.
1-8ADSP-21161N EZ-KIT Lite Evaluation System Manual
Page 33
Using EZ-KIT Lite
FLAG Pins
The ADSP-21161N holds 12 asynchronous FLAG IO pins. Ten of these
pins (
FLAG0–9) are available for interaction with the running program.
After the processor is reset, the FLAGs are configured as inputs. The directions of the FLAGs are configured though the
and read though the
FLAG registers. The FLAG registers are summarized in
Table 1-2. For more information on FLAGs, refer to the ADSP-21161
SHARC Processor Hardware Reference.
Table 1-2. FLAG Pin Summary
MODE2 register and are set
1
FLAG
FLAG0SW1/AD1836_SPI_SELECTFLAG0 connects to push button SW1 for user
FLAG1SW2/AD1852_SPI_SELECT FLAG1 connects to push button SW2 for user
FLAG2SW3FLAG2 connects to push button SW3 for user
FLAG3SW4FLAG3 connects to push button SW4 for user
FLAG4–FLAG9LED2–LED7FLAG4–9 connect to LEDs on the EZ-KIT Lite
FLAG10 and
FLAG11
1 FLAG0–FLAG3 are available on connector P10.
Connects ToDescription
input and to the
audio codec.
input and to the
auxiliary DAC.
input.
input.
board and are for user output.
Not connectedNot available
SPI select pin on the AD1836
SPI select pin on the AD1852
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Interrupt Pins
Interrupt Pins
The ADSP-21161N holds three interrupt pins (IRQ0–2) that let you interact with the running program. Each of the three external interrupts is
directly accessible through the push button switches
Lite board. Interrupt pins are summarized in Table 1-3. For more infor-
mation, refer to the ADSP-21161 SHARC Processor Hardware Reference.
Table 1-3. Interrupt Pin Summary
SW5–7 on the EZ-KIT
Interrupt
IRQ0SW5IRQ0–2 connect to the push buttons and supply
IRQ1SW6
IRQ2SW7
1 IRQ0–3 are available on connector P10.
1
Connects ToDescription
feedback for program execution. For instance, you
can write your code to trigger a FLAG when a
routine is complete.
Audio Interface
The audio interface consists of the AD1836 audio codec, the AD1852
auxiliary DAC and the CS8414 SPDIF receiver.
nect to the audio devices and provide 3 channels of stereo input (1
channel digital, 2 channels analog) and 4 channels of stereo output.
Analog audio input is facilitated by a 3.5 mm stereo jack (
RCA mono jacks (
P6). One of the AD1836 stereo input channels is dedi-
cated to two of the RCA mono jacks. The other stereo input channels can
either be supplied by the 3.5 mm stereo jack or the other two RCA mono
jacks.
JP11 determines which jack is used for audio input. Digital audio
input can be provided on either a single RCA mono jack (
input connector (
P4). JP2 determines the source. Three of the stereo out-
SPORT0 and SPORT2 con-
P7) and four
P5) or an optical
1-10ADSP-21161N EZ-KIT Lite Evaluation System Manual
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Using EZ-KIT Lite
put channels come from the AD1836, while the final channel is from the
AD1852. See “Audio Connectors (P4–8, P17)” on page 2-18 for more
information about the connectors.
The AD1836 multi-channel codec features six digital-to-analog converters
(DACs) and four analog-to-digital converters (ADCs) and supports multiple digital stereo channels with 24-bit conversion resolution and a 96 kHz
sample rate. The AD1836 features a 108 dB dynamic range for each of its
six DACs and a 104 dB dynamic range for its four ADCs. The AD1836 is
configured through its SPI port. The ADSP-21161N processor is capable
of accessing the AD1836’s SPI port through the SPI port as well as
through
SPORT1. For more information, see “AD1836 Control Selection
Jumper (JP23)” on page 2-12.
The AD1852 is a complete 18/20/24-bit single-chip stereo digital audio
playback system. It is comprised of a multibit sigma-delta modulator, digital interpolation filters, and analog output drive circuitry. Other features
include an on-chip stereo attenuator and mute, programmed through an
SPI-compatible serial control port. The AD1852 is fully compatible with
all known DVD formats, including 192 kHz and 96 kHz sample frequencies and 24 bits. It also is backwards compatible by supporting 50/15µs
digital de-emphasis intended for “redbook” Compact Discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rate.
The CS8414 is a monolithic CMOS device that receives and decodes
audio data up to 96 kHz, according to the AES/EBU, IEC958, S/PDIF,
and EIAJ CP340/1201 interface standards. The CS8414 receives data
from a transmission line, recovers the clock and synchronization signals,
and de-multiplexes the audio and digital data. The CS8414 is setup to
operate in Two-Wire Interface (TWI) compatible mode.
The
Microphone and Line-In jacks connect to the left and right ADC1
channel on the AD1836, depending on the setting of jumpers. See “MIC
Gain Selection Jumpers (JP9–10)” on page 2-8 and “ADC1 Input Selection Jumper (JP11)” on page 2-9 for more information. Two RCA jacks
ADSP-21161N EZ-KIT Lite Evaluation System Manual1-11
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Example Programs
connect to
ADC2 on the AD1836. This input is configured though the
input mode selection jumpers, See “ADC2 Input Mode Selection Jumpers
(JP7–8)” on page 2-8 for more information.
The
Line-Out jacks connect to the left and right DAC outputs of the
AD1836 and AD1852.
The CS8414 includes an error flag (
put may not be valid. This signal connects to a LED (
VERF) to indicate that the audio out-
LED9) on the board.
This signal may also be used by interpolation filters to provide error
correction.
Example Programs
Example programs are provided with the ADSP-21161N EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
\…\211xx\EZ-KITs\ADSP-21161N\Examples subdirectory of the Visu-
alDSP++ installation directory. Please refer to the readme file provided
with each example for more information.
Flash Programmer Utility
The ADSP-21161N EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on
the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++.
Once the utility is installed, it is accessible from the Tools pull-down
menu.
For more information on the Flash Programmer utility, go to online Help.
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Using EZ-KIT Lite
VisualDSP++ Interface
This section provides information about the following parts of the VisualDSP++ graphical user interface:
•“Boot Load” on page 1-13
•“Target Options” on page 1-13
•“Core Hang Conditions” on page 1-15
•“Restricted Software Breakpoints” on page 1-16
Boot Load
Choosing Boot Load from the Settings menu runs the processor and performs a hard reset on the board. This command saves you from having to
shut down VisualDSP++, reset the EZ-KIT Lite board, and bring up VisualDSP++ again when you want to perform a hard reset.
Use this feature when loading debug boot code from an external part or
when you want to put the device into a known state.
Target Options
Choosing Target Options from the Settings menu opens the Target
Options dialog box (Figure 1-2). Use target options to control certain
aspects of the processor on the ADSP-21161N EZ-KIT Lite evaluation
system.
While Target is Halted and On Emulator Exit Options
This target option controls the processor’s behavior when VisualDSP++
relinquishes processor control (for example, when exiting VisualDSP++).
The options are detailed in Table 1-4 and Table 1-5.
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VisualDSP++ Interface
Figure 1-2. Target Options Dialog Box
Table 1-4. While Target is Halted Options
OptionDescription
Stop I/O DMA Stops IO DMAs in emulator space. This option disables DMA requests when
the emulator has control of the processor. Data in the EP, LINK, or SPORT
DMA buffers are held there unless the internal DMA request was already
granted. This option holds off incoming data and ceases outgoing data. Because
SPORT-receive data cannot be held off, it is lost, and the overrun bit is set. The
direct write buffer (internal memory write) and the EP pad buffer are allowed
to flush any remaining data to internal memory.
Table 1-5. On Emulator Exit Options
OptionDescription
On Emulator
Exit
Determines the state the processor is left in when the emulator relinquishes control of the processor:
Reset DSP and Run causes the processor to reset and begin execution from its
reset vector location.
Run from current PC causes the processor to begin running from its current
location.
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Other Options
Table 1-6 describes other available target options.
Table 1-6. Other Target Options
OptionDescription
Using EZ-KIT Lite
Verify all writes to target
memory
Reset cycle counters on
run
Auto configure external
memory
Validates all memory writes to the processor. After each write, a read
is performed and the values are checked for a matching condition.
Enable this option during initial program development to locate
and fix initial build problems (such as attempting to load data into
non-existent memory).
Clear this option to increase performance while loading executable
files since VisualDSP++ does not perform the extra reads that are
required to verify each write.
Resets the cycle count registers to zero before a Run command is
issued. Select this option to count the number of cycles executed
between breakpoints in a program.
Enables the automatic configuration of the SDRAM registers (done
through the debugger).
Core Hang Conditions
Certain peripheral devices, such as host ports, DMA, and link ports, can
hold off the execution of processor instructions. This is known as a hung
condition and commonly occurs when reading from an empty port or
writing to a full port. If an attempt to halt the processor is made during
one of these conditions, the EZ-KIT Lite may encounter a core hang.
Normally, a core hang can be cleared by the board using a special
clear/abort bit. However, there are cases in which it is desirable or possible
not to clear the core hang. Sometimes it is desirable to wait for the core
hang to clear itself, such as when waiting for a host processor to read or
write data. In other cases, it is not possible to clear the core hang, and a
processor reset must occur to continue the debugging session.
Table 1-7 describes the EZ-KIT Lite’s core hang operations.
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VisualDSP++ Interface
Table 1-7. Core Hang Operations
OptionDescription
AbortAbort the hung operation. This causes the offending instruction to be
aborted in the pipeline.
RetryAllows you to remedy the hung operation. For example, if a host proces-
sor is holding off the processor, you can cause the host to clear the hung
condition.
IgnorePerforms a software reset on the target board.
ClearAborts the hung operation. This causes the offending instruction to be
aborted in the pipeline.
AcknowledgeAllows you to remedy the hung operation. For example, if a host proces-
sor is holding off the processor, you can cause the host to clear the hung
condition.
ResetPerforms a software reset on the target board.
Restricted Software Breakpoints
The EZ-KIT Lite development system restricts breakpoint placement
when certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus
architecture, pipeline depth, and ordering of the EZ-KIT Lite and its target processor.
1-16ADSP-21161N EZ-KIT Lite Evaluation System Manual
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2EZ-KIT LITE HARDWARE
REFERENCE
This chapter describes the hardware design of the ADSP-21161N EZ-KIT
Lite board. The following topics are covered.
•“System Architecture” on page 2-2
Describes the configuration of the ADSP-21161N EZ-KIT Lite
board and explains how the board components interface with the
processor.
•“Jumper Settings” on page 2-5
Shows the location and describes the function of the on-board
jumpers.
•“LEDs and Push Buttons” on page 2-13
Shows the location and describes the function of the LEDs and
push buttons.
•“Connectors” on page 2-16
Shows the location and gives the part number for the on-board
connectors. Also, the manufacturer and part number information is
given for the mating parts.
•“Specifications” on page 2-21
Provides the board’s measurements and power supply
specifications.
ADSP-21161N EZ-KIT Lite Evaluation System Manual2-1
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System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture Block Diagram
The ADSP-21161N processor’s core voltage is 1.8V, and the external
interface voltage is 3.3V.
A 25 MHz through-hole oscillator supplies the input clock to the processor. Footprints are provided on the board for a surface-mount oscillator
and a through-hole crystal for alternate user-installed clocks. The speed at
2-2ADSP-21161N EZ-KIT Lite Evaluation System Manual
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EZ-KIT Lite Hardware Reference
which the core operates is determined by the location of the clock mode
jumper (
JP21) as described on page 2-11. By default, the processor core
runs at 100 MHz.
External Port
The External Port (EP) of the processor connects to a 512K x 8-bit flash
memory. The flash memory connects to the boot memory select (
pin and the memory select 1 (
memory to be used to boot the processor as well as to store information
during normal operation.
The external memory interface also connects to 1M x 48-bit SDRAM
memory. The SDRAM memory connects to the memory select 0 (
pin. Refer to “SDRAM Disable Jumper (JP1)” on page 2-5 for information on how to configure the width of the SDRAM. Refer to “SDRAM
Memory” on page 1-6 for a summary of the processor’s memory map.
~MS1) pin. The connection allows the flash
~BMS)
~MS0)
Some of the address, data, and control signals are available externally via
two off-board connectors. The EP connectors’ pinout (
P9 and P10) can be
found in Appendix B, “Schematics”.
Host Processor Interface (HPI)
The Host Port Interface (HPI) signals are brought to an unpopulated
off-board connector (
P9). This allows the HPI to interface with a user
application. The pinout of the host port connector can be found in
Appendix B, “Schematics”.
SPORT Audio Interface
SPORT0 and SPORT2 are connected to the AD1836 codec (U10). A 3.5 mm
stereo jack and four RCA mono jacks facilitate an audio input, while a
3.5 mm stereo jack and eight RCA mono jacks facilitate an audio output.
ADSP-21161N EZ-KIT Lite Evaluation System Manual2-3
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System Architecture
The codec contains two input channels. One channel connects to a
3.5 mm stereo jack and two RCA jacks. The 3.5 mm stereo jack connects
to a microphone. The two RCA jacks can connect to a
LINE-OUT from an
audio device. You can supply an audio input to the codec microphone
input channel (
of
JP11 determine whether the LINE_IN channel of the codec is driven by
the
P6 connector or by the P7 connector.
MIC1) or to the LINE_IN input channel. The jumper settings
SPI Audio Interface
The SPI port is connected to the AD1836 and AD1852. The SPI port is
used for writing and reading the control registers of the audio devices.
Breadboard Area
Use the breadboard area to add external circuitry to:
•All board voltages and grounds
•Package footprints:
D 1x SOIC16
D 1x SOIC20
D 4x SOT23-6
D 1x PSOP44
D 2x SOT23
D 27x 0805
Analog Devices does not support and is not responsible for the
[
effects of additional circuitry.
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EZ-KIT Lite Hardware Reference
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory, as well as the special function registers,
through a 14-pin header.
For a detailed description of the interface’s connectors, see EE-68 published on the Analog Devices website. For more information, see “JTAG
Connector (P12)” on page 2-19. For more information about available
emulators, contact Analog Devices (see “Product Information”).
Jumper Settings
This section describes the function of all the jumpers. Figure 2-2 shows
the locations of all the jumpers.
SDRAM Disable Jumper (JP1)
The JP1 jumper is used to enable or disable the third SDRAM device.
When the jumper is installed, the ADSP-21161N can access the SDRAM
as 48-bit-wide external memory.
The upper 16 bits of data are multiplexed with the Link Ports and the
external data bus; therefore, when the jumper is installed, the Link Ports
are not available. To use the Link Ports, the
JP1 jumper must be removed.
SPDIF Selection Jumper (JP2)
The JP2 jumper is used select the SPDIF input to the CS8414 digital
audio receiver. When the jumper is configured for an optical connection,
the TOSLINK optical input connector (
jumper is configured for a coax connection, the RCA input connector (
should be used.
ADSP-21161N EZ-KIT Lite Evaluation System Manual2-5
P4) should be used. When the
P5)
Page 46
Jumper Settings
e
D
m
p
e
p
JP11: ADC1 In
JP5: FLAG1 Enabl
JP1: External Memory
Width
JP22: BMS Enable
JP19: DSP I
JP20: Boot Mod
JP21: Clock Mode
JP26: SW1 Enable
JP27: SW2 Enable
JP4: FLAG0 Enable
JP23: AD1836 Control Select
JP6: Sa
JP3: MCLK Select
JP2: SPDIF Select
JP9: Mic Gain Right
JP10: Mic Gain Left
JP7: ADC2 Input Mode Left
JP8: ADC2 Input Mode Right
ut Selector
le Frequency
Figure 2-2. Jumper Locations
MCLK Selection Jumper (JP3)
The JP3 jumper is used to select the MCLK source for the AD1836 and
AD1852.
2-6ADSP-21161N EZ-KIT Lite Evaluation System Manual
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EZ-KIT Lite Hardware Reference
Table 2-1. SPDIF Modes
Jumper LocationMode
1 and 2Optical (factory default)
2 and 3Coax
Table 2-2. MCLK Selection
Jumper LocationMCLK Source
1 and 2Audio Oscillator (12.288 MHz) (factory default)
2 and 3Derived clock from SPDIF Stream
FLAG0 Enable Jumper (JP4)
In standard configuration, FLAG0 is connected to the AD1836 and used as
a select for the SPI port. This jumper should be removed to use the push
button switch or the signal on the expansion connector (
jumper is removed, the SPI can no longer communicate with the
AD1836.
P10). Once the
FLAG1 Enable Jumper (JP5)
In standard configuration, FLAG1 is connected to the AD1852 and used as
a select for the SPI port. The
push button switch or the signal on the expansion connector (
JP5 jumper should be removed to use the
P10). Once
the jumper is removed, the SPI can no longer communicate with the
AD1852.
Sample Frequency Jumper (JP6)
The JP6 jumper is used to select the sample frequency for the AD1852
device. Table 2-3 shows the valid frequency modes.
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Jumper Settings
Table 2-3. Sample Frequencies
Jumper LocationSample Frequency
None installed Not allowed
3 and 4192 kHz (2x Interpolator)
1 and 296 kHz (4x Interpolator)
1 and 2, 3 and 448 kHz (8x Interpolator) (factory default)
ADC2 Input Mode Selection Jumpers (JP7–8)
The JP7 and JP8 jumpers control the input mode to ADC2 on the
AD1836 (see Table 2-4). In high-performance mode, the signal is routed
straight in to the ADC. In PGA mode, the signal goes through a multiplexer and a programmable gain amplifier inside of the codec.
Table 2-4. ADC Input Mode
Jumper LocationInput Mode
3 and 5, 4 and 6PGA (factory default)
1 and 3, 2 and 4High Performance
MIC Gain Selection Jumpers (JP9–10)
The JP9 and JP10 jumpers are used to select the pre-amp gain for the
microphone circuit (see Table 2-5). The gain for the left and right channel
should be configured the same.
Table 2-5. MIC Pre Amp Gain
Jumper PositionGain
Not Installed0 dB
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EZ-KIT Lite Hardware Reference
J
Table 2-5. MIC Pre Amp Gain (Cont’d)
Jumper PositionGain
1 and 220 dB
2 and 340 dB (factory default)
ADC1 Input Selection Jumper (JP11)
The JP11 jumper is used to select the input source for ADC2. If the input
source for ADC2 is
If the input source for ADC2 is a microphone, then the mini stereo plug
P7 should be used. If a microphone is used, the gain of the circuit may be
increased, as described in “MIC Gain Selection Jumpers (JP9–10)” on
page 2-8.
LINE-IN, then the RCA connector P6 should be used.
When the
4, the connection is to
and between pins 4 and 6, the connection is to
JP11 jumpers are between pins 1 and 3 and between pins 2 and
P7. When the jumpers are between pins 3 and 5
P6. The jumper settings are
illustrated in Table 2-6). (The words MIC and LINE are on the board as a
reference.)
Table 2-6. Audio Input Jumper Settings
Microphone InputStereo LINE_IN (Default)
1 2
1 2
P11
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Jumper Settings
Processor ID Jumper (JP19)
The JP19 jumper is used to select a different ID for the processor. During
typical operation of the EZ-KIT Lite board, there is only a single processor in the system. The jumper should be set to the single processor setting.
When a second processor is attached to the board though the link port,
these jumpers should be changed to configure one board for processor 1
and the other board for processor 2. System configuration options are
shown in Table 2-7.
Table 2-7. Processor ID Modes
Jumper PositionDescription
1 and 2, 3 and 4, 5 and 6Single processor (default)
3 and 4, 5 and 6Processor 1
1 and 2, 5 and 6Processor 2
OtherInvalid
Boot Mode Selection Jumper (JP20)
The JP20 jumper determines how the ADSP-21161N processor boots.
Table 2-8 shows the jumper setting for the processor boot modes.
Not installedNot installedInstalled (input)Reserved
LBOOT
Pins 3 & 4
BMS
Pins 5 & 6
(input)
Processor Boot Mode
Link Port Boot
Clock Mode Selection Jumper (JP21)
The JP21 jumper controls the speed for the core and external port of the
ADSP-21161N processor. The frequency supplied to CLKIN of the processor may be changed by removing the 25 MHz oscillator (
shipped with the board and replacing it with a different oscillator or crystal (
Y2). A clock mode and frequency should be selected so that the
minimum and maximum specs of the ADSP-21161N processor are not
exceeded. For more information on clock modes, see the ADSP-21161 SHARC Processor Hardware Reference. Table 2-9 shows the jumper setting
for the clock modes.
Table 2-9. Clock Mode Selections
U24) that is
CLKDBL
Pins 1 & 2
Not installedInstalledInstalled2:11x
Not installedInstalledNot installed3:11x
Not installedNot installedInstalled4:11x (default)
InstalledInstalledInstalled4:12x
InstalledInstalledNot installed6:12x
InstalledNot installedInstalled8:12x
CLK_CFG1
Pins 3 & 4
CLK_CFG0
Pins 5 & 6
Core Clock
Ratio
External Port
Clock Ratio
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Jumper Settings
~BMS Enable Jumper (JP22)
The JP22 jumper is used to control the routing of the Boot Memory Select
~BMS) signal. When the jumper is installed, the ~BMS signal is routed to
(
the flash memory interface and can be used for reading, writing, and booting. The jumper should be installed when using EPROM boot mode. The
jumper should be removed when using the serial boot or no-boot mode. If
the jumper remains “
ON” in serial boot or no-boot modes, the ~BMS signal
is grounded, and the flash memory is selected.
AD1836 Control Selection Jumper (JP23)
The AD1836 control registers are programmed through an SPI port. The
SPI port can be configured to be connected to the processor’s SPI port or
SPORT1. When the jumper is installed at JP23, the AD1836 SPI port is
connected to
AD1836 SPI port connects to the processor’s SPI port. By default, the
jumper is installed.
SPORT1 of the processor. When the jumper is removed, the
SW1 Enable Jumper (JP26)
The SW1 push button is attached though a driver to FLAG0 of the processor.
To disconnect the driver from
put), remove
JP26.
FLAG0 (for example, to use FLAG1 as an out-
SW2 Enable Jumper (JP27)
The SW2 push button is attached though a driver to FLAG1 of the processor.
To disconnect the driver from (for example, to use
remove
JP27.
2-12ADSP-21161N EZ-KIT Lite Evaluation System Manual
FLAG1 as an output),
Page 53
EZ-KIT Lite Hardware Reference
LEDs and Push Buttons
This section describes the functionality of the LEDs and push buttons.
Figure 2-3 shows the locations of the LEDs and push buttons.
USB Monitor: LED10
VERF: LED9
DSP Reset: LED8
Reset: LED1
Power: LED11
FLAG4-9: LED2 - 7
Reset: SW8
IRQ0-2: SW5-7
FLAG0-3: SW1-4
Figure 2-3. LED and Push Button Locations
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LEDs and Push Buttons
Reset LEDs (LED1 and LED8)
When LED1 is lit, the master reset of all the major ICs is active.
When
LED8 is lit, the ADSP-21161N processor (U1) is being reset. The
USB interface resets the processor during USB communication
initialization.
FLAG LEDs (LED2–7)
The FLAG LEDs connect to the processor’s flag pins (FLAG4–9). The
LEDs are active
Refer to “LEDs and Push Buttons” on page 2-13 for more information on
how to use the programmable flags to program the processor. Table 2-10
shows the FLAG signals and the corresponding LEDs.
Table 2-10. FLAG LEDs
FLAG PinLED Reference Designator
FLAG4LED7
FLAG5LED6
FLAG6LED5
FLAG7LED4
FLAG8LED3
HIGH and are lit by an output of “1” from the processor.
FLAG9LED2
VERF LED (LED9)
The VERF LED indicates that there is a possible error in the audio stream
of the CS8414 digital receiver. The error may occur when digital audio
cables disconnect from the optical or coaxial SPDIF connectors.
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EZ-KIT Lite Hardware Reference
USB Monitor LED (LED10)
The USB monitor LED (LED10) indicates that USB communication has
been initialized successfully, and you may connect to the processor using a
VisualDSP++ EZ-KIT Lite session. If the LED does not light, try cycling
power on the board and/or reinstalling the USB driver (see the Visu-alDSP++ Installation Quick Reference Card).
L
Lite target board, the LED can flicker, indicating communications
handshake.
Power LED (LED11)
When VisualDSP++ is actively communicating with the EZ-KIT
When LED11 is lit (green), it indicates that power is being properly supplied to the board.
Programmable FLAG Push Buttons (SW1–4)
Four push buttons (SW1–4) are provided for general-purpose user input.
The push buttons connect to the processor’s
are active “
HIGH” and, when pressed, send a High (1) to the processor.
Refer to “FLAG Pins” on page 1-9 for more information. The push but-
ton reference designators and corresponding FLAGs are summarized in
Table 2-11.
Table 2-11. FLAG Switches
FLAG PinPush Button Reference
Designator
FLAG PinPush Button Reference
FLAG pins. The push buttons
Designator
FLAG0SW1FLAG2SW3
FLAG1SW2FLAG3SW4
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Connectors
Interrupt Push Buttons (SW5–7)
Three push buttons are provided for general-purpose user interrupts. SW5–
connect to the processor’s programmable FLAG pins. The push but-
SW7
tons are active “
processor. Refer to “FLAG Pins” on page 1-9 for more information. The
push button reference designators and corresponding interrupt signals are
summarized in Table 2-12.
Table 2-12. Interrupt Switches
Interrupt SignalPush Button Reference Designator
IRQ0SW5
IRQ1SW6
IRQ2SW7
HIGH” and, when pressed, send a High (1) to the
Board Reset Push Button (SW8)
The RESET push button (SW8) resets all of the ICs on the board. During
reset, the USB interface is automatically reinitialized.
[
Pressing the RESET push button (SW8) while VisualDSP++ is running disrupts communication and causes errors in the current
debug session. VisualDSP++ must be closed and re-opened.
Connectors
This section describes the connector functionality and provides information about mating connectors. Figure 2-4 shows the connector locations.
USB Connector (P2)
The USB connector (P2) is a standard Type B USB receptacle.
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Figure 2-4. Connector Locations
Part DescriptionManufacturerPart Number
Type B USB receptacleMill-Max897-30-004-90-000
Digi-KeyED90003-ND
Mating Connector (provided with the EZ-KIT Lite)
USB cable AssmannAK672-5
Digi-KeyAK672-5ND
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Connectors
Audio Connectors (P4–8, P17)
There are two 3.5 mm stereo audio jacks, 13 RCA jacks, and one optical
connector.
Part DescriptionManufacturerPart Number
3.5 mm stereo jack (P7 and P17)ShogyoSJ-0359AM-5
RCA Jacks (P6)SWITCHCRAFTPJRAS2X2S01
RCA Jacks (
TORX (P4)TOSHIBATORX173
Coaxial (P5)SWITCHCRAFTPJRAN1X1U01
3.5mm stereo plug to 3.5mm stereo
cable (
Two channel RCA interconnect cable
(
P6 and P8)
Digital Fiber-Optic Cable (P4)Monster CableILS100-1M
Digital Coaxial Cable (P5)Monster CableIDL100-1M
P8)SWITCHCRAFTPJRAS4X2U01
Mating Connectors
Radio ShackL12-2397A
P7 and P17)
Monster CableBI100-1M
External Port Connector (P9)
A 40-pin 0.05' spacing connector provides access to some of the processor’s External Port signals. By default, this connector is not populated.
Part DescriptionManufacturerPart Number
40-pin 0.05’ (male)SamtecFTSH-120-01-F-D-K
Mating Connector
Female to female cable SamtecFFSD-20-D-5.000-01-N
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Host Processor Interface Connector (P10)
A 20-pin 0.05' spacing connector provides access to some of the processor’s External Port signals. By default, this connector is not populated.
Part DescriptionManufacturerPart Number
20-pin 0.05’ (male)SamtecFTSH-110-01-F-D-K
Mating Connector
Female to female cable SamtecFFSD-10-D-5.000-01-N
JTAG Connector (P12)
The JTAG header (P12) is the connecting point for a JTAG in-circuit
emulator pod. When an emulator is connected to the JTAG header, the
USB debug interface is disabled.
Pin 3 is missing to provide keying. Pin 3 in the mating connector should
have a plug.
L
Part DescriptionManufacturerPart Number
14-pin IDC Header (P12)Berg54102-T08-07
When using an emulator with the EZ-KIT Lite board, follow the
connection instructions provided with the emulator.
Link Port Connectors (P13–14)
Each link port is connected to a 26-pin connector. Refer to EE-106 found
on the ADI website at http://www.analog.com for more information
about the link port connectors.
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Connectors
Part DescriptionManufacturerPart Number
26 position connectorHondaRMCA-26JL-AD
Mating Connector
Cable connectorHondaRMCA-E26F1S-A
ShroudHondaRMCA-E26L1A
Coaxial cableGoreDXN2132
SPORT1 and SPORT3 Connector (P15)
SPORT1 and SPORT3 are connected to a 20-pin connector.
Part DescriptionManufacturerPart Number
20 position AMPMODU system 50
receptacle
20 position AMPMODU system 20
connector
20 position AMPMODU system 20
connector (w/o lock)
Flexible film contacts (20 per connector)
AMP104069-1
Mating Connector
AMP2-487937-0
AMP2-487938-0
AMP487547-1
Power Connector (P16)
The power connector (P16) provides all of the power necessary to operate
the EZ-KIT Lite board.
Part DescriptionManufacturerPart Number
2.5 mm Power Jack (
P16)SWITCHCRAFTRAPC712
Digi-KeySC1152-ND
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EZ-KIT Lite Hardware Reference
Part DescriptionManufacturerPart Number
Mating Power Supply (shipped with EZ-KIT Lite)
5V Power SupplyCUI StackDTS070175SUDC-p6-SZ
Specifications
This section provides the requirements for powering the board.
Power Supply
The power connector supplies DC power to the EZ-KIT Lite board.
Table 2-13 shows the power supply specifications.
Table 2-13. Power Supply Specifications
TerminalConnection
Center pin+7V@2 amps
Outer RingGND
Board Current Measurements
The ADSP-21161N EZ-KIT Lite board provides two zero-ohm resistors
that may be removed to measure current draw. Table 2-14 shows the resistor number, the voltage plane, and a description of the components on the
plane.
Table 2-14. Current Measurement Resistors
ResistorVoltage PlaneDescription
R168VDDINTCore Voltage of the processor
R169VDDEXTIO Voltage of the processor
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Specifications
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ABILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website,