Page 1
a
SHARC
Commercial Grade
®
Family DSP Microcomputer
ADSP-21061/ADSP-21061L
SUMMARY
High performance signal processor for communications,
graphics, and imaging applications
Super Harvard Architecture
Four independent buses for dual data fetch, instruction
fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
CORE PROCESSOR
INSTRUCTION
DAG1
8 4 32
DAG2
8 4 24
PM ADDRESS BUS
DM ADDRESS BUS
TIMER
CACHE
32 48-BIT
PROGRAM
SEQUENCER
24
32
Dual data address generators with modulo and bit-reverse
addressing
Efficient program sequencing with zero-overhead looping:
single-cycle loop setup
IEEE JTAG Standard 1149.1 test access port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
240-lead MQFP package, thermally enhanced MQFP, 225-ball
plastic ball grid array (PBGA)
Lead (Pb) free packages. For more information, see Ordering
Guide on Page 53.
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
ADDR DATA ADDR
ADDR DATA
DATA
DATA ADDR
IOD
48
BLOCK 0
IOA
17
BLOCK 1
JTAG
TEST AND
EMULATION
EXTERNAL
PORT
ADDR BUS
MUX
7
32
DATA
REGISTER
FILE
16 40-BIT
PM DATA BUS
BUS
CONNECT
(PX)
MULT
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DM DATA BUS
BARREL
SHIFTER
48
40/32
ALU
S
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
Figure 1. Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
IOP
CONTROLLER
SERIAL PORTS
I/O PROCESSOR
DMA
(2)
MULTIPROCESSOR
INTERFACE
DATA BU S
MUX
HOST PORT
4
6
6
48
Page 2
ADSP-21061/ADSP-21061L
Parallel Computations
Single-cycle multiply and ALU operations in parallel with
dual memory read/write and instruction fetch
Multiply with add and subtract for accelerated FFT butterfly
computation
1M bit On-Chip SRAM
Dual-ported for independent access by core processor and
DMA
Off-Chip Memory Interfacing
4 gigawords addressable
Programmable wait state generation, page-mode DRAM
support
DMA Controller
6 DMA channels for transfers between ADSP-21061 internal
memory and external memory, external peripherals, host
processor, or serial ports
Background DMA transfers at up to 40 MHz, in parallel with
full-speed processor execution
Host Processor Interface to 16- and 32-Bit Microprocessors
Host can directly read/write ADSP-21061 internal memory
Multiprocessing
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus connect
of up to six ADSP-21061s plus host
240 MBps transfer rate over parallel bus
Serial Ports
Two 40 Mbps synchronous serial ports with companding
hardware
Independent transmit and receive functions
Rev. C | Page 2 of 56 | July 2007
Page 3
CONTENTS
ADSP-21061/ADSP-21061L
General Description ................................................. 4
SHARC Family Core Architecture ............................ 4
Memory and I/O Interface Features ........................... 5
Porting Code From the ADSP-21060 or ADSP-21062 .... 8
Development Tools ............................................... 8
Evaluation Kit ...................................................... 9
Designing an Emulator-Compatible DSP
Board (Target) .................................................. 9
Additional Information .......................................... 9
Pin Function Descriptions ........................................ 10
Target Board Connector For EZ-ICE Probe ................ 13
ADSP-21061 Specifications ....................................... 15
Operating Conditions (5 V) .................................... 15
Electrical Characteristics (5 V) ................................ 15
Internal Power Dissipation (5 V) ............................. 16
External Power Dissipation (5 V) ............................. 17
ADSP-21061L Specifications ..................................... 18
Operating Conditions (3.3 V) ................................. 18
Electrical Characteristics (3.3 V) .............................. 18
Internal Power Dissipation (3.3 V) ........................... 19
External Power Dissipation (3.3 V) .......................... 20
Absolute Maximum Ratings ................................... 21
ESD Sensitivity .................................................... 21
Package Marking Information ................................ 21
Timing Specifications ........................................... 21
Test Conditions ................................................... 44
Environmental Conditions ..................................... 47
225-Ball PBGA Pin Configurations ............................. 48
240-Lead MQFP Pin Configurations ............................ 50
Outline Dimensions ................................................ 51
Surface-Mount Design .......................................... 53
Ordering Guide ...................................................... 53
REVISION HISTORY
7/07—Rev B to Rev C
Added
Porting Code From the ADSP-21060 or ADSP-21062 ....... 8
Added several new lead (Pb) free models. See
Ordering Guide ......................................................53
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for
33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The
product name“ADSP-21061” is used throughout this data sheet
to represent all devices, except where expressly noted.
Rev. C | Page 3 of 56 | July 2007
Page 4
ADSP-21061/ADSP-21061L
GENERAL DESCRIPTION
The ADSP-21061 SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21061
SHARC is a 32-bit processor optimized for high performance
DSP applications. The ADSP-21061 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dualported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 1 shows performance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC represents a new standard of integration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features including 1M bit SRAM memory, a host processor
interface, a DMA controller, serial ports, and parallel bus connectivity for glueless DSP multiprocessing.
Table 1. Benchmarks (at 50 MHz)
Benchmark Algorithm Speed Cycles
1024 Point Complex FFT (Radix 4,
.37 ms 18,221
with reversal)
FIR Filter (per tap) 20 ns 1
IIR Filter (per biquad) 80 ns 4
Divide (y/x) 120 ns 6
Inverse Square Root 180 ns 9
DMA Transfer Rate 300M Bps
The ADSP-21061 continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1, illustrates the following architectural features:
• Computation units (ALU, multiplier, and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
•Interval timer
•On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor interface
• DMA controller
•Serial ports
• JTAG test access port
ADSP-21061
1 ⫻ CLOCK
TO GND
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
3
4
CLKIN
EBOOT
LBOOT
IRQ
2–0
FLAG
3–0
TIMEXP
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
RPBA
ID
2–0
RESET JTAG
BMS
ADDR
DATA
ACK
MS
PAGE
SBTS
ADRCLK
DMAR
DMAG
HBR
HBG
REDY
BR
31–0
47–0
RD
WR
3–0
SW
1–2
1–2
CS
1–6
CPA
7
L
O
R
T
N
O
C
CS
BOOT
EPROM
ADDR
(OPTIONAL)
DATA
ADDR
MEMORY-
DATA
MAPPED
OE
DEVICES
WE
(OPTIONAL)
ACK
CS
S
S
A
E
T
R
D
D
A
A
D
DATA
DMA DEVICE
(OPTIONAL)
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
HOST
Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 processors
are code- and function-compatible with the ADSP-21020,
ADSP-21060, and ADSP-21062 SHARC processors.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all perform single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit singleprecision floating-point, extended-precision 40-bit floatingpoint, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for storing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Rev. C | Page 4 of 56 | July 2007
Page 5
ADSP-21061/ADSP-21061L
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(Figure 1 on Page 1). With its separate program and data mem-
ory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.
Instruction Cache
The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21061’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21061 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21061 can conditionally execute a multiply, an add, a
subtract, and a branch, all in a single instruction.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-21061 processors add the following architectural
features to the SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21061 contains one megabit of on-chip SRAM, organized as two blocks of 0.5M bits each. Each bank has eight 16-bit
columns with 4k 16-bit words per column. Each memory block
is dual-ported for single-cycle, independent accesses by the core
processor and I/O processor or DMA controller. The dualported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 memory map).
On the ADSP-21061, the memory can be configured as a maximum of 32k words of 32-bit data, 64k words for 16-bit data, 16k
words of 48-bit instructions (and 40-bit data) or combinations
of different word sizes up to 1 megabit. All the memory can be
accessed as 16-bit, 32-bit, or 48-bit.
A 16-bit floating-point storage format is supported, which effectively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-21061’s external port.
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s interface to off-chip memory and peripherals. The 4-gigaword offchip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program memory, data memory, and I/O—are multiplexed at the external port
to create an external system bus with a single 32-bit address bus
and a single 48-bit (or 32-bit) data bus. The on-chip Super Harvard Architecture provides three-bus performance, while the
off-chip unified address space gives flexibility to the designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold, and disable time
requirements.
Host Processor Interface
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s external port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
), host bus grant (HBG), and
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zerooverhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
Rev. C | Page 5 of 56 | July 2007
Page 6
ADSP-21061/ADSP-21061L
CLKIN
RESET
RPBA
3
ID2–0
011
ADSP-2 1061 #6
ADSP-2 1061 #5
ADSP-2 1061 #4
ADSP-21061 #3
ADDR31–0
DATA47–0
CONTROL
L
S
S
O
R
T
N
O
C
A
E
T
R
A
D
D
D
A
RESET
CLOCK
010
001
BUS
PRIORITY
CLKIN
RESET
RPBA
3
ID2–0
CLKIN
RESET
RPBA
3
ID2–0
BR1–2, BR4–6
ADSP-21061 #2
ADDR31–0
DATA47–0
CONTROL
BR1, BR3–6
ADSP-21061 #1
ADDR31–0
DATA47–0
L
O
MS3–0
R
T
N
O
C
PAGE
SBTS
REDY
BR2–6
BR3
CPA
BR2
RDx
WRx
ACK
BMS
HBR
HBG
CPA
BR1
CS
5
5
L
S
S
O
R
T
N
O
C
5
A
E
T
R
A
D
D
D
A
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
ADDR
DATA
GLOBAL MEMORY
AND
PERIPHERAL (O PTIONAL)
BOOT EPROM (OPTIONAL)
HOSTPROCESSOR
INTERFACE (O PTIONAL)
Figure 3. Shared Memory Multiprocessing System
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.
Rev. C | Page 6 of 56 | July 2007
DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32, or 48-bit words is performed during DMA transfers.
Page 7
ADSP-21061/ADSP-21061L
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA request/grant lines
(DMAR
, DMAG
1–2
). Other DMA features include interrupt
1–2
generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
Serial Ports
The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maximum data rate of 40 Mbps. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
ADDRESS
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally generated. The serial ports also include keyword and key mask
features to enhance interprocessor communication.
Multiprocessing
The ADSP-21061 offers powerful features tailored to multiprocessor DSP systems. The unified address space (see Figure 4)
allows direct interprocessor accesses of each ADSP-21061’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-21061s and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock allows
indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 500 Mbps
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21061s and can be used to
implement reflective semaphores.
ADDRESS
INTERNAL
MEMORY
SPACE
MULTIPROCESSOR
MEMOR Y
SPACE
IOP REGISTERS
NORMAL WORD ADDRESSING
(32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS)
SHORT WORD ADDRESSING
(16-BIT DATA WORDS)
INTERNAL MEMORY SPACE
WITH ID = 001
INTERNAL MEMORY SPACE
WITH ID = 010
INTERNAL MEMORY SPACE
WITH ID = 011
INTERNAL MEMORY SPACE
WITH ID = 100
INTERNAL MEMORY SPACE
WITH ID = 101
INTERNAL MEMORY SPACE
WITH ID = 110
BROADCASTWRITE
TO ALL ADSP-21061s
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0012 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
EXTERNAL
MEMORY
SPACE
BANK 0
SDRAM
(OPTIONAL)
BANK 1
BANK 2
BANK 3
NONBANKED
0x0040 0000
MS0
MS1
MS2
MS3
Figure 4. Memory Map
Rev. C | Page 7 of 56 | July 2007
0x0FFF FFFF
NOTE: BANK SIZES ARE SELECTED BY
MSIZE BITS OF THE SYSCON REGISTER
Page 8
ADSP-21061/ADSP-21061L
Program Booting
The internal memory of the ADSP-21061 can be booted at system power-up from either an 8-bit EPROM, or a host processor.
Selection of the boot source is controlled by the BMS
(boot
memory select), EBOOT (EPROM boot), and LBOOT (host
boot) pins. 32-bit and 16-bit host processors can be used for
booting.
PORTING CODE FROM THE ADSP-21060 OR ADSP-21062
The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the link port pins of the ADSP-21060/
ADSP-21062 are no-connects.
The ADSP-21061 is object code compatible with the
ADSP-21060/ADSP-21062 processors except for the folowing
functional elements:
• The ADSP-21061 memory is organized into two blocks
with eight columns that are 4k deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per
block.
• Link port functions are not available.
• Handshake external port DMA pins DMAR2 and DMAG2
are assigned to external port DMA Channel 6 instead of
Channel 8.
• 2-D DMA capability of the SPORT is not available.
• The modify registers in SPORT DMA are not
programmable.
On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the
ADSP- 21061—these addresses will alias into the actual Block 1
of each processor.
If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8k of instructions
or up to 16k of data in each bank of the ADSP-21062, or any
combination of instructions or data that does not exceed the
memory bank.
DEVELOPMENT TOOLS
The ADSP-21061 is supported by a complete set of
CROSSCORE
Devices emulators and VisualDSP++
ment. The same emulator hardware that supports other SHARC
processors also fully emulates the ADSP-21061.
†
CROSSCORE is a registered trademark of Analog Devices, Inc.
‡
VisualDSP++ is a registered trademark of Analog Devices, Inc.
®
†
software development tools, including Analog
®
‡
development environ-
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21061
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-21061
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits programmers
to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tools’
command line switches
The VisualDSP++ kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
Rev. C | Page 8 of 56 | July 2007
Page 9
ADSP-21061/ADSP-21061L
eliminating the need to start from the very beginning when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, and examine run-time stack and heap usage. The
expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphical and textual environments.
In addition to the software development tools available from
Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Third-party software
tools include DSP libraries, real-time operating systems, and
block diagram design tools.
EVALUATION KIT
®
Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a
standalone unit, without being connected to the PC.
†
evaluation plat-
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any
custom-defined system. Connecting an Analog Devices JTAG
emulator to the EZ-KIT Lite board enables high speed, nonintrusive emulation.
DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21061
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer
to the ADSP-21061 SHARC User’s Manual, Revision 2.1.
†
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
Rev. C | Page 9 of 56 | July 2007
Page 10
ADSP-21061/ADSP-21061L
PIN FUNCTION DESCRIPTIONS
ADSP-21061 pin definitions are listed below. All pins are identical on the ADSP-21061 and ADSP-21061L. Inputs identified as
synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST
).
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DATA47-0, FLAG3-0, SW
internal pull-up or pull-down resistors (CPA
, and inputs that have
, ACK, DTx, DRx,
TCLKx, RCLKx, TMS, and TDI)—these pins can be left floating. These pins have a logic-level hold circuit that prevents the
input from floating internally.
Table 2. Pin Descriptions
Pin Type Function
ADDR
31–0
DATA
47–0
MS
3–0
RD
WR
PAG E O /T DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page boundary
ADRCLK O/T Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.
SW
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS
I/O/T External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system the bus master outputs addresses for read/write of the internal memory or
IOP registers of other ADSP-21061s. The ADSP-21061 inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
I/O/T External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins. 32-bit single-
precision floating-point data and 32-bit fixed-point data is transferred over Bits 47 to 16 of the bus. 40-bit
extended-precision floating-point data is transferred over Bits 47 to 8 of the bus. 16-bit short word data is
transferred over Bits 31 to 16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23 to 16. Pullup resistors on unused DATA pins are not necessary.
O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external
memory. Memory bank size must be defined in the ADSP-21061’s system control register (SYSCON). The
lines are decoded memory address lines that change at the same time as the other address lines.
MS
3–0
When no external memory access is occurring the MS
conditional memory access instruction is executed, whether or not the condition is true. MS
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS
lines are output by the bus master.
I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external memory devices
or from the internal memory of other ADSP-21061s. External devices (including other ADSP-21061s) must
assert RD
bus master and is input by all other ADSP-21061s.
I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory devices
or to the internal memory of other ADSP-21061s. External devices must assert WR to write to the
ADSP-21061’s internal memory. In a multiprocessing system WR
all other ADSP-21061s.
has been crossed. DRAM page size must be defined in the ADSP-21061’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for
Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
I/O/T Synchronous Write Select. This signal is used to interface the ADSP-21061 to synchronous memory devices
(including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indication of an
impending write cycle, which can be aborted if WR
instruction). In a multiprocessing system, SW
ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the same
time as the address output. A host processor using synchronous writes must assert this pin when writing to
the ADSP-21061(s).
is asserted, or when the ADSP-21061 is a bus slave)
to read from the ADSP-21061’s internal memory. In a multiprocessing system RD is output by the
is output by the bus master and is input by all other
lines are inactive; they are active however when a
3–0
is output by the bus master and is input by
is not later asserted (e.g., in a conditional write
can be used
0
3–0
Rev. C | Page 10 of 56 | July 2007
Page 11
ADSP-21061/ADSP-21061L
Table 2. Pin Descriptions (Continued)
Pin Type Function
ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21061 deasserts ACK as an output to add wait states to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-21061 deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
SBTS
IRQ
2–0
FLAG
3–0
TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
HBR
HBG
CS
REDY O (O/D) Host Bus Acknowledge. The ADSP-21061 deasserts REDY (low) to add wait states to an asynchronous access
DMAR
2–1
DMAG
2–1
BR
6–1
ID2–0
RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
CPA
DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,
selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061 attempts to access
external memory while SBTS is asserted, the processor halts and the memory access is not complete until
is deasserted. SBTS should only be used to recover from host processor/ADSP-21061 deadlock, or used
SBTS
with a DRAM controller.
I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as
a condition. As an output, they can be used to signal external peripherals.
I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-21061’s
external bus. When HBR
is asserted in a multiprocessing system, the ADSP-21061 that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address, data, select,
and strobe lines in a high impedance state. HBR
has priority over all ADSP-21061 bus requests BR
6–1
in a
multiprocessing system.
I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the
external bus. HBG is asser ted (held low) by the ADSP-21061 until HBR is released. In a multiprocessing system,
is output by the ADSP-21061 bus master and is monitored by all others.
HBG
I/A Chip Select. Asserted by host processor to select the ADSP-21061.
of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if
and HBR inputs are asserted.
the CS
I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 6).
O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 6).
I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061 processors to arbitrate for bus
mastership. An ADSP-21061 only drives its own BR
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BR
x line (corresponding to the value of its ID2-0 inputs) and
x pins should
be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.
O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-21061.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc., ID = 000 in single-processor systems. These
lines are a system configuration selection which should be hardwired or changed at reset only.
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection which must be set to the same value on every ADSP-21061. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave to interrupt
background DMA transfers and gain access to the external bus. CPA
connected to all ADSP-21061s in the system. The CPA
pin has an internal 5 kΩ pull-up resistor. If core access
is an open-drain output that is
priority is not required in a system, the CPA pin should be left unconnected.
Rev. C | Page 11 of 56 | July 2007
Page 12
ADSP-21061/ADSP-21061L
Table 2. Pin Descriptions (Continued)
Pin Type Function
TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM.
When EBOOT is low, the LBOOT and BMS
description below. This signal is a system configuration selection that should be hardwired.
LBOOT I Link Boot. Must be tied to GND.
BMS
CLKIN I Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may
RESET
TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
EMU
ICSA O Reserved. Leave unconnected.
VDD P Power Supply. Nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins)
GND G Power Supply Return. (30 pins)
NC Do Not Connect. Reserved pins which must be left open and unconnected.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS
I/O/T* Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS
booting will occur and that ADSP-21061 will begin executing instructions from external memory. See table
below. This input is a system configuration selection that should be hardwired. *Three-statable only in
EPROM boot mode (when BMS
EBOOT LBOOT BMS Booting Mode
1 0 Output EPROM (Connect BMS
0 0 1(Input) Host Processor.
0 0 0 (Input) No Booting. Processor executes from external memory.
not be halted, changed, or operated below the minimum specified frequency.
I/A Processor Reset. Resets the ADSP-21061 to a known state and begins program execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
resistor.
I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-21061. TRST has a 20 kΩ internal pull-up resistor.
O Emulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only. EMU has a
50 kΩ internal pull-up resistor.
is asserted, or when the ADSP-21061 is a bus slave)
is an output).
inputs determine booting mode. See the table in the BMS pin
is output by the bus master. Input: When low, indicates that no
to EPROM chip select.)
Rev. C | Page 12 of 56 | July 2007
Page 13
ADSP-21061/ADSP-21061L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x’s CLKIN, TMS, TCK, TDI, TDO, and
GND signals be made accessible on the target system via a
14-pin connector (a 2-row, 7-pin strip header) such as that
shown in Figure 5. The EZ-ICE probe plugs directly onto this
connector for chip-on-board emulation. You must add this connector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZICE connector and the farthest device sharing the EZ-ICE JTAG
pin should be limited to 15 inches maximum for guaranteed
operation. This length restriction must include EZ-ICE JTAG
signals that are routed to one or more ADSP-2106x devices, or a
combination of ADSP-2106x devices and other JTAG devices
on the chain.
12
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator
3 4
56
7 8
910
11 12
BTDI
13 14
GND
TOP VIE W
(Jumpers in Place)
9
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location—Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inches in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST
, and BTDI signals are provided so that the test access
port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 5. If you are not going to use the test access port for
board testing, tie BTRST
V
. The TRST pin must be asserted (pulsed low) after power-
DD
up (through BTRST
to GND and tie or pull up BTCK to
on the connector) or held low for proper
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.
EMU
GND
TMS
TCK
TRST
TDI
TDO
The JTAG signals are terminated on the EZ-ICE probe as shown
in Table 3.
Table 3. Core Instruction Rate/CLKIN Ratio Selection
Signal Termination
TMS Driven Through 22 Ω Resistor (16 mA Driver)
TCK Driven at 10 MHz Through 22 Ω Resistor (16 mA
Driver)
1
TRST
Active Low Driven Through 22 Ω Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
TDI Driven by 22 Ω Resistor (16 mA Driver)
TDO One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU
Active Low, 4.7 kΩ Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
1
TRST is driven low until the EZ-ICE probe is turned on by the emulator at software
startup. After software startup, is driven high.
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform operations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple processors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-21061 processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between processors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU
should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-21061s (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See
Figure 7 below and “JTAG Clock Tree” and “Clock Distribu-
tion” in the “High Frequency Design Considerations” section of
the ADSP-21061 SHARC User’s Manual, Revision 2.1.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU,
and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.
Rev. C | Page 13 of 56 | July 2007
Page 14
ADSP-21061/ADSP-21061L
OTHER
JTAG
CONTROLLER
JTAG
DEVICE
(OPTIONAL)
TDI
K
C
T
TDO TDO
T
S
S
M
R
T
T
EZ-ICE
JTAG
CONNECTOR
EMU
TRST
CLKIN
TDI
TCK
TMS
TDO
ADSP-2106x
TDI
K
C
T
OPTIONAL
#1
TDO
T
U
S
S
M
R
M
T
T
E
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems
TDI TDO TDI TDO
5k⍀
*
TDI TDO
TDI TDO
TDI TDO
TDI TDO
ADSP-2106x
TDI
K
C
M
T
T
n
T
U
S
S
M
R
E
T
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
5k⍀
*
*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e,
EMU
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
SYSTEM
CLKIN
Rev. C | Page 14 of 56 | July 2007
Page 15
ADSP-21061/ADSP-21061L
ADSP-21061 SPECIFICATIONS
OPERATING CONDITIONS (5 V)
K Grade
Parameter Description Min Max Unit
V
DD
T
CASE
1
V
1
IH
2
2
V
IH
2
1,
V
IL
1
Applies to input and bidirectional pins: DATA
TFS1, RFS0, RFS1, EBOOT, BMS
2
Applies to input pins: CLKIN, RESET, TRST.
Supply Voltage 4.75 5.25 V
Case Operating Temperature 0 85 °C
High Level Input Voltage @ VDD = Max 2.0 VDD + 0.5 V
High Level Input Voltage @ VDD = Max 2.2 VDD + 0.5 V
Low Level Input Voltage @ VDD = Min –0.5 +0.8 V
, ADDR
, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
47–0
, RD, WR, SW , ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR
31–0
6–1
, ID
2–0
, RPBA, CPA, TFS0,
ELECTRICAL CHARACTERISTICS (5 V)
Parameter Description Test Conditions Min Max Unit
1, 2
V
OH
1, 2
V
OL
3, 4
I
IH
3
I
IL
4
I
ILP
5, 6, 7, 8
I
OZH
5
I
OZL
I
OZHP
7
I
OZLC
9
I
OZLA
8
I
OZLAR
6
I
OZLS
10, 11
C
IN
1
Applies to output and bidirectional pins: DATA
BR
, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.
6–1
2
See “Output Drive Currents” for typical drive current capabilities.
3
Applies to input pins: ACK, SBTS, IRQ
4
Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI, EMU.
5
Applies to three-statable pins: DATA
TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
mastership.)
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to CPA pin.
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
is not requesting bus mastership).
9
Applies to ACK pin when keeper latch enabled.
10
Applies to all signal pins.
11
Guaranteed but not tested.
High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 4.1 V
Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V
High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 150 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA
Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 150 μA
Input Capacitance fIN = 1 MHz, T
, ADDR
47-0
, HBR, CS, DMAR1, DMAR2, ID
2–0
47–0
, ADDR
31–0
, MS
, 3-0, MS
31-0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
3–0
, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
2–0
= 25°C, VIN = 2.5 V 4.7 pF
CASE
, HBG, REDY, DMAG1, DMAG2, BMS, BR
3–0
= 001 and another ADSP-21061 is not requesting bus
2–0
= 001 and another ADSP-21061L
2–0
6–1
, TFSx, RFSx,
Rev. C | Page 15 of 56 | July 2007
Page 16
ADSP-21061/ADSP-21061L
INTERNAL POWER DISSIPATION (5 V)
These specifications apply to the internal power portion of VDD
only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For
Operation Peak Activity (I
a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation
Measurements.”
Specifications are based on the operating scenarios:
) High Activity (I
DDINPEAK
) Low Activity (I
DDINHIGH
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your program spends in that state:
%PEAK I
%IDLE I
DDINPEAK
DDIDLE
+ %HIGH I
DDINHIGH
= power consumption
+ %LOW I
DDINLOW
+
Parameter Test Conditions Max Unit
4
5
DDINPEAK
1
tCK = 30 ns, VDD = Max
= 25 ns, VDD = Max
t
CK
tCK = 20 ns, VDD = Max
2
tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max
tCK = 20 ns, VDD = Max
3
tCK = 30 ns, VDD = Max
= 25 ns, VDD = Max
t
CK
tCK = 20 ns, VDD = Max
VDD = Max
VDD = Max
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
is a composite average based on a range of low activity code.
DDINLOW
595
680
850
460
540
670
270
320
390
200
55
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
I
I
1
The test program used to measure I
2
I
3
I
4
Idle denotes ADSP-21061L state during execution of IDLE instruction.
5
Idle16 denotes ADSP-2106x state during execution of IDLE16 instruction.
Supply Current (Internal)
DDINPEAK
Supply Current (Internal)
DDINHIGH
Supply Current (Internal)
DDINLOW
Supply Current (Idle)
DDIDLE
Supply Current (Idle16)
DDIDLE
measurements made using typical applications are less than specified.
is a composite average based on a range of high activity code. I
DDINHIGH
is a composite average based on a range of low activity code.
DDINLOW
DDINLOW
)
Rev. C | Page 16 of 56 | July 2007
Page 17
ADSP-21061/ADSP-21061L
EXTERNAL POWER DISSIPATION (5 V)
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
P
= I
INT
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
—the number of output pins that switch during each cycle
(O)
—the maximum frequency at which they can switch (f)
—their load capacitance (C)
—their voltage swing (V
and is calculated by:
PEXT = O
DDIN
× V
DD
×
C × V
DD
)
DD
2
× f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t
). The write
CK
strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t
Example: Estimate P
), but selects can switch on each cycle.
CK
with the following assumptions:
EXT
• A system with one bank of external data memory RAM
(32-bit)
• Four 128k × 8 RAM chips are used, each with a load of
10 pF
• External data memory writes occur every other cycle, a rate
of 1/(4t
• The instruction cycle rate is 40 MHz (t
The P
EXT
), with 50% of the pins switching
CK
= 25 ns)
CK
equation is calculated for each class of pins that can
drive:
Table 4. External Power Calculations
Pin Type No. of Pins % Switching × C × f × V
DD
2
= P
EXT
Address 15 50 × 44.7 pF × 10 MHz × 25 V = 0.084 W
MS0
WR
10 × 44.7 pF × 10 MHz × 25 V = 0.000 W
1— × 44.7 pF × 20 MHz × 25 V = 0.022 W
Data 32 50 × 14.7 pF × 10 MHz × 25 V = 0.059 W
ADDRCLK 1 — × 4.7 pF × 20 MHz × 25 V = 0.002 W
P
= 0.167 W
EXT
. Select pins
CK
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
= P
TOTAL
EXT
+ (I
Note that the conditions causing a worst-case P
from those causing a worst-case P
DDIN2
× 5.0 V)
. Maximum P
INT
are different
EXT
cannot
INT
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Rev. C | Page 17 of 56 | July 2007
Page 18
ADSP-21061/ADSP-21061L
ADSP-21061L SPECIFICATIONS
OPERATING CONDITIONS (3.3 V)
A Grade K Grade
Parameter Description Min Max Min Max Unit
V
DD
T
CASE
1
V
1
IH
2
2
V
IH
2
1,
V
IL
1
Applies to input and bidirectional pins: DATA
TFS1, RFS0, RFS1, EBOOT, BMS
2
Applies to input pins: CLKIN, RESET, TRST
Supply Voltage 3.15 3.45 3.15 3.45 V
Case Operating Temperature –40 +85 0 +85 °C
High Level Input Voltage @ VDD = Max 2.0 VDD + 0.5 2.0 VDD + 0.5 V
High Level Input Voltage @ VDD = Max 2.2 VDD + 0.5 2.2 VDD + 0.5 V
Low Level Input Voltage @ VDD = Min –0.5 +0.8 –0.5 +0.8 V
, ADDR
, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1
47–0
, RD, WR, SW , ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR
31–0
6–1
, ID
2–0
, RPBA, CPA, TFS0,
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter Description Test Conditions Min Max Unit
1,2
V
OH
1, 2
V
OL
3, 4
I
IH
3
I
IL
4
I
ILP
5, 6, 7, 8
I
OZH
5
I
OZL
I
OZHP
7
I
OZLC
9
I
OZLA
8
I
OZLAR
6
I
OZLS
10, 11
C
IN
1
Applies to output and bidirectional pins: DATA
BR
, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.
6–1
2
See “Output Drive Currents” for typical drive current capabilities.
3
Applies to input pins: ACK, SBTS, IRQ
4
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI, EMU.
5
Applies to three-statable pins: DATA
TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
mastership.)
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to CPA pin.
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
is not requesting bus mastership).
9
Applies to ACK pin when keeper latch enabled.
10
Applies to all signal pins.
11
Guaranteed but not tested.
High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 2.4 V
Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V
High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 150 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA
Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 150 μA
Input Capacitance fIN = 1 MHz, T
, ADDR
47–0
, HBR, CS, DMAR1, DMAR2, ID
2–0
47–0
, ADDR
31–0
, MS
, 3-0, MS
31–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
3–0
, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
2–0
= 25°C, VIN = 2.5 V 4.7 pF
CASE
, HBG, REDY, DMAG1, DMAG2, BMS, BR
3–0
= 001 and another ADSP-21061 is not requesting bus
2–0
= 001 and another ADSP-21061L
2–0
, TFSx, RFSx,
6–1
Rev. C | Page 18 of 56 | July 2007
Page 19
ADSP-21061/ADSP-21061L
INTERNAL POWER DISSIPATION (3.3 V)
These specifications apply to the internal power portion of VDD
only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For
Operation Peak Activity (I
a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation
Measurements.”
Specifications are based on the operating scenarios:
) High Activity (I
DDINPEAK
) Low Activity (I
DDINHIGH
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your program spends in that state:
%PEAK I
= power consumption
I
DDIDLE
DDINPEAK
+ %HIGH I
DDINHIGH
+ %LOW I
DDINLOW
+ %IDLE
Parameter Test Conditions Max Unit
4
5
DDINPEAK
1
2
3
tCK = 25 ns, VDD = Max
= 22.5 ns, VDD = Max
t
CK
tCK = 25 ns, VDD = Max
= 22.5 ns, VDD = Max
t
CK
tCK = 25 ns, VDD = Max
tCK = 22.5 ns, VDD = Max
VDD = Max
VDD = Max
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
is a composite average based on a range of low activity code.
DDINLOW
480
535
380
425
220
245
180
50
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
I
I
1
The test program used to measure I
2
I
3
IDDINLOW
4
Idle denotes ADSP-21061L state during execution of IDLE instruction.
5
Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction.
Supply Current (Internal)
DDINPEAK
Supply Current (Internal)
DDINHIGH
Supply Current (Internal)
DDINLOW
Supply Current (Idle)
DDIDLE
Supply Current (Idle)
DDIDLE
measurements made using typical applications are less than specified.
is a composite average based on a range of high activity code. I
DDINHIGH
is a composite average based on a range of low activity code.
DDINLOW
)
Rev. C | Page 19 of 56 | July 2007
Page 20
ADSP-21061/ADSP-21061L
EXTERNAL POWER DISSIPATION (3.3 V)
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
P
= I
INT
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
—the number of output pins that switch during each cycle
(O)
—the maximum frequency at which they can switch (f)
—their load capacitance (C)
—their voltage swing (V
and is calculated by:
PEXT = O
DDIN
× V
DD
×
C × V
DD
)
DD
2
× f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t
strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t
Example: Estimate P
), but selects can switch on each cycle.
CK
with the following assumptions:
EXT
). The write
CK
CK
• A system with one bank of external data memory RAM
(32-bit)
• Four 128k × 8 RAM chips are used, each with a load of
10 pF
• External data memory writes occur every other cycle, a rate
of 1/(4t
• The instruction cycle rate is 40 MHz (t
The P
EXT
), with 50% of the pins switching
CK
= 25 ns)
CK
equation is calculated for each class of pins that can
drive:
Table 5. External Power Calculations
Pin Type No. of Pins % Switching × C × f × V
DD
2
= P
EXT
Address 15 50 × 44.7 pF × 10 MHz × 10.9 V = 0.037 W
MS0
WR
10 × 44.7 pF × 10 MHz × 10.9 V = 0.000 W
1— × 44.7 pF × 20 MHz × 10.9 V = 0.010 W
Data 32 50 × 14.7 pF × 10 MHz × 10.9 V = 0.026 W
ADDRCLK 1 — × 4.7 pF × 20 MHz × 10.9 V = 0.001 W
P
= 0.074 W
EXT
. Select pins
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
= P
TOTAL
EXT
+ (I
Note that the conditions causing a worst-case P
from those causing a worst-case P
DDIN2
× 5.0 V)
. Maximum P
INT
are different
EXT
cannot
INT
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Rev. C | Page 20 of 56 | July 2007
Page 21
ADSP-21061/ADSP-21061L
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
Parameter 5 V 3.3 V
Supply Voltage (V
) –0.3 V to +7.0 V –0.3 V to +4.6 V
DD
Input Voltage –0.5 V to V
Output Voltage Swing –0.5 V to V
Load Capacitance 200 pF 200 pF
Storage Temperature Range –65°C to +150°C–65°C to +150°C
Lead Temperature (5 seconds) 280°C280°C
Junction Temperature Under Bias 130°C130°C
than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
+0.5 V –0.5 V to V
DD
+0.5 V –0.5 V to V
DD
DD
DD
+0.5 V
+0.5 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
PACKAGE MARKING INFORMATION
The information presented in Figure 8 provides details about
the package branding for the ADSP-21061 processor. For a
complete listing of product availability, see Ordering Guide on
Page 53.
a
ADSP-21061
tppZccc
vvvvvv.x n.n
yyww count ry_of_ori gin
S
Figure 8. Typical Package Marking (Actual Marking Format May Vary)
Table 6. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z Lead Free Option
ccc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
TIMING SPECIFICATIONS
The timing specifications shown are based on a CLKIN frequency of 40 MHz (t
calculation of timing specifications within the min to max range
of the t
specification (see Table 7). DT is the difference
CK
between the derated CLKIN period (t
25 ns:
DT = t
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
For voltage reference levels, see Figure 29 under Test
Conditions.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
= 25 ns). The DT derating enables the
CK
) and a CLKIN period of
CK
– 25 ns
CK
Rev. C | Page 21 of 56 | July 2007
Page 22
ADSP-21061/ADSP-21061L
Clock Input
Table 7. Clock Input
Parameter
Timing Requirements
t
t
t
t
CLKIN Period 20 100 22.5 100 25 100 30 100 ns
CK
CLKIN Width Low 7777ns
CKL
CLKIN Width High 5555ns
CKH
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 ns
CKRF
CLKIN
ADSP-21061
50 MHz, 5 V
t
CKH
Figure 9. Clock Input
ADSP-21061L
44 MHz, 3.3 V
t
CK
t
CKL
ADSP-21061/
ADSP-21061L
40 MHz,
5 V and 3.3 V
ADSP-21061
33 MHz, 5 V
UnitMin Max Min Max Min Max Min Max
Reset
Table 8. Reset
5 V and 3.3 V
Parameter Min Max
Unit
Timing Requirements
t
WRST
t
SRST
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including startup time of external clock oscillator).
2
Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
RESET Pulse Width Low
RESET Setup Before CLKIN High
CLKIN
RESET
1
2
Figure 10. Reset
4t
CK
14 + DT/2 t
t
WRST
t
SRST
ns
CK
ns
Rev. C | Page 22 of 56 | July 2007
Page 23
ADSP-21061/ADSP-21061L
Interrupts
Table 9. Interrupts
5 V and 3.3 V
Parameter Min Max
Timing Requirements
t
SIR
t
HIR
t
IPW
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t
IRQ2–0 Setup Before CLKIN High
IRQ2–0 Hold Before CLKIN High
IRQ2–0 Pulsewidth
and t
SIR
requirements are not met.
HIR
2
CLKIN
IRQ2–0
1
1
Figure 11. Interrupts
18 + 3DT/4 ns
12 + 3DT/4 ns
2+t
CK
t
SIR
t
HIR
t
IPW
Unit
ns
Tim er
Table 10. Timer
5 V and 3.3 V
Parameter Min Max
Switching Characteristic
t
DTEX
CLKIN
TIMEXP
CLKIN High to TIMEXP 15 ns
t
DTEX
Figure 12. Timer
t
Unit
DTEX
Rev. C | Page 23 of 56 | July 2007
Page 24
ADSP-21061/ADSP-21061L
Flags
Table 11. Flags
5 V and 3.3 V
Parameter Min Max
Timing Requirements
t
SFI
t
HFI
t
DWRFI
t
HFIWR
FLAG3–0 IN Setup Before CLKIN High
FLAG3–0 IN Hold After CLKIN High
FLAG3–0 IN Delay After RD/WR Low
FLAG3–0 IN Hold After RD/WR Deasserted
Switching Characteristics
t
DFO
t
HFO
t
DFOE
t
DFOD
1
Flag inputs meeting these setup and hold times for Instruction Cycle N will affect conditional instructions in Instruction Cycle N+2.
FLAG3–0
FLAG3–0 OUT Delay After CLKIN High 16 ns
FLAG3–0 OUT Hold After CLKIN High 4 ns
CLKIN High to FLAG3–0 OUT Enable 3 ns
CLKIN High to FLAG3–0 OUT Disable 14 ns
CLKIN
t
DFOE
OUT
1
1
1
1
t
DFO
t
HFO
FLAG OUTPUT
8 + 5DT/16 ns
0 – 5DT/16 ns
5 + 7DT/16 ns
0ns
t
DFO
t
DFOD
Unit
CLKIN
FLAG3–0
RD WR
t
SFI
IN
t
DWRFI
FLAG INPU T
t
HFI
t
HFIWR
Figure 13. Flags
Rev. C | Page 24 of 56 | July 2007
Page 25
ADSP-21061/ADSP-21061L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD
DMAGx
strobe timin g parameters only applies to asynchronous
access mode.
Table 12. Memory Read—Bus Master
5 V and 3.3 V
Parameter Min Max
Timing Requirements
t
DAD
t
DRLD
t
HDA
t
HDRH
t
DAAK
t
DSAK
Address, Selects Delay to Data Valid1,
RD Low to Data Valid
1
Data Hold from Address, Selects
Data Hold from RD High
3
ACK Delay from Address, Selects2,
ACK Delay from RD Low
4
2
18 + DT+ W ns
12 + 5DT/8 + W ns
3
0.5 ns
2.0 ns
4
15 + 7DT/8 + W ns
8 + DT/2 + W ns
Switching Characteristics
t
DRHA
t
DARL
t
RW
t
RWR
t
SADADC
W = (number of wait states specified in WAIT register) ⴛ t
HI = t
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
CK
H = t
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
CK
1
Data delay/setup: user must meet t
2
The falling edge of MSx, SW, BMS is referenced.
3
Data hold: user must meet t
and dc loads.
4
ACK delay/setup: user must meet t
for assertion of ACK (High).
Address, Selects Hold After RD High 0+H ns
Address, Selects to RD Low
2
2 + 3DT/8 ns
RD Pulse Width 12.5 + 5DT/8 + W ns
RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI ns
SSDATI
CK
2
0 + DT/4 ns
.
.
(Table 13 on Page 26) for deassertion of ACK (Low), all three specifications must be met
SACKC
Address, Selects Setup Before ADRCLK High
or t
or synchronous spec t
DRLD
or synchronous spec t
or t
or synchronous specification t
DSAK
. See Example System Hold Time Calculation on Page 44 for the calculation of hold times given capacitive
HSDATI
HDA
or t
DAD
HDRH
DAAK
, WR, and
Unit
ADDRESS
MSX, SW
BMS
DATA
ACK
WR, DMAG
ADDRCLK
(OUT)
RD
t
SADADC
t
DARL
t
DAAK
t
RW
t
DRLD
t
DAD
t
DSAK
Figure 14. Memory Read—Bus Master
Rev. C | Page 25 of 56 | July 2007
t
HDRH
t
t
HDA
DRHA
t
RWR
Page 26
ADSP-21061/ADSP-21061L
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD
DMAGx
strobe timin g parameters only applies to asynchronous
access mode.
Table 13. Memory Write—Bus Master
5 V and 3.3 V
Parameter Min Max
Timing Requirements
t
DAAK
t
DSAK
ACK Delay from Address, Selects
ACK Delay from WR Low
1, 2
1
15 + 7DT/8 + W ns
8 + DT/2 + W ns
Switching Characteristics
t
DAWH
t
DAWL
t
WW
t
DDWH
t
DWHA
t
DATRWH
t
WWR
t
DDWR
t
WDE
t
SADADC
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulse Width 13 + 9DT/16 + W ns
Data Setup Before WR High 7 + DT/2 + W ns
Address Hold After WR Deasserted 1 + DT/16 + H ns
Data Disable After WR Deasserted
WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H ns
Data Disable Before WR or RD Low 5 + 3DT/8 + I ns
WR Low to Data Enabled –1 + DT/16 ns
Address, Selects to ADRCLK High
W = (number of wait states specified in WAIT register) × t
H = t
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
CK
I = t
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
CK
1
ACK delay/setup: User must meet t
(high).
2
The falling edge of MSx, SW, BMS is referenced.
3
For more information, see Example System Hold Time Calculation on Page 44 for calculation of hold times given capacitive and dc loads.
DAAK
or t
DSAK
2
2
3
2
CK
or synchronous specification t
17 + 15DT/16 + W ns
3 + 3DT/8 ns
1 + DT/16 +H 6 + DT/16+H ns
0 + DT/4 ns
.
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
SAKC
, WR, and
Unit
ADDRESS
MSX, SW
BMS
WR
DATA
ACK
RD, DMAG
ADRCLK
(OUT)
t
DAWL
t
SADADC
t
DAAK
t
t
DSAK
t
DAWH
WDE
t
WW
Figure 15. Memory Write—Bus Master
Rev. C | Page 26 of 56 | July 2007
t
DDWH
t
DATRWH
t
DWHA
t
WWR
t
DDWR
Page 27
ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Bus Master on Page 26). When accessing a slave ADSP-21061,
these switching characteristics must meet the slave’s timing
requirements for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on Page 29). The slave ADSP-21061
must also meet these (bus master) timing requirements for data
and acknowledge setup and hold times.
Memory Read—Bus Master on Page 25 and Memory Write—
Table 14. Synchronous Read/Write—Bus Master
5 V and 3.3 V
Parameter Min Max
Unit
Timing Requirements
t
SSDATI
t
HSDATI
t
DAAK
t
SACKC
t
HACK
Data Setup Before CLKIN
(50 MHz, t
= 20 ns)1
CK
Data Hold After CLKIN 3.5 – DT/8 ns
ACK Delay After Address, Selects
ACK Setup Before CLKIN
3
2, 3
ACK Hold After CLKIN –1 – DT/4 ns
2 + DT/8
ns
1.5 + DT/8
15 + 7DT/8 + W ns
6.5+DT/4 ns
Switching Characteristics
t
DADRO
t
HADRO
t
DPGC
t
DRDO
t
DWRO
Address, MSx, BMS, SW Delay After CLKIN
Address, MSx, BMS, SW Hold After CLKIN –1 – DT/8 ns
PAGE Delay After CLKIN 9 + DT/8 16 + DT/8 ns
RD High Delay After CLKIN –1.5 – DT/8 4 – DT/8 ns
WR High Delay After CLKIN
(50 MHz, tCK = 20 ns)
t
DRWL
t
SDDATO
t
DATTR
t
DADCCK
t
ADRCK
t
ADRCKH
t
ADRCKL
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at tCK < 25 ns. For all other devices, use the preceding timing specification of the same name.
2
The falling edge of MSx, SW, BMS is referenced.
3
ACK delay/setup: User must meet t
(high).
4
See Example System Hold Time Calculation on Page 44 for calculation of hold times given capacitive and dc loads.
RD/WR Low Delay After CLKIN 8 + DT/4 12 + DT/4 ns
Data Delay After CLKIN 19 + 5DT/16 ns
Data Disable After CLKIN
4
ADRCLK Delay After CLKIN 4 + DT/8 10 + DT/8 ns
ADRCLK Period t
ADRCLK Width High (tCK/2 – 2) ns
ADRCLK Width Low (tCK/2 – 2) ns
or t
DAAK
or synchronous specification t
DSAK
2
–2.5 – 3DT/16
–1.5 – 3DT/16
6.5 – DT/8 ns
4 – 3DT/16
4 – 3DT/16
0 – DT/8 7 – DT/8 ns
CK
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
SAKC
ns
ns
Rev. C | Page 27 of 56 | July 2007
Page 28
ADSP-21061/ADSP-21061L
CLKI N
t
DADCCK
ADDRCLK
t
ADRCKH
t
ADRCK
t
ADRCKL
ADDRESS, BMS,
SW, MSx
PAGE
ACK
(IN)
READ CYCLE
RD
DATA ( IN)
WRITE CYCLE
WR
t
DADRO
t
t
DRWL
t
DRWL
DPGC
t
DAAK
t
SACKC
t
SSDATI
t
DRDO
t
DWRO
t
t
HACK
t
HSDATI
HADRO
DATA
(OUT)
t
SDDATO
Figure 16. Synchronous Read/Write—Bus Master
Rev. C | Page 28 of 56 | July 2007
t
DATTR
Page 29
ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
Table 15. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Parameter Min Max
Timing Requirements
t
SADRI
t
HADRI
t
SRWLI
t
HRWLI
t
RWHPI
t
SDATWH
t
HDATWH
Address, SW Setup Before CLKIN 14 + DT/2 ns
Address, SW Hold After CLKIN 5 + DT/2 ns
RD/WR Low Setup Before CLKIN
RD/WR Low Hold After CLKIN
44 MHz/50 MHz
2
1
8.5 + 5DT/16 ns
–4 – 5DT/16
–3.5 – 5DT/16
8 + 7DT/16
8 + 7DT/16
RD/WR Pulse High 3 ns
Data Setup Before WR High 3 ns
Data Hold After WR High 1 ns
Switching Characteristics
t
SDDATO
t
DATTR
t
DACKAD
t
ACKTR
1
t
(min) = 9.5 + 5DT/16 when multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
2
This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), operating at tCK < 25 ns. For all other devices, use the
preceding timing specification of the same name.
3
See Example System Hold Time Calculation on Page 44 for calculation of hold times given capacitive and dc loads.
4
t
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup
DACKAD
times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of
the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
Data Delay After CLKIN 19 + 5DT/16 ns
Data Disable After CLKIN
ACK Delay After Address, SW
ACK Disable After CLKIN
3
4
2
.
ACKTR
0 – DT/8 7 – DT/8 ns
8ns
–1 – DT/8 6 – DT/8 ns
(min)= 4 + DT/8.
SRWLI
Unit
ns
Rev. C | Page 29 of 56 | July 2007
Page 30
ADSP-21061/ADSP-21061L
CLKIN
ADDRESS, SW
ACK
t
DACKAD
t
SADRI
t
HADRI
t
ACKTR
READ ACCESS
RD
DATA
(OU T)
WRITE ACCESS
WR
DATA
(IN)
t
SRWLI
t
SDDATO
t
SRWLI
Figure 17. Synchronous Read/Write—Bus Slave
t
SDATWH
t
HRWLI
t
HRWLI
t
DATTR
t
HDATWH
t
RWHPI
t
RWHPI
Rev. C | Page 30 of 56 | July 2007
Page 31
ADSP-21061/ADSP-21061L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21061s (BRx
synchronous and asynchronous (HBR
Table 16. Multiprocessor Bus Request and Host Bus Request
Parameter Min Max
Timing Requirements
t
HBGRCSV
t
SHBRI
t
HHBRI
t
SHBGI
t
HHBGI
t
SBRI
t
HBRI
t
RPBA Setup Before CLKIN 20 + 3DT/4 ns
SRPBAI
t
HRPBAI
HBG Low to RD/WR/CS Valid
HBR Setup Before CLKIN
HBR Hold After CLKIN
HBG Setup Before CLKIN 13 + DT/2 ns
HBG Hold After CLKIN High 6 + DT/2 ns
BRx, CPA Setup Before CLKIN
BRx, CPA Hold After CLKIN High 6 + DT/2 ns
RPBA Hold After CLKIN 12 + 3DT/4 ns
Switching Characteristics
t
DHBGO
t
HHBGO
t
DBRO
t
HBRO
t
DCPAO
t
TRCPA
t
DRDYCS
t
TRDYHG
t
ARDYTR
1
For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by t
easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21061” sectio n in the ADSP-21061 SHARC
User’s Manual, Revision 2.1.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
For the ADSP-21061L (3.3 V), this specification is 8.5 – DT/8 ns max.
5
(O/D) = open drain, (A/D) = active drive.
6
For the ADSP-21061L (3.3 V), this specification is 12 ns max.
7
For the ADSP-21061L (3.3 V), this specification is 40 + 23DT/16 ns min.
HBG Delay After CLKIN 7 – DT/8 ns
HBG Hold After CLKIN –2 – DT/8 ns
BRx Delay After CLKIN 5.5 – DT/8 ns
BRx Hold After CLKIN –2 – DT/8 ns
CPA Low Delay After CLKIN
CPA Disable After CLKIN –2 – DT/8 4.5 – DT/8 ns
REDY (O/D) or (A/D) Low from CS and HBR Low5,
REDY (O/D) Disable or REDY (A/D) High from HBG5,
REDY (A/D) Disable from CS or HBR High
) or a host processor, both
, HBG).
1
2
2
3
4
5
5 V and 3.3 V
Unit
20 + 5DT/4 ns
20 + 3DT/4 ns
14 + 3DT/4 ns
13 + DT/2 ns
6.5 – DT/8 ns
6
7
44 + 27DT/16 ns
8ns
10 ns
after HBG goes low. This is
HBGRCSV
Rev. C | Page 31 of 56 | July 2007
Page 32
ADSP-21061/ADSP-21061L
B
CLKIN
t
SHBRI
HBR
HBG (OUT)
BRx (OUT)
CP A (OUT , O/D)
HB G (I N)
Rx, CPA ( IN, O/ D)
t
HHBGO
t
HBRO
t
HHBRI
t
DHBGO
t
DBRO
t
DCPAO
t
SHBGI
t
SBRI
t
HHBGI
t
HBRI
t
TRCPA
RPBA
HBR
CS
RE D Y
(O/ D)
REDY
(A/ D)
HBG (OUT)
RD
WR
CS
t
SRPBAI
t
DRDYCS
O/D = OPEN-DRAIN, A/ D = ACTIVE DRI VE
Figure 18. Multiprocessor Bus Request and Host Bus Request
t
HRPBAI
t
HBGRCSV
t
TRDYHG
t
ARDYTR
Rev. C | Page 32 of 56 | July 2007
Page 33
ADSP-21061/ADSP-21061L
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor
accesses of an ADSP-21061, after the host has asserted CS
(low). After HBG is returned by the ADSP-21061, the host
HBR
and
Table 17. Read Cycle
Parameter Min Max
Timing Requirements
t
SADRDL
t
HADRDH
t
WRWH
t
DRDHRDY
t
DRDHRDY
Address Setup/CS Low Before RD Low
Address Hold/CS Hold Low After RD 0ns
RD/WR High Width 6 ns
RD High Delay After REDY (O/D) Disable 0 ns
RD High Delay After REDY (A/D) Disable 0 ns
1
Switching Characteristics
t
SDATRDY
t
DRDYRDL
t
RDYPRD
t
HDARWH
1
Not required if RD and address are valid t
low or by t
ADSP-21061” section in the ADSP-21061 SHARC User’s Manual, Revision 2.1.
2
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
HBGRCSV
Data Valid Before REDY Disable from Low 2 ns
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read 45 + DT ns
Data Disable After RD High 2 8 ns
after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the
HBGRCSV
can drive the RD
and WR pins to access the ADSP-21061’s
internal memory or IOP registers. HBR
low for this timing.
2
and HBG are assumed
5 V and 3.3 V
0ns
10 ns
Unit
before RD or WR goes
CLK
Table 18. Write Cycle
5 V and 3.3 V
Parameter Min Max
Unit
Timing Requirements
t
SCSWRL
t
HCSWRH
t
SADWRH
t
HADWRH
t
WWRL
t
WRWH
t
DWRHRDY
t
SDATWH
t
HDATWH
CS Low Setup Before WR Low 0 ns
CS Low Hold After WR High 0 ns
Address Setup Before WR High 5 ns
Address Hold After WR High 2 ns
WR Low Width 8 ns
RD/WR High Width 6 ns
WR High Delay After REDY (O/D) or (A/D) Disable 0 ns
Data Setup Before WR High
50 MHz, T
CK
= 20 ns
1
3
2.5
ns
Data Hold After WR High 1 ns
Switching Characteristics
t
DRDYWRL
t
RDYPWR
t
SRDYCK
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at tCK < 25 ns. For all other devices, use the preceding timing specification of the same name.
2
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
REDY (O/D) or (A/D) Low Delay After WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write 15 ns
REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 ns
2
11 ns
Rev. C | Page 33 of 56 | July 2007
Page 34
ADSP-21061/ADSP-21061L
CL KI N
REDY (O/D)
REDY (A/ D)
O/D = OPEN-DRAIN, A/D = ACTIVE DRIVE
READ CYCLE
ADDRESS/CS
RD
t
SADRDL
t
Figure 19. Synchronous REDY Timing
SRDYCK
t
HADRDH
t
HDARWH
t
WRWH
DATA (O UT)
REDY(O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
CS
WR
DA TA ( IN )
t
SCS WR L
t
DRDYRDL
t
DRDYWRL
t
SDATWH
t
WW RL
t
S DAT RD Y
t
RD YPRD
t
RDY PWR
t
DRDHRDY
t
SADWRH
t
t
HCSWRH
DWRHRDY
t
HADWRH
t
HDATWH
t
WRWH
RE DY ( O/D )
REDY (A/D)
O/D = OPEN-DRAIN,A/D = ACT IV E DRIVE
Figure 20. Asynchronous Read/Write—Host to ADSP-21061
Rev. C | Page 34 of 56 | July 2007
Page 35
ADSP-21061/ADSP-21061L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS
pin.
Table 19. Three-State Timing—Bus Master, Bus Slave
Parameter Min Max
Timing Requirements
t
STSCK
t
HTSCK
Switching Characteristics
t
MIENA
t
MIENS
t
MIENHG
t
MITRA
t
MITRS
t
MITRHG
t
DATEN
t
DATTR
t
ACKEN
t
ACKTR
t
ADCEN
t
ADCTR
t
MTRHBG
t
MENHBG
1
Strobes = RD, WR, PAGE, DMAGx, MSx, BMS, SW.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).
pin. This timing is applicable to bus master transi-
5 V and 3.3 V
SBTS Setup Before CLKIN 12 + DT/2 ns
SBTS Hold Before CLKIN 6 + DT/2 ns
Address/Select Enable After CLKIN –1 – DT/8 ns
Strobes Enable After CLKIN
1
–1.5 – DT/8 ns
HBG Enable After CLKIN –1.5 – DT/8 ns
Address/Select Disable After CLKIN 0 – DT/4 ns
Strobes Disable After CLKIN
1
1.5 – DT/4 ns
HBG Disable After CLKIN 2.0 – DT/4 ns
Data Enable After CLKIN
Data Disable After CLKIN
ACK Enable After CLKIN
ACK Disable After CLKIN
2
2
2
2
9 + 5DT/16 ns
0 – DT/8 7 – DT/8 ns
7.5 + DT/4 ns
–1 – DT/8 6 – DT/8 ns
ADRCLK Enable After CLKIN –2 – DT/8 ns
ADRCLK Disable After CLKIN 8 – DT/4 ns
Memory Interface Disable Before HBG Low
Memory Interface Enable After HBG High
3
3
0 + DT/8 ns
19 + DT ns
Unit
CLKIN
SBTS
MEMO RY
INTERFACE
DATA
ACK
CLKOUT
t
STSCK
t
HTSCK
t
MIENA,tMIENS ,tMIENHG
t
DATTR
t
ACKTR
t
t
ADCEN
t
DATEN
ACKEN
Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
Rev. C | Page 35 of 56 | July 2007
t
MITRA,tMITRS,tMITRHG
t
ADCTR
Page 36
ADSP-21061/ADSP-21061L
HBG
MEMORY
INTERFACE
t
MENHBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW,PAGE,DMAGx. BMS (IN EPROM BOOT MODE)
Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
t
MTRHBG
Rev. C | Page 36 of 56 | July 2007
Page 37
ADSP-21061/ADSP-21061L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes, DMARx
Handshake mode, DMAGx
is used to initiate transfers. For
controls the latching or enabling of
data externally. For External Handshake mode, the data transfer
is controlled by the ADDR31–0, RD
, WR, SW, PAGE, MS3–0,
ACK, and DMAG
transfer is controlled by ADDR31–0, RD
ACK (not DMAG
Bus Master, Memory Write-Bus Master, and Synchronous
Read/Write-Bus Master timing specifications for ADDR31–0,
RD
, WR, MS3–0, SW, PAGE, DATA47–0, and ACK also apply.
x signals. For Paced Master mode, the data
, WR, MS3–0, and
). For Paced Master mode, the Memory Read-
Table 20. DMA Handshake
5 V and 3.3 V
Parameter Min Max
Timing Requirements
t
SDRLC
t
SDRHC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
DMARx Low Setup Before CLKIN
DMARx High Setup Before CLKIN
DMARx Width Low (Nonsynchronous) 6 ns
Data Setup After DMAGx Low
Data Hold After DMAGx High 2 ns
Data Valid After DMARx High
DMARx Low Edge to Low Edge
DMARx Width High 6 ns
1
1
2
2
3
5ns
5ns
10 + 5DT/8 ns
16 + 7DT/8 ns
23 + 7DT/8 ns
Switching Characteristics
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
VDATDGH
t
DATRDGH
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
DGWR
t
DADGH
t
DDGHA
W = (number of wait states specified in WAIT register) ⴛ t
HI = t
1
Only required for recognition in the current cycle.
2
t
SDATDGL
be driven t
3
For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min.
4
t
VDATDGH
the number of extra cycles that the access is prolonged.
5
See Example System Hold Time Calculation on Page 44 for calculation of hold times given capacitive and dc loads.
6
For the ADSP-21061L (3.3 V), this specification is –1.0 ns min.
DMAGx Low Delay After CLKIN 9 + DT/4 15 + DT/4 ns
DMAGx High Width 6 + 3DT/8 ns
DMAGx Low Width 12 + 5DT/8 ns
DMAGx High Delay After CLKIN –2 – DT/8 6 – DT/8 ns
Data Valid Before DMAGx High
Data Disable After DMAGx High
4
5
8 + 9DT/16 ns
07ns
WR Low Before DMAGx Low 0 2 ns
DMAGx Low Before WR High 10 + 5DT/8 +W ns
WR High Before DMAGx High 1 + DT/16 3 + DT/16 ns
RD Low Before DMAGx Low 0 2 ns
RD Low Before DMAGx High 11 + 9DT/16 + W ns
RD High Before DMAGx High 0 3 ns
DMAGx High to WR, RD, DMAGx Low 5 + 3DT/8 + HI ns
Address/Select Valid to DMAGx High 17 + DT ns
Address/Select Hold after DMAGx High
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
CK
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
after DMARx is brought high.
DATDRH
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
6
.
CK
–0.5 ns
–.25t
VDATDGH=tCK
–8+(n×tCK) where n equals
CCLK
Unit
Rev. C | Page 37 of 56 | July 2007
Page 38
ADSP-21061/ADSP-21061L
CLKIN
t
SDRLC
DMARx
DMAGx
t
WDR
t
DDGL
t
DMARLL
t
SDRHC
t
WDGL
t
DMARH
t
HDGC
t
WDGH
TRANSFERS BETWEEN ADSP-2106x
INTERNAL MEMORY AND EXTERNAL DEVICE
DATA
(FROM ADSP-2106x TO EXTERNAL DEVICE)
DATA
(FROM EXTERN AL DEVICE TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
WR
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
RD
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
ADDR
MSx, SW
*MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW MS3–0,ANDACKALSO APPLY HERE.
t
DGWRL
Figure 23. DMA Handshake
t
DGRDL
t
DADGH
t
SDATDGL
t
DGWRH
t
DRDGH
t
DATDRH
t
VDATDGH
t
t
HDATIDG
DGWRR
t
DATRDGH
t
DGRDR
t
DDGHA
Rev. C | Page 38 of 56 | July 2007
Page 39
ADSP-21061/ADSP-21061L
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 21. Serial Ports—External Clock
5 V and 3.3 V
Parameter
Timing Requirements
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK1,
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width 9 ns
TCLK/RCLK Period t
1
2
1
1
Table 22. Serial Ports—Internal Clock
Min Max
3.5 ns
4ns
1.5 ns
4ns
CK
Unit
ns
5 V and 3.3 V
Parameter
Min Max
Timing Requirements
t
SFSI
t
HFSI
t
SDRI
t
HDRI
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
TFS Setup Before TCLK1; RFS Setup Before RCLK
TFS/RFS Hold After TCLK/RCLK1,
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
2
1
1
1
8ns
1ns
3ns
3ns
Table 23. Serial Ports—External or Internal Clock
5 V and 3.3 V
Parameter
Min Max
Switching Characteristics
t
DFSE
t
HOFSE
1
Referenced to drive edge.
RFS Delay After RCLK (Internally Generated RFS)
RFS Hold After RCLK (Internally Generated RFS)
1
1
3ns
13 ns
Table 24. Serial Ports—External Clock
5 V and 3.3 V
Parameter
Min Max
Switching Characteristics
t
DFSE
t
HOFSE
t
DDTE
t
HODTE
1
Referenced to drive edge.
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
1
1
1
1
3ns
13 ns
16 ns
5ns
Unit
Unit
Unit
Rev. C | Page 39 of 56 | July 2007
Page 40
ADSP-21061/ADSP-21061L
Table 25. Serial Ports—Internal Clock
Parameter
Switching Characteristics
t
DFSI
t
HOFSI
t
DDTI
t
HDTI
t
SCLKIW
1
Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
t
DDTEN
t
DDTTE
t
DDTIN
t
DDTTI
t
DCLK
t
DPTR
1
Referenced to drive edge.
2
For the ADSP-21061L (3.3 V), this specification is 3.5 ns min.
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TCLK/RCLK Width t
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Delay from CLKIN 22 + 3DT/8 ns
SPORT Disable After CLKIN 17 ns
5 V and 3.3 V
Min Max
1
1
1
1
–1.5 ns
0ns
/2 –1.5 t
SCLK
4.5 ns
7.5 ns
/2+1.5 ns
SCLK
Unit
5 V and 3.3 V
Min Max
1, 2
1
1
1
4.5 ns
10.5 ns
0ns
3ns
Unit
Table 27. Serial Ports—External Late Frame Sync
Parameter
Switching Characteristics
t
DDTLFSE
t
DDTENFS
1
MCE = 1, TFS enable and TFS valid follow t
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
DDTLFSE
and t
DDTENFS
.
5 V and 3.3 V
Min Max
1
1
3.5 ns
12 ns
Unit
Rev. C | Page 40 of 56 | July 2007
Page 41
ADSP-21061/ADSP-21061L
RCLK
RFS
TCLK
TFS
DATA RECEIVE— INTERNAL CLOCK
DRIVE
EDGE
t
DFSE
t
HOFSE
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT— INTERNAL C LOCK
DRIVE
EDGE
t
t
DFSI
DDTI
t
HOFSI
t
HDTI
t
SCLKIW
t
SCLKIW
t
SFSI
t
t
SDRI
SFSI
SAMPLE
EDGE
SAMPLE
EDGE
t
t
t
HFSI
HFSI
HDRI
RCLK
RFS
DR
TCLK
TFS
DATA RECEIVE— EXTERNAL CLOCK
DRIVE
t
HOFSE
EDGE
t
DFSE
t
SCLKW
t
SFSE
t
DATA TRANSMIT— EXTERNAL CLOCK
DRIVE
t
HOFSE
t
EDGE
HDTE
t
DFSE
t
DDTE
t
SCLKW
t
SDRE
SFSE
SAMPLE
EDGE
SAMPLE
EDGE
t
t
HDRE
t
HFSE
HFSE
DT
TCLK
(EXT)
DT
TCLK
(INT)
DT
CLKIN
TCLK, RCLK
TFS,RFS,DT
TCLK (INT)
RCLK (INT)
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE DRIVE EDGE
TCLK/RCLK
t
DRIVE
EDGE
t
STFSCK
DDTTE
t
DDTTI
t
HTFSCK
t
DDTEN
DRIVE
EDGE
t
DDTIN
t
DPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
t
DCLK
LOW TO HIGH O NLY
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CY CLES
TCLK/RCLK
CLKIN
TFS (EXT )
NOTE: APPLIES ONLY T O GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS,AS USED IN TH E SERIAL PORT SYSTEM I/O
FOR MESHMULTIPROCESSING.
Figure 24. Serial Ports
Rev. C | Page 41 of 56 | July 2007
Page 42
ADSP-21061/ADSP-21061L
RCLK
RFS
DRIVE SAMPLE DRIVE
TCLK
TFS
DT
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE SAMPLE DRIVE
t
SFSE/I
t
HDTE/I
1ST BIT 2ND BITDT
LATE EXTERNAL TFS
t
DDTE/I
t
HDTE/I
1STBIT 2NDBIT
t
DDTLFSE
t
DDTENFS
t
SFSE/I
TDDTENFS
t
DDTE/I
t
HOFSE/I
t
HOFSE/I
t
DDTLFSE
Figure 25. Serial Ports—External Late Frame Sync
Rev. C | Page 42 of 56 | July 2007
Page 43
ADSP-21061/ADSP-21061L
JTAG Test Access Port and Emulation
For JTAG Test Access Port and Emulation, see Table 28 and
Figure 26.
Table 28. JTAG Test Access Port and Emulation
5 V and 3.3 V
Parameter
Min Max
Timing Requirements
t
TCK
t
STAP
t
HTAP
t
SSYS
t
HSYS
t
TRSTW
TCK Period t
TDI, TMS Setup Before TCK High t
CK
CK
TDI, TMS Hold After TCK High 6 ns
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulse Width 4t
1
1
7ns
18 ns
CK
Switching Characteristics
t
DTDO
t
DSYS
1
System Inputs = DATA47–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, CPA, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA47–0, ADDR31–0, MS3–0, RD, WR, SW, ACK, ADRCLK, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, FLAG3–0, TIMEXP, DT0, DT1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
TDO Delay from TCK Low 13 ns
System Outputs Delay After TCK Low
2
18.5 ns
Unit
ns
ns
ns
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
DTDO
t
t
STAP
DSYS
t
HTAP
Figure 26. JTAG Test Access Port and Emulation
t
SSYS
t
HSYS
Rev. C | Page 43 of 56 | July 2007
Page 44
ADSP-21061/ADSP-21061L
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, C
load current, I
. This decay time can be approximated by the
L
following equation:
CLVΔ
EXT
=
---------------
I
L
P
, and the
L
TO
OUTPUT
PIN
50pF
I
OL
1.5V
I
OH
The output disable time t
t
MEASURED
and t
as shown in Figure 27. The time t
DECAY
is the difference between
DIS
MEASURED
is
the interval from when the reference signal switches to when the
output voltage decays ΔV from the measured output high or
output low voltage. t
is calculated with test loads CL and IL,
DECAY
and with ΔV equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driving. The output enable time t
is the interval from when a
ENA
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure27). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
using the equation given above. Choose ΔV
DECAY
to be the difference between the ADSP-21061’s output voltage
and the input threshold for the device requiring the hold time. A
typical ΔV will be 0.4 V. C
line), and I
is the total leakage or three-state current (per data
L
line). The hold time will be t
time (i.e., t
REFERENCE
SIGNAL
V
OH (MEASURED)
V
OL (MEASURED)
for the write cycle).
DATRWH
t
DIS
is the total bus capacitance (per data
L
plus the minimum disable
DECAY
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
t
DECAY
- ⌬V
+ ⌬V
t
ENA
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
Figure 28. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
INPUT
OR
OUTPUT
1.5V 1.5V
Figure 29. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Output Drive Characteristics
Figure 30 through Figure 37 show typical characteristics for the
output drivers of the ADSP-21061 (5 V) and ADSP-21061L
(3 V). The curves represent the current drive capability and
switching behavior of the output drivers as a function of
resistive and capacitive loading.
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 31,
Figure 32, Figure 35, and Figure 36 show how output rise time
varies with capacitance. Figure 33 and Figure 37 show graphi-
cally how output delays and holds vary with load capacitance.
(Note that this graph or derating does not apply to output disable delays; see the previous section Output Disable Time under
Test Conditions.) The graphs of Figure 31, Figure 32, Figure 35,
and Figure 36 may not be linear outside the ranges shown.
OUTPUT STOPS
DRIVING
HIGH IMPEDANCE STATE.
TESTCONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V.
Figure 27. Output Enable/Disable
OUTPUT STARTS
DRIVING
Rev. C | Page 44 of 56 | July 2007
Page 45
Output Characteristics (5 V)
75
50
25
)
A
m
(
0
T
N
E
R
-
25
R
U
C
-
50
E
C
R
U
-
75
O
S
-
100
-
125
-
150
5.25V,-40°C
05.25
0.75 1.50 2.25 3.00 3.75 4.50
5.0V, +25°C
4.75V,+ 100°C
SOURCE VOLTAGE(V)
4.75V, +100°C
5.0V, +25°C
5.25V,-40°C
ADSP-21061/ADSP-21061L
3.5
)
V
0
3.0
.
2
o
t
V
2.5
8
.
0
(
)
s
n
2.0
(
S
E
M
I
T
L
L
A
F
D
N
A
E
S
I
R
Y = 0.009x + 1.1
1.5
1.0
0.5
0
020020 40 60 80 100 120 140 160 180
Figure 32. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance
RISETIME
Y = 0.005x + 0.6
LOAD CAPACITANCE (pF)
= 5 V)
(V
DD
FAL L T IM E
Figure 30. Typical Output Drive Currents (VDD = 5 V)
16.0
14.0
12.0
)
)
s
n
%
(
0
9
S
10.0
E
o
t
M
I
%
T
0
L
1
L
,
V
A
F
.5
4
D
o
N
t
A
V
E
.5
S
I
0
(
R
Y = 0.005x + 3.7
8.0
6.0
4.0
2.0
0
020020 40 60 80 100 120 140 160 180
RISETIME
FAL L T IM E
Y = 0.0031x + 1.1
LOAD CAPACITANCE (pF)
Figure 31. Typical Output Rise Time (10% to 90% V
(V
= 5 V)
DD
) vs. Load Capacitance
DD
5
)
s
n
4
(
D
L
O
H
3
R
O
Y
A
L
E
2
D
T
U
P
T
1
U
O
NOMINAL
-
1
25 20050 75 100 125 150 175
Y=0.03X-1.45
LOAD CAPACITANCE (pF)
Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Maximum
Case Temperature) (V
DD
= 5 V)
Rev. C | Page 45 of 56 | July 2007
Page 46
ADSP-21061/ADSP-21061L
5
Input/Output Characteristics (3.3 V)
120
100
80
60
)
A
40
m
(
T
N
E
R
R
U
C
E
C
R
U
O
S
3.0V, +85°C
20
0
-
20
-
40
-
60
-
80
-
100
-
120
0 3.5
0.5 1.0 1.5 2.0 2.5 3.0
Figure 34. Typical Drive Currents (VDD = 3.3 V)
3.3V, + 2 5° C
V
OH
3.0V, +85°C
V
OL
SOURCE VOLTAGE (V)
3.3V, + 2 5 ° C
3.6V,-40°C
3.6V,-40°C
9
)
8
V
0
.
2
o
7
t
V
.8
6
0
(
)
s
n
(
5
S
E
M
I
4
T
L
L
A
3
F
D
N
2
A
E
S
I
1
R
0020 40 60 80 100 120
Y=0.0391x + 0.36
RISETIME
FALL TIME
LOAD CAPACITANCE (pF)
Y=0.0305x + 0.24
140 160 180200
Figure 36. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance
= 3.3 V)
(V
DD
18
)
16
%
0
9
o
t
14
%
0
1
(
12
)
s
n
(
10
S
E
M
I
8
T
L
L
A
F
6
D
N
A
4
E
S
I
R
2
0
0
20 40 60 80100120
Y = 0.0796x + 1.17
RISETIME
Y = 0.0467x + 0.55
FALL TIME
LOAD CAPACITANCE (pF)
Figure 35. Typical Output Rise Time (10% to 90% V
(V
= 3.3 V)
DD
140 160 180200
) vs. Load Capacitance
DD
4
)
s
n
(
D
L
3
O
H
R
O
Y
2
A
L
E
D
T
U
1
P
T
U
O
NOMINAL
-
1
25 20050 75 100 125 150 175
LOAD CAPACITANCE (pF)
Y=0.0329x-1.65
Figure 37. Typical Output Delay or Hold vs. Load Capacitance (at Maximum
Case Temperature) (V
= 3.3 V)
DD
Rev. C | Page 46 of 56 | July 2007
Page 47
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-21061 is available in 240-lead thermally enhanced
MQFP package. The top surface of the thermally enhanced
MQFP contains a metal slug from which most of the die heat is
dissipated. The slug is flush with the top surface of the package.
Note that the metal slug is internally connected to GND
through the device substrate.
The ADSP-21061L is available in 240-lead MQFP and 225-ball
plastic BGA packages.
All packages are specified for a case temperature (T
ensure that the T
is not exceeded, a heatsink and/or an air-
CASE
flow source may be used. A heat sink should be attached with a
thermal adhesive.
T
T
CASE
CASE
= T
+ ( PD θ CA)
AMB
= Case temperature (measured on top surface of package)
PD =Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under
Power Dissipation).
=Value from tables below.
θ
CA
CASE
). To
ADSP-21061/ADSP-21061L
Table 29. ADSP-21061 (5 V Thermally Enhanced ED/MQFP
Package)
Parameter Condition (Linear Ft./Min.) Typical Unit
θ
CA
Airflow = 0
Airflow = 100
Airflow = 200
Airflow = 400
Airflow = 600
10
9
8
7
6
°C/W
Table 30. ADSP-21061L (3.3 V MQFP Package)
Parameter Condition (Linear Ft./Min.) Typical Unit
θ
CA
Airflow = 0
Airflow = 100
Airflow = 200
Airflow = 400
Airflow = 600
19.6
17.6
15.6
13.9
12.2
°C/W
Table 31. ADSP-21061L (3.3 V PBGA Package)
Parameter Condition (Linear Ft./Min.) Typical Unit
θ
CA
Airflow = 0
Airflow = 200
Airflow = 400
19.0
13.6
11.2
°C/W
Rev. C | Page 47 of 56 | July 2007
Page 48
ADSP-21061/ADSP-21061L
225-BALL PBGA PIN CONFIGURATIONS
Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
BMS A01 ADDR25 D01 ADDR14 G01 ADDR6 K01 EMU N01
ADDR30 A02 ADDR26 D02 ADDR15 G02 ADDR5 K02 TDO N02
DMAR2 A03 MS2 D03 ADDR16 G03 ADDR3 K03 IRQ0 N03
DT1 A04 ADDR29 D04 ADDR19 G04 ADDR0 K04 IRQ1
RCLK1 A05 DMAR1
TCLK0 A06 TFS1 D06 V
RCLK0 A07 CPA
ADRCLK A08 HBG
CS
A09 DMAG2 D09 V
CLKIN A10 BR5
PAG E A 1 1 B R1
BR3
A1 2 D ATA4 0 D1 2 D ATA2 2 G1 2 D ATA8 K 1 2 N C N 12
D05 GND G05 ICSA K05 ID2 N05
G06 GND K06 NC N06
G07 V
G08 V
G09 V
DD
DD
DD
K07 NC N07
K08 NC N08
K09 NC N09
G10 GND K10 NC N10
D07 V
D08 V
D10 V
DD
DD
DD
DD
DD
D11 GND G11 GND K11 NC N11
N04
DATA47 A13 DATA37 D13 DATA25 G13 DATA11 K13 NC N13
DATA44 A14 DATA35 D14 DATA24 G14 DATA13 K14 DATA1 N14
DATA42 A15 DATA34 D15 DATA23 G15 DATA14 K15 DATA3 N15
MS0
SW
B01 ADDR21 E01 ADDR12 H01 ADDR2 L01 TRST P01
B02 ADDR22 E02 ADDR11 H02 ADDR1 L02 TMS P02
ADDR31 B03 ADDR24 E03 ADDR13 H03 FLAG0 L03 EBOOT P03
HBR
B04 ADDR27 E04 ADDR10 H04 FLAG3 L04 ID0 P04
DR1 B05 GND E05 GND H05 RPBA L05 NC P05
DT0 B06 GND E06 V
DR0 B07 GND E07 V
REDY B08 GND E08 V
RD
B09 GND E09 V
ACK B10 GND E10 V
BR6
BR2
B11 NC E11 GND H11 NC L11 NC P11
B 12 D ATA3 3 E 1 2 DATA 1 8 H 12 D ATA4 L1 2 N C P 12
DD
DD
DD
DD
DD
H06 GND L06 NC P06
H07 GND L07 NC P07
H08 GND L08 NC P08
H09 GND L09 NC P09
H10 GND L10 NC P10
DATA45 B13 DATA30 E13 DATA19 H13 DATA7 L13 NC P13
DATA43 B14 DATA32 E14 DATA21 H14 DATA9 L14 NC P14
DATA39 B15 DATA31 E15 DATA20 H15 DATA10 L15 DATA0 P15
MS3
MS1
ADDR28 C03 ADDR20 F03 ADDR7 J03 TIMEXP M03 RESET
SBTS
C01 ADDR17 F01 ADDR9 J01 FLAG1 M01 TCK R01
C02 ADDR18 F02 ADDR8 J02 FLAG2 M02 IRQ2 R02
R03
C04 ADDR23 F04 ADDR4 J04 TDI M04 ID1 R04
TCLK1 C05 GND F05 GND J05 LBOOT (GND) M05 NC R05
RFS1 C06 GND F06 V
TFS0 C07 V
RFS0 C08 V
WR
DMAG1
BR4
C09 V
C10 GND F10 V
C11 GND F11 GND J11 NC M11 NC R11
DD
DD
DD
F07 V
F08 V
F09 V
DD
DD
DD
DD
DD
J06 NC M06 NC R06
J07 NC M07 NC R07
J08 NC M08 NC R08
J09 NC M09 NC R09
J10 NC M10 NC R10
DATA46 C12 DATA29 F12 DATA12 J12 NC M12 NC R12
Rev. C | Page 48 of 56 | July 2007
Page 49
Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments (Continued)
ADSP-21061/ADSP-21061L
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
DATA41 C13 DATA26 F13 DATA15 J13 DATA2 M13 NC R13
DATA38 C14 DATA28 F14 DATA16 J14 DATA5 M14 NC R14
DATA36 C15 DATA27 F15 DATA17 J15 DATA6 M15 NC R15
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DATA47DATA44DATA42
DATA45DATA43DATA39
BR3
DATA46DATA41DATA38DATA36
DATA40DATA37DATA35DATA34
DATA22DATA25DATA24DATA23
CLKINPAGE
BR6BR2
ACK
CS
RD
WRDMAG1BR4
ADRCLK
DR1DT0DR0REDY
TCLK1RFS1TFS0RFS0
CPAHBGDMAG2BR5BR1
TFS1
DMAR1
ADDR29
DT1RCLK1TCLK0RCLK0
HBR
SBTS
DMAR2
ADDR31
ADDR28
MS2
ADDR30
BMS
MS0SW
MS3MS1
ADDR25ADDR26
ADDR21ADDR22ADDR24ADDR27GNDGNDGNDGNDGNDGNDNCDATA33DATA30DATA32DATA31
ADDR17ADDR18ADDR20ADDR23GNDGNDVDDVDDVDDGNDGNDDATA29DATA26DATA28DATA27
ADDR14ADDR15ADDR16ADDR19GNDVDDVDDVDDVDDVDDGND
ADDR12ADDR11ADDR13ADDR10GNDVDDVDDVDDVDDVDDGNDDATA18DATA19DATA21DATA20
A
B
C
D
E
F
G
H
NC = NO CONNECT
LBOOT
NCNCNCNCNCNCNCDATA2DATA5DATA6
NCNCNCNCNCNCNCNCDATA0
Figure 38. BGA Pin Assignments (Top View, Summary)
(GND)
ID2NCNCNCNCNCNCNCNCDATA1DATA3
ADDR9ADDR8ADDR7ADDR4GNDVDDVDDVDDVDDVDDGNDDATA12DATA15DATA16DATA17
ADDR6ADDR5ADDR3ADDR0ICSAGNDVDDVDDVDDGNDGNDDATA8DATA11DATA13DATA14
ADDR2ADDR1FLAG0FLAG3RPBAGNDGNDGNDGNDGNDNCDATA4DATA7DATA9DATA10
FLAG1FLAG2TIMEXPTDI
IRQ0IRQ1
ID1NCNCNCNCNC NC NC NC NC NC NC
TDO
TMSEBOOTID0NCNC
IRQ2RESET
TRST
EMU
TCK
J
K
L
M
N
P
R
Rev. C | Page 49 of 56 | July 2007
Page 50
ADSP-21061/ADSP-21061L
240-LEAD MQFP PIN CONFIGURATIONS
Table 33. ADSP-21061 MQFP/ED (SP-240); ADSP-21061L MQFP (S-240) Pin Assignments
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
TDI 1 ADDR20 41 TCLK0 81 DATA41 121 DATA14 161 NC 201
TRST
V
DD
TDO 4 ADDR22 44 RCLK0 84 V
TIMEXP 5 ADDR23 45 RFS0 85 DATA38 125 DATA11 165 V
EMU
ICSA 7 V
FLAG3 8 GND 48 GND 88 GND 128 V
FLAG2 9 V
FLAG110ADDR2550REDY90DATA35130DATA7170NC 210
FLAG011ADDR2651HBG
GND12ADDR2752CS
ADDR0 13 GND 53 RD
ADDR1 14 MS3
V
DD
ADDR2 16 MS1
ADDR3 17 MS0
ADDR4 18 SW
GND 19 BMS
ADDR520ADDR2860DMAG2
ADDR6 21 GND 61 DMAG1
ADDR7 22 V
V
DD
ADDR824ADDR2964BR6
ADDR925ADDR3065BR5
ADDR10 26 ADDR31 66 BR4
GND 27 GND 67 BR3
ADDR11 28 SBTS
ADDR12 29 DMAR2
ADDR13 30 DMAR1
V
DD
ADDR14 32 DT1 72 GND 112 V
ADDR15 33 TCLK1 73 DATA47 113 DATA20 153 NC 193 RPBA 233
GND 34 TFS1 74 DATA46 114 DATA19 154 NC 194 RESET
ADDR16 35 DR1 75 DATA45 115 DATA18 155 GND 195 EBOOT 235
ADDR17 36 RCLK1 76 V
ADDR18 37 RFS1 77 DATA44 117 DATA17 157 V
V
DD
V
DD
ADDR19 40 DT0 80 GND 120 V
2 ADDR21 42 TFS0 82 DATA40 122 DATA13 162 NC 202
3GND43 DR0 83 DATA39 123 DATA12 163 NC 203
DD
124 GND 164 NC 204
DD
205
6ADDR2446VDD86 DATA37 126 DATA10 166 NC 206
DD
DD
47 V
DD
49 ADRCLK 89 NC 129 DATA8 169 NC 209
87 DATA36 127 DATA9 167 NC 207
DD
168 NC 208
91 DATA34 131 DATA6 171 NC 211
92 DATA33 132 GND 172 GND 212
93 V
54 WR 94 V
DD
DD
133 DATA5 173 NC 213
134 DATA4 174 NC 214
15 MS2 55 GND 95 GND 135 DATA3 175 NC 215
56 V
DD
96 DATA32 136 V
DD
176 NC 216
57 GND 97 DATA31 137 DATA2 177 NC 217
58 CLKIN 98 DATA30 138 DATA1 178 NC 218
59 ACK 99 GND 139 DATA0 179 V
DD
219
100 DATA29 140 GND 180 GND 220
23 V
DD
DD
101 DATA28 141 GND 181 V
DD
62 PAGE 102 DATA27 142 NC 182 NC 222
63 V
DD
103 V
104 V
DD
DD
143 NC 183 NC 223
144 NC 184 NC 224
221
105 DATA26 145 NC 185 NC 225
106 DATA25 146 NC 186 NC 226
107 DATA24 147 NC 187 NC 227
68 BR2 108 GND 148 V
DD
188 GND 228
69 BR1 109 DATA23 149 NC 189 ID2 229
70 GND 110 DATA22 150 NC 190 ID1 230
31 HBR 71 V
DD
111 DATA21 151 NC 191 ID0 231
DD
152 NC 192 LBOOT (GND) 232
234
DD
116 GND 156 GND 196 IRQ2 236
DD
197 IRQ1 237
38 GND 78 DATA43 118 DATA16 158 NC 198 IRQ0 238
39 CPA 79 DATA42 119 DATA15 159 NC 199 TCK 239
DD
160 NC 200 TMS 240
Rev. C | Page 50 of 56 | July 2007
Page 51
OUTLINE DIMENSIONS
0.66
0.56
0.46
SEATING
PLANE
4.10
3.78
3.55
ADSP-21061/ADSP-21061L
34.60 BSC
SQ
240
1
PIN 1
HEAT SLUG
TOP VIEW
(PINS DOWN)
29.50 REF
SQ
181
180
24.00 REF
SQ
32.00 BSC
SQ
3.50
3.40
3.30
0.38
0.25
ROTATED 90° CCW
0.076
COPLANARITY
VIEW A
0.20
0.09
7°
0°
VIEW A
60
61
0.50
BSC
LEAD PITCH
0.27 MAX
0.17 MIN
120
121
3.92 u 45°
(4 PLACES)
Figure 39. 240-Lead Metric Quad Flat Package, Thermally Enhanced [MQFP/ED] (SP-240-2)
Rev. C | Page 51 of 56 | July 2007
Page 52
ADSP-21061/ADSP-21061L
0.75
0.60
0.45
SEATING
PLANE
0.50
BSC
0.27
0.17
4.10
MAX
34.85
34.60 SQ
34.35
32.00 BSC
SQ
181042
1
180
PIN 1
29.50
REF
SQ
2.70 MAX
0.08 MAX
COPLANARITY
0.50
0.25
BALL A1
INDICATOR
60
3.50
3.40
3.20
Figure 40. 240-Lead Metric Quad Flat Package, [MQFP] (S-240)
23.20
23.00 SQ
22.80
TOP VIEW
DETAIL A
20.10
20.00 SQ
19.90
0.50 R
3 PLACES
BSC SQ
0.70
0.60
0.50
18.00
1.27
BSC
DETAIL A
15141312111098765
BOTTOM VIEW
121
12061
A1 CORNER
INDEX AREA
31
42
1.30
1.20
1.10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
SEATING
PLANE
0.90
0.75
0.60
BALL DIAMETER
Figure 41. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2)
Rev. C | Page 52 of 56 | July 2007
0.15 MAX
COPLANARITY
Page 53
ADSP-21061/ADSP-21061L
SURFACE-MOUNT DESIGN
Table 34 is provided as an aide to PCB design. For industry-
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Table 34. BGA Data for Use with Surface-Mount Design
Package Ball Attach Type Solder Mask Opening Ball Pad Size
225-Ball Grid Array (PBGA) Solder Mask Defined 0.63 mm diameter 0.73 mm diameter
ORDERING GUIDE
Model
Tem p er at u re
Range
Instruction
Rate
On-Chip
SRAM
Operating
Voltage Package Description
Package
Option
ADSP-21061KS-133 0°C to 85°C 33 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KSZ-133
1
0°C to 85°C 33 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KS-160 0°C to 85°C 40 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KSZ-160
1
0°C to 85°C 40 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KS-200 0°C to 85°C 50 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KSZ-200
1
0°C to 85°C 50 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061LKB-160 0°C to 85°C 40 MHz 1M Bit 3.3 V 225-Ball PBGA B-225-2
ADSP-21061LKBZ-160
1
0°C to 85°C 40 MHz 1M Bit 3.3 V 225-Ball PBGA B-225-2
ADSP-21061LKS-160 0°C to 85°C 40 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LKSZ-160
1
0°C to 85°C 40 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LAS-176 –40°C to +85°C 44 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LASZ-176
1
–40°C to +85°C 44 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LKS-176 0°C to 85°C 44 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LKSZ-176
1
Z = RoHS Compliant Part.
1
0°C to 85°C 44 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
Rev. C | Page 53 of 56 | July 2007
Page 54
ADSP-21061/ADSP-21061L
Rev. C | Page 54 of 56 | July 2007
Page 55
ADSP-21061/ADSP-21061L
Rev. C | Page 55 of 56 | July 2007
Page 56
ADSP-21061/ADSP-21061L
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D001
70-0-7/07(C)
Rev. C | Page 56 of 56 | July 2007
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