Datasheet ADSP-21060C Datasheet (Analog Devices)

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Page 1

ADSP-21060 Industrial SHARC

SUMMARY High Performance Signal Processor for Communica-

tions, Graphics, and Imaging Applications

Super Harvard Architecture

Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

32-Bit IEEE Floating-Point Computation Units—

Multiplier, ALU, and Shifter

Dual-Ported On-Chip SRAM and Integrated I/O

Peripherals—A Complete System-On-A-Chip Integrated Multiprocessing Features Industrial Temperature Grade Hermetic Ceramic QFP

Package

KEY FEATURES 40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction

Execution 120 MFLOPS Peak, 80 MFLOPS Sustained Performance Dual Data Address Generators with Modulo and Bit-

Reverse Addressing

DSP Microcomputer Family

ADSP-21060C/ADSP-21060LC

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation 240-Lead Thermally Enhanced CQFP Package 32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats or 32-Bit Fixed-

Point Data Format

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel

with Dual Memory Read/Writes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT

Butterfly Computation

4 Mbit On-Chip SRAM

Dual-Ported for Independent Access by Core Processor

and DMA

Off-Chip Memory Interfacing

4 Gigawords Addressable Programmable Wait State Generation, Page-Mode

DRAM Support

DAG1

8 x 4 x 32

BUS

CONNECT

(PX)

MULTIPLIER

CORE PROCESSOR

TIMER INSTRUCTION

DAG2

8 x 4 x 24

PM ADDRESS BUS

DATA

FILE

16 x 40-BIT

DM ADDRESS BUS

SEQUENCER

PM DATA BUS

DM DATA BUS

BARREL SHIFTER

CACHE

32 x 48-BIT

PROGRAM

40/32

PROCESSOR PORT I/O PORT

ADDR DATA ADDR

ADDR DATA

ALU

Figure 1. Block Diagram

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

DATA

IOD 48

IOP

REGISTERS

(

MEMORY MAPPED)

CONTROL, STATUS &

DATA BUFFERS

I/O PROCESSOR

BLOCK 0

BLOCK 1

ADDR

IOA 17

DMA

CONTROLLER

SERIAL PORTS

(2)

LINK PORTS

(6)

JTAG

TEST &

EMULATION

EXTERNAL

PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

DATA BUS

MUX

HOST PORT

SHARC is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

Page 2

ADSP-21060C/ADSP-21060LC

DMA Controller

10 DMA Channels for Transfers Between ADSP-2106x

Internal Memory and External Memory, External Peripherals, Host Processor, Serial Ports, or Link Ports

Background DMA Transfers at 40 MHz, in Parallel with

Full-Speed Processor Execution

Host Processor Interface to 16- and 32-Bit Microprocessors

Host Can Directly Read/Write ADSP-2106x Internal

Memory

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3

ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4

ADSP-21060C/ADSP-21060LC FEATURES . . . . . . . . . . . 4

DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ADDITIONAL INFORMATION . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8

TARGET BOARD CONNECTOR FOR EZ-ICE

PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RECOMMENDED OPERATING CONDITIONS (5 V) . 13

ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 13

POWER DISSIPATION ADSP-21060C (5 V) . . . . . . . . . . 14

RECOMMENDED OPERATING CONDITIONS (3.3 V) 15

ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 15

POWER DISSIPATION ADSP-21060LC (3.3 V) . . . . . . . . 16

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20

Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21

Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22

Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24

Multiprocessor Bus Request and Host Bus Request . . . . . 25

Asynchronous Read/Write—Host to ADSP-2106x . . . . . . 27

Three-State Timing—Bus Master, Bus Slave,

HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Link Ports: 1 × CLK Speed Operation . . . . . . . . . . . . . . 32

Link Ports: 2 × CLK Speed Operation . . . . . . . . . . . . . . 33

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 38

OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 39

POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 42

240-LEAD METRIC CQFP PIN CONFIGURATIONS . . 43

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 45

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

FIGURES

Figure 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. ADSP-2106x System . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6

Figure 4. ADSP-21060C/ADSP-21060LC Memory Map . . . 7 Figure 5. Target Board Connector for ADSP-2106x

EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11

Figure 6. JTAG Scan Path Connections for Multiple

EZ-ICE is a registered trademark of Analog Devices, Inc.

Multiprocessing

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up to Six ADSP-2106xs Plus Host

Six Link Ports for Point-to-Point Connectivity and Array

Multiprocessing 240 Mbytes/s Transfer Rate Over Parallel Bus 240 Mbytes/s Transfer Rate Over Link Ports

Serial Ports

Two 40 Mbit/s Synchronous Serial Ports with

Companding Hardware Independent Transmit and Receive Functions

ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. JTAG Clocktree for Multiple ADSP-2106x

Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 20

Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 21

Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 23

Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 24

Figure 17. Multiprocessor Bus Request and Host Bus

Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27

Figure 18b. Asynchronous Read/Write—Host to

ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19a. Three-State Timing (Bus Transition Cycle,

SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19b. Three-State Timing (Host Transition Cycle) . . 29

Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31

Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 37

Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 38

Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 40

Figure 26. Equivalent Device Loading for AC Measurements

(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 27. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 40

Figure 28. ADSP-2106x Typical Drive Currents

= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 29. Typical Output Rise Time (10%–90% V

vs. Load Capacitance (V

= 5 V) . . . . . . . . . . . . . . . . . . . 41

)

Figure 30. Typical Output Rise Time (0.8 V–2.0 V)

vs. Load Capacitance (V

= 5 V) . . . . . . . . . . . . . . . . . . . 41

Figure 31. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (V

= 5 V) . . . . . . . . . 41

Figure 32. ADSP-2106x Typical Drive Currents

= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 33. Typical Output Rise Time (10%–90% V

vs. Load Capacitance (V

= 3.3 V) . . . . . . . . . . . . . . . . . 41

)

Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load

Capacitance (V

= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 35. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (V

= 3.3 V) . . . . . . . . 42

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Page 3

GENERAL DESCRIPTION

The ADSP-2106x SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. Table I shows performance benchmarks for the ADSP-2106x.

The ADSP-2106x SHARC represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory host processor interface,

ADSP-21060C/ADSP-21060LC

DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.

Figure 1 shows a block diagram of the ADSP-21060C/ ADSP-21060LC, illustrating the following architectural features:

Computation Units (ALU, Multiplier and Shifter) with a

Shared Data Register File Data Address Generators (DAG1, DAG2) Program Sequencer with Instruction Cache Interval Timer On-Chip SRAM External Port for Interfacing to Off-Chip Memory and

Peripherals Host Port and Multiprocessor Interface DMA Controller Serial Ports and Link Ports JTAG Test Access Port

Figure 2 shows a typical single-processor system. A multiprocessing system is shown in Figure 3.

Table I. ADSP-21060C/ADSP-21060LC Benchmarks (@ 40 MHz)

1024-Pt. Complex FFT 0.46 ms 18,221 cycles

(Radix 4, with Digit Reverse)

FIR Filter (per Tap) 25 ns 1 cycle IIR Filter (per Biquad) 100 ns 4 cycles Divide (y/x) 150 ns 6 cycles Inverse Square Root (1/√x) 225 ns 9 cycles DMA Transfer Rate 240 Mbytes/s

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ADSP-21060C/ADSP-21060LC

ADSP-21000 FAMILY CORE ARCHITECTURE

The ADSP-2106x includes the following architectural features of the ADSP-21000 family core. The ADSP-21060C is codeand function-compatible with the ADSP-21061 and ADSP-21062.

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter all perform single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit singleprecision floating-point, extended precision 40-bit floatingpoint, and 32-bit fixed-point data formats.

ADSP-2106x

DATA

ADDR

DATA

ADDR

DATA

PERIPHERALS

(OPTIONAL)

ACK

DMA DEVICE

(OPTIONAL)

DATA

PROCESSOR

INTERFACE

(OPTIONAL)

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

MEMORY

AND

HOST

1x CLOCK

LINK

DEVICES

(6 MAXIMUM)

(OPTIONAL)

SERIAL DEVICE

(OPTIONAL)

SERIAL DEVICE

(OPTIONAL)

3-0

BMS

ADDR

31-0

DATA

47-0

ACK

PAGE

SBTS

ADRCLK

DMAR1-2 DMAG1-2

CS HBR HBG

REDY

CPA

JTAG

ADDRESS

CONTROL

3-0

1-6

CLKIN EBOOT LBOOT

IRQ

2-0

FLAG

3-0

TIMEXP

LxCLK LxACK LxDAT

TCLK0 RCLK0 TFS0 RSF0 DT0 DR0

TCLK1 RCLK1 TFS1 RFS1 DT1 DR1

RPBA ID

2-0

RESET

Figure 2. ADSP-2106x System

Data Register File

A general purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP21000 Harvard architecture, allows unconstrained data flow between computation units and internal memory.

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-2106x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1). With its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle.

Instruction Cache

The ADSP-2106x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular Buffers

The ADSP-2106x’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-2106x contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP2106x can conditionally execute a multiply, an add, a subtract and a branch, all in a single instruction.

ADSP-21060C/ADSP-21060LC FEATURES

Augmenting the ADSP-21000 family core, the ADSP-21060 adds the following architectural features:

Dual-Ported On-Chip Memory

The ADSP-21060C contains four megabits of on-chip SRAM, organized as two blocks of 2 Mbits each, which can be configured for different combinations of code and data storage. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle.

On the ADSP-21060C, the memory can be configured as a maximum of 128K words of 32-bit data, 256K words of 16-bit data, 80K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. All of the memory can be accessed as 16-bit, 32-bit, or 48-bit words.

A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floatingpoint formats is done in a single instruction.

While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the ADSP2106x’s external port.

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ADSP-21060C/ADSP-21060LC

Off-Chip Memory and Peripherals Interface

The ADSP-2106x’s external port provides the processor’s interface to off-chip memory and peripherals. The 4-gigaword offchip address space is included in the ADSP-2106x’s unified address space. The separate on-chip buses—for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus.

Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-2106x provides programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold, and disable time requirements.

Host Processor Interface

The ADSP-2106x’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the processor are supported. The host interface is accessed through the ADSP-2106x’s external port and is memory-mapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead.

The host processor requests the ADSP-2106x’s external bus with the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-2106x, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands.

DMA Controller

The ADSP-2106x’s on-chip DMA controller allows zerooverhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions.

DMA transfers can occur between the ADSP-2106x’s internal memory and either external memory, external peripherals or a host processor. DMA transfers can also occur between the ADSP-2106x’s internal memory and its serial ports or link ports. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32-, or 48-bit words is performed during DMA transfers.

Ten channels of DMA are available on the ADSP-2106x—two via the link ports, four via the serial ports, and four via the processor’s external port (for either host processor, other ADSP-2106xs, memory or I/O transfers). Four additional link port DMA channels are shared with serial port 1 and the external port. Programs can be downloaded to the ADSP-2106x using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other DMA features include inter- rupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.

Serial Ports

The ADSP-2106x features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at the full clock rate of the processor, providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via DMA. Each of the serial ports offers TDM multichannel mode.

The serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated.

Multiprocessing

The ADSP-2106x offers powerful features tailored to multiprocessing DSP systems. The unified address space (see Figure 4) allows direct interprocessor accesses of each ADSP2106x’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-2106xs and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 240 Mbytes/s over the link ports or external port. Broadcast writes allow simultaneous transmission of data to all ADSP-2106xs and can be used to implement reflective semaphores.

Link Ports

The ADSP-2106x features six 4-bit link ports that provide additional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer eight bits per cycle. Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems.

The link ports can operate independently and simultaneously, with a maximum data throughput of 240 Mbytes/s. Link port data is packed into 32- or 48-bit words, and can be directly read by the core processor or DMA-transferred to on-chip memory.

Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive.

Program Booting

The internal memory of the ADSP-2106x can be booted at system power-up from either an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot source is controlled by the BMS (Boot Memory Select), EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit host processors can be used for booting.

REV. B

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Page 6

ADSP-21060C/ADSP-21060LC

ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4

011 ID

010

ADSP-2106x #3

ADDR

DATA

1-2

CLKIN

RESET

RPBA

2-0

CONTROL

ADSP-2106x #2

CLKIN

RESET

RPBA

2-0

CONTROL

ADDR

DATA

, BR

31-0

47-0

CPA

31-0

47-0

CPA

CONTROL

4-6

3-6

DATA

ADDRESS

CLOCK

RESET RESET

001

ADSP-2106x #1

CLKIN

RPBA

2-0

CONTROL

Figure 3. Shared Memory Multiprocessing System

ADDR

DATA

ACK

BMS

PAGE

SBTS

ADRCLK

HBR HBG

REDY

CPA

31-0

47-0

CONTROL

3-0

2-6

DATA

ADDRESS

ADDR

DATA

OE WE

ACK

ADDR

DATA

ADDR

DATA

GLOBAL

MEMORY

AND

PERIPHERALS

(OPTIONAL)

BOOT

EPROM

(OPTIONAL)

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

–6–

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Page 7

ADSP-21060C/ADSP-21060LC

INTERNAL

MEMORY

SPACE

MULTIPROCESSOR

MEMORY SPACE

NORMAL WORD ADDRESSING: 32-BIT DATA WORDS 48-BIT INSTRUCTION WORDS

SHORT WORD ADDRESSING: 16-BIT DATA WORDS

IOP REGISTERS

NORMAL WORD ADDRESSING

SHORT WORD ADDRESSING

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=001

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=010

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=011

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=100

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=101

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=110

BROADCAST WRITE

TO ALL

ADSP-2106xs

0x0000 0000

0x0002 0000

0x0004 0000

0x0008 0000

0x0010 0000

0x0018 0000

0x0020 0000

0x0028 0000

0x0030 0000

0x0038 0000

0x003F FFFF

EXTERNAL

MEMORY

SPACE

BANK 0

DRAM

(OPTIONAL)

BANK 1

BANK 2

BANK 3

NONBANKED

0x0040 0000

BANK SIZE IS SELECTED BY MSIZE BIT FIELD OF SYSCON REGISTER.

0xFFFF FFFF

Figure 4. ADSP-21060C/ADSP-21060LC Memory Map

DEVELOPMENT TOOLS

The ADSP-21060C is supported with a complete set of software and hardware development tools, including an EZ-ICE Circuit Emulator, EZ-Kit, and development software. The SHARC tion and prototyping. The EZ-Kit contains a PC plug-in card (EZ-LAB

EZ-Kit is a complete low cost package for DSP evalua-

) with an ADSP-21062 (5 V) processor. The EZ-Kit

In-

also includes an optimizing compiler, assembler, instruction level simulator, run-time libraries, diagnostic utilities and a complete set of example programs.

Analog Devices ADSP-21000 Family Development Software includes an easy to use Assembler based on an algebraic syntax, Assembly Library/Librarian, Linker, instruction-level Simulator, an ANSI C optimizing Compiler, the CBug™ C Source—Level Debugger and a C Runtime Library including DSP and mathematical functions. The ADSP-21000 Family Development Software is available for both the PC and Sun platforms.

The ADSP-2106x EZ-ICE

Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x processor to monitor and control the target board processor during emulation. The EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

Further details and ordering information are available in the

ADSP-21000 Family Hardware and Software Development Tools

data sheet (ADDS-210xx-TOOLS). This data sheet can be requested from any Analog Devices sales office or distributor.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC ware tools include SHARC SHARC

VME boards, and daughter and modules with multiple

PC plug-in cards multiprocessor

processor family. Hard-

SHARCs and additional memory. These modules are based on the SHARCPAC™ module specification. Third Party software tools include an Ada compiler, DSP libraries, operating systems and block diagram design tools.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21060C architecture and functionality. For detailed information on the ADSP-21000 Family core architecture and instruction set, refer to the ADSP-2106x SHARC User’s Manual, Second Edition.

CBUG and SHARCPAC are trademarks of Analog Devices, Inc. EZ-LAB is a registered trademark of Analog Devices, Inc.

REV. B

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Page 8

ADSP-21060C/ADSP-21060LC

PIN FUNCTION DESCRIPTIONS

ADSP-21060C pin definitions are listed below. All pins are identical on the ADSP-21060C and ADSP-21060LC. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDD or GND, except for ADDR

, DATA

31-0

, FLAG

47-0

, SW, and inputs that

3-0

DRx, TCLKx, RCLKx, LxDAT

, LxCLK, LxACK, TMS and

3-0

TDI)—these pins can be left floating. These pins have a logiclevel hold circuit that prevents the input from floating internally.

A = Asynchronous G = Ground I = Input O = Output P = Power Supply S = Synchronous (A/D) = Active Drive (O/D) = Open Drain T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

have internal pull-up or pull-down resistors (CPA, ACK, DTx,

Pin Type Function

ADDR

31-0

I/O/T External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on

these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal memory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.

DATA

47-0

I/O/T External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit

single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23–16. Pull-up resistors on unused DATA pins are not necessary.

3-0

O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of

external memory. Memory bank size must be defined in the ADSP-2106x’s system control register (SYSCON). The MS other address lines. When no external memory access is occurring the MS

lines are decoded memory address lines that change at the same time as the

3-0

lines are inactive; they are

3-0

active however when a conditional memory access instruction is executed, whether or not the condition is true. MS multiprocessing system the MS

can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a

lines are output by the bus master.

3-0

RD I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory

devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP2106xs) must assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system

RD is output by the bus master and is input by all other ADSP-2106xs.

WR I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory

devices or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to the ADSP-2106x’s internal memory. In a multiprocessing system WR is output by the bus master and is input by all other ADSP-2106xs.

PAGE O/T DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page

boundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.

ADRCLK O/T Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master. SW I/O/T Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous

memory devices (including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the ADSP-2106x(s).

ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external

memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add wait states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven.

–8–

REV. B

Page 9

ADSP-21060C/ADSP-21060LC

Pin Type Function

SBTS I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,

data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106x attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-2106x deadlock, or used with a DRAM controller.

IRQ

2-0

FLAG

3-0

TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to

HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP-2106x’s

HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take

CS I/A Chip Select. Asserted by host processor to select the ADSP-2106x.

REDY (O/D) O Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-

DMAR1 I/A DMA Request 1 (DMA Channel 7). DMAR2 I/A DMA Request 2 (DMA Channel 8). DMAG1 O/T DMA Grant 1 (DMA Channel 7). DMAG2 O/T DMA Grant 2 (DMA Channel 8). BR

6-1

2-0

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor

CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave

DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor. DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor. TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor. RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.

I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be

tested as a condition. As an output, it can be used to signal external peripherals.

zero.

external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests (BR

) in a multiprocessing system.

6-1

control of the external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.

nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.

I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-

ship. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID

inputs) and

2-0

monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.

I Multiprocessing ID. Determines which multiprocessing bus request (BR1 – BR6) is used by ADSP-

2106x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor systems. These lines are a system configuration selection which should be hardwired or only changed at reset.

bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.

to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to all ADSP-2106xs in the system. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.

REV. B

–9–

Page 10

ADSP-21060C/ADSP-21060LC

Pin Type Function

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).

RFSx I/O Receive Frame Sync (Serial Ports 0, 1).

LxDAT

LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is

LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor

EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-

LBOOT I Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When

BMS I/O/T* Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

CLKIN I Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN.

RESET I/A Processor Reset. Resets the ADSP-2106x to a known state and begins execution at the program

TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up

TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-

EMU (O/D) O Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.

ICSA O Reserved, leave unconnected.

VDD P Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).

GND G Power Supply Return. (30 pins).

NC Do Not Connect. Reserved pins which must be left open and unconnected.

3-0

I/O Link Port Data (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

that is enabled or disabled by the LPDRD bit of the LCOM register.

bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table below. This signal is a system configuration selection that should be hardwired.

LBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See table below. This signal is a system configuration selection that should be hardwired.

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This input is a system configuration selection that should be hardwired.

*Three-statable only in EPROM boot mode (when BMS is an output).

EBOOT LBOOT BMS Booting Mode

1 0 Output EPROM (Connect BMS to EPROM chip select.) 0 0 1 (Input) Host Processor 0 1 1 (Input) Link Port 0 0 0 (Input) No Booting. Processor executes from external memory. 0 1 0 (Input) Reserved 1 1 x (Input) Reserved

CLKIN may not be halted, changed, or operated below the minimum specified frequency.

memory location specified by the hardware reset vector address. This input must be asserted (low) at power-up.

resistor.

pull-up resistor.

up or held low for proper operation of the ADSP-2106x. TRST has a 20 kΩ internal pull-up resistor.

–10–

REV. B

Page 11

ADSP-21060C/ADSP-21060LC

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2 row × 7 pin strip header) such as that shown in Figure 5. The EZ-ICE

probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your target board design if you intend to use the ADSP-2106x EZ-ICE. The total trace length between the EZICE connector and the furthest device sharing the EZ-ICE JTAG pins should be limited to 15 inches maximum for guaranteed operation. This length restriction must include EZ-ICE JTAG signals that are routed to one or more ADSP-2106x devices, or a combination of ADSP-2106x devices and other JTAG devices on the chain.

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

910

11 12

13 14

TOP VIEW

EMU

CLKIN (OPTIONAL)

TMS

TCK

TRST

TDI

TDO

Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator (Jumpers in Place)

The 14-pin, 2-row pin strip header is keyed at the Pin 3 location — Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec.

The BTMS, BTCK, BTRST and BTDI signals are provided so the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the Bxxx pins and the xxx pins. If the test access port will not be used for board testing, tie BTRST to GND and tie or pull BTCK up to VDD. The TRST pin must be asserted after power-up (through BTRST on the connector) or held low for proper operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE

probe.

The JTAG signals are terminated on the EZ-ICE probe as follows:

Signal Termination

TMS Driven through 22 Ω Resistor (16 mA Driver) TCK Driven at 10 MHz through 22 Ω Resistor (16 mA

Driver)

TRST* Active Low Driven through 22 Ω Resistor (16 mA

Driver) (Pulled Up by On-Chip 20 kΩ Resistor)

TDI Driven by 22 Ω Resistor (16 mA Driver) TDO One TTL Load, Split Termination (160/220) CLKIN One TTL Load, Split Termination (160/220) EMU Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

*TRST is driven low until the EZ-ICE probe is turned on by the emulator at

software start-up. After software start-up, TRST is driven high.

Figure 6 shows JTAG scan path connections for systems that contain multiple ADSP-2106x processors.

REV. B

JTAG

DEVICE

(OPTIONAL)

TDI

TCK

TDO TDO

TMS

TRST

OTHER

JTAG

CONTROLLER

EZ-ICE

JTAG

CONNECTOR

EMU

TRST

TDO

CLKIN

TDI

TCK

TMS

ADSP-2106x

TDI

TCK

OPTIONAL

TMS

TDO

EMU

TRST

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

–11–

ADSP-2106x

TDI

TCK

TMS

EMU

TRST

Page 12

ADSP-21060C/ADSP-21060LC

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform operations such as starting, stopping and single-stepping multiple ADSP-21060 in a synchronous manner. If you do not need these operations to occur synchronously on the multiple processors, simply tie Pin 4 of the EZ-ICE

header to ground.

If synchronous multiprocessor operations are needed and CLKIN is connected, clock skew between the multiple ADSP-21060C/ ADSP-21060LC processors and the CLKIN pin on the EZ-ICE header must be minimal. If the skew is too large, synchronous operations may be off by one or more cycles between processors. For synchronous multiprocessor operation TCK, TMS,

TDI TDO TDI TDO

5k

TDI TDO

CLKIN and EMU should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. If TCK, TMS and CLKIN are driving a large number of ADSP-21060 (more than eight) in your system, then treat them as a clock tree using multiple drivers to minimize skew. (See Figure 7, JTAG Clock Tree, and Clock Distribution in the High Frequency Design Considerations section of the ADSP- 2106x User’s Manual, Second Edition.)

If synchronous multiprocessor operations are not needed (i.e., CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU, and TRST are not critical signals in terms of skew.

For complete information on the SHARC EZ-ICE, see the ADSP- 2100 Family JTAG EZ-ICE User’s Guide and Reference.

TDI TDO

TDI

EMU

TCK

TMS

TRST

TDO

CLKIN

5k

OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,

EMU

Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems

SYSTEM CLKIN

–12–

REV. B

Page 13

ADSP-21060C/ADSP-21060LC

ADSP-21060C–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS (5 V)

K Grade

Parameter Test Conditions Min Max Unit

CASE

IH1

IH2

NOTES

Applies to input and bidirectional pins: DATA CPA, TFS0, TFS1, RFS0, RFS1, LxDAT

Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (5 V)

Parameter Test Conditions Min Max Unit

ILP

OZH

OZL

OZHP

OZLC

OZLA

OZLAR

OZLS

NOTES

Applies to output and bidirectional pins: DATA DMAG2, BR

See “Output Drive Currents” for typical drive current capabilities.

Applies to input pins: SBTS, IRQ

Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

Applies to three-statable pins: DATA TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID not requesting bus mastership.)

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

Applies to CPA pin.

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID ADSP-21060 is not requesting bus mastership).

Applies to three-statable pins with internal pull-downs: LxDAT

Applies to ACK pin when keeper latch enabled.

Applies to all signal pins.

Guaranteed but not tested.

Specifications subject to change without notice.

Supply Voltage 4.75 5.25 V Case Operating Temperature –40 +100 °C High Level Input Voltage High Level Input Voltage Low Level Input Voltage

High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Input Capacitance

, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT

6-1

11, 12

, HBR, CS, DMAR1, DMAR2, ID

2-0

47-0

1, 2

, ADDR

47-0

, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

3-0

3, 4

5, 6, 7, 8

5, 9

, ADDR

47-0

, ADDR

31-0

, MS

@ VDD = max 2.0 VDD + 0.5 V @ VDD = max 2.2 VDD + 0.5 V @ VDD = min –0.5 +0.8 V

, RD, WR, SW, ACK, SBTS, IRQ

31-0

@ VDD = min, IOH = –2.0 mA @ VDD = min, IOL = 4.0 mA @ VDD = max, VIN = V

, FLAG

2-0

max 10 µA

, HBG, CS, DMAR1, DMAR2, BR

3-0

4.1 V

6-1

0.4 V

@ VDD = max, VIN = 0 V 10 µA @ VDD = max, VIN = 0 V 150 µA @ VDD = max, VIN = V

max 10 µA

@ VDD = max, VIN = 0 V 10 µA @ VDD = max, VIN = V

max 350 µA

@ VDD = max, VIN = 0 V 1.5 mA @ VDD = max, VIN = 1.5 V 350 µA @ VDD = max, VIN = 0 V 4.2 mA @ VDD = max, VIN = 0 V 150 µA fIN = 1 MHz, T

, MS

31-0

, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG

3-0

, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG

3-0

, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

2-0

, LxCLK, LxACK.

3-0

= 25°C, VIN = 2.5 V 4.7 pF

CASE

, TIMEXP, HBG, REDY, DMAG1,

3-0

, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

3-0

, REDY, HBG, DMAG1, DMAG2, BMS, BR

3-0

= 001 and another ADSP-21060 is

2-0

= 001 and another

2-0

, ID

, RPBA,

2-0

6–1

REV. B

–13–

Page 14

ADSP-21060C/ADSP-21060LC

POWER DISSIPATION ADSP-21060C (5 V)

These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation Peak Activity (I

DDINPEAK

) High Activity (I

DDINHIGH

) Low Activity (I

DDINLOW

)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None

Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state:

%PEAK × I

DDINPEAK

+ %HIGH × I

DDINHIGH

+ %LOW × I

DDINLOW

+ %IDLE × I

= power consumption

DDIDLE

Parameter Test Conditions Max Unit

DDINPEAK

Supply Current (Internal)

tCK = 30 ns, VDD = max 745 mA tCK = 25 ns, VDD = max 850 mA

DDINHIGH

Supply Current (Internal)

tCK = 30 ns, VDD = max 575 mA tCK = 25 ns, VDD = max 670 mA

DDINLOW

Supply Current (Internal)

tCK = 30 ns, VDD = max 340 mA tCK = 25 ns, VDD = max 390 mA

DDIDLE

NOTES

The test program used to measure I power measurements made using typical applications are less than specified.

Idle denotes ADSP-21060C state during execution of IDLE instruction.

is a composite average based on a range of high activity code. I

DDINHIGH

Supply Current (Idle)

DDINPEAK

represents worst case processor operation and is not sustainable under normal application conditions. Actual internal

VDD = max 200 mA

is a composite average based on a range of low activity code.

DDINLOW

–14–

REV. B

Page 15

ADSP-21060C/ADSP-21060LC

ADSP-21060LC–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS (3.3 V)

K Grade

Parameter Test Conditions Min Max Unit

CASE

IH1

IH2

NOTES

Applies to input and bidirectional pins: DATA CPA, TFS0, TFS1, RFS0, RFS1, LxDAT RCLK1.

Applies to input pins: CLKIN, RESET, TRST.

Supply Voltage 3.15 3.45 V Case Operating Temperature –40 +100 °C High Level Input Voltage High Level Input Voltage Low Level Input Voltage

1, 2

, ADDR

47-0

, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0,

3-0

@ VDD = max 2.0 VDD + 0.5 V @ VDD = max 2.2 VDD + 0.5 V @ VDD = min –0.5 0.8 V

, RD, WR, SW, ACK, SBTS, IRQ

31-0

, FLAG

2-0

, HBG, CS, DMAR1, DMAR2, BR

3-0

, ID

6-1

2-0

, RPBA,

ELECTRICAL CHARACTERISTICS (3.3 V)

Parameter Test Conditions Min Max Unit

ILP

OZH

OZL

OZHP

OZLC

OZLA

OZLAR

OZLS

NOTES

Applies to output and bidirectional pins: DATA

DMAG2, BR

See “Output Drive Currents” for typical drive current capabilities.

Applies to input pins: ACK SBTS, IRQ

Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

Applies to three-statable pins: DATA TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID is not requesting bus mastership.)

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

Applies to CPA pin.

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID ADSP-21060LC is not requesting bus mastership).

Applies to three-statable pins with internal pull-downs: LxDAT

Applies to ACK pin when keeper latch enabled.

Applies to all signal pins.

Guaranteed but not tested.

Specifications subject to change without notice.

, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT

6-1

11, 12

47-0

3, 4

5, 6, 7, 8

5, 9

@ VDD = min, IOH = –2.0 mA @ VDD = min, IOL = 4.0 mA @ VDD = max, VIN = V @ VDD = max, VIN = 0 V 10 µA @ VDD = max, VIN = 0 V 150 µA @ VDD = max, VIN = V @ VDD = max, VIN = 0 V 10 µA @ VDD = max, VIN = V @ VDD = max, VIN = 0 V 1.5 mA @ VDD = max, VIN = 2 V 350 µA @ VDD = max, VIN = 0 V 4.2 mA @ VDD = max, VIN = 0 V 150 µA fIN = 1 MHz, T

, ADDR

47-0

, HBR, CS, DMAR1, DMAR2, ID

2-0

, ADDR

31-0

, MS

31-0

, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG

3-0

, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG

3-0

, LxCLK, LxACK.

3-0

= 25°C, VIN = 2.5 V 4.7 pF

CASE

, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

2-0

max 10 µA

max 350 µA

, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

3-0

, REDY, HBG, DMAG1, DMAG2, BMS, BR

3-0

2.4 V

0.4 V

, TIMEXP, HBG, REDY, DMAG1,

3-0

= 001 and another ADSP-21060LC

2-0

= 001 and another

2-0

6–1

REV. B

–15–

Page 16

ADSP-21060C/ADSP-21060LC

POWER DISSIPATION ADSP-21060LC (3.3 V)

Specifications are based on the following operating scenarios:

Operation Peak Activity (I

DDINPEAK

) High Activity (I

DDINHIGH

) Low Activity (I

DDINLOW

)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None

Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state:

%PEAK × I

DDINPEAK

+ %HIGH × I

DDINHIGH

+ %LOW × I

DDINLOW

+ %IDLE × I

= power consumption

DDIDLE

Parameter Test Conditions Max Unit

DDINPEAK

Supply Current (Internal)

tCK = 30 ns, VDD = max 540 mA tCK = 25 ns, VDD = max 600 mA

DDINHIGH

Supply Current (Internal)

tCK = 30 ns, VDD = max 425 mA tCK = 25 ns, VDD = max 475 mA

DDINLOW

Supply Current (Internal)

tCK = 30 ns, VDD = max 250 mA tCK = 25 ns, VDD = max 275 mA

DDIDLE

NOTES

The test program used to measure I

power measurements made using typical applications are less than specified.

Idle denotes ADSP-21060LC state during execution of IDLE instruction.

is a composite average based on a range of high activity code. I

DDINHIGH

Supply Current (Idle)

DDINPEAK

represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal

VDD = max 180 mA

is a composite average based on a range of low activity code.

DDINLOW

–16–

REV. B

Page 17

ADSP-21060C/ADSP-21060LC

ABSOLUTE MAXIMUM RATINGS (5 V)*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . 280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21060C/ADSP-21060LC features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS (3.3 V)*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . 280°C

*Stresses greater than those listed above may cause permanent damage to the

WARNING!

ESD SENSITIVE DEVICE

+ 0.5 V

TIMING SPECIFICATIONS

Two speed grades of the ADSP-21060C are offered, 40 MHz and 33.3 MHz. The specifications shown are based on a CLKIN frequency of 40 MHz (t allows specifications at other CLKIN frequencies (within the min–max range of the t

specification; see Clock Input below).

DT is the difference between the actual CLKIN period and a CLKIN period of 25 ns:

DT = t

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.

= 25 ns). The DT derating

– 25 ns

See Figure 28 under Test Conditions for voltage reference levels.

Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

(O/D) = Open Drain (A/D) = Active Drive

REV. B

–17–

Page 18

ADSP-21060C/ADSP-21060LC

ADSP-21060C ADSP-21060LC

40 MHz 33 MHz 40 MHz 33 MHz

Parameter Min Max Min Max Min Max Min Max Unit

Clock Input

Timing Requirements:

CKL

CKH

CKRF

Parameter Min Max Min Max Unit

Reset

Timing Requirements:

WRST

SRST

NOTES

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.

CLKIN Period 25 100 30 100 25 100 30 100 ns CLKIN Width Low 7 7 9.5 9.5 ns CLKIN Width High 5555ns CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 3 3 ns

CLKIN

CKH

CKL

Figure 8. Clock Input

ADSP-21060C ADSP-21060LC

RESET Pulsewidth Low RESET Setup before CLKIN High

14 + DT/2 t

ns ns

CLKIN

SRST

RESET

WRST

Figure 9. Reset

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Interrupts

Timing Requirements:

SIR

HIR

IPW

NOTES

Only required for IRQx recognition in the following cycle.

Applies only if t

IRQ2-0 Setup before CLKIN High IRQ2-0 Hold before CLKIN High IRQ2-0 Pulsewidth

and t

SIR

requirements are not met.

HIR

CLKIN

IRQ2-0

18 + 3DT/4 18 + 3DT/4 ns

12 + 3DT/4 12 + 3DT/4 ns

2 + t

IPW

SIR

HIR

2 + t

Figure 10. Interrupts

–18–

REV. B

Page 19

ADSP-21060C/ADSP-21060LC

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timer

Switching Characteristic:

DTEX

Parameter Min Max Min Max Unit

Flags

Timing Requirements:

SFI

HFI

DWRFI

HFIWR

CLKIN High to TIMEXP 15 15 ns

CLKIN

DTEX

TIMEXP

DTEX

Figure 11. Timer

ADSP-21060C ADSP-21060LC

FLAG3-0 FLAG3-0 FLAG3-0 FLAG3-0

Setup before CLKIN High

Hold after CLKIN High

Delay after RD/WR Low

Hold after RD/WR Deasserted100 ns

8 + 5DT/16 8 + 5DT/16 ns 0 – 5DT/16 0 – 5DT/16 ns

5 + 7DT/16 5 + 7DT/16 ns

Switching Characteristics:

DFO

HFO

DFOE

DFOD

NOTE

Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.

FLAG3-0

RD, WR

FLAG3-0 FLAG3-0 CLKIN High to FLAG3-0 CLKIN High to FLAG3-0

CLKIN

DFOE

OUT

CLKIN

Delay after CLKIN High 16 16 ns

OUT

Hold after CLKIN High 4 4 ns

OUT

DWRFI

FLAG INPUT

Enable 3 3 ns

OUT

Disable 14 14 ns

OUT

DFO

FLAG OUTPUT

HFIWR

HFI

SFI

DFO

HFO

Figure 12. Flags

DFOD

REV. B

–19–

Page 20

ADSP-21060C/ADSP-21060LC

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is

characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write – Bus Master below). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).

the bus master accessing external memory space. These switching

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

DAD

DRLD

HDA

HDRH

DAAK

DSAK

Address, Selects Delay to Data Valid RD Low to Data Valid Data Hold from Address, Selects Data Hold from RD High ACK Delay from Address, Selects ACK Delay from RD Low

1, 2

2, 4

0.5 0.5 ns

2.0 2.0 ns

18 + DT + W 18 + DT + W ns 12 + 5DT/8 + W 12 + 5DT/8 + W ns

14 + 7DT/8 + W 14 + 7DT/8 + W ns 8 + DT/2 + W 8 + DT/2 + W ns

Switching Characteristics:

DRHA

DARL

RWR

SADADC

W = (number of wait states specified in WAIT register) × t HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

NOTES

Data Delay/Setup: User must meet t

The falling edge of MSx, SW, BMS is referenced.

Data Hold: User must meet t

given capacitive and dc loads.

ACK Delay/Setup: User must meet t

tion of ACK (High).

Address, Selects Hold after RD High 0 + H 0 + H ns Address, Selects to RD Low

2 + 3DT/8 2 + 3DT/8 ns

RD Pulsewidth 12.5 + 5DT/8 + W 12.5 + 5DT/8 + W ns RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI 8 + 3DT/8 + HI ns

Address, Selects Setup before ADRCLK High

HDA

or t

DAD

DRLD

or t

or synchronous spec t

HDRH

or t

DAAK

0 + DT/4 0 + DT/4 ns

CK.

or synchronous spec t

or synchronous specification t

DSAK

SSDATI

. See System Hold Time Calculation under Test Conditions for the calculation of hold times

HSDATI

for deassertion of ACK (Low), all three specifications must be met for asser-

SACKC

ADDRESS

MSx, SW

BMS

DATA

ACK

WR, DMAG

ADRCLK

(OUT)

SADADC

DARL

DRLD

DAD

DAAK

DSAK

Figure 13. Memory Read—Bus Master

HDRH

DRHA

HDA

RWR

–20–

REV. B

Page 21

ADSP-21060C/ADSP-21060LC

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is

characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write–Bus Master). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).

the bus master accessing external memory space. These switching

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

DAAK

DSAK

ACK Delay from Address, Selects ACK Delay from WR Low

1, 2

14 + 7DT/8 + W 14 + 7DT/8 + W ns 8 + DT/2 + W 8 + DT/2 + W ns

Switching Characteristics:

DAWH

DAWL

DDWH

DWHA

DATRWH

WWR

DDWR

WDE

SADADC

W = (number of wait states specified in WAIT register) × tCK. H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOTES

ACK Delay/Setup: User must meet t

tion of ACK (High).

The falling edge of MSx, SW, BMS is referenced.

See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

Address, Selects to WR Deasserted217 + 15DT/16 + W 17 + 15DT/16 + W ns Address, Selects to WR Low

3 + 3DT/8 3 + 3DT/8 ns

WR Pulsewidth 12 + 9DT/16 + W 12 + 9DT/16 + W ns Data Setup before WR High 7 + DT/2 + W 7 + DT/2 + W ns Address Hold after WR Deasserted 0.5 + DT/16 + H 0.5 + DT/16 + H ns Data Disable after WR Deasserted

1 + DT/16 + H 6 + DT/16 + H 1 + DT/16 + H 6 + DT/16 + H ns

WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H 8 + 7DT/16 + H ns Data Disable before WR or RD Low 5 + 3DT/8 + I 5 + 3DT/8 + I ns WR Low to Data Enabled –1 + DT/16 –1 + DT/16 ns Address, Selects to ADRCLK High20 + DT/4 0 + DT/4 ns

or t

DAAK

or synchronous specification t

DSAK

for deassertion of ACK (Low), all three specifications must be met for asser-

SACKC

ADDRESS

MSx , SW

BMS

DATA

ACK

RD , DMAG

ADRCLK

(OUT)

SADADC

DAWL

DAWH

WDE

DSAK

DAAK

Figure 14. Memory Write—Bus Master

DDWH

DATRWH

DWHA

WWR

DDWR

REV. B

–21–

Page 22

ADSP-21060C/ADSP-21060LC

Synchronous Read/Write—Bus Master

Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asyn-

When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-2106x must also meet these (bus master) timing

requirements for data and acknowledge setup and hold times. chronous memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

SSDATI

HSDATI

DAAK

SACKC

HACK

Data Setup before CLKIN 3 + DT/8 3 + DT/8 ns Data Hold after CLKIN 3.5 – DT/8 3.5 – DT/8 ns ACK Delay after Address, MSx, SW, BMS ACK Setup before CLKIN

1, 2

6.5 + DT/4 6.5 + DT/4 ns

14 + 7 DT/8 + W 14 + 7 DT/8 + W ns

ACK Hold after CLKIN –1 – DT/4 –1 – DT/4 ns

Switching Characteristics:

DADRO

HADRO

Address, MSx, BMS, SW Delay after CLKIN

Address, MSx, BMS, SW Hold

7 – DT/8 7 – DT/8 ns

after CLKIN –1 – DT/8 –1 – DT/8 ns

DPGC

DRDO

DWRO

DRWL

SDDATO

DATTR

DADCCK

ADRCK

ADRCKH

ADRCKL

W = (number of Wait states specified in WAIT register) × tCK.

NOTES

The falling edge of MSx, SW, BMS is referenced.

ACK Delay/Setup: User must meet t

of ACK (High).

See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

PAGE Delay after CLKIN 9 + DT/8 16 + DT/8 9 + DT/8 16 + DT/8 ns

RD High Delay after CLKIN –2 – DT/8 4 – DT/8 –2 – DT/8 4 – DT/8 ns WR High Delay after CLKIN –3 – 3DT/16 4 – 3DT/16 –3 – 3DT/16 4 – 3DT/16 ns RD/WR Low Delay after CLKIN 8 + DT/4 12.5 + DT/4 8 + DT/4 12.5 + DT/4 ns

Data Delay after CLKIN 19 + 5DT/16 19.25 + 5DT/16 ns Data Disable after CLKIN

0 – DT/8 7 – DT/8 0 – DT/8 7 – DT/8 ns ADRCLK Delay after CLKIN 4 + DT/8 10 + DT/8 4 + DT/8 10 + DT/8 ns ADRCLK Period t

ns ADRCLK Width High (tCK/2 – 2) (tCK/2 – 2) ns ADRCLK Width Low (tCK/2 – 2) (tCK/2 – 2) ns

or t

DAAK

or synchronous specification t

DSAK

for deassertion of ACK (Low), all three specifications must be met for assertion

SACKC

–22–

REV. B

Page 23

CLKIN

ADRCLK

ADDRESS

MSx, SW

PAGE

ACK

(IN)

READ CYCLE

DATA

(IN)

DADRO

DADCCK

DPGC

DRWL

DAAK

ADRCKH

ADSP-21060C/ADSP-21060LC

ADRCK

SACKC

SSDATI

HADRO

HACK

HSDATI

ADRCKL

DRDO

WRITE CYCLE

DATA (OUT)

DRWL

SDDATO

Figure 15. Synchronous Read/Write—Bus Master

DWRO

DATTR

REV. B

–23–

Page 24

ADSP-21060C/ADSP-21060LC

Synchronous Read/Write—Bus Slave

Use these specifications for ADSP-2106x bus master accesses of

memory space). The bus master must meet these (bus slave) timing requirements.

a slave’s IOP registers or internal memory (in multiprocessor

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

SADRI

HADRI

SRWLI

HRWLI

RWHPI

SDATWH

HDATWH

Address, SW Setup before CLKIN 15 + DT/2 15 + DT/2 ns Address, SW Hold before CLKIN 5 + DT/2 5 + DT/2 ns RD/WR Low Setup before CLKIN

9.5 + 5DT/16 9.5 + 5DT/16 ns

RD/WR Low Hold after CLKIN –3.5 – 5DT/16 8 + 7DT/16 –3.75 – 5DT/16 8 + 7DT/16 ns RD/WR Pulse High 3 3 ns

Data Setup before WR High 5 5 ns Data Hold after WR High 1 1 ns

Switching Characteristics:

SDDATO

DATTR

DACKAD

ACKTR

NOTES

SRWLI

= 4 + DT/8.

See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

DACKAD

setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t

Data Delay after CLKIN 19 + 5DT/16 19.25 + 5DT/16 ns Data Disable after CLKIN ACK Delay after Address, SW ACK Disable after CLKIN

(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t

0 – DT/8 7 – DT/8 0 – DT/8 7 – DT/8 ns

99ns

–1 – DT/8 6 – DT/8 –1 – DT/8 6 – DT/8 ns

(min)

SRWLI

is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have

ACKTR

CLKIN

ADDRESS

ACK

READ ACCESS

DATA

(OUT)

WRITE ACCESS

DATA

(IN)

SDDATO

DACKAD

SADRI

SRWLI

HADRI

SDATWH

Figure 16. Synchronous Read/Write—Bus Slave

HRWLI

HDATWH

DATTR

ACKTR

RWHPI

–24–

REV. B

Page 25

ADSP-21060C/ADSP-21060LC

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between multiprocessing ADSP-2106xs (BRx) or a host processor (HBR, HBG).

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

HBGRCSV

SHBRI

HHBRI

SHBGI

HHBGI

SBRI

HBRI

SRPBAI

HRPBAI

HBG Low to RD/WR/CS Valid HBR Setup before CLKIN HBR Hold before CLKIN HBG Setup before CLKIN 13 + DT/2 13 + DT/2 ns HBG Hold before CLKIN High 6 + DT/2 6 + DT/2 ns BRx, CPA Setup before CLKIN BRx, CPA Hold before CLKIN High 6 + DT/2 6 + DT/2 ns

RPBA Setup before CLKIN 21 + 3DT/4 21 + 3DT/4 ns RPBA Hold before CLKIN 12 + 3DT/4 12 + 3DT/4 ns

Switching Characteristics:

DHBGO

HHBGO

DBRO

HBRO

DCPAO

TRCPA

DRDYCS

TRDYHG

HBG Delay after CLKIN 7 – DT/8 7 – DT/8 ns HBG Hold after CLKIN –2 – DT/8 –2 – DT/8 ns BRx Delay after CLKIN 7 – DT/8 7 – DT/8 ns BRx Hold after CLKIN –2 – DT/8 –2 – DT/8 ns CPA Low Delay after CLKIN 8 – DT/8 8.5 – DT/8 ns CPA Disable after CLKIN –2 – DT/8 4.5 – DT/8 –2 – DT/8 4.5 – DT/8 ns

REDY (O/D) or (A/D) Low from CS and HBR Low

REDY (O/D) Disable or REDY (A/D) High from HBG

ARDYTR

REDY (A/D) Disable from CS or HBR High

20 + 3DT/4 20 + 3DT/4 ns

13 + DT/2 13 + DT/2 ns

20+ 5DT/4 20+ 5DT/4 ns

14 + 3DT/4 14 + 3DT/4 ns

8.5 11.0 ns

40 + 23DT/16 40 + 23DT/16 ns

10 10 ns

NOTES

For first asynchronous access after HBR and CS asserted, ADDR

low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition.

Only required for recognition in the current cycle.

CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.

(O/D) = open drain, (A/D) = active drive.

must be a non-MMS value 1/2 tCK before RD or WR goes low or by t

31-0

HBGRCSV

after HBG goes

REV. B

–25–

Page 26

ADSP-21060C/ADSP-21060LC

CLKIN

SHBRI

HBR

HBG

(OUT)

BRx

(OUT)

CPA (OUT)

(O/D)

HBG (IN)

BRx (IN)

CPA (IN) (O/D)

RPBA

SRPBAI

HHBRI

HHBGO

HRPBAI

HBRO

DHBGO

DBRO

DCPAO

SHBGI

SBRI

HHBGI

HBRI

TRCPA

HBR

AND

REDY (O/D)

REDY (A/D)

HBG (OUT)

DRDYCS

RD WR CS

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 17. Multiprocessor Bus Request and Host Bus Request

HBGRCSV

TRDYHG

ARDYTR

–26–

REV. B

Page 27

ADSP-21060C/ADSP-21060LC

Asynchronous Read/Write—Host to ADSP-2106x

Use these specifications for asynchronous host processor accesses of an ADSP-2106x, after the host has asserted CS and HBR

drive the RD and WR pins to access the ADSP-2106x’s internal memory or IOP registers. HBR and HBG are assumed low for this timing.

(low). After HBG is returned by the ADSP-2106x, the host can

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Read Cycle

Timing Requirements:

SADRDL

HADRDH

WRWH

DRDHRDY

Address Setup/CS Low before RD Low Address Hold/CS Hold Low after RD 00ns

RD/WR High Width 6 6 ns RD High Delay after REDY (O/D) Disable 0 0 ns RD High Delay after REDY (A/D) Disable 0 0 ns

00ns

Switching Characteristics:

SDATRDY

DRDYRDL

RDYPRD

Data Valid before REDY Disable from Low 2 2 ns REDY (O/D) or (A/D) Low Delay after RD Low 10 12.5 ns REDY (O/D) or (A/D) Low Pulsewidth for Read 45 + 21DT/16 45 + 21DT/16 ns

HDARWH

Data Disable after RD High 2 8 2 8.5 ns

Write Cycle

Timing Requirements:

SCSWRL

HCSWRH

SADWRH

HADWRH

WWRL

WRWH

DWRHRDY

CS Low Setup before WR Low 0 0 ns CS Low Hold after WR High 0 0 ns

Address Setup before WR High 5 5 ns Address Hold after WR High 2 2 ns

WR Low Width 7 7 ns RD/WR High Width 6 6 ns WR High Delay after REDY

(O/D) or (A/D) Disable 0 0 ns

SDATWH

HDATWH

Data Setup before WR High 5 5 ns Data Hold after WR High 1 1 ns

Switching Characteristics:

DRDYWRL

REDY (O/D) or (A/D) Low Delay after WR/CS Low 10 12.5 ns

RDYPWR

REDY (O/D) or (A/D) Low Pulsewidth for Write 15 + 7DT/16 15 + 7DT/16 ns

SRDYCK

NOTE

Not required if RD and address are valid t or WR goes low or by t sor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition.

REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 1 + 7DT/16 8 + 7DT/16 ns

after HBG goes low. For first access after HBR asserted, ADDR

after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-

HBGRCSV

CLKIN

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 18a. Synchronous REDY Timing

SRDYCK

must be a non-MMS value 1/2 t

31-0

before RD

CLK

REV. B

–27–

Page 28

ADSP-21060C/ADSP-21060LC

READ CYCLE

ADDRESS/CS

SADRDL

DATA (OUT)

REDY (O/D)

REDY (A/D)

WRITE CYCLE

ADDRESS

SCSWRL

DRDYRDL

SDATRDY

RDYPRD

DRDHRDY

SADWRH

HCSWRH

HDARWH

HADWRH

HADRDH

WRWH

DATA (IN)

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x

DRDYWRL

WWRL

RDYPWR

SDATWH

DWRHRDY

HDATWH

WRWH

–28–

REV. B

Page 29

ADSP-21060C/ADSP-21060LC

Three-State Timing—Bus Master, Bus Slave, HBR, SBTS

These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

STSCK

HTSCK

SBTS Setup before CLKIN 12 + DT/2 12 + DT/2 ns SBTS Hold before CLKIN 6 + DT/2 6 + DT/2 ns

Switching Characteristics:

MIENA

MIENS

MIENHG

MITRA

MITRS

MITRHG

DATEN

DATTR

ACKEN

ACKTR

ADCEN

ADCTR

MTRHBG

MENHBG

Address/Select Enable after CLKIN –1.5 – DT/8 –1.25 – DT/8 ns Strobes Enable after CLKIN

–1.5 – DT/8 –1.5 – DT/8 ns

HBG Enable after CLKIN –1.5 – DT/8 –1.5 – DT/8 ns Address/Select Disable after CLKIN 0 – DT/4 0.25 – DT/4 ns Strobes Disable after CLKIN HBG Disable after CLKIN 2.0 – DT/4 2.0 – DT/4 ns Data Enable after CLKIN Data Disable after CLKIN ACK Enable after CLKIN ACK Disable after CLKIN

9 + 5DT/16 9 + 5DT/16 ns 0 – DT/8 7 – DT/8 0 – DT/8 7 – DT/8 ns

7.5 + DT/4 7.5 + DT/4 ns –1 – DT/8 6 – DT/8 –1 – DT/8 6 – DT/8 ns

1.5 – DT/4 1.5 – DT/4 ns

ADRCLK Enable after CLKIN –2 – DT/8 –2 – DT/8 ns ADRCLK Disable after CLKIN 8 – DT/4 8 – DT/4 ns Memory Interface Disable before HBG Low Memory Interface Enable after HBG High

0 + DT/8 0 + DT/8 ns

19 + DT 19 + DT ns

NOTES

Strobes = RD, WR, SW, PAGE, DMAG.

In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).

CLKIN

STSCK

SBTS

MIENA, tMIENS, tMIENHG

MEMORY

INTERFACE

DATA

ACK

ADRCLK

ADCEN

DATEN

ACKEN

Figure 19a. Three-State Timing (Bus Transition Cycle,

HTSCK

MITRA, tMITRS, tMITRHG

DATTR

ACKTR

ADCTR

SBTS

Assertion)

REV. B

HBG

MEMORY

INTERFACE

MENHBG

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 19b. Three-State Timing (Host Transition Cycle)

–29–

MTRHBG

Page 30

ADSP-21060C/ADSP-21060LC

DMA Handshake

These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR

, RD, WR, SW, PAGE, MS

31-0

3-0

transfer is controlled by ADDR (not DMAG). For Paced Master mode, the Memory Read–Bus Master, Memory Write–Bus Master, and Synchronous Read/ Write–Bus Master timing specifications for ADDR

, SW, PAGE, DATA

3-0

, RD, WR, MS

31-0

, and ACK also apply.

47-0

, and ACK

3-0

, RD, WR,

31-0

ACK, and DMAG signals. For Paced Master mode, the data

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

SDRLC

SDRHC

WDR

SDATDGL

HDATIDG

DATDRH

DMARLL

DMARH

DMARx Low Setup before CLKIN155ns DMARx High Setup before CLKIN155ns DMARx Width Low

(Nonsynchronous) 6 6 ns Data Setup after DMAGx Low Data Hold after DMAGx High 2 2 ns Data Valid after DMARx High

10 + 5DT/8 10 + 5DT/8 ns

16 + 7DT/8 16 + 7DT/8 ns

DMARx Low Edge to Low Edge 23 + 7DT/8 23 + 7DT/8 ns DMARx Width High 6 6 ns

Switching Characteristics:

DDGL

WDGH

WDGL

HDGC

VDATDGH

DATRDGH

DGWRL

DGWRH

DGWRR

DGRDL

DRDGH

DGRDR

DGWR

DMAGx Low Delay after CLKIN 9 + DT/4 15 + DT/4 9 + DT/4 15 + DT/4 ns DMAGx High Width 6 + 3DT/8 6 + 3DT/8 ns DMAGx Low Width 12 + 5DT/8 12 + 5DT/8 ns DMAGx High Delay after CLKIN –2 – DT/8 6 – DT/8 –2 – DT/8 6 – DT/8 ns

Data Valid before DMAGx High Data Disable after DMAGx High

8 + 9DT/16 8 + 9DT/16 ns

070 7ns

WR Low before DMAGx Low 0 2 0 2 ns DMAGx Low before WR High 10 + 5DT/8 + W 10 + 5DT/8 + W ns WR High before DMAGx High 1 + DT/16 3 + DT/16 1 + DT/16 3 + DT/16 ns RD Low before DMAGx Low 0 2 0 2 ns RD Low before DMAGx High 11 + 9DT/16 + W 11 + 9DT/16 + W ns RD High before DMAGx High 0 3 0 3 ns DMAGx High to WR, RD, DMAGx

Low 5 + 3DT/8 + HI 5 + 3DT/8 + HI ns

DADGH

DDGHA

Address/Select Valid to DMAGx High 17 + DT 17 + DT ns Address/Select Hold after DMAGx High –0.5 –0.5 ns

W = (number of wait states specified in WAIT register) × tCK. HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

NOTES

Only required for recognition in the current cycle.

is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the

SDATDGL

data can be driven t

is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t

VDATDGH

n equals the number of extra cycles that the access is prolonged.

See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

after DMARx is brought high.

DATDRH

= 8 + 9DT/16 + (n × tCK) where

VDATDGH

–30–

REV. B

Page 31

ADSP-21060C/ADSP-21060LC

CLKIN

SDRLC

DMARx

DATA (FROM

ADSP-2106x TO

EXTERNAL DRIVE)

DATA (FROM

EXTERNAL DRIVE

TO ADSP-2106x)

WDR

SDRHC

DMARH

DMARLL

HDGC

WDGH

DDGL

WDGL

DMAGx

VDATDGH

DATDRH

DATRDGH

HDATIDG

DGWRL

DGWRH

DGWRR

DGRDL

DRDGH

DGRDR

SDATDGL

MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER

TIMING SPECIFICATIONS FOR ADDR

31-0

, RD, WR, SW, MS

3-0

AND ACK ALSO APPLY HERE.

(EXTERNAL DEVICE

TO EXTERNAL

MEMORY)

(EXTERNAL

MEMORY TO

EXTERNAL DEVICE)

TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE

TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

DDGHA

ADDRESS

MSx, SW

DADGH

Figure 20. DMA Handshake Timing

REV. B

–31–

Page 32

ADSP-21060C/ADSP-21060LC

Link Ports: 1  CLK Speed Operation

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Receive

Timing Requirements:

SLDCL

HLDCL

LCLKIW

LCLKRWL

LCLKRWH

Switching Characteristics:

DLAHC

DLALC

ENDLK

TDLK

Transmit

Timing Requirements:

SLACH

HLACH

Switching Characteristics:

DLCLK

DLDCH

HLDCH

LCLKTWL

LCLKTWH

DLACLK

ENDLK

TDLK

Data Setup before LCLK Low 3.5 3 ns Data Hold after LCLK Low 3 3 ns LCLK Period (1 × Operation) t

ns LCLK Width Low 6 6 ns LCLK Width High 5 5 ns

LACK High Delay after CLKIN High 18 + DT/2 28.5 + DT/2 18 + DT/2 29.0 + DT/2 ns LACK Low Delay after LCLK High

–3 13 –3 13 ns LACK Enable from CLKIN 5 + DT/2 5 + DT/2 ns LACK Disable from CLKIN 20 + DT/2 20 + DT/2 ns

LACK Setup before LCLK High 18 20 ns LACK Hold after LCLK High –7 –7 ns

LCLK Delay after CLKIN (1 × Operation) 15.5 16.75 ns Data Delay after LCLK High 3 2.5 ns Data Hold after LCLK High –3 –3 ns LCLK Width Low (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1 (tCK/2) + 2.25 ns LCLK Width High (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 2.25 (tCK/2) + 1.0 ns LCLK Low Delay after LACK High (tCK/2) + 8.5 (3 × tCK/2) + 17 (tCK/2) + 8.0 (3 × tCK/2) + 18.5 ns LDAT, LCLK Enable after CLKIN 5 + DT/2 5 + DT/2 ns LDAT, LCLK Disable after CLKIN 20 + DT/2 20 + DT/2 ns

Link Port Service Request Interrupts: 1 × and 2 × Speed Operations

Timing Requirements:

SLCK

HLCK

NOTES

LACK will go low with t

Only required for interrupt recognition in the current cycle.

LACK/LCLK Setup before CLKIN Low210 10 ns LACK/LCLK Hold after CLKIN Low

relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

DLALC

22 ns

–32–

REV. B

Page 33

ADSP-21060C/ADSP-21060LC

Link Ports: 2  CLK Speed Operation

Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK, (setup skew = t

LCLKTWH

duced in LCLK relative to LDATA, (hold skew = t specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew times shown below are calculated to include only one tester guardband.

ADSP-21060C Setup Skew = 0.62 ns max (If port 2 is transmitter, setup skew is 0.39) ADSP-21060C Hold Skew = 2.40 ns max

ADSP-21060LC Setup Skew = 1.23 ns max ADSP-21060LC Hold Skew = 2.76 ns max

Parameter Min Max Min Max Unit

Receive

Timing Requirements:

SLDCL

HLDCL

LCLKIW

LCLKRWL

LCLKRWH

Data Setup before LCLK Low 2.5 2.25 ns Data Hold after LCLK Low 2.25 2.25 ns LCLK Period (2 × Operation) tCK/2 tCK/2 ns LCLK Width Low 4.5 5.25 ns LCLK Width High 4.25 4.5 ns

Switching Characteristics:

DLAHC

DLALC

LACK High Delay after CLKIN High 18 + DT/2 28.5 + DT/2 18 + DT/2 29.5 + DT/2 ns LACK Low Delay after LCLK High16 16.5 6 18.5 ns

min – t

LCLKTWL

DLDCH

min – t

– t

HLDCH

). Hold skew is the maximum delay that can be intro-

SLDCL

– t

). Calculations made directly from 2 × speed

HLDCL

ADSP-21060C ADSP-21060LC

Transmit

Timing Requirements:

SLACH

HLACH

LACK Setup before LCLK High 19 19 ns LACK Hold after LCLK High –6.75 –6.5 ns

Switching Characteristics:

DLCLK

DLDCH

HLDCH

LCLKTWL

LCLKTWH

DLACLK

NOTE

LACK will go low with t

LCLK Delay after CLKIN 8 8 ns Data Delay after LCLK High 2.5 2.25 ns Data Hold after LCLK High –2.0 –2.0 ns LCLK Width Low (tCK/4) – 1 (tCK/4) + 1.5 (tCK/4) – 0.75 (tCK/4) + 1.5 ns LCLK Width High (tCK/4) – 1.5 (tCK/4) + 1 (tCK/4) – 1.5 (tCK/4) + 1 ns LCLK Low Delay after LACK High (tCK/4) + 9 (3 * tCK/4) + 16.5 (tCK/4) + 9 (3 * tCK/4) + 16.5 ns

DLALC

relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

REV. B

–33–

Page 34

ADSP-21060C/ADSP-21060LC

TRANSMIT

CLKIN

LCLK 1x

LCLK 2x

DLCLK

LCLKTWH

HLDCH

DLDCH

LCLKTWL

LAST NIBBLE

TRANSMITTED

FIRST NIBBLE TRANSMITTED

LCLK INACTIVE

(HIGH)

LDAT(3:0)

LACK (IN)

THE

OUT

SLACH

REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

SLACH

RECEIVE

CLKIN

LCLKIW

HLDCL

LCLK 1x

LCLK 2x

LDAT(3:0)

LACK (OUT)

DLAHC

LCLKRWH

SLDCL

LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION

CLKIN

LCLK

LDAT(3:0)

LACK

ENDLK

LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.

LCLKRWL

TDLK

HLACH

DLALC

DLACLK

LINK PORT INTERRUPT SETUP TIME

CLKIN

SLCK

LCLK

LACK

HLCK

Figure 21. Link Ports

–34–

REV. B

Page 35

ADSP-21060C/ADSP-21060LC

Serial Ports

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

External Clock

Timing Requirements:

SFSE

HFSE

SDRE

HDRE

SCLKW

SCLK

TFS/RFS Setup before TCLK/RCLK TFS/RFS Hold after TCLK/RCLK Receive Data Setup before RCLK Receive Data Hold after RCLK TCLK/RCLK Width 9.5 9.5 ns TCLK/RCLK Period t

Internal Clock

Timing Requirements:

SFSI

HFSI

SDRI

HDRI

TFS Setup before TCLK1; RFS Setup before RCLK

TFS/RFS Hold after TCLK/RCLK Receive Data Setup before RCLK Receive Data Hold after RCLK

External or Internal Clock

Switching Characteristics:

DFSE

HOFSE

RFS Delay after RCLK (Internally Generated RFS) RFS Hold after RCLK (Internally Generated RFS)

External Clock

Switching Characteristics:

DFSE

HOFSE

DDTE

HODTE

TFS Delay after TCLK (Internally Generated TFS) TFS Hold after TCLK (Internally Generated TFS)

Transmit Data Delay after TCLK Transmit Data Hold after TCLK

Internal Clock

Switching Characteristics:

DFSI

HOFSI

DDTI

HDTI

SCLKIW

TFS Delay after TCLK (Internally Generated TFS) TFS Hold after TCLK (Internally Generated TFS)

Transmit Data Delay after TCLK Transmit Data Hold after TCLK TCLK/RCLK Width (t

Enable and Three-State

Switching Characteristics:

DDTEN

DDTTE

DDTIN

DDTTI

DCLK

DPTR

Gated SCLK with External TFS (Mesh Multiprocessing)

Data Enable from External TCLK Data Disable from External TCLK Data Enable from Internal TCLK Data Disable from Internal TCLK TCLK/RCLK Delay from CLKIN 22 + 3DT/8 22 + 3DT/8 ns SPORT Disable after CLKIN 17 17 ns

Timing Requirements:

STFSCK

HTFSCK

TFS Setup before CLKIN 5 5 ns TFS Hold after CLKIN tCK/2 tCK/2 ns

External Late Frame Sync

Switching Characteristics:

DDTLFSE

Data Delay from Late External TFS or 12 12.8 ns External RFS with MCE = 1, MFD = 0

DDTENFS

Data Enable from late FS or MCE = 1, MFD = 0

1, 2

3.5 3.5 ns 44ns

1.5 1.5 ns 44ns

88ns 11ns 33ns 33ns

13 13 ns

33ns

13 13 ns

33ns

16 16 ns

55ns

4.5 4.5 ns

–1.5 –1.5 ns

7.5 7.5 ns

00ns

/2) – 2 (t

SCLK

/2) + 2 (t

SCLK

/2) – 2.5 (t

SCLK

/2) + 2.5 ns

SCLK

3.5 4.0 ns

10.5 10.5 ns

00ns

33ns

3 3.5 ns

determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync se

and hold, 2) data delay & data setup and hold, and 3) SCLK width.

REV. B

–35–

tup

Page 36

ADSP-21060C/ADSP-21060LC

NOTES

Referenced to sample edge.

RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

Referenced to drive edge.

Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.

MCE = 1, TFS enable and TFS valid follow t

DDTLFSE

and t

DDTENFS

DATA RECEIVE– INTERNAL CLOCK

DRIVE

RCLK

RFS

EDGE

HOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DFSE

SCLKIW

SFSI

SDRI

DATA TRANSMIT– INTERNAL CLOCK

DRIVE

TCLK

TFS

EDGE

HOFSI

HDTI

DFSI

DDTI

SCLKIW

SFSI

SAMPLE

EDGE

SAMPLE

EDGE

HFSI

HDRI

HFSI

DATA RECEIVE– EXTERNAL CLOCK

DRIVE

RCLK

RFS

EDGE

HOFSE

DFSE

SCLKW

SFSE

SDRE

DATA TRANSMIT– EXTERNAL CLOCK

DRIVE

TCLK

TFS

EDGE

HOFSE

HDTE

DFSE

DDTE

SCLKW

SFSE

SAMPLE

EDGE

SAMPLE

EDGE

HFSE

HDRE

HFSE

TCLK (EXT)

TCLK (INT)

CLKIN

TCLK, RCLK

TFS, RFS, DT

TCLK (INT)

RCLK (INT)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

TCLK / RCLK

DDTEN

DRIVE EDGE

DDTIN

SPORT DISABLE DELAY

FROM INSTRUCTION

LOW TO HIGH ONLY

DCLK

DPTR

SPORT ENABLE AND THREE-STATE LATENCY IS TWO CYCLES

TCLK / RCLK

CLKIN

TFS (EXT)

NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING.

DRIVE

EDGE

DDTTI

DDTTE

STFSCK

Figure 22. Serial Ports

HTFSCK

–36–

REV. B

Page 37

EXTERNAL RFS with MCE = 1, MFD = 0

ADSP-21060C/ADSP-21060LC

DRIV E SAMPLE

RCLK

RFS

DDTLFSE

LATE EXTERNAL TFS

DRIV E SAMPLE

TCLK

TFS

DDTLFSE

DRIVE

(SEE NOTE 2)

DRIVE

HOFSE/I

DDTE/I

(SEE NOTE 2)

DDTENFS

SFSE/I

DDTENFS

SFSE/I

HDTE/I

1ST BIT 2ND BIT

HDTE/I

1ST BIT 2ND BIT

Figure 23. External Late Frame Sync

REV. B

–37–

Page 38

ADSP-21060C/ADSP-21060LC

JTAG Test Access Port and Emulation

ADSP-21060C ADSP-21060LC

Parameter Min Max Min Max Unit

Timing Requirements:

TCK

STAP

HTAP

SSYS

HSYS

TRSTW

Switching Characteristics:

DTDO

DSYS

NOTES

System Inputs = DATA

TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT

System Outputs = DATA

DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT

TCK Period t

ns TDI, TMS Setup before TCK High 5 5 ns TDI, TMS Hold after TCK High 6 6 ns System Inputs Setup before TCK Low System Inputs Hold after TCK Low TRST Pulsewidth 4t

TDO Delay from TCK Low 13 13 ns System Outputs Delay after TCK Low

, ADDR

47-0

OUTPUTS

, ADDR

SYSTEM

, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR

31-0

, MS

, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR

3-0

DTDO

TCK

TMS

TDI

TDO

INPUTS

31-0

STAP

DSYS

77ns 18 18.5 ns

18.5 18.5 ns

, ID

, RPBA, IRQ

6-1

, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.

3-0

, LxCLK, LxACK, BMS.

3-0

TCK

HTAP

SSYS

2-0

HSYS

, FLAG

2-0

, CPA, FLAG

6-1

, DR0, DR1,

3-0

, TIMEXP, DT0,

3-0

Figure 24. IEEE 11499.1 JTAG Test Access Port

–38–

REV. B

Page 39

ADSP-21060C/ADSP-21060LC

OUTPUT DRIVE CURRENTS

Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-2106x. The curves represent the current drive capability of the output drivers as a function of output voltage.

POWER DISSIPATION

Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way:

INT

= I

DDIN

× V

The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:

– the number of output pins that switch during each cycle (O) – the maximum frequency at which they can switch (f) – their load capacitance (C) – their voltage swing (V

)

and is calculated by:

= O × C × V

EXT

× f

The load capacitance should include the processor’s package capacitance (C

). The switching frequency includes driving the

load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2t can switch every cycle at a frequency of 1/t at 1/(2t

), but selects can switch on each cycle.

). The write strobe

. Select pins switch

Example:

Estimate P

with the following assumptions:

EXT

–A system with one bank of external data memory RAM (32-bit) –Four 128K

8 RAM chips are used, each with a load of 10 pF

–External data memory writes occur every other cycle, a rate

of 1/(4t

–The instruction cycle rate is 40 MHz (t

The P

), with 50% of the pins switching

equation is calculated for each class of pins that can

EXT

= 25 ns).

drive:

Table II. External Power Calculations (5 V Device)

Pin # of % Type Pins Switching  C  f  V

Address 15 50 × 44.7 pF × 10 MHz × 25 V = 0.084 W

MS0 10 × 44.7 pF × 10 MHz × 25 V = 0.000 W WR 1– × 44.7 pF × 20 MHz × 25 V = 0.022 W

Data 32 50 × 14.7 pF × 10 MHz × 25 V = 0.059 W ADDRCLK 1 – × 4.7 pF × 20 MHz × 25 V = 0.002 W

= 0.167 W

EXT

= P

EXT

Table III. External Power Calculations (3.3 V Device)

Pin # of % Type Pins Switching  C  f  V

Address 15 50 × 44.7 pF × 10 MHz × 10.9 V = 0.037 W

MS0 10 × 44.7 pF × 10 MHz × 10.9 V = 0.000 W WR 1– × 44.7 pF × 20 MHz × 10.9 V = 0.010 W

Data 32 50 × 14.7 pF × 10 MHz × 10.9 V = 0.026 W ADDRCLK 1 – × 4.7 pF × 20 MHz × 10.9 V = 0.001 W

= 0.074 W

EXT

= P

EXT

A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation:

= P

TOTAL

EXT

+ (I

Note that the conditions causing a worst-case P from those causing a worst-case P

× 5.0 V )

DDIN2

. Maximum P

INT

are different

EXT

cannot

INT

occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.

TEST CONDITIONS Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, C the load current, I

. This decay time can be approximated by

and

the following equation:

∆V

DECAY

The output disable time t and t

as shown in Figure 25. The time t

DECAY

DIS

is the difference between t

MEASURED

is the

interval from when the reference signal switches to when the output voltage decays ∆V from the measured output high or output low voltage. t

, and with ∆V equal to 0.5 V.

is calculated with test loads CL and

DECAY

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time t

is the interval from when a

ENA

reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 25). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

REV. B

–39–

Page 40

ADSP-21060C/ADSP-21060LC

Example System Hold Time Calculation

To determine the data output hold time in a particular system, first calculate t

using the equation given above. Choose ∆V

DECAY

to be the difference between the ADSP-2106x’s output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0.4 V. C data line), and I

is the total leakage or three-state current (per

data line). The hold time will be t disable time (i.e., t

REFERENCE

SIGNAL

OH (MEASURED)

OL (MEASURED)

DATRWH

DIS

OUTPUT STOPS

DRIVING

is the total bus capacitance (per

plus the minimum

DECAY

for the write cycle).

MEASURED

OH (MEASURED)

OL (MEASURED)

DECAY

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V

– V

+ V

ENA

2.0V

1.0V

OUTPUT STARTS

DRIVING

OH (MEASURED)

OL (MEASURED)

Figure 25. Output Enable/Disable

OUTPUT

50pF

+1.5V

Figure 26. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

1.5V 1.5V

Figure 27. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

Capacitive Loading

Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 26). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for loads other than the nominal value of 50 pF. Figures 29–30, 33–34 show how output rise time varies with capacitance. Figures 31, 35 show graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see the previous section Output Disable Time under Test Conditions.) The graphs of Figures 29, 30 and 31 may not be linear outside the ranges shown.

–40–

REV. B

Page 41

LOAD CAPACITANCE – pF

OUTPUT DELAY OR HOLD – ns

–1

25 20050 75 100 125 150 175

NOMINAL

Y = 0.03X –1.45

SOURCE VOLTAGE – V

–20

–80

3.5

SOURCE CURRENT – mA

0.5 1 1.5 2 2.5 3

–40

–60

3.0V, +100°C

100

120

–100

–120

3.3V, +25°C

3.6V, –40°C

3.3V, +25°C

3.6V, –40°C

LOAD CAPACITANCE – pF

20 40 60 80 100 120

Y = 0.0796X + 1.17

Y = 0.0467X + 0.55

RISE TIME

FALL TIME

140 160 180 200

RISE AND FALL TIMES – ns (10% – 90%)

SOURCE CURRENT – mA

–25

–50

–75

–100

–125

–150

5.25V, –40C

0.75 1.50 2.25 3.00 3.75 4.50

0 5.25

5.0V, +25C

4.75V, +100C

5.0V, +25C

5.25V, –40C

SOURCE VOLTAGE – V

Figure 28. ADSP-2106x Typical Drive Currents (VDD = 5 V)

16.0

14.0

12.0

RISE TIME

FALL TIME

RISE AND FALL TIMES – ns

10.0

8.0

6.0

(0.5V – 4.5V, 10% – 90%)

4.0

Y = 0.005X + 3.7

ADSP-21060C/ADSP-21060LC

Figure 31. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (V

= 5 V)

2.0

0 20020 40 60 80 100 120 140 160 180

Figure 29. Typical Output Rise Time (10%–90% VDD) vs. Load Capacitance (V

3.5

3.0

2.5

2.0 Y = 0.009X + 1.1

1.5

1.0

REV. B

0.5

RISE AND FALL TIMES – ns (0.8V – 2.0V)

0 20020 40 60 80 100 120 140 160 180

Figure 30. Typical Output Rise Time (0.8 V–2.0 V) vs. Load Capacitance (V

Y = 0.0031X + 1.1

LOAD CAPACITANCE – pF

= 5 V)

RISE TIME

Y = 0.005X + 0.6

LOAD CAPACITANCE – pF

= 5 V)

FALL TIME

Figure 32. ADSP-2106x Typical Drive Currents (VDD = 3.3 V)

Figure 33. Typical Output Rise Time (10%–90% VDD) vs. Load Capacitance (V

= 3.3 V)

–41–

Page 42

ADSP-21060C/ADSP-21060LC

RISE AND FALL TIMES – ns (0.8V – 2.0V)

0020 40 60 80 100 120

Y = 0.0391X + 0.36

RISE TIME

FALL TIME

LOAD CAPACITANCE – pF

Y = 0.0305X + 0.24

140 160 180 200

Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load Capacitance (V

= 3.3 V)

ENVIRONMENTAL CONDITIONS Thermal Characteristics

The ADSP-2106x is packaged in a 240-lead thermally enhanced ceramic QFP (CQFP). There are two package versions, one with a copper/tungsten heat slug on top of the package (CZ) for air cooling, and one with the heat slug on the bottom (CW) for cooling through the board. The ADSP-2106x is specified for a case temperature (T

). To ensure that the T

CASE

data sheet

CASE

specification is not exceeded, a heatsink and/or an air flow

OUTPUT DELAY OR HOLD – ns

NOMINAL

–1

25 20050 75 100 125 150 175

LOAD CAPACITANCE – pF

Y = 0.0329X –1.65

Figure 35. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (V

= 3.3 V)

source may be used. A heatsink should be attached with a thermal adhesive.

(PD

× θ

CASE = TAMB +

= Case temperature (measured on the heat slug surface)

CASE

)

PD = Power dissipation in W (this value depends upon the

specific application; a method for calculating PD is shown under Power Dissipation).

= Value from the following table.

Airflow (Linear Ft./Min.) 0 100 200 400 600

θCA (°C/W) 21060CW/LCW 19.5 16 14 12 10

21060CZ/LCZ 20 16 14 11.5 9.5

NOTES This represents thermal resistance at total power of 5 W. With air flow, no variance is seen in θ

θCA at 0 LFM varies with power

21060CW/LCW: at 2 W, θCA = 23°C/W; at 3 W, θCA = 21.5°C/W. 21060CZ/LCZ: at 2 W, θCA = 24°C/W; at 3 W, θCA = 21.5°C/W.

θJC= 0.24°C/W.

of 5 W.

–42–

REV. B

Page 43

ADSP-21060C/ADSP-21060LC

240-LEAD METRIC CQFP PIN CONFIGURATION

HEAT SLUG UP VERSION (CZ)

181240

TOP VIEW

PINS DOWN

HEAT SLUG

180

Pin Pin No. Name

1 TDI 2 TRST 3 VDD 4 TDO 5 TIMEXP 6 EMU 7 ICSA 8 FLAG3 9 FLAG2 10 FLAG1 11 FLAG0 12 GND 13 ADDR0 14 ADDR1 15 VDD 16 ADDR2 17 ADDR3 18 ADDR4 19 GND 20 ADDR5 21 ADDR6 22 ADDR7 23 VDD 24 ADDR8 25 ADDR9 26 ADDR10 27 GND 28 ADDR11 29 ADDR12 30 ADDR13 31 VDD 32 ADDR14 33 ADDR15 34 GND 35 ADDR16 36 ADDR17 37 ADDR18 38 VDD 39 VDD 40 ADDR19

Pin Pin No. Name

41 ADDR20 42 ADDR21 43 GND 44 ADDR22 45 ADDR23 46 ADDR24 47 VDD 48 GND 49 VDD 50 ADDR25 51 ADDR26 52 ADDR27 53 GND 54 MS3 55 MS2 56 MS1 57 MS0 58 SW 59 BMS 60 ADDR28 61 GND 62 VDD 63 VDD 64 ADDR29 65 ADDR30 66 ADDR31 67 GND 68 SBTS 69 DMAR2 70 DMAR1 71 HBR 72 DT1 73 TCLK1 74 TFS1 75 DR1 76 RCLK1 77 RFS1 78 GND 79 CPA 80 DT0

61 120

THE 240–LEAD PACKAGE CONTAINS A COPPER/TUNGSTEN HEAT SLUG ON ITS TOP SURFACE. HEAT SLUG AND PACKAGE LID ARE ELECTRICALLY ISOLATED.

Pin Pin No. Name

81 TCLK0 82 TFS0 83 DR0 84 RCLK0 85 RFS0 86 VDD 87 VDD 88 GND 89 ADRCLK 90 REDY 91 HBG 92 CS 93 RD 94 WR 95 GND 96 VDD 97 GND 98 CLKIN 99 ACK 100 DMAG2 101 DMAG1 102 PAGE 103 VDD 104 BR6 105 BR5 106 BR4 107 BR3 108 BR2 109 BR1 110 GND 111 VDD 112 GND 113 DATA47 114 DATA46 115 DATA45 116 VDD 117 DATA44 118 DATA43 119 DATA42 120 GND

Pin Pin No. Name

121 DATA41 122 DATA40 123 DATA39 124 VDD 125 DATA38 126 DATA37 127 DATA36 128 GND 129 NC 130 DATA35 131 DATA34 132 DATA33 133 VDD 134 VDD 135 GND 136 DATA32 137 DATA31 138 DATA30 139 GND 140 DATA29 141 DATA28 142 DATA27 143 VDD 144 VDD 145 DATA26 146 DATA25 147 DATA24 148 GND 149 DATA23 150 DATA22 151 DATA21 152 VDD 153 DATA20 154 DATA19 155 DATA18 156 GND 157 DATA17 158 DATA16 159 DATA15 160 VDD

121

Pin Pin No. Name

161 DATA14 162 DATA13 163 DATA12 164 GND 165 DATA11 166 DATA10 167 DATA9 168 VDD 169 DATA8 170 DATA7 171 DATA6 172 GND 173 DATA5 174 DATA4 175 DATA3 176 VDD 177 DATA2 178 DATA1 179 DATA0 180 GND 181 GND 182 L0DAT3 183 L0DAT2 184 L0DAT1 185 L0DAT0 186 L0CLK 187 L0ACK 188 VDD 189 L1DAT3 190 L1DAT2 191 L1DAT1 192 L1DAT0 193 L1CLK 194 L1ACK 195 GND 196 GND 197 VDD 198 L2DAT3 199 L2DAT2 200 L2DAT1

Pin Pin No. Name

201 L2DAT0 202 L2CLK 203 L2ACK 204 NC 205 VDD 206 L3DAT3 207 L3DAT2 208 L3DAT1 209 L3DAT0 210 L3CLK 211 L3ACK 212 GND 213 L4DAT3 214 L4DAT2 215 L4DAT1 216 L4DAT0 217 L4CLK 218 L4ACK 219 VDD 220 GND 221 VDD 222 L5DAT3 223 L5DAT2 224 L5DAT1 225 L5DAT0 226 L5CLK 227 L5ACK 228 GND 229 ID2 230 ID1 231 ID0 232 LBOOT 233 RPBA 234 RESET 235 EBOOT 236 IRQ2 237 IRQ1 238 IRQ0 239 TCK 240 TMS

REV. B

–43–

Page 44

ADSP-21060C/ADSP-21060LC

240-LEAD METRIC CQFP PIN CONFIGURATION

HEAT SLUG DOWN VERSION (CW)

181240

Pin Pin No. Name

1 GND 2 DATA0 3 DATA1 4 DATA2 5 VDD 6 DATA3 7 DATA4 8 DATA5 9 GND 10 DATA6 11 DATA7 12 DATA8 13 VDD 14 DATA9 15 DATA10 16 DATA11 17 GND 18 DATA12 19 DATA13 20 DATA14 21 VDD 22 DATA15 23 DATA16 24 DATA17 25 GND 26 DATA18 27 DATA19 28 DATA20 29 VDD 30 DATA21 31 DATA22 32 DATA23 33 GND 34 DATA24 35 DATA25 36 DATA26 37 VDD 38 VDD 39 DATA27 40 DATA28

Pin Pin No. Name

41 DATA29 42 GND 43 DATA30 44 DATA31 45 DATA32 46 GND 47 VDD 48 VDD 49 DATA33 50 DATA34 51 DATA35 52 NC 53 GND 54 DATA36 55 DATA37 56 DATA38 57 VDD 58 DATA39 59 DATA40 60 DATA41 61 GND 62 DATA42 63 DATA43 64 DATA44 65 VDD 66 DATA45 67 DATA46 68 DATA47 69 GND 70 VDD 71 GND 72 BR1 73 BR2 74 BR3 75 BR4 76 BR5 77 BR6 78 VDD 79 PAGE 80 DMAG1

TOP VIEW

PINS DOWN

HEAT SLUG

61 120

THE 240–LEAD PACKAGE CONTAINS A COPPER/TUNGSTEN HEAT SLUG ON ITS BOTTOM SURFACE. HEAT SLUG AND PACKAGE LID ARE ELECTRICALLY ISOLATED.

Pin Pin No. Name

81 DMAG2 82 ACK 83 CLKIN 84 GND 85 VDD 86 GND 87 WR 88 RD 89 CS 90 HBG 91 REDY 92 ADRCLK 93 GND 94 VDD 95 VDD 96 RFS0 97 RCLK0 98 DR0 99 TFS0 100 TCLK0 101 DT0 102 CPA 103 GND 104 RFS1 105 RCLK1 106 DR1 107 TFS1 108 TCLK1 109 DT1 110 HBR 111 DMAR1 112 DMAR2 113 SBTS 114 GND 115 ADDR31 116 ADDR30 117 ADDR29 118 VDD 119 VDD 120 GND

Pin Pin No. Name

121 ADDR28 122 BMS 123 SW 124 MS0 125 MS1 126 MS2 127 MS3 128 GND 129 ADDR27 130 ADDR26 131 ADDR25 132 VDD 133 GND 134 VDD 135 ADDR24 136 ADDR23 137 ADDR22 138 GND 139 ADDR21 140 ADDR20 141 ADDR19 142 VDD 143 VDD 144 ADDR18 145 ADDR17 146 ADDR16 147 GND 148 ADDR15 149 ADDR14 150 VDD 151 ADDR13 152 ADDR12 153 ADDR11 154 GND 155 ADDR10 156 ADDR9 157 ADDR8 158 VDD 159 ADDR7 160 ADDR6

180

121

Pin Pin No. Name

161 ADDR5 162 GND 163 ADDR4 164 ADDR3 165 ADDR2 166 VDD 167 ADDR1 168 ADDR0 169 GND 170 FLAG0 171 FLAG1 172 FLAG2 173 FLAG3 174 ICSA 175 EMU 176 TIMEXP 177 TDO 178 VDD 179 TRST 180 TDI 181 TMS 182 TCK 183 IRQ0 184 IRQ1 185 IRQ2 186 EBOOT 187 RESET 188 RPBA 189 LBOOT 190 ID0 191 ID1 192 ID2 193 GND 194 L5ACK 195 L5CLK 196 L5DAT0 197 L5DAT1 198 L5DAT2 199 L5DAT3 200 VDD

Pin Pin No. Name

201 GND 202 VDD 203 L4ACK 204 L4CLK 205 L4DAT0 206 L4DAT1 207 L4DAT2 208 L4DAT3 209 GND 210 L3ACK 211 L3CLK 212 L3DAT0 213 L3DAT1 214 L3DAT2 215 L3DAT3 216 VDD 217 NC 218 L2ACK 219 L2CLK 220 L2DAT0 221 L2DAT1 222 L2DAT2 223 L2DAT3 224 VDD 225 GND 226 GND 227 L1ACK 228 L1CLK 229 L1DAT0 230 L1DAT1 231 L1DAT2 232 L1DAT3 233 VDD 234 L0ACK 235 L0CLK 236 L0DAT0 237 L0DAT1 238 L0DAT2 239 L0DAT3 240 GND

–44–

REV. B

Page 45

PIN 1

ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters within parentheses).

240-Lead CQFP with Heat Slug Up and Formed Leads (QS-240)

1.441 (36.60)

1.422 (36.13) SQ

1.404 (35.65)

1.270 (32.25)

1.260 (32.00) SQ

240

1.250 (31.75)

181

180

181

180

1.104 (28.05)

1.094 (27.80) SQ

1.085 (27.55)

LIDSEAL RING

240

0.837 (21.25)

0.827 (21.00) SQ

0.817 (20.75)

0.169 (4.30) MAX

7

0.035 (0.90)

–3

0.030 (0.75)

0.024 (0.60)

TOP VIEW

PINS DOWN

HEAT SLUG

61 120

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

0.758 (19.25)

0.748 (19.00) SQ

0.738 (18.75)

0.020 (0.50) TYP

LEAD PITCH

0.067 (1.70)

LEAD THICKNESS

0.006 (0.15)0.006 (0.15)

0.014 (0.35)

0.012 (0.30)

0.010 (0.25)

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

BOTTOM VIEW

121

120

0.146 (3.70)

0.127 (3.22)

0.108 (2.75)

-C-

0.024 (0.60)

0.008 (0.20)

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

SEATING PLANE

0.004 (0.10)

REV. B

–45–

Page 46

ADSP-21060C/ADSP-21060LC

Dimensions shown in inches and (millimeters within parentheses).

240-Lead Metric CQFP with Heat Slug Up and Unformed Leads (QS-240)

2.953 (75.00) SQ

1.161 (29.50) BSC

OUTLINE DIMENSIONS

0.665 (16.88)

8  0.650 (16.50)

0.635 (16.12)

2 

2.594

(65.90)

121

180

120

181

TOP VIEW

HEAT SLUG

2.972 (75.50) SQ

0.067 (1.70)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

INDEX 1

240

GOLD PLATED

0.006 (0.15)0.006 (0.15)

0.014 (0.35)

0.012 (0.30)

0.010 (0.25)

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

SEAL RING

BOTTOM VIEW

240 181

INDEX 2

0.079 (2.00) NO GOLD

NONCONDUCTIVE CERAMIC TIE BAR

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

LID

120

121

180

–46–

REV. B

Page 47

ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters within parentheses).

240-Lead Metric CQFP with Heat Slug Down and Formed Leads (QS-240A)

PIN 1

0.165 (4.20) MAX

7

–3

1.441 (36.60)

1.422 (36.13) SQ

1.404 (35.65)

1.270 (32.25)

1.260 (32.00) SQ

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

1.250 (31.75)

TOP VIEW

PINS DOWN

1.104 (28.05)

1.094 (27.80) SQ

1.085 (27.55)

0.020 (0.50) TYP

LEAD PITCH

0.067 (1.70)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

LIDSEAL RING

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

240

61 120

0.035 (0.90)

0.030 (0.75)

0.024 (0.60)

0.006 (0.15)0.006 (0.15)

0.014 (0.35)

0.012 (0.30)

0.010 (0.25)

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

0.837 (21.25)

0.827 (21.00) SQ

0.817 (20.75)

0.758 (19.25)

0.748 (19.00) SQ

181

0.020 (0.50)

0.004 (0.10)

181

180

121

121 60

120

0.146 (3.70)

0.127 (3.22)

0.108 (2.75)

-C-

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

0.738 (18.75)

BOTTOM VIEW

HEAT SLUG

SEATING PLANE

0.004 (0.10)

240

REV. B

–47–

Page 48

ADSP-21060C/ADSP-21060LC

Dimensions shown in inches and (millimeters within parentheses).

240-Lead Metric CQFP with Heat Slug Down and Unformed Leads (QS-240A)

2.953 (75.00) SQ

1.161 (29.50) BSC

OUTLINE DIMENSIONS

0.665 (16.88)

8  0.650 (16.50)

0.635 (16.12)

2 

2.594

(65.90)

120

121

180

181

SEAL RING

TOP VIEW

2.972 (75.50) SQ

0.067 (1.70)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

LID

240

0.006 (0.15)0.006 (0.15)

0.014 (0.35)

0.012 (0.30)

0.010 (0.25)

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

INDEX 1 GOLD PLATED

BOTTOM VIEW

HEAT SLUG

INDEX 2

0.079 (2.00) NO GOLD

NONCONDUCTIVE CERAMIC TIE BAR

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

240 181

120

121

180

C00168a–0–2/01 (rev. B)

ORDERING GUIDE

Part Number Case Temperature Range Heat Slug Orientation Instruction Rate Operating Voltage

ADSP-21060CZ-133 –40°C to +100°C Heat Slug Up 33 MHz 5 V ADSP-21060CZ-160 –40°C to +100°C Heat Slug Up 40 MHz 5 V ADSP-21060CW-133 –40°C to +100°C Heat Slug Down 33 MHz 5 V ADSP-21060CW-160 –40°C to +100°C Heat Slug Down 40 MHz 5 V ADSP-21060LCW-133 –40°C to +100°C Heat Slug Down 33 MHz 3.3 V ADSP-21060LCW-160 –40°C to +100°C Heat Slug Down 40 MHz 3.3 V

–48–

REV. B

PRINTED IN U.S.A.

Datasheet ADSP-21060C Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual