Datasheet ADS-B931, ADS-931MM, ADS-931MC Datasheet (DATEL)

PIN FUNCTION PIN FUNCTION

1 +3.2V REF. OUT 40 NO CONNECTION
2 UNIPOLAR 39 NO CONNECTION
3 ANALOG INPUT 38 +5V ANALOG SUPPLY
4 ANALOG GROUND 37 –5V SUPPLY
5 OFFSET ADJUST 36 ANALOG GROUND
6 GAIN ADJUST 35 COMP. BITS
7 DIGITAL GROUND 34 OUTPUT ENABLE
8 FIFO/DIR 33 OVERFLOW

9 FIFO READ 32 EOC
10 FSTAT1 31 +5V DIGITAL SUPPLY
11 FSTAT2 30 DIGITAL GROUND
12 START CONVERT 29 BIT 1 (MSB)
13 BIT 16 (LSB) 28 BIT 1 (MSB)
14 BIT 15 27 BIT 2
15 BIT 14 26 BIT 3
16 BIT 13 25 BIT 4
17 BIT 12 24 BIT 5
18 BIT 11 23 BIT 6
19 BIT 10 22 BIT 7
20 BIT 9 21 BIT 8

FEATURES

• 16-bit resolution

• 1MHz sampling rate

• Functionally complete

• No missing codes over full military temperature range

• Edge-triggered

• ±5V supplies, 1.85 Watts

• Small, 40-pin, ceramic TDIP

• 87dB SNR, –89dB THD

• Ideal for both time and frequency-domain applications

16-Bit, 1MHz

Sampling A/D Converters

®

®

INNOV A TION and EX CELLENCE

GENERAL DESCRIPTION

The low-cost ADS-931 is a 16-bit, 1MHz sampling A/D
converter. This device accurately samples full-scale input
signals up to Nyquist frequencies with no missing codes. The
dynamic performance of the ADS-931 has been optimized to
achieve a signal-to-noise ratio (SNR) of 87dB and a total
harmonic distortion (THD) of –89dB.

Packaged in a 40-pin TDIP, the functionally complete ADS-931
contains a fast-settling sample-hold amplifier, a subranging (two­pass) A/D converter, an internal reference, timing/control logic,
and error-correction circuitry. Digital input and output levels are
TTL. The ADS-931 only requires the rising edge of the start
convert pulse to operate.

Requiring only ±5V supplies, the ADS-931 dissipates 1.85
Watts. The device is offered with a bipolar (±2.75V) analog
input range or a unipolar (0 to –5.5V) input range. Models are
available for use in either commercial (0 to +70°C) or military
(–55 to +125°C) operating temperature ranges. A proprietary,
auto-calibrating, error-correcting circuit enables the device to
achieve specified performance over the full military
temperature range. Typical applications include medical
imaging, radar, sonar, communications and instrumentation.

INPUT/OUTPUT CONNECTIONS

ADS-931

DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: [phone] Fax: [phone] • E-mail:[e-mail] • Internet: www.datel.com

Figure 1. ADS-931 Functional Block Diagram

3-STATE

OUTPUT REGISTER

29 BIT 1 (MSB)
28 BIT 1 (MSB)
27 BIT 2
26 BIT 3
25 BIT 4
24 BIT 5
23 BIT 6
22 BIT 7
21 BIT 8
20 BIT 9
19 BIT 10
18 BIT 11
17 BIT 12
16 BIT 13
15 BIT 14
14 BIT 15
13 BIT 16 (LSB)

TIMING AND

CONTROL LOGIC

GAIN ADJUST 6

+3.2V REF. OUT 1

OFFSET ADJUST 5

EOC 32

ANALOG GROUND 4, 36
DIGITAL GROUND 7, 30
+5V DIGITAL SUPPLY 31
–5V SUPPLY 37
+5V ANALOG SUPPLY 38
NO CONNECTION 39, 40

CUSTOM GATE ARRAY

POWER and GROUNDING

2-PASS ANALOG-TO-DIGITAL CONVERTER

S/H

GAIN

ADJUST

CKT.

OFFSET
ADJUST

CKT.

PRECISION

+3.2V REFERENCE

ANALOG INPUT 3

START CONVERT 12

COMP. BITS 35

10 FSTAT1
11 FSTAT2

8 FIFO/DIR
9 FIFO/READ

34 OUTPUT ENABLE

33 OVERFLOW

UNIPOLAR 2

OFFSET ADJUST 5

ADS-931

® ®

2

+25°C 0 to +70°C –55 to +125°C

ANALOG INPUTS MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

Input Voltage Ranges

Unipolar — 0 to –5.5 — — 0 to –5.5 — — 0 to –5.5 — Volts
Bipolar — ±2.75 — — ±2.75 — — ±2.75 — Volts

Input Resistance (pin 3) — 685 — — 685 — — 685 — Ω
Input Resistance (pin 2) — 400 — — 426 — — 426 — Ω
Input Capacitance — 10 15 — 10 15 — 10 15 pF

DIGITAL INPUTS

Logic Levels

Logic "1" +2.0 — — +2.0 — — +2.0 — — Volts
Logic "0" — — +0.8 — — +0.8 — — +0.8 Volts
Logic Loading "1" — — +20 — — +20 — — +20 µA
Logic Loading "0" ➁ — — –20 — — –20 — — –20 µA

Start Convert Positive Pulse Width ➂ 40 100 — 40 100 — 40 100 — ns

STATIC PERFORMANCE

Resolution — 16 — — 16 — — 16 — Bits
Integral Nonlinearity — ±1 — — ±1.5 — — ±2 — LSB
Differential Nonlinearity (f

in = 10kHz) –0.95 ±0.5 +1.0 –0.95 ±0.5 +1.0 –0.95 ±0.5 +1.5 LSB

Full Scale Absolute Accuracy — ±0.1 ±0.3 — ±0.15 ±0.5 — ±0.5 ±0.8 %FSR
Bipolar Zero Error (Tech Note 2) — ±0.1 ±0.2 — ±0.2 ±0.4 — ±0.5 ±0.9 %FSR
Bipolar Offset Error (Tech Note 2) — ±0.1 ±0.3 — ±0.2 ±0.5 — ±0.4 ±0.9 %FSR
Gain Error (Tech Note 2) — ±0.1 ±0.3 — ±0.15 ±0.5 — ±0.5 ±0.9 %
No Missing Codes (f

in = 10kHz) 16 — — 16 — — 16 — — Bits

DYNAMIC PERFORMANCE

Peak Harmonics (–0.5dB)

dc to 250kHz — –91 –85 — –91 –85 — –90 –83 dB
250kHz to 500kHz — –91 –85 — –91 –85 — –90 –83 dB

Total Harmonic Distortion (–0.5dB)

dc to 250kHz — –89 –83 — –89 –83 — –87 –81 dB
250kHz to 500kHz — –87 –80 — –87 –80 — –85 –79 dB

Signal-to-Noise Ratio

(w/o distortion, –0.5dB)
dc to 250kHz 84 87 — 84 87 — 82 86 — dB
250kHz to 500kHz 83 86 — 83 86 — 80 84 — dB

Signal-to-Noise Ratio ➃

(& distortion, –0.5dB)
dc to 250kHz 80 85 — 80 85 — 77 83 — dB
250kHz to 500MHz 79 84 — 79 84 — 76 82 — dB

Noise — 82 — — 82 — — 82 — µVrms
Two-Tone Intermodulation

Distortion (f

in = 98kHz,

240kHz, f

s = 1MHz, –0.5dB) — –89 — — –89 — — –89 — dB

Input Bandwidth (–3dB)

Small Signal (–20dB input) — 4.8 — — 4.8 — — 4.8 — MHz
Large Signal (–0.5dB input) — 4.1 — — 4.1 — — 4.1 — MHz

Feedthrough Rejection

(f

in = 480kHz) — 90 — — 90 — — 90 — dB

Slew Rate — ±51 — — ±51 — — ±51 — V/µs
Aperture Delay Time — +8 — — +8 — — +8 — ns
Aperture Uncertainty — 5 — — 5 — — 5 — ps rms
S/H Acquisition Time

( to ±0.001%FSR, 5.5V step) 700 725 — 700 725 — 700 725 — ns

PARAMETERS MIN. TYP. MAX. UNITS

Operating Temp. Range, Case

ADS-931MC 0 — +70 °C
ADS-931MM –55 — +125 °C

Thermal Impedance

θjc — 4 — °C/Watt
θca — 18 — °C/Watt

Storage Temperature Range –65 — +150 °C
Package Type 40-pin, metal-sealed, ceramic TDIP

Weight 0.56 ounces (16 grams)

ABSOLUTE MAXIMUM RATINGS

PARAMETERS LIMITS UNITS

+5V Supply (Pins 31, 38) 0 to +6 Volts
–5V Supply (Pin 37) 0 to –6 Volts
Digital Inputs (Pins 8, 9, 12, 34, 35) –0.3 to +V

DD +0.3 Volts

Analog Input (Pin 3) Volts

Bipolar ±5 Volts
Unipolar –10 to +5 Volts

Lead Temperature (10 seconds) +300 °C

PHYSICAL/ENVIRONMENTAL

FUNCTIONAL SPECIFICATIONS

(TA = +25°C, ±VCC = ±5V, +VDD = +5V, 1MHz sampling rate, and a minimum 3 minute warm-up ➀ unless otherwise specified.)

ADS-931

® ®

3

+25°C 0 TO +70°C –55 TO +125°C

DYNAMIC PERFORMANCE (Cont.) MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

Overvoltage Recovery Time ➄ — — 1000 — — 1000 — — 1000 ns
A/D Conversion Rate 1 — — 1 — — 1 — — MHz

Footnotes:

➃ Effective bits is equal to:

➀ All power supplies must be on before applying a start convert pulse. All supplies

and the clock (START CONVERT) must be present during warm-up periods.
The device must be continuously converting during this time. There is a slight
degradation in performance when operating the device in the unipolar mode.

➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA.
➂ A 1MHz clock with a positive pulse width is used for all production testing. See

Timing Diagram for more details.
40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns

6.02

(SNR + Distortion) – 1.76 + 20 log

Full Scale Amplitude

Actual Input Amplitude

➄ This is the time required before the A/D output data is valid once the analog input

is back within the specified range. This time is only guaranteed if the input does not

exceed ±4.75V (bipolar) or +2 to –7.5V (unipolar).

➅ The minimum supply voltages of +4.9V and –4.9V for ±V

DD are required for

–55°C operation only. The minimum limits are +4.75V and –4.75V when

operating at +125°C.

TECHNICAL NOTES

1. Obtaining fully specified performance from the ADS-931
requires careful attention to pc-card layout and power supply
decoupling. The device's analog and digital ground systems
are connected to each other internally. For optimal perfor­mance, tie all ground pins (4, 7, 30 and 36) directly to a large
analog ground plane beneath the package.

Bypass all power supplies and the +3.2V reference output to
ground with 4.7µF tantalum capacitors in parallel with 0.1µF
ceramic capacitors. Locate the bypass capacitors as close to
the unit as possible.

2. The ADS-931 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain calibration hardware,
make adjustments following warm-up. To avoid interaction,
always adjust offset before gain. Tie pins 5 and 6 to
ANALOG GROUND (pin 4) if not using offset and gain
adjust circuits.

3. Pin 35 (COMP. BITS) is used to select the digital output
coding format of the ADS-931 (see Tables 2a and 2b). When
this pin has a TTL logic "0" applied, it complements the ADS­931’s B1-B16 & B1 outputs.

Pin 35 is TTL compatible and can be directly driven with digital
logic in applications requiring dynamic control over its function.
There is an internal pull-up resistor on pin 35 allowing it to be
either connected to +5V or left open when a logic "1" is
required.

4. To enable the three-state outputs, connect OUTPUT
ENABLE (pin 34) to a logic "0" (low). To disable, connect
pin 34 to a logic "1" (high).

5. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") will initiate a new and probably
inaccurate conversion cycle. Data from both the interrupted
and subsequent conversions will be invalid.

ANALOG OUTPUT

Internal Reference

Voltage 3.15 +3.2 3.25 3.15 +3.2 3.25 3.15 +3.2 3.25 Volts
Drift — ±30 — — ±30 — — ±30 — ppm/°C

External Current — 5 — — 5 — — 5 — mA

DIGITAL OUTPUTS

Logic Levels

Logic "1" +2.4 — — +2.4 — — +2.4 — — Volts
Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts
Logic Loading "1" — — –4 — — –4 — — –4 mA
Logic Loading "0" — — +4 — — +4 — — +4 mA

Delay, Falling Edge of Enable to
Output Data Valid — — 20 — — 20 — — 20 ns

Output Coding

Straight Binary, Complementary Binary, Complementary Offset Binary,
Complementary Two's Complement, Offset Binary, Two's Complement

POWER REQUIREMENTS

Power Supply Ranges ➅

+5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 Volts
–5V Supply –4.75 –5.0 –5.25 –4.75 –5.0 –5.25 –4.9 –5.0 –5.25 Volts

Power Supply Currents

+5V Supply — +225 260 — +225 260 — +225 260 mA
–5V Supply –140 –135 — –140 –135 — –140 –135 — mA

Power Dissipation — 1.85 2.0 — 1.85 2.0 — 1.85 2.0 Watts
Power Supply Rejection — — ±0.07 — — ±0.07 — — ±0.07 %FSR/%V

ADS-931

® ®

4

DELAY PIN TRANSITION MIN. TYP. MAX. UNITS

Direct mode to FIFO enabled 8 – 10 20 ns
FIFO enabled to direct mode 8 – 10 20 ns
FIFO READ to output data valid 9 – – 40 ns
FIFO READ to status update when changing

from <half full (1 word) to empty

9 – – 20 ns

FIFO READ to status update when changing
from ≥half full (8 words) to <half full (7 words)

9 – – 110 ns

FIFO READ to status update when changing
from full (16 words) to ≥half full (15 words)

9 – – 190 ns

Falling edge of EOC to status update when writing
first word into empty FIFO

32 – – 190 ns

Falling edge of EOC to status update when
changing FIFO from <half full (7 words) to 32 – – 110 ns
≥half full (8 words)

Falling edge of EOC to status update when filling
FIFO with 16th word

32 – – 28 ns

When the FIFO is initially empty, digital data from the first
conversion (the "oldest" data) appears at the output of the
FIFO immediately after the first conversion has been
completed and remains there until the FIFO is read.

If the output three-state register has been enabled (logic "0"
applied to pin 34), data from the first conversion will appear at
the output of the ADS-931. Attempting to write a 17th word to a
full FIFO will result in that data, and any subsequent conversion
data, being lost.

Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both
equal to "1"), it can be read by dropping the FIFO READ line
(pin 9) to a logic "0" and then applying a series of 15 rising
edges to the read line. Since the first data word is already
present at the FIFO output, the first read command (the first
rising edge applied to FIFO READ) will bring data from the
second conversion to the output. Each subsequent read
command/rising edge brings the next word to the output lines.
After the 15th rising edge brings the 16th data word to the
FIFO output, the subsequent falling edge on READ will update
the status outputs (after a 20ns maximum delay) to FSTAT1 =
0, FSTAT2 = 1 indicating that the FIFO is empty.

If a read command is issued after the FIFO empties, the last
word (the 16th conversion) will remain present at the outputs.

FIFO Reset Feature

At any time, the FIFO can be reset to an empty state by putting
the ADS-931 into its "direct" mode (logic "0" applied to pin 8,
FIFO/DIR) and also applying a logic "0" to the FIFO READ line
(pin 9). The empty status of the FIFO will be indicated by
FSTAT1 going to a "0" and FSTAT2 going to a "1". The status
outputs change 40ns after applying the control signals.

FIFO Status, FSTAT1 and FSTAT2

Monitor the status of the data in the FIFO by reading the two
status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11).

CONTENTS FSTAT1 FSTAT2

Empty (0 words) 0 1
<half full (<8 words) 0 0
half-full or more (≥8 words) 1 0
Full (16 words) 1 1

Table 1. FIFO Delays

1

0

0

1

1

0

0

1

0

1

0

1

0

1

1

0

1

0

6. Do not enable/disable or complement the output bits or read
from the FIFO during the conversion process (from the rising
edge of EOC to the falling edge of EOC).

7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the
input voltage exceeds that which produces an output of all
1’s or when the input equals or exceeds the voltage that
produces all 0’s. When COMP BITS is activated, the above
conditions are reversed.

8. When configuring the ADS-931 for the unipolar mode, Pin 1
(+3.2V REF.) should be connected to Pin 2 (Unipolar) through
a non-inverting op-amp. For precision DC applications an OP­07 type amplifier is recommended, while AC applications
requiring the lowest level of harmonic distortion should
consider the AD9631.
When configuring the ADS-931 for the bipolar mode, Pin 2
(Unipolar) should be physically disconnected from the
surrounding circuitry. This will help prevent noise from
coupling into the A/D.

INTERNAL FIFO OPERATION

The ADS-931 contains an internal, user-initiated, 18-bit, 16-word
FIFO memory. Each word in the FIFO contains the 16 data bits
as well as the MSB and overflow bits. Pins 8 (FIFO/DIR) and 9
(FIFO READ) control the FIFO's operation. The FIFO's status
can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2).

When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is
inserted into the digital data path. When pin 8 has a logic "0"
applied, the FIFO is transparent and the output data goes
directly to the output three-state register (whose operation is
controlled by pin 34 (ENABLE)). Read and write commands
to the FIFO are ignored when the ADS-931 is operated in the
"direct" mode. It takes a maximum of 20ns to switch the FIFO
in or out of the ADS-931’s digital data path.

FIFO Write and Read Modes

Once the FIFO has been enabled (pin 8 high), digital data is
automatically written to it, regardless of the status of FIFO
READ (pin 9). Assuming the FIFO is initially empty, it will
accept data (18-bit words) from the next 16 consecutive A/D
conversions. As a precaution, pin 9 (which controls the
FIFO's READ function) should not be low when data is first
written to an empty FIFO.

ADS-931

® ®

5

for operation without gain adjustment.

Zero/Offset Adjust Procedure

1. Apply a train of pulses to the START CONVERT input (pin

12) so that the converter is continuously converting.

2. For unipolar or bipolar zero/offset adjust, apply –42µV to the
ANALOG INPUT (pin 3).

3. For bipolar inputs, adjust the offset potentiometer until the
code flickers between 1000 0000 0000 0000 and 0111
1111 1111 1111 with pin 35 tied high (complementary
offset binary) or between 0111 1111 1111 1111 and 1000
0000 0000 0000 with pin 35 tied low (offset binary).
For unipolar inputs, adjust the offset potentiometers until all
output bits are 0's and the LSB flickers between 0 and 1
with Pin 35 tied high (straight binary) or until all bits are 1's
and the LSB flickers between 0 and 1 with pin 35 tied low
(complementary binary).

4. Two's complement coding requires using BIT 1 (MSB) (pin

29). With pin 35 tied low, adjust the trimpot until the output
code flickers between all 0’s and all 1’s.

Gain Adjust Procedure

1. Apply +2.749874V to the ANALOG INPUT (pin 3).

2. For bipolar inputs, adjust the gain potentiometer until all output
bits are 0’s and the LSB flickers between a 1 and 0 with pin 35
tied high (complementary offset binary) or until all output bits
are 1’s and the LSB flickers between a 1 and 0 with pin 35 tied
low (offset binary).

3. Two's complement coding requires using BIT 1 (MSB)
(pin 29). With pin 35 tied low, adjust the gain trimpot until
the output code flickers equally between 0111 1111 1111
1111 and 0111 1111 1111 1110.

CALIBRATION PROCEDURE

Connect the converter per Figure 2. Any offset/gain calibration
procedures should not be implemented until the device is fully
warmed up. To avoid interaction, adjust offset before gain. The
ranges of adjustment for the circuits in Figure 2 are guaranteed
to compensate for the ADS-931’s initial accuracy errors and
may not be able to compensate for additional system errors.

A/D converters are calibrated by positioning their digital outputs
exactly on the transition point between two adjacent digital
output codes. This is accomplished by connecting LED's to the
digital outputs and performing adjustments until certain LED's
"flicker" equally between on and off. Other approaches employ
digital comparators or microcontrollers to detect when the
outputs change from one code to the next.

For the ADS-931, offset adjusting is normally accomplished
when the analog input is 0 minus ½ LSB (–42µV). See Table
2b for the proper bipolar output coding.

Gain adjusting is accomplished when the analog input is at
nominal full scale minus 1½ LSB's (+2.749874V).

Note: Connect pin 5 to ANALOG GROUND (pin 4) for
operation without zero/offset adjustment. Connect pin 6 to pin 4

Figure 2. Bipolar Connection Diagram

Complementary Offset Binary 1
Offset Binary 0
Complementary Two’s Complement 1

(Using MSB, pin 29)
Two’s Complement 0

(Using MSB, pin 29)
Straight Binary 1

Complimentary Binary 0

OUTPUT FORMAT PIN 35 LOGIC LEVEL

Table 2a. Setting Output Coding Selection (Pin 35)

ADS-931

20k

Ω

33
32
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13

OVERFLOW
EOC
BIT 1 (MSB)
BIT 1 (MSB)
BIT2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16 (LSB)

ANALOG
GROUND

DIGITAL
GROUND

0.1µF

4.7µF

0.1µF

COMP. BITS

4.7µF

+3.2V
REF. OUT

FIFO READ

31

7, 30

35

1

9

+5V
DIGITAL

–5V+5V

OFFSET
ADJUST

GAIN

ADJUST

5

6

3

0.1µF

4.7µF

4, 36

37

0.1µF

4.7µF

38

+ +

20k

Ω

–5V+5V

–5V

+5V ANALOG

12START CONVERT

ANALOG INPUT

34 ENABLE

8 FIFO/DIR

10

FSTAT1

11

FSTAT2

+5V

+5V

+5V

–5V

UNIPOLAR

CONNECT for UNIPOLAR MODE

2

6.8µF

ADS-931

® ®

6

THERMAL REQUIREMENTS

All DATEL sampling A/D converters are fully characterized and
specified over operating temperature (case) ranges of 0 to
+70°C and –55 to +125°C. All room-temperature (T

A = +25°C)

production testing is performed without the use of heat sinks or
forced-air cooling. Thermal impedance figures for each device
are listed in their respective specification tables.

These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should be
used to ensure devices do not overheat. The ground and power
planes beneath the package, as well as all pcb signal runs to
and from the device, should be as heavy as possible to help
conduct heat away from the package. Electrically
insulating, thermally-conductive "pads" may be installed

underneath the package. Devices should be soldered to boards
rather than "socketed", and of course, minimal air flow over the
surface can greatly help reduce the package temperature.

In more severe ambient conditions, the package/junction
temperature of a given device can be reduced dramatically
(typically 35%) by using one of DATEL's HS Series heat sinks.
See Ordering Information for the assigned part number. See
page 1-183 of the DATEL Data Acquisition Components Catalog
for more information on the HS Series. Request DATEL
Application Note AN-8, "Heat Sinks for DIP Data Converters," or
contact DATEL directly, for additional information.

Figure 4. FFT Analysis of ADS-931

Figure 3. ADS-931 Timing Diagram

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100
–110
–120
–130
–140
–150
–160
–170

0 50 100 150 200 250 300 350 400 450 500

Frequency (kHz)

(fs = 1MHz, fin = 480kHz, Vin = –0.5dB, 16,384-point FFT)

Amplitude Relative to Full Scale (dB)

This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data
from the first conversion to appear at the output of the A/D.

START

CONVERT

INTERNAL S/H

N N+1

Acquisition Time

730ns typ.

20ns typ.

EOC

60ns typ.

OUTPUT

DATA

Data N-4 Valid Data N-2 Valid

Invalid

Data

Data N-3 Valid

20ns typ.

N+2

Data N-1 Valid

940ns typ.

60ns typ.

Invalid

Data

Notes:

100ns typ.

N+3

55ns typ.

280ns typ.

Conversion Time

Hold

The start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec
(when sampling at 1MHz) to ensure proper operation. For sampling rates lower than 1MHz, the start pulse
can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. A 1MHz

clock with a 100nsec positive pulse width is used for all production testing.

Scale is approximately 50ns per division. fs = 1MHz.1.

2.

3.

270ns typ.

ADS-931

®

®

7

Figure 5. ADS-931 Evaluation Board Schematic.

20K

R4

1

2

3

U2

9

8

7

6

5

4

3

2

11

1

19

18

17

16

15

14

13

12

1020

74H C T573

UUT

B6

B7

B8

B9

B10

B11

+5VD

DGND

MSB

MSB

B2

B3

B4

B5

B12

B13

B14

B15

LSB

STARTCON

FSTAT2

FSTAT1

NC

NC

+5VA

5VA

AGND

COMP

ENABLE

OF

EOC

READ

FIFO/DIR

DGND

GAIN

OFFSET

AGND

ANA IN

2

+3.2VREF

U6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20 21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

U1

12

11

13

8

9

10

74HC T74

2.2µF

C13

1

2

33

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

34

32

30

28

26

24

22

20

18

16

14

12

10

8

6

4

2

P1

FST2STARTCO

FST1

B16

FIF/DIRB15

READB14

NC

B13

COMPLIMB12

ENABLEB11

DGNDB10

DGND

B9

DGND

B8

DGND

B7

DGND

B6

DGND

B5

DGND

B4

EOC

B3

OVRFLW

B2

B1BB1(M SB)

2.2µF

C11

1

2

.1 µ F

C20

1

2

U4

9

8

7

6

5

4

3

2

11

1

19

18

17

16

15

14

13

12

1020

74H C T573

.1 µ F

C15

1

2

33pF

C10

1

2

.1 µ F

C18

1

2

.1 µ F

C3

1

2

2.2µF

C1

1

2

2.2µF

C14

1

2

2.2µF

C2

1

2

2.2µF

C9

1

2

SG8

SG7

2.2µF

C12

1

2

2.2µF

C21

1

2

R2

12

R1

12

3.3K

R3

12

U1

2

3

1

6

5

4

74HC T74

SG9

12

2.2µF

C22

2.2µF

C4

1

2

20µH

L4

12

+



AR1

2

3

4

6

7

.1uF

C5

1

2

20µH

L3

12

U3

9

8

7

6

5

4

3

2

11

1

19

18

17

16

15

14

13

12

1020

74H C T573

SG4

12

SG3

12

X1

1

78

14

1M H Z

SG2

12

20K

R5

1

2

3

74HC86

1
2

3

C6

1

2

2.2µF

20µH

L2

12

.1 µ F

C19

1

2

+



AR2

2

3

4

6

7

OP07

J5

P2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

50

R6

12

SG5

12

74HC86

12

13

11

74HC86

U5

4
5

6

J2

20µH

L1

12

74HC86

9

10

8

B2

1

2

J3

.1 µ F

C16

1

2

.1 µ F

C17

1

2

2.2µF

C7

1

2

B1

1

2

J4

J1

.1 µ F

C8

1

2

SG1

12

B3

COMP

COMP

ENABLE

ENABLE

+5VA

+5VA +5VA

+5VA

+5VA

+5VA +5V A

+5VA

+5VF

+5VF

+5VF

+5VF

+5VF

+5VF

+5VF

+5VF

+5VF

FIF

FIF

RD

RD

STARTCONV

B2

AB9

AB9

+15V

+15V

+15V

EOC

EOC

OF

AB8

AB8

AB1

AB1

AB2

AB2

AB3

AB3

AB4

AB4

AB5

AB5

AB6

AB6

AB7

AB7

AB16

AB16

AB15

AB15

AB14

AB14

AB13

AB13

AB12

AB12

AB11

AB11

AB10AB10

AB10

FIFO /DIR

READ

COMPLIM

FST1

B15

B14

FST2

OVRFLW

B1

+5VD +5VD

+5VD

+5VD

+5VD

+5VD

B4

B5

B6

B7

B1B

B13

B16

B8

B12

B11

B10

B9

15V

15V

15V

AGND AGND AGN D AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGN D

5VA

-5 V A -5 V A

5VA

5VA

-5 V A -5 V A

-5 V A

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGNDDGND

DGND

DGND

DGND

DGND

DGND DGND DG ND

DGND

DGND

DGND

DGND

DGND

DGND

START CONVER T

ANALOG INPUT

OPTION

AM PLIFIER

N.C.

33221

1

7

14

7

(L S B )

GAIN ADJ

OFFSET ADJ

3

3

3

3

2

2

2

2

1

1

1

1

(M S B )

(M S B )

(L S B )

(M S B )

14

NV

U5

U5

U5

ADS-931

® ®

8

Complementary Offset Binary 1
Offset Binary 0
Complementary Two’s Complement 1

(Using MSB, pin 29)
Two’s Complement 0

(Using MSB, pin 29)
Straight Binary 1

Complimentary Binary 0

OUTPUT FORMAT PIN 35 LOGIC LEVEL

Table 2a. Setting Output Coding Selection (Pin 35)

Table 2b. Output Coding

1111 1111 1111 1111

LSB "1" to "0"
1110 0000 0000 0000
1100 0000 0000 0000
1000 0000 0000 0000
0111 1111 1111 1111
0100 0000 0000 0000
0010 0000 0000 0000
0000 0000 0000 0001

LSB "0" to "1"
0000 0000 0000 0000

MSB LSB MSB LSB

+FS –1 LSB

+FS –1 1/2 LSB

+3/4 FS
+1/2 FS

0

–1 LSB
–1/2 FS
–3/4 FS

–FS +1 LSB

–FS + 1/2 LSB

–FS

STRAIGHT BINARY

INPUT

RANGE

±2.75V

+2.749916
+2.749874
+2.062500
+1.375000

0.000000
–0.000084
–1.375000
–2.062500
–2.749916
–2.749958
–2.750000

0000 0000 0000 0000

LSB "0" to "1"
0001 1111 1111 1111
0011 1111 1111 1111
0111 1111 1111 1111
1000 000 000 0000
1011 1111 1111 1111
1101 1111 1111 1111
1111 1111 1111 1110

LSB "1" to "0"

1111 1111 1111 1111

0111 1111 1111 1111

LSB "1" to "0"
0110 0000 0000 0000
0100 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1100 0000 0000 0000
1010 0000 0000 0000
1000 0000 0000 0001

LSB "0" to "1"
1000 0000 0000 0000

1000 0000 0000 0000

LSB "0" to "1"
1001 1111 1111 1111
1011 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0011 1111 1111 1111
0101 1111 1111 1111
0111 1111 1111 1110

LSB "1" to "0"
0111 1111 1111 1111

BIPOLAR

SCALE

INPUT

RANGE

0 to –5.5V

UNIPOLAR

SCALE

–5.499916
–5.499874
–4.812500
–4.125000
–2.750000
–2.749958
–1.375000
–0.687500
–0.000084
–0.000042

0.000000

–FS+1 LSB

–FS +1 1/2 LSB

–7/8 FS
–3/4 FS
–1/2 FS

–1/2FS–1/2LSB

–1/4 FS
–1/8 FS

–1 LSB

–1/2 LSB

0

MSB LSB MSB LSB

OUTPUT CODING

COMP. BINARY

COMP. OFF. BIN.OFFSET BINARY TWO'S COMP. COMP. TWO'S COMP.

0 to –5.5V Pin 3 Pin 1 To Pin 2
±2.75V Pin 3 Pin 2 is No Connect

Input Range Input Pin Connect

Table 3. Input Connections

ADS-931

® ®

9

0

2147

0.00

0.71

–0.56

65,536

65,536

0

Figure 5. ADS-931 Histogram and Differential Nonlinearity

DNL (LSB's)

Codes

Digital Output Code

Number of Occurrences

Figure 6. ADS-931 Grounded Input Histogram

This histogram represents the typical peak-to-peak noise

(including quantization noise) associated with the ADS-931.

Digital Output Code

0

1000

2000

3000

4000

4530

ADS-931

® ®

® ®

INNOV A TION and EX CELLENCE

DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting
of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

DS-0307 9/97

MECHANICAL DIMENSIONS INCHES (mm)

ORDERING INFORMATION

OPERATING

MODEL TEMP. RANGE
ADS-931MC 0 to +70°C

ADS-931MM –55 to +125°C

Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead
Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.

ACCESSORIES
ADS-B931 Evaluation Board (without ADS-931)

HS-40 Heat Sink for all ADS-931 models

PIN 1 INDEX
( ON TOP)

2.12/2.07

(53.85/52.58)

0.018 ±0.002
(0.457)

0.100 TYP.
(2.540)

0.110/0.090

(2.794/2.286)

SEATING

PLANE

0.035/0.015

(0.889/0.381)

0.200/0.175

(5.080/4.445)

0.245 MAX.
(6.223)

0.210 MAX.
(5.334)

0.045/0.035

(1.143/0.889)

1.11/1.08

(28.20/27.43)

1 20

21 40

1.900 ±0.008
(48.260)

Dimension Tolerances (unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)

Lead Material:

Kovar alloy

Lead Finish: 50 microinches (minimum) gold plating
over 100 microinches (nominal) nickel plating

0.015/0.009

(0.381/0.229)

0.900 ±0.010
(22.86)

0.110/0.090
(2.794/2.286

ISO 9001

ISO 9001

REGISTERED

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: [phone] [phone] Fax: [phone]
Internet: www.datel.com E-mail:[e-mail]
Data Sheet Fax Back: [phone]

DATEL (UK) LTD. Tadley, England Tel: [phone]
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: [phone]
DATEL GmbH München, Germany Tel: [phone]
DATEL KK Tokyo, Japan Tel: [phone], Osaka Tel: [phone]