Datasheet ADS7862YB-2K5, ADS7862YB-250, ADS7862Y-2K5, ADS7862 Datasheet (Burr Brown Corporation)

1

ADS7862

®

Dual 500kHz, 12-Bit, 2 + 2 Channel

Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 4 INPUT CHANNELS

● FULLY DIFFERENTIAL INPUTS

● 2µs TOTAL THROUGHPUT PER CHANNEL

● GUARANTEED NO MISSING CODES

● PARALLEL INTERFACE

● 1MHz EFFECTIVE SAMPLING RATE

● LOW POWER: 40mW

APPLICATIONS

● MOTOR CONTROL

● MULTI-AXIS POSITIONING SYSTEMS

● 3-PHASE POWER CONTROL

DESCRIPTION

The ADS7862 is a dual 12-bit, 500kHz analog-to­digital converter (A/D) with 4 fully differential input
channels grouped into two pairs for high speed simulta­neous signal acquisition. Inputs to the sample-and-hold
amplifiers are fully differential and are maintained dif­ferential to the input of the A/D converter. This provides
excellent common-mode rejection of 80dB at 50kHz
which is important in high noise environments.

The ADS7862 offers parallel interface and control in­puts to minimize software overhead. The output data for
each channel is available as a 12-bit word. The ADS7862
is offered in an TQFP-32 package and is full specified
over the –40°C to +85°C operating range.

®

ADS7862

© 1998 Burr-Brown Corporation PDS-1475B Printed in U.S.A. May, 2000

SAR

Interface

Conversion

and

Control

Output

Registers

COMP

CONVST

BUSY

RD

CS

Data Output

12

CLOCK

A0

CDAC

Internal

2.5V

Reference

S/H

Amp

S/H

Amp

CH A0–

CH A0+

REF

IN

CH A1–

CH A1+

SAR

COMP

CDAC

MUX

MUX

CH B0–

CH B0+

CH B1–

CH B1+

REF

OUT

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

ADS7862

¤

For most current data sheet and other product

information, visit www.burr-brown.com

2

ADS7862

®

SPECIFICATIONS

All specifications T

MIN

to T

MAX

, +VA = +VD = +5V, V

REF

= internal +2.5V and f

CLK

= 8MHz, f

SAMPLE

= 500kHz, unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

ADS7862Y ADS7862YB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻ Bits

ANALOG INPUT

Input Voltage Range-Bipolar V

CENTER

= Internal V

REF

at 2.5V –V

REF

+V

REF

✻✻V

Absolute Input Range +IN –0.3 V

CC

+ 0.3 V

–IN –0.3 V

CC

+ 0.3 V
Input Capacitance 15 ✻ pF
Input Leakage Current CLK = GND ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 12 ✻ Bits
Integral Linearity ±0.75 ±2 ±0.5 ±1 LSB
Integral Linearity Match 0.5 1 ✻✻ LSB
Differential Linearity ±0.75 ±0.5 ±1 LSB
Bipolar Offset Error Referenced to REF

IN

±0.75 ±3 ±0.5 ±2 LSB
Bipolar Offset Error Match 3 2 LSB
Positive Gain Error Referenced to REF

IN

±0.15 ±0.75 ±0.1 ±0.5 % of FSR
Positive Gain Error Match 2 1 LSB
Negative Gain Error Referenced to REF

IN

±0.15 ±0.75 ±0.1 ±0.5 % of FSR
Negative Gain Error Match 2 1 LSB
Common-Mode Rejection Ratio At DC 80 ✻ dB

V

IN

= ±1.25Vp-p at 50kHz 80 ✻ dB
Noise 120 ✻ µVrms
Power Supply Rejection Ratio ±0.5 ±2 ✻✻ LSB

SAMPLING DYNAMICS

Conversion Time per A/D 1.75 ✻ µs
Acquisition Time 0.25 ✻ µs
Throughput Rate 500 ✻ kHz
Aperture Delay 3.5 ✻ ns
Aperture Delay Matching 100 ✻ ps
Aperture Jitter 50 ✻ ps
Small-Signal Bandwidth 40 ✻ MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion V

IN

= ±2.5Vp-p at 100kHz 75 ✻ dB
SINAD V

IN

= ±2.5Vp-p at 100kHz 71 ✻ dB
Spurious Free Dynamic Range V

IN

= ±2.5Vp-p at 100kHz –78 ✻ dB
Channel-to-Channel Isolation V

IN

= ±2.5Vp-p at 100kHz –80 ✻ dB

VOLTAGE REFERENCE

Internal 2.475 2.5 2.525 ✻✻✻ V
Internal Drift ±25 ✻ ppm/°C
Internal Noise 50 ✻ µVp-p
Internal Source Current 2 ✻ mA
Internal Load Rejection 0.005 ✻ mV/µA
Internal PSRR 65 ✻ dB
External Voltage Range 1.2 2.5 2.6 ✻✻✻ V
Input Current 0.05 1 ✻✻ µA
Input Capacitance 5 ✻ pF

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻
Logic Levels: V

IH

IIH = +5µA 3.0

+VDD + 0.3

✻✻V

V

IL

IIL = +5µA –0.3 0.8 ✻✻V

V

OH

IOH = –500µA 3.5 ✻ V

V

OL

IOL = 500µA 0.4 ✻ V
External Clock 0.2 8 ✻✻MHz
Data Format Binary Two’s Complement ✻

POWER SUPPLY REQUIREMENTS

Power Supply Voltage, +V 4.75 5 5.25 ✻✻✻ V
Quiescent Current, +V

A

58 ✻✻ mA

Power Dissipation 25 40 ✻✻ mW

✻ Specifications same as ADS7862Y.

3

ADS7862

®

PIN NAME DESCRIPTION

1 REF

IN

Reference Input

2 REF

OUT

+2.5V Reference Output. Connect directly to REF

IN

(pin 1) when using internal reference.
3 AGND Analog Ground
4+V

A

Analog Power Supply, +5VDC. Connect directly to

digital power supply (pin 24). Decouple to analog

ground with a 0.1µF ceramic capacitor and a 10µF

tantalum capacitor.
5 DB11 Data Bit 11, MSB
6 DB10 Data Bit 10
7 DB9 Data Bit 9
8 DB8 Data Bit 8
9 DB7 Data Bit 7

10 DB6 Data Bit 6
11 DB5 Data Bit 5
12 DB4 Data Bit 4
13 DB3 Data Bit 3
14 DB2 Data Bit 2
15 DB1 Data Bit 1
16 DB0 Data Bit 0, LSB
17 BUSY HIGH when a conversion is in progress.
18 CONVST Convert Start
19 CLOCK An external CMOS-compatible clock can be applied to

the CLOCK input to synchronize the conversion pro-

cess to an external source. The CLOCK pin controls

the sampling rate by the equation: CLOCK 16 • f

SAMPLE

.
20 CS Chip Select
21 RD Synchronization pulse for the parallel output. During a

Read operation, the first falling edge selects the A
register and the second edge selects the B register,
A0, then controls whether input 0 or input 1 is read.

22 A0 On the falling edge of Convert Start, when A0 is LOW

Channel A0 and Channel B0 are converted and when
it is HIGH, Channel A1 and Channel B1 are converted.
During a Read operation, the first falling edge selects
the A register and the second edge selects the B of RD
register, A0, then controls whether input 0 or input 1 is

read.
23 DGND Digital Ground. Connect directly to analog ground (pin 3).
24 +V

D

Digital Power Supply, +5VDC
25 CH B1+ Non-Inverting Input Channel B1
26 CH B1– Inverting Input Channel B1
27 CH B0+ Non-Inverting Input Channel B0
28 CH B0– Inverting Input Channel B0
29 CH A1– Inverting Input Channel A1
30 CH A1+ Non-Inverting Input Channel A1
31 CH A0– Inverting Input Channel A0
32 CH A0+ Non-Inverting Input Channel A0

PIN CONFIGURATION

Top View

PIN DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGS

Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V)

REF

IN

............................. –0.3V to (+VD + 0.3V)

Digital Inputs to DGND .......................................... –0.3V to (+V

D

+ 0.3V)

Ground Voltage Differences: AGND, DGND ................................... ±0.3V

+V

D

to AGND......................... –0.3V to +6V

Power Dissipation .......................................................................... 325mW

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................ –40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi­cations.

REF

IN

REF

OUT

AGND

+V

A

DB11
DB10

DB9
DB8

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

+V

D

DGND
A0
RD
CS
CLOCK
CONVST
BUSY

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

9 10111213141516

CH A0+

CH A0–

CH A1+

CH A1–

CH B0–

CH B0+

CH B1–

CH B1+

32 31 30 29 28

ADS7862

27 26 25

4

ADS7862

®

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM
RELATIVE GAIN PACKAGE SPECIFICATION

ACCURACY ERROR DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT (LSB) (%) PACKAGE NUMBER

(1)

RANGE MARKING

(2)

NUMBER

(3)

MEDIA

ADS7862Y ±2 ±0.75 TQFP-32 351 –40°C to +85°C A62 ADS7862Y/250 Tape and Reel
ADS7862Y

""""""ADS7862Y/2K5 Tape and Reel

ADS7862YB ±1 ±0.5 TQFP-32 351 –40°C to +85°C A62 ADS7862YB/250 Tape and Reel
ADS7862YB

""""""ADS7862YB/2K5 Tape and Reel

NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked
on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices
per reel). Ordering 2500 pieces of ”ADS7862Y/2K5“ will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the
www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions.

BASIC OPERATION

REF

IN

REF

OUT

AGND
+V

A

DB11
DB10
DB9
DB8

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

+V

D

DGND

A0
RD
CS

CLOCK

CONVST

BUSY

Address Select
Read Input
Chip Select
Clock Input
Conversion Start
Busy Output

ADS7862Y

10µF

+

0.1µF

+5V

Analog Supply

+

32

31

30

29

28

27

26

25

CH A0+

CH A0–

CH A1+

CH A1–

CH B0–

CH B0+

CH B1–

CH B1+

9

10

11

12

13

14

15

16

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

5

ADS7862

®

FREQUENCY SPECTRUM

(4096 Point FFT; f

IN

= 199.9kHz, –0.5dB)

Frequency (kHz)

0

–20

–40

–60

–80

–100

–120

Amplitude (dB)

0 62.5 125 250187.5

TYPICAL PERFORMANCE CURVES

At TA = +25°C, +VA = +VD = +5V, V

REF

= internal +2.5V and f

CLK

= 8MHz, f

SAMPLE

= 500kHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f

IN

= 99.9kHz, –0.5dB)

Frequency (kHz)

0

–20

–40

–60

–80

–100

–120

Amplitude (dB)

0 62.5 125 250187.5

CHANGE IN SIGNAL-TO-NOISE RATIO

AND SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

Temperature (°C)

0.25

0.2

0.15

0.1

0.05
0

–0.05

–0.1

–0.15

–0.2

–0.25

Delta from +25°C (dB)

–40 25 85

SNR

SINAD

CHANGE IN SPURIOUS FREE DYNAMIC RANGE

AND TOTAL HARMONIC DISTORTION

vs TEMPERATURE

Temperature (°C)

0.65

0.45

0.25

0.05

–0.15

–0.35

–0.55

–0.75

0.65

0.45

0.25

0.05

–0.15

–0.35

–0.55

–0.75

SFDR Delta from +25°C (dB)

THD Delta from +25°C (dB)

–40 25 85

SFDR

THD

CHANGE IN POSITIVE GAIN MATCH

vs TEMPERATURE

(Maximum Deviation for All Four Channels)

Temperature (°C)

0.6

0.5

0.4

0.3

0.2

0.1

0

Change in Positive Gain Match (LSB)

–40 25 85 150

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE+DISTORTION)

vs INPUT FREQUENCY

10k 100k1k 1M

Input Frequency (Hz)

SNR and SINAD (dB)

74

72

70

68

66

64

76

SINAD

SNR

6

ADS7862

®

INTEGRAL LINEARITY ERROR vs CODE

Hex BTC Code

1

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6
–0.8

–1

ILE (LSB)

800 000 7FF

Typical of All Four Channels

TYPICAL PERFORMANCE CURVES (Cont.)

At TA = +25°C, +VA = +VD = +5V, V

REF

= internal +2.5V and f

CLK

= 8MHz, f

SAMPLE

= 500kHz, unless otherwise noted.

CHANGE IN NEGATIVE GAIN MATCH

vs TEMPERATURE

(Maximum Deviation for All Four Channels)

Temperature (°C)

0.2

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02
0

Change in Negative Gain Match (LSB)

–40 25 85 150

CHANGE IN REFERENCE VOLTAGE

vs TEMPERATURE

Temperature (°C)

2.51

2.505

2.5

2.495

2.49

2.485

Change in Reference (V)

–40 25 85 150

CHANGE IN BIPOLAR ZERO

vs TEMPERATURE

Temperature (°C)

0.75

0.5

0.25

0

–0.25

–0.5

–0.75

Change in Bipolar Zero (LSB)

–40 25

A Channel

B Channel

85 150

CHANGE IN BPZ MATCH vs TEMPERATURE

Temperature (°C)

1

0.75

0.5

0.25

0

Change in Bipolar Zero Match (LSB)

–40 25 85 150

CHANGE IN CMRR vs TEMPERATURE

Temperature (°C)

86
85
84
83
82
81
80
79
78

Change in CMRR (dB)

–40 –5 25 55 85

7

ADS7862

®

DIFFERENTIAL LINEARITY ERROR vs CODE

Hex BTC Code

Typical of All Four Channels

1

0.75

0.5

0.25
0

–0.25

–0.5

–0.75

–1

DLE (LSB)

800 000 7FF

TYPICAL PERFORMANCE CURVES (Cont.)

At TA = +25°C, +VA = +VD = +5V, V

REF

= internal +2.5V and f

CLK

= 8MHz, f

SAMPLE

= 500kHz, unless otherwise noted.

INTEGRAL LINEARITY ERROR MATCH

vs CODE CHANNEL A0/CHANNEL A1

(Same Converter, Different Channels)

Hex BTC Code

0.25

0.2

0.15

0.1

0.05
0

–0.05

–0.1

–0.15

–0.2

–0.25

ILE (LSB)

800 000 7FF

INTEGRAL LINEARITY ERROR MATCH

vs CODE CHANNEL A0/CHANNEL B1

(Different Converter, Different Channels)

Hex BTC Code

0.25

0.2

0.15

0.1

0.05
0

–0.05

–0.1

–0.15

–0.2

–0.25

ILE (LSB)

800 000 7FF

INTEGRAL LINEARITY ERROR vs TEMPERATURE

Positive ILE

Negative ILE

Temperature (°C)

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

Change in ILE (LSB)

–40 25 85 150

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

Temperature (°C)

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6
–0.8

DLE Error (LSB)

–40 25

Positive DLE

Negative DLE

85 150

INTEGRAL LINEARITY ERROR MATCH

vs TEMPERATURE

CHANNEL A0/CHANNEL B0

(Different Converter, Different Channels)

Temperature (°C)

0.19

0.18

0.17

0.16

0.15

0.14

0.13

0.12

Change in ILE Match (LSB)

–40 25 85 150

8

ADS7862

®

REFERENCE

Under normal operation, the REF

OUT

pin (pin 2) should be
directly connected to the REFIN pin (pin 1) to provide an
internal +2.5V reference to the ADS7862. The ADS7862
can operate, however, with an external reference in the range
of 1.2V to 2.6V for a corresponding full-scale range of 2.4V
to 5.2V.

The internal reference of the ADS7862 is double-buffered.
If the internal reference is used to drive an external load, a
buffer is provided between the reference and the load ap­plied to pin 2 (the internal reference can typically source
2mA of current—load capacitance should not exceed 100pF).
If an external reference is used, the second buffer provides
isolation between the external reference and the CDAC.
This buffer is also used to recharge all of the capacitors of
both CDACs during conversion.

ANALOG INPUT

The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS7862: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is the
(common-mode +V

REF

) and the (common-mode –V

REF

).

The value of V

REF

determines the range over which the

common-mode voltage may vary (see Figure 3).
When the input is differential, the amplitude of the input is the

difference between the +IN and –IN input, or: (+IN) – (–IN).
The peak-to-peak amplitude of each input is ±1/2V

REF

around

this common voltage. However, since the inputs are 180° out
of phase, the peak-to-peak amplitude of the differential voltage
is +V

REF

to –V

REF

. The value of V

REF

also determines the
range of the voltage that may be common to both inputs (see
Figure 4).

INTRODUCTION

The ADS7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual 2µs successive
approximation A/Ds, two differential sample-and-hold am­plifiers, an internal +2.5V reference with REFIN and REF

OUT

pins and a high speed parallel interface. There are four
analog inputs that are grouped into two channels (A and B)
selected by the A0 input (A0 LOW selects Channels A0 and
B0, while A0 HIGH selects Channels A1 and B1). Each
A/D converter has two inputs (A0 and A1 and B0 and B1)
that can be sampled and converted simultaneously, thus
preserving the relative phase information of the signals on
both analog inputs. The part accepts an analog input voltage
in the range of –V

REF

to +V

REF

, centered around the internal
+2.5V reference. The part will also accept bipolar input
ranges when a level shift circuit is used at the front end (see
Figure 7).

A conversion is initiated on the ADS7862 by bringing the
CONVST pin LOW for a minimum of 15ns. CONVST
LOW places both sample-and-hold amplifiers in the hold
state simultaneously and the conversion process is started on
both channels. The BUSY output will then go HIGH and
remain HIGH for the duration of the conversion cycle.
Depending on the status of the A0 pin, the data will either
reflect a conversion of Channel 0 (A0 LOW) or Channel 1
(A0 HIGH). The data can be read from the parallel output
bus following the conversion by bringing both RD and CS
LOW.

Conversion time for the ADS7862 is 1.75µs when an 8MHz
external clock is used. The corresponding acquisition time is

0.25µs. To achieve maximum output rate (500kHz), the read
function can be performed immediately at the start of the
next conversion.

NOTE: This mode of operation is described in more detail
in the Timing and Control section of this data sheet.

SAMPLE-AND-HOLD SECTION

The sample-and-hold amplifiers on the ADS7862 allow the
A/Ds to accurately convert an input sine wave of full-scale
amplitude to 12-bit accuracy. The input bandwidth of the
sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the A/D even when
the A/D is operated at its maximum throughput rate of
500kHz. The typical small-signal bandwidth of the sample­and-hold amplifiers is 40MHz.

Typical aperture delay time or the time it takes for the
ADS7862 to switch from the sample to the hold mode
following the CONVST pulse is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS7862 to capture AC input signals accurately at the
exact same moment in time.

ADS7862

ADS7862

Single-Ended Input

Common

Voltage

–V

REF

to +V

REF

peak-to-peak

Differential Input

Common

Voltage

V

REF

peak-to-peak

V

REF

peak-to-peak

FIGURE 1. Methods of Driving the ADS7862 Single-Ended

or Differential.

9

ADS7862

®

FIGURE 3. Single-Ended Input: Common-Mode Voltage

Range vs V

REF

.

1.0 1.5

1.2

2.0 2.5

2.6

3.0

V

REF

(V)

Common Voltage Range (V)

–1

0

1

2

3

4

5

2.7

2.3

4.1

0.9

V

CC

= 5V

Single-Ended Input

Differential Input

1.0 1.5

1.2

2.0 2.5

2.6

3.0

V

REF

(V)

Common Voltage Range (V)

–1

0

1

2

3

4

5

4.7

0.3

V

CC

= 5V

4.05

0.90

FIGURE 2. Using the ADS7862 in the Single-Ended and Differential Input Modes.

FIGURE 4. Differential Input: Common-Mode Voltage

Range vs V

REF

.

In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, which
will change with both temperature and input voltage.

The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS7862 charges the inter­nal capacitor array during the sampling period. After this

capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (15pF) to a 12-bit settling
level within 2 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.

Care must be taken regarding the absolute analog input
voltage. The +IN input should always remain within the
range of GND – 300mV to VDD + 0.3V.

CM +V

REF

+V

REF

–V

REF

Single-Ended Inputs

t

+IN

CM

Voltage

CM

–VREF

CM +1/2V

REF

Differential Inputs

NOTES: Common-Mode Voltage (Differential Mode) = Common-Mode Voltage (Single-Ended Mode) = IN–.

(IN+) + (IN–)

2

The maximum differential voltage between +IN and –IN of the ADS7862 is V

REF

. See Figures 3 and 4 for a further

explanation of the common voltage range for single-ended and differential inputs.

t

+IN

–IN

CM

Voltage

CM

–1/2V

REF

–IN = CM Voltage

+V

REF

–V

REF

10

ADS7862

®

Three timing diagrams are used to explain the operation of
the ADS7862. Figure 8 shows the timing relationship be­tween the CLOCK, CONVST (pin 18) and the conversion

Code (decimal)

8000
7000
6000
5000
4000
3000
2000
1000

0

Number of Conversions

2044 2045 2046 2047 2048

FIGURE 5. Histogram of 8,000 Conversions of a DC Input.

FIGURE 6. Test Circuits for Timing Specifications.

FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.

FIGURE 8. Conversion Mode.

TRANSITION NOISE

Figure 5 shows a histogram plot for the ADS7862 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7862.

BIPOLAR INPUTS

The differential inputs of the ADS7862 were designed to
accept bipolar inputs (–V

REF

and +V

REF

) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis­tors, the ADS7862 can be configured to except bipolar
inputs. The conventional ±2.5V, ±5V, and ±10V input
ranges can be interfaced to the ADS7862 using the resistor
values shown in Figure 7.

TIMING AND CONTROL

The ADS7862 uses an external clock (CLOCK, pin 19)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2µs maximum throughput time.

DATA

1.4V

Test Point

3kΩ

100pF
C

LOAD

t

R

DATA

Voltage Waveforms for DATA Rise and Fall Times t

R

, and tF.

V

OH

V

OL

t

F

R

1

R

2

+IN
–IN

REF

OUT

(pin 2)

2.5V

4kΩ

20kΩ

Bipolar Input

BIPOLAR INPUT R

1

R

2

±10V 1kΩ 5kΩ

±5V 2kΩ 10kΩ

±2.5V 4kΩ 20kΩ

OPA132

ADS7862

CONVST

CONVERSION

MODE

SAMPLE HOLD CONVERT

CLOCK

t

CKH

t

CKP

t

3

t

CKL

NOTE: The ADS7862 will switch from the sample to the hold mode the instant CONVST goes LOW regardless of
the state of the external clock. The conversion process is initiated with the first rising edge of the external clock
following CONVST going LOW.

11

ADS7862

®

FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle.

DESCRIPTION ANALOG INPUT

Full-Scale Input Span –V

REF

to +V

REF

(1)

Least Significant (–V

REF

to +V

REF

)/ 4096

(2)

Bit (LSB)
+Full Scale 4.99878V 0111 1111 1111 7FF
Midscale 2.5V 0000 0000 0000 000
Midscale – 1 LSB 2.49878V 1111 1111 1111 FFF
–Full Scale 0V 1000 0000 0000 800

NOTES: (1) –V

REF

to +V

REF

around V

REF

. With a 2.5V reference, this corre-

sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.

TABLE I. Ideal Input Voltages and Output Codes.

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT
BINARY CODE HEX CODE

mode. Figure 9, in conjunction with Table I, shows the basic
read/write functions of the ADS7862 and highlights all of
the timing specifications. Figure 10 shows a more detailed
description of initiating a conversion using CONVST. Fig­ure 11 illustrates three consecutive conversions and, with the
accompanying text, describes all of the read and write
capabilities of the ADS7862.

The Figure 11 timing diagram can be divided into three
sections: (a) initiating a conversion (n – 2), (b) starting a
second conversion (n – 1) while reading the data output from
the previous conversion (n – 2), and (c) starting a third
conversion (n) while reading both previous conversions
(n – 2 and n – 1). In this sequence, Channel 0 is converted

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

CONV

Conversion Time 1.75 µs

t

ACQ

Acquisition Time 0.25 µs

t

CKP

Clock Period 125 5000 ns

t

CKL

Clock LOW 40 ns

t

CKH

Clock HIGH 40 ns

t

1

CS to RD Setup Time 0 ns

t

2

CS to RD Hold Time 0 ns

t

3

CONVST LOW 15 ns

t

4

RD Pulse Width 30 ns

t

5

RD to Valid Data (Bus Access) 16 25 ns

t

6

RD to HI-Z Delay (Bus Relinquish) 10 20 ns

t

7

Time Between Conversion Reads 40 ns

t

8

Address Setup Time 250 ns

t

9

CONVST HIGH 20 ns

t

10

Address Hold Time 20 ns

t

11

CONVST to BUSY Propagation Delay 30 ns

t

12

CONVST LOW Prior to CLOCK Rising Edge

10 ns

t

13

CONVST LOW After CLOCK Rising Edge

5ns

t

F

Data Fall Time 13 25 ns

t

R

Data Rise Time 20 30 ns

TIMING SPECIFICATIONS

first followed by Channel 1. Channel 1 can be converted
prior to Channel 0 if the user wishes by simply starting the
conversion process with the A0 pin at logic HIGH (Channel

1) followed by logic LOW (Channel 0).

t12t

13

t

3

t

9

t

11

Conversion n

Conversion n – 1 Results Conversion n Results

BUSY

A0

CS

RD

DATA

Conversion n + 1

1CLOCK

CONVST

2 3 4 5 14 15 16 1 2 3 4 5 14 15 16

t

CONV

t

ACQ

t

8

t

4

t

10

t

1

t

5

CHA1 CHB1 CHA0 CHB0

t

6

t

2

t

7

12

ADS7862

®

NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.

CLOCK

CONVST

Cycle 1 Cycle 2

t

CKP

125ns

10ns

5ns

10ns

5ns

A B C

FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion.

FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality.

1 11

SECTION A

CLOCK

CONVST

A0

RD

CS

DATA

BUSY

TIME 0 1µ 2µ 3µ 4µ 5µ

min 250ns

SECTION B SECTION C

ChA0 ChB0

Time (seconds)

ChA1 ChA0

4 Output-Register

Data of Ch0 Still Stored

A0 Selects Between
Ch0 and Ch1 at Output

Conversion of Ch0

Low Data Level Tri-state of Output

Conversion of Ch0

High Data Level Output Active

1616

A0 = 1 Conversion of Ch1

min 250ns

CS Needed Only During Reading

Conversion of Ch1

ChB0ChB1

A0 = 0 Conversion of Ch0

A0 = 0 Conversion of Ch0

1st RD After CONVST ChA at Output

2nd RD After CONVST ChB at Output

13

ADS7862

®

SECTION A

Conversions are initiated by bringing the CONVST pin (pin

18) LOW for a minimum of 5ns (after the 5ns minimum
requirement has been met, the CONVST pin can be brought
HIGH). The ADS7862 will switch from the sample to the
hold mode on the falling edge of the CONVST command.
Following the first rising edge of the external clock after a
CONVST LOW, the ADS7862 will begin conversion (this
first rising edge of the external clock represents the start of
clock cycle one; the ADS7862 requires sixteen cycles to
complete a conversion). The input channel is also latched in
at this point in time. The A0 input (pin 22) must be selected
250ns prior to the CONVST pin going LOW so that the
correct address will be selected prior to conversion. The
BUSY output will go HIGH immediately following CONVST
going LOW. BUSY will stay HIGH through the conversion
process and return LOW when the conversion has ended.
After CONVST has remained LOW for the minimum time,
the ADS7862 will switch from the hold mode to the conver­sion mode synchronous to the next rising edge of the
external clock and conversion ‘n – 2’ will begin. Both RD
(pin 21) and CS (pin 20) can be HIGH during and before a
conversion. However, they must both be LOW to enable the
output bus and read data out.

SECTION B

The CONVST pin is switched from HIGH to LOW a second
time to initiate conversion ‘n – 1’. Again, the address must be
selected 250ns prior to CONVST going LOW to ensure that
the new address is selected for conversion. Both the RD and
CS pins are brought LOW in order to enable the parallel output
bus with the ‘n – 2’ conversion results of Channel A0. While
continuing to hold CS LOW, RD is held LOW for a minimum
of 30ns which enables the output bus with the Channel A0
results of conversion ‘n – 2’. The RD pin is toggled from
HIGH to LOW a second time in order to enable the output bus
with the Channel B0 results of conversion ‘n – 2’.

SECTION C

CONVST is brought LOW for a third time to initiate
conversion ‘n’ (Channel 0). While the conversion is in
process, the results for both conversions ‘n – 2’ and ‘n – 1’
can be read. The address pin is brought HIGH while CS and
RD are brought LOW which enables the output bus with the
Channel A1 results of conversion ‘n – 1’. The RD pin is
toggled from HIGH to LOW for a second time in Section C
and the ‘n – 1’ conversion results for Channel B1 appear at
the output bus. The address pin (A0) is then brought LOW
and the read process repeats itself with the most recent
conversion results for Channel 0 (n – 2) appearing at the
output bus.

READING DATA

The ADS7862 outputs full parallel data in Binary Two’s
Complement data output format. The parallel output will be
active when CS (pin 20) and RD (pin 21) are both LOW. The

output data should not be read 125ns prior to the falling edge
of CONVST and 10ns after the falling edge. Any other
combination of CS and RD will tri-state the parallel output.
Valid conversion data can be read on pins 5 through 16
(MSB-LSB). Refer to Table I for ideal output codes.

LAYOUT

For optimum performance, care should be taken with the
physical layout of the ADS7862 circuitry. This is particu­larly true if the CLOCK input is approaching the maximum
throughput rate.

The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver­sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver­sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter­nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.

With this in mind, power to the ADS7862 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low-pass filter a noisy supply. On average, the ADS7862
draws very little current from an external reference as the
reference voltage is internally buffered. If the reference
voltage is external and originates from an op amp, make sure
that it can drive the bypass capacitor or capacitors without
oscillation. A bypass capacitor is not necessary when using
the internal reference (tie pin 1 directly to pin 2).

The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the ‘analog’
ground. Avoid connections which are too close to the ground­ing point of a microcontroller or digital signal processor. If
required, run a ground trace directly from the converter to
the power supply entry point. The ideal layout will include
an analog ground plane dedicated to the converter and
associated analog circuitry.

APPLICATIONS

An applications section will be added featuring the ADS7862
interfacing to popular DSP processors. The updated data
sheet will be available in the near future on the Burr-Brown
web site:

http: //www.burr-brown.com/