Page 1
ADS1258
FEATURES DESCRIPTION
APPLICATIONS
24−Bit
ADC
Digital
Filter
Internal
Monitoring
16:1
Analog
Input
MUX
1
16
AINCOM
…
ADC
IN
Extclk
In/Out
AVSS DGND
32.768kHz
AVDD DVDD
MUX
OUT
SPI
Interface
CS
DRDY
SCLK
DIN
DOUT
ControlOscillator
GPIO
START
RESET
PWDN
GPIO[7:0]V
REF
ADS1258
Analog Inputs
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
16-Channel, 24-Bit Analog-to-Digital Converter
• 24 Bits, No Missing Codes
The ADS1258 is a 16-channel (multiplexed),
low-noise, 24-bit, delta-sigma ( ∆ Σ ) analog-to-digital
• Fixed-Channel or Automatic Channel Scan
converter (ADC) that provides single-cycle settled
• Fixed-Channel Data Rate: 125kSPS
data at channel scan rates from 1.8k to 23.7k
• Auto-Scan Data Rate: 23.7kSPS/Channel
samples per second (SPS) per channel. A flexible
• Single-Conversion Settled Data input multiplexer accepts combinations of eight
differential or 16 single-ended inputs with a full-scale
• 16 Single-Ended or 8 Differential Inputs
differential range of 5V or true bipolar range of ± 2.5V
• Unipolar (+5V) or Bipolar ( ± 2.5V) Operation
when operating with a 5V reference. The fourth-order
• Low Noise: 2.8 µ V
RMS
at 1.8kSPS
delta-sigma modulator is followed by a fifth-order
sinc digital filter optimized for low-noise performance.
• 0.0003% Integral Nonlinearity
• DC Stability (typical): The differential output of the multiplexer is accessible
to allow signal conditioning prior to the input of the
0.02 µ V/ ° C Offset Drift, 0.4ppm/ ° C Gain Drift
ADC. Internal system monitor registers provide
• Open-Sensor Detection
supply voltage, temperature, reference voltage, gain,
• Conversion Control Pin
and offset data.
• Multiplexer Output for External Signal
An onboard PLL generates the system clock from a
Conditioning
32.768kHz crystal, or can be overridden by an
• On-Chip Temperature, Reference, Offset,
external clock source. A buffered system clock
Gain, and Supply Voltage Readback
output (15.7MHz) is provided to drive a
microcontroller or additional converters.
• 42mW Power Dissipation
Serial digital communication is handled via an
• Standby, Sleep, and Power-Down Modes
SPI™-compatible interface. A simple command word
• 8 General-Purpose Inputs/Outputs (GPIO)
structure controls channel configuration, data rates,
• 32.768kHz Crystal Oscillator or External Clock
digital I/O, monitor functions, etc.
Programmable sensor bias current sources can be
used to bias sensors or verify sensor integrity.
• Medical, Avionics, and Process Control
The ADS1258 operates from a unipolar +5V or
• Machine and System Monitoring
bipolar ± 2.5V analog supply and a digital supply
• Fast Scan Multi-Channel Instrumentation
compatible with interfaces ranging from 2.7V to
• Industrial Systems
5.25V. The ADS1258 is available in a QFN-48
• Test and Measurement Systems
package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Page 2
www.ti.com
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
(1)
ADS1258 UNIT
AVDD to AVSS –0.3 to +5.5 V
AVSS to DGND –2.8 to +0.3 V
DVDD to DGND –0.3 to +5.5 V
Input Current 100, Momentary mA
Input Current 10, Continuous mA
Analog Input Voltage AVSS – 0.3 to AVDD + 0.3 V
Digital Input Voltage to DGND –0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 ° C
Operating Temperature Range –40 to +105 ° C
Storage Temperature Range –60 to +150 ° C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
Submit Documentation Feedback
Page 3
www.ti.com
ELECTRICAL CHARACTERISTICS
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
All specifications at TA= –40 ° C to +105 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
=
15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, V
REF
= +4.096V, and VREFN = –2.5V, unless otherwise
noted.
ADS1258
PARAMETER CONDITIONS MIN TYP MAX UNIT
Analog Multiplexer Inputs
AIN0–AIN15,
Absolute Input Voltage AVSS – 100mV AVDD + 100mV V
AINCOM with respect to DGND
On-Channel Resistance 80 Ω
Crosstalk fIN= 1kHz –110 dB
SBCS[1:0] = 01 1.5
Sensor Bias (Current Source) µ A
SBCS[1:0] = 11 24
1.5 µ A:24 µ A Ratio Error 1 %
ADC Input
Full-Scale Input Voltage (V
IN
= ADCINP – ADCINN) ± 1.0 6V
REF
V
Absolute Input Voltage (ADCINP, ADCINN) AVSS – 100mV AVDD + 100mV V
Differential Input Impedance 65 k Ω
System Performance
Resolution No Missing Codes 24 Bits
Data Rate, Fixed-Channel Mode 1.953 125 kSPS
Data Rate, Auto-Scan Mode 1.805 23.739 kSPS
Integral Nonlinearity (INL)
(1)
Differential Input 0.0003 0.0010 % of FSR
(2)
Chopping Off 20
Offset Error Shorted Inputs µ V
Chopping On 1 10
Chopping Off 0.5
Offset Drift
(3)
Shorted Inputs µ V/ ° C
Chopping On 0.02 0.1
Gain Error 0.1 0.5 %
Gain Drift
(3)
0.4 2 ppm/ ° C
Noise (see Table 4 )
Common-Mode Rejection fCM= 60Hz 90 100 dB
AVDD, AVSS 70 85
Power-Supply Rejection fPS= 60Hz dB
DVDD 80 95
Voltage Reference Input
Reference Input Voltage (V
REF
= VREFP – VREFN) 0.5 4.096 AVDD – AVSS V
Negative Reference Input (VREFN) AVSS – 0.1V VREFP – 0.5 V
Positive Reference Input (VREFP) VREFN + 0.5 AVDD + 0.1V V
Reference Input Impedance 40 k Ω
System Parameters
External Reference Reading Error 1 3 %
Analog Supply Reading Error 1 3 %
Voltage TA= +25 ° C 168 mV
Temperature Sensor Reading
Coefficient 394 µ V/ ° C
Digital Input/Output
V
IH
0.7DVDD DVDD V
V
IL
DGND 0.3DVDD V
Logic Levels
V
OH
IOH= 2mA 0.8DVDD DVDD V
V
OL
IOL= 2mA DGND 0.2DVDD V
Input Leakage VIN= DVDD, GND 10 µ A
Frequency 0.1 16 MHz
Master Clock Input (CLKIO)
Duty Cycle 40 60 %
(1) Best straight line fit method.
(2) FSR = Full-scale range = 2.1 3V
REF
.
(3) Ensured by characterization.
3
Submit Documentation Feedback
Page 4
www.ti.com
PIN CONFIGURATION
Top V iew QFN
36
35
34
33
32
31
30
29
28
27
26
25
AIN12
AIN13
AIN14
AIN15
AINCOM
VREFP
VREFN
DGND
DVDD
CS
START
DRDY
AIN4
AIN5
AIN6
AIN7
MUXOUTP
MUXOUTN
ADCINP
ADCINN
AIN8
AIN9
AIN10
AIN11
CLKIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
SCLK
DIN
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
AIN3
AIN2
AIN1
AIN0
AVSS
AVDD
PLLCAP
XTAL1
XTAL2
PWDN
RESET
CLKSEL
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 233724
ADS1258
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= –40 ° C to +105 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
=
15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, V
REF
= +4.096V, and VREFN = –2.5V, unless otherwise
noted.
ADS1258
PARAMETER CONDITIONS MIN TYP MAX UNIT
Crystal Frequency 32.768 kHz
Clock Output Frequency 15.729 MHz
Crystal Oscillator
(see Crystal Oscillator section)
Start-Up Time (Clock Output Valid) 150 mS
Clock Output Duty Cycle 40 60 %
Power Supply
DVDD 2.7 5.25 V
AVSS –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 V
External Clock
0.25 0.6 mA
Operation
Internal Oscillator
Operation, Clock 0.04 mA
Output Disabled
DVDD Supply Current
Internal Oscillator
Operation, Clock 1.4 mA
Output Enabled
(4)
Power-Down
(5)
1 25 µA
Converting 8.2 12 mA
Standby 5.6 mA
AVDD, AVSS Supply Current
Sleep 2.1 mA
Power-Down 2 85 µA
Converting 42 62 mW
Standby 29 mW
Power Dissipation
Sleep 11 mW
Power-Down 14 µ W
(4) CLKIO load = 20pF.
(5) No clock applied to CLKIO.
4
Submit Documentation Feedback
Page 5
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
PIN ASSIGNMENTS
ANALOG/DIGITAL
PIN # NAME INPUT/OUTPUT DESCRIPTION
1 AIN3 Analog Input Analog Input 3: Single-Ended Channel 3, Differential Channel 1 (–)
2 AIN2 Analog Input Analog Input 2: Single-Ended Channel 2, Differential Channel 1 (+)
3 AIN1 Analog Input Analog Input 1: Single-Ended Channel 1, Differential Channel 0 (–)
4 AIN0 Analog Input Analog Input 0: Single-Ended Channel 0, Differential Channel 0 (+)
Negative Analog Power Supply: 0V for unipolar operation, –2.5V for bipolar operation.
5 AVSS Analog
(Internally connected to exposed thermal pad of QFN package.)
6 AVDD Analog Positive Analog Power Supply: +5V for unipolar operation, +2.5V for bipolar operation.
7 PLLCAP Analog PLL Bypass Capacitor: Connect 22nF capacitor to AVSS when using crystal oscillator.
8 XTAL1 Analog 32.768kHz Crystal Oscillator Input 1; see Crystal Oscillator section.
9 XTAL2 Analog 32.768kHz Crystal Oscillator Input 2; see Crystal Oscillator section.
10 PWDN Digital Input Power-Down Input: Hold low for minimum of two f
CLK
cycles to engage low-power mode.
11 RESET Digital Input Reset Input: Hold low for minimum of two f
CLK
cycles to reset the device.
Clock Select Input: Low = Activates Crystal Oscillator, f
CLK
output on CLKIO.
12 CLKSEL Digital Input
High = Disables Crystal Oscillator, apply f
CLK
to CLKIO.
13 CLKIO Digital I/O System Clock Input/Output (See CLKSEL pin.)
14 GPIO0 Digital I/O General-Purpose Digital Input/Output 0
15 GPIO1 Digital I/O General-Purpose Digital Input/Output 1
16 GPIO2 Digital I/O General-Purpose Digital Input/Output 2
17 GPIO3 Digital I/O General-Purpose Digital Input/Output 3
18 GPIO4 Digital I/O General-Purpose Digital Input/Output 4
19 GPIO5 Digital I/O General-Purpose Digital Input/Output 5
20 GPIO6 Digital I/O General-Purpose Digital Input/Output 6
21 GPIO7 Digital I/O General-Purpose Digital Input/Output 7
22 SCLK Digital Input SPI Interface Clock Input: Data clocked in on rising edge, clocked out on falling edge.
23 DIN Digital Input SPI Interface Data Input: Data is input to the device.
24 DOUT Digital Output SPI Interface Data Output: Data is output from the device.
25 DRDY Digital Output Data Ready Output: Active low.
26 START Digital Input Start Conversion Input: Active high.
27 CS Digital Input SPI Interface Chip Select Input: Active low.
28 DVDD Digital Digital Power Supply: 2.7V to 5.25V
29 DGND Digital Digital Ground
30 VREFN Analog Input Reference Input Negative
31 VREFP Analog Input Reference Input Positive
32 AINCOM Analog Input Analog Input Common: Common input pin to all single-ended inputs.
33 AIN15 Analog Input Analog Input 15: Single-Ended Channel 15, Differential Channel 7 (–)
34 AIN14 Analog Input Analog Input 14: Single-Ended Channel 14, Differential Channel 7 (+)
35 AIN13 Analog Input Analog Input 13: Single-Ended Channel 13, Differential Channel 6 (–)
36 AIN12 Analog Input Analog Input 12: Single-Ended Channel 12, Differential Channel 6 (+)
37 AIN11 Analog Input Analog Input 11: Single-Ended Channel 11, Differential Channel 5 (–)
38 AIN10 Analog Input Analog Input 10: Single-Ended Channel 10, Differential Channel 5 (+)
39 AIN9 Analog Input Analog Input 9: Single-Ended Channel 9, Differential Channel 4 (–)
40 AIN8 Analog Input Analog Input 8: Single-Ended Channel 8, Differential Channel 4 (+)
41 ADCINN Analog Input ADC Differential Input (–)
42 ADCINP Analog Input ADC Differential Input (+)
43 MUXOUTN Analog Output Multiplexer Differential Output (–)
44 MUXOUTP Analog Output Multiplexer Differential Output (+)
45 AIN7 Analog Input Analog Input 7: Single-Ended Channel 7, Differential Channel 3 (–)
46 AIN6 Analog Input Analog Input 6 : Single-Ended Channel 6, Differential Channel 3 (+)
47 AIN5 Analog Input Analog Input 5: Single-Ended Channel 5, Differential Channel 2 (–)
48 AIN4 Analog Input Analog Input 4: Single-Ended Channel 4, Differential Channel 2 (+)
5
Submit Documentation Feedback
Page 6
www.ti.com
PARAMETER MEASUREMENT INFORMATION
SCLK
CS
(1)
DIN
DOUT
t
SCLK
t
CSSC
t
SPW
t
DIST
t
DIHD
t
SPW
t
CSDO
Hi-ZHi-Z
t
DOPD
t
DOHD
NOTE: (1) CS can be tiedlow.
DRDY
DOUT
t
DRDY
t
DDO
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Figure 1. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
At TA= –40 ° C to +105 ° C and DVDD = 2.7V to 5.25V, unless otherwise noted.
SYMBOL DESCRIPTION MIN MAX UNITS
t
SCLK
SCLK Period 2 τ
CLK
(1)
t
SPW
SCLK High or Low Pulse Width (exceeding max resets SPI interface) 0.8 4096
(2)
τ
CLK
t
CSSC
CS Low to First SCLK: Setup Time
(3)
0.5 τ
CLK
t
DIST
Valid DIN to SCLK Rising Edge: Setup Time 10 ns
t
DIHD
Valid DIN to SCLK Rising Edge: Hold Time 5 ns
t
DOPD
SCLK Falling Edge to Valid New DOUT: Propagation Delay
(4)
20 ns
t
DOHD
SCLK Falling Edge to Old DOUT Invalid: Hold Time 0 ns
t
CSDO
CS High to DOUT Invalid (tri-state) 5 τ
CLK
(1) τ
CLK
= master clock period = 1/f
CLK
.
(2) Programmable to 256 τ
CLK
.
(3) CS can be tied low.
(4) DOUT load = 20 pF || 100k Ω to DGND.
Figure 2. DRDY Update Timing
DRDY UPDATE TIMING CHARACTERISTICS
SYMBOL DESCRIPTION TYP UNITS
t
DRDY
DRDY High Pulse Width Without Data Read 1 τ
CLK
t
DDO
Valid DOUT to DRDY Falling Edge ( CS = 0) 0.5 τ
CLK
6
Submit Documentation Feedback
Page 7
www.ti.com
TYPICAL CHARACTERISTICS
Number of Occurrences
Offset (µV)
3000
2500
2000
1500
1000
500
0
−
50
−
45
−
40
−
35
−
30
−
25
−
20
−
15
−
10
5
0
5
10
15
20
25
30
35
40
45
50
DRATE[1:0] = 11
16384 Points
Number of Occurrences
Offset (µV)
4500
4000
3500
3000
2500
2000
1500
1000
500
0
−
35
−
30
−
25
−
20
−
15
−
10
−
5
0
5
10
15
20
25
30
35
DRATE[1:0] = 10
16384 Points
Number of Occurrences
Offset (µV)
3500
3000
2500
2000
1500
1000
500
0
−
20
−
16
−
12
−
8
−
4
0
4
8
12
16
20
DRATE[1:0] = 01
16384 Points
Number of Occurrences
Offset (µV)
2500
2000
1500
1000
500
0
−
12
−
10
−
8
−
6
−
4
−
2
0
2
4
6
8
10
12
DRATE[1:0] = 00
16384 Points
RMS Noise (
µ
V)
Input Voltage (%FS)
20
15
10
5
0
−
100−75 10075
−50−
25 50250
DRATE[1:0] = 11
DRATE[1:0] = 10
DRATE[1:0] = 01
DRATE[1:0] = 00
Number of Occurrences
RMS Noise (µV)
20
15
10
5
0
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
50 units from two production lots.
DRATE[1:0] = 11
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
= 15.729MHz (internal clock), OPA227
buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
READING HISTOGRAM READING HISTOGRAM
Figure 3. Figure 4.
READING HISTOGRAM READING HISTOGRAM
Figure 5. Figure 6.
NOISE HISTOGRAM NOISE vs INPUT VOLTAGE
Figure 7. Figure 8.
7
Submit Documentation Feedback
Page 8
www.ti.com
RMS Noise (
µ
V)
V
REF
(V)
16
14
12
10
8
6
4
2
0
0.5 1.5 5.52.5 3.5 4.5
DRATE[1:0] = 11
DRATE[1:0] = 10
DRATE[1:0] = 01
DRATE[1:0] = 00
RMS Noise (
µ
V)
DVDD, AVDD−AVSS (V)
20
18
16
14
12
10
8
6
4
2.5 3.0 5.53.5 4.0 4.5 5.0
DRATE[1:0] = 11
from DVDD
from AVDD−AVSS
RMS Noise (
µ
V)
Temperature (_C)
20
18
16
14
12
10
8
6
4
−40−
20 0
20 40 60 80 100
DRATE[1:0] = 11
RMS Noise (
µ
V)
Common−Mode Input Voltage (V)
20
15
10
5
0
Offset (
µ
V)
5
0
−
5
−
10
−
15
−
3
−
2 3
−
1 0 1 2
OFFSET
CHOP = 1
OFFSET
CHOP = 0
NOISE
Number of Occurrences
Offset (µV)
200
180
160
140
120
100
80
60
40
20
0
−
10
−
8
−
6
−
4
−
2
0
2
4
6
8
10
311 units from one production lot.
CHOP = 1
Number of Occurrences
Offset Drift (µV/_C)
80
60
40
20
0
−
0.10
−
0.09
−
0.08
−
0.07
−
0.06
−
0.05
−
0.04
−
0.03
−
0.02
−
0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
50 units from two
production lots.
Based on 20_C intervals
over the range of
−
40_C to +105_C.
CHOP = 1
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
= 15.729MHz (internal clock), OPA227
buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
NOISE vs V
REF
NOISE vs SUPPLY VOLTAGE
Figure 9. Figure 10.
NOISE AND OFFSET vs
NOISE vs TEMPERATURE COMMON-MODE INPUT VOLTAGE
Figure 11. Figure 12.
OFFSET HISTOGRAM OFFSET DRIFT HISTOGRAM
Figure 13. Figure 14.
8
Submit Documentation Feedback
Page 9
www.ti.com
Normalized Offset (
µ
V)
Temperature (_C)
20
0
−
20
−
40
−
60
−40−
20 1000 20 806040
CHOP = 1
CHOP = 1, No Buffer
CHOP = 0, No Buffer
50 units from two production lots.
Normalized Offset (
µ
V)
V
REF
(V)
0.5 1.0
10
8
6
4
2
0
−
2
−
4
−
6
−
8
−
10
5.51.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Normalized Offset (
µ
V)
Time After Power−On (s)
10
8
6
4
2
0
−
2
−
4
−
6
−
8
−
10
0 10 6020 30 40 50
Free−Air
Number of Occurrences
Absolute Gain Error (ppm)
80
60
40
20
0
100
300
500
700
900
1100
1300
1500
1700
1900
320 units from one production lot.
Normalized Gain Error (ppm)
Temperature (_C)
30
20
10
0
−
10
−40−
20 1000 20 806040
Number of Occurrences
Gain Drift (ppm/_C)
80
60
40
20
0
−
1.8
−
1.6
−
1.4
−
1.2
−
1.0
−
0.8
−
0.6
−
0.4
−
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
50 units from two productionlots.
Based on 20_C intervals over the
range of−40_C to +105_C.
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
= 15.729MHz (internal clock), OPA227
buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
OFFSET vs TEMPERATURE OFFSET vs V
REF
Figure 15. Figure 16.
OFFSET POWER-ON WARMUP GAIN ERROR HISTOGRAM
Figure 17. Figure 18.
GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE
Figure 19. Figure 20.
9
Submit Documentation Feedback
Page 10
www.ti.com
Normalized Gain Error (ppm)
V
REF
(V)
20
15
10
5
0
−
5
−
10
−
15
−
20
0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5
Normalized Gain Error (ppm)
Time After Power−On (s)
10
8
6
4
2
0
−
2
−
4
−
6
−
8
−
10
0 10 6020 30 40 50
Free−Air
Linearity Error (ppm)
V
REF
(V)
10
8
6
4
2
0
0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5
Linearity Error (ppm)
VIN(V)
−5−
4
10
8
6
4
2
0
−
2
−
4
−
6
−
8
−
10
5
−3−2−
1 0 1 2 3 4
V
REF
= 5V
TA=−40_C,−10_C, +25_C, +55_C, +85_C, +105_C
INL (ppm)
Temperature (_C)
8
6
4
2
0
−40−
20 1201000 20 806040
Level (dBFS)
Frequency (Hz)
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
−
160
−
180
1 10 100k100 1k 10k
f = 1kHz,−0.5dBFs
DRATE[1:0] = 11
65536 Points
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
= 15.729MHz (internal clock), OPA227
buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
GAIN ERROR vs V
REF
GAIN ERROR POWER-ON WARMUP
Figure 21. Figure 22.
INTEGRAL NONLINEARITY vs V
REF
INTEGRAL NONLINEARITY vs INPUT LEVEL
Figure 23. Figure 24.
INTEGRAL NONLINEARITY vs TEMPERATURE OUTPUT SPECTRUM
Figure 25. Figure 26.
10
Submit Documentation Feedback
Page 11
www.ti.com
Temperature Sensor Voltage (mV)
Temperature (_C)
210
200
190
180
170
160
150
140
−40−
20 12040
0 20 60 80 100
Number of Occurrences
Temperature Reading (_C)
8
7
6
5
4
3
2
1
0
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
50 units from two production lots.
TA= +25_C
Ratio (
µ
A/
µ
A)
Temperature (_C)
18
17
16
15
14
−40−
20 120100
0 20 806040
Number of Occurrences
Ratio (µA/µA)
25
20
15
10
5
0
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
50 units from two production lots.
AVDD, AVSS Current (mA)
Temperature (_C)
10
8
6
4
2
0
DVDD Current (mA)
1.0
0.8
0.6
0.4
0.2
0
−40−
20 120
0 20 40 60 80 100
AVDD, AVSS
DVDD
RMS Noise (
µ
V)
Master Clock (MHz)
20
16
12
8
4
0
Linearity Error (ppm)
20
16
12
8
4
0
0.1 1 10010
DRATE[1:0] = 11
Noise
Linearity
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
CLK
= 16MHz (external clock) or f
CLK
= 15.729MHz (internal clock), OPA227
buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM
Figure 27. Figure 28.
SENSOR BIAS CURRENT SOURCE RATIO SENSOR BIAS CURRENT SOURCE RATIO
HISTOGRAM vs TEMPERATURE
Figure 29. Figure 30.
SUPPLY CURRENT vs TEMPERATURE NOISE AND INL vs MASTER CLOCK
Figure 31. Figure 32.
11
Submit Documentation Feedback
Page 12
www.ti.com
OVERVIEW
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AINCOM
Control
Logic
VREFPVREFN
AVSS
PLLCAP XTAL1XTAL2
DRDY
PWDN
RESET
START
SPI
Interface
CS
SCLK
DIN
DOUT
Digital Filter
Clock Control
16−Channel
MUX
AVDD
Sensor
Bias
M
UXOUTP
MUX
OUTN
ADCINP GND
AD
CINN
ADC Channel Control
Supply Monitor
GPIO
G
PIO[7:0]
DVDD
Temperature
Ext Ref Monitor
Internal Ref
ADC
CLKSELCLKIO
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
provides a low-noise digital output. The ADC channel
The ADS1258 is a flexible, 24-bit, low-noise ADC
block controls the multiplexer Auto-Scan feature.
optimized for fast multi-channel, high-resolution
Channel Auto-Scan occurs at a maximum rate of
measurement systems. The converter provides a
23.7kSPS. Slower scan rates can be used with
maximum channel scan rate of 23.7kSPS, providing
corresponding increases in resolution.
a complete 16-channel scan in less than 700 µ s.
Communication is handled over an SPI-compatible
Figure 33 shows the block diagram of the ADS1258.
serial interface with a set of simple commands
The input multiplexer selects the analog input pins
providing control of the ADS1258. Onboard registers
connected to the multiplexer output pins
store the various settings for the input multiplexer,
(MUXOUTP/MUXOUTN). External signal
sensor detect bias, data rate selection, etc. Either an
conditioning can be used between the multiplexer
external 32.768kHz crystal, connected to pins XTAL1
output pins and the ADC input pins
and XTAL2, or an external clock applied to pin
(ADCINP/ADCINN) or the multiplexer output can be
CLKIO can be used as the clock source. When using
routed internally to the ADC inputs without external
the external crystal oscillator, the system clock is
circuitry. Selectable current sources within the input
available as an output for driving other devices or
multiplexer can be used to bias sensors or detect for
controllers. General-purpose digital I/Os (GPIO)
a failed sensor. On-chip system function readings
provide input and output control of eight pins.
provide readback of temperature, supply voltage,
gain, offset, and external reference.
The ADS1258 converter is comprised of a
fourth-order, delta-sigma modulator followed by a
programmable digital filter. The modulator
measures the differential input signal,
V
IN
= (ADCINP – ADCINN), against the differential
reference input, V
REF
= (VREFP – VREFN). The
digital filter receives the modulator signal and
Figure 33. ADS1258 Block Diagram
12
Submit Documentation Feedback
Page 13
www.ti.com
MULTIPLEXER INPUTS
AVSS* 100mV tǒVREFP or VREFNǓt AVDD) 100mV
(1)
VOLTAGE REFERENCE INPUTS
ESD
Diodes
ESD
Diodes
3pF
R
eff
= 40k
Ω
(f
CLK
= 16MHz)
AVDD
AVSS
VREFP
VREFN
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
ESD diodes protect the reference inputs. To keep
A simplified diagram of the input multiplexer is these diodes from turning on, make sure the
illustrated in Figure 35 . The multiplexer connects one voltages on the reference pins do not go below
of 16 single-ended external inputs, one of eight AVSS by more than 100mV, and likewise do not
differential external inputs, or one of the on-chip exceed AVDD by 100mV, as described in
internal variables to the ADC inputs. The output of Equation 1 :
the channel multiplexer can be routed to external
pins and then to the input of the ADC. This flexibility
A high-quality reference voltage is essential for
allows for use of external signal conditioning. See
achieving the best performance from the ADS1258.
the External Multiplexer Loop section.
Noise and drift on the reference degrade overall
ESD diodes protect the analog inputs. To keep these
system performance. It is especially critical that
diodes from turning on, make sure the voltages on
special care be given to the circuitry that generates
the input pins do not go below AVSS by more than
the reference voltages and the layout when operating
100mV, and likewise do not exceed AVDD by more
in the low-noise settings (that is, with low data rates)
than 100mV:
to prevent the voltage reference from limiting
performance. See the Reference Inputs description
AVSS – 100mV < (Analog Inputs) < AVDD + 100mV.
in the Hardware Considerations segment of the
Overdriving the multiplexer inputs may affect the
Applications section.
conversions of other channels. See the Input
Overload Protection description in the Hardware
Considerations segment of the Applications section.
The converter supports two modes of channel
access through the multiplexer: the Auto-Scan mode
and the Fixed-Channel mode. These modes are
selected by the MUXMOD bit of register CONFIG0.
The Auto-Scan mode scans through the selected
channels automatically, with break-before-make
switching. The Fixed-Channel mode requires the
user to set the channel address for each channel
measured.
(VREFP, VREFN)
The voltage reference for the ADS1258 ADC is the
differential voltage between VREFP and VREFN:
V
REF
= VREFP – VREFN. The reference inputs use a
structure similar to that of the analog inputs with the
circuitry on the reference inputs shown in Figure 34 .
Figure 34. Simplified Reference Input Circuit
The load presented by the switched capacitor can be
modeled with an effective resistance (R
eff
) of 40k Ω
for f
CLK
= 16MHz. Note that the effective impedance
of the reference inputs will load an external reference
with a non-zero source impedance.
13
Submit Documentation Feedback
Page 14
www.ti.com
ADC
AIN0
VREFN
VREFP
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AINCOM
Multiplexer
Reference/Gain Monitor
NOTE: ESD diodes not shown.
Supply Monitor
AVDD
AVSS
AVDD
AVSS
Temperature Sensor Monitor
1x 2x
8x 1x
AVDD
(AVDD−AVSS)/2
AVSS
Sensor Bias Offset Monitor
MUXOUTP
MUXOUTN
ADCINP
ADCINN
Internal
Reference
AVSS
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Figure 35. Input Multiplexer
14
Submit Documentation Feedback
Page 15
www.ti.com
ADC INPUTS
t
SAMPLE
ON
OFF
S
1
S
2
OFF
ON
S
1
S
1
AVSS + 1.3V
R
AIN
= R
effB
|| 2R
effA
AVSS + 1.3V
R
effA
= 190k
Ω
R
effB
= 78kΩ(f
CLK
= 16MHz)
R
effA
= 190k
Ω
ADCINN
ADCINP
CA1= 0.65pF
CB= 1.6pF
CA2= 0.65pF
ADCINN
S
2
AVSS + 1.3V
S
2
AVSS + 1.3V
ADCINP
Equivalent
Circuit
R
eff
= t
SAMPLE/CX
NOTE: ESD input diodes not shown.
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
As with the multiplexer and reference inputs, ESD
diodes protect the ADC inputs. To keep these diodes
The ADS1258 ADC inputs (ADCINP, ADCINN)
from turning on, make sure the voltages on the input
measure the input signal using internal capacitors
pins do not go below AVSS by more than 100mV,
that are continuously charged and discharged. The
and likewise do not exceed AVDD by more than
left side of Figure 37 shows a simplified schematic of
100mV.
the ADC input circuitry; the right side of Figure 37
shows the input circuitry with the capacitors and
switches replaced by an equivalent circuit. Figure 36
shows the ON/OFF timings of the switches shown in
Figure 37 . S
1
switches close during the input
sampling phase. With S
1
closed, C
A1
charges to
ADCINP, C
A2
charges to ADCINN, and C
B
charges
to (ADCINP – ADCINN). For the discharge phase, S
1
opens first and then S
2
closes. C
A1
and C
A2
discharge to approximately AVSS + 1.3V and C
B
discharges to 0V. This two-phase sample/discharge
cycle repeats with a period of t
SAMPLE
= 2/f
CLK
.
Figure 36. S1and S2Switch Timing for Figure 37
The charging of the input capacitors draws a
transient current from the source driving the
ADS1258 ADC inputs. The average value of this
current can be used to calculate an effective
impedance (R
eff
) where R
eff
= VIN/I
AVERAGE
. These
impedances scale inversely with f
CLK
. For example, if
f
CLK
is reduced by a factor of two, the impedances
will double.
Figure 37. Simplified ADC Input Structure
15
Submit Documentation Feedback
Page 16
www.ti.com
MASTER CLOCK (f
CLK
)
50
Ω
32.768kHz
(1)
4.7pF 4.7pF
22nF
CLKSEL XTAL1 XTAL2 PLLCAP
AVSS
CLKIO
ClockOutput
(15.729MHz)
0Vto−2.5V
NOTE:(1)Parallelresonanttype,CL=12.5pF,ESR= 35kΩ(max).
Placethe crystalandloadcapacitorsas closeaspossibleto thedevicepins.
32.768kHz
Crystal Oscillator
and PLL
MUX
CLKENB
Bit
Internal Master Clock(f
CLK
)
CLKSEL
CLKIO
XTAL1 XTAL2 PLL
External Clock Input
Crystal Oscillator
50
Ω
CLKSEL XTAL1 XTAL2 PLLCAP
DVDD
CLKIO
Clock Input
(16MHz)
2.7V
to 5V
No Connection
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
The ADS1258 oversamples the analog input at a
high rate. This requires a high-frequency master
clock to be supplied to the converter. As shown in
Figure 38 , the clock comes from either a crystal
oscillator or an external clock source.
Figure 39. Crystal Oscillator Connection
Table 1. System Clock Source
CLKSEL CLKENB
PIN CLOCK SOURCE BIT CLKIO FUNCTION
32.768kHz Disabled
0 0
Crystal Oscillator (internally grounded)
32.768kHz
0 1 Output (15.729MHz)
Crystal Oscillator
Figure 38. Clock Generation Block Diagram
1 External Clock Input X Input (16MHz)
The CLKSEL pin determines the source of the
Table 2. Approved Crystal Vendors
system clock, as shown in Table 1 . The CLKIO pin
VENDOR CRYSTAL PRODUCT
functions as an input or as an output. When the
CLKSEL pin is set to '1', CLKIO is configured as an
Epson C-001R
input to receive the master clock. When the CLKSEL
pin is set to '0', the crystal oscillator generates the
clock. The CLKIO pin can then be configured to
output the master clock. When the clock output is not
When using an external clock to operate the device,
needed, it can be disabled to reduce device power
apply the master clock to the CLKIO pin. For this
consumption.
mode, the CLKSEL pin is tied high. CLKIO then
becomes an input, as shown in Figure 40 .
Make sure to use a clock source clean from jitter or
An on-chip oscillator and Phase-Locked Loop (PLL)
interference. Ringing or under/overshoot should be
can be used to generate the system clock. For this
avoided. A 50 Ω resistor in series with the CLKIO pin
mode, tie the CLKSEL pin low. A 22nF PLL filter
(placed close to the source) can often help.
capacitor, connected from the PLLCAP pin to the
AVSS pin, is required. The internal clock of the PLL
can be output to the CLKIO to drive other converters
or controllers. If not used, disable the clock output to
reduce device power consumption; see Table 1 for
settings. The clock output is enabled by a register bit
setting (default is ON). Figure 39 shows the oscillator
connections. Place these components as close to the
pins as possible to avoid interference and coupling.
Do not connect XTAL1 or XTAL2 to any other logic.
The oscillator start-up time may vary, depending on
the crystal and ambient temperature. The user
Figure 40. External Clock Connection
should verify the oscillator start-up time.
16
Submit Documentation Feedback
Page 17
www.ti.com
ADC
Modulator
f
CLK
128(4
11b*DR
) 4.265625) TD) 2
CHOP
(2)
f
CLK
128(4
11b*DR
) CHOP(4.265625) TD)) 2
CHOP
(3)
Digital Filter
Analog
Modulator
sinc
5
Filter
Programmable
Averager
Data Rate = f
CLK
/128Modulator Rate = f
CLK
/2
Num_Ave
Data Rate
(1)
= f
CLK
/(128×Num_Ave)
NOTE: (1) Datarate for Fixed−Channel Mode, Chop = 0, Delay= 0.
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
higher data rate. The filter is comprised of two
sections, a fixed filter followed by a programmable
The ADC block of the ADS1258 is composed of two
filter. Figure 41 shows the block diagram of the filter.
blocks: a modulator and a digital filter.
Data is supplied to the filter from the analog
modulator at a rate of f
CLK
/2. The fixed filter is a
fifth-order sinc filter with a decimation value of 64
that outputs data at a rate of f
CLK
/128. The second
The modulator converts the analog input voltage into
stage of the filter is a programmable averager
a Pulse Code Modulated (PCM) data stream. When
(first-order sinc filter) with the number of averages
the level of differential analog input (ADCINP –
set by the DRATE[1:0] bits.
ADCINN) is near the level of the reference voltage,
the '1' density of the PCM data stream is at its
The data rate depends upon the system clock
highest. When the level of the differential analog
frequency (f
CLK
) and the converter configuration. The
input is near zero, the PCM '0' and '1' densities are
data rate can be computed by Equation 2 or
nearly equal. The fourth-order modulator shifts the
Equation 3 :
quantization noise to a high frequency (out of the
passband) where the digital filter can easily remove Data Rate (Auto-Scan):
it.
The modulator continuously chops the input,
resulting in excellent offset and offset drift
Data Rate (Fixed-Channel Mode):
performance. It is important to note that offset or
offset drift originating from the external circuitry is not
removed by the modulator chopping. These errors
can be effectively removed by using the external
Where:
chopping feature of the ADS1258 (see the External
DR = DRATE[1:0] register bits (binary).
Chopping section).
CHOP = Chop register bit.
TD = time delay value given in Table 5 from the
DLY[2:0] register bits (128/f
CLK
periods).
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution
digital output. By adjusting the amount of filtering,
tradeoffs can be made between resolution and data
rate: filter more for higher resolution, filter less for
Figure 41. Block Diagram of Digital Filter
17
Submit Documentation Feedback
Page 18
www.ti.com
FREQUENCY RESPONSE
Ť
Hǒf
Ǔ
Ť
+
Ť
H
sinc
5
ǒfǓ
Ť
Ť
H
Averager
ǒfǓ
Ť
+
sin
ǒ
128p f
f
CLK
Ǔ
64 sin
ǒ
2p f
f
CLK
Ǔ
ȧ
ȧ
ȧ
ȧ
5
ȧ
ȧ
ȧ
ȧ
sin
ǒ
128p Num_Ave f
f
CLK
Ǔ
Num_Ave sin
ǒ
128p f
f
CLK
Ǔ
ȧ
ȧ
ȧ
ȧ
(4)
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
Frequency (kHz)
Gain (dB)
125 2500 375 500 625
Data Rate
Auto−Scan Mode
(23.739kSPS)
Data Rate
Fixed−Channel Mode
(125kSPS)
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
Frequency (kHz)
Gain (dB)
125 2500 375 500 625
Data Rate
Auto−Scan Mode
(15.123kSPS)
Data Rate
Fixed−Channel Mode
(31.25kSPS)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Table 3 shows a listing of the averaging and data Figure 43 shows the response with averaging set to
rates for each of the four DRATE[1:0] register 4 (DRATE[1:0] = 10). 4-reading, post-averaging
settings for the Auto-Scan and Fixed-Channel produces three equally-spaced notches between
modes, with CHOP, DLY = 0. Note that the data rate each main notch of the sinc
5
filter. The frequency
scales directly with f
CLK
. For example, reducing f
CLK
response of DRATE[1:0] = 01 and 00 follows a
by 2x reduces the maximum data rate by 2x. similar pattern, but with 15 and 63 equally-spaced
notches between the main sinc
5
notches,
respectively.
The low-pass digital filter sets the overall frequency
response for the ADS1258. The filter response is the
product of the responses of the fixed and
programmable filter sections and is given by
Equation 4 :
The digital filter attenuates noise on the modulator
output including noise from within the ADS1258 and
external noise present within the ADS1258 input
signal. Adjusting the filtering by changing the number
Figure 42. Frequency Response, DRATE[1:0] = 11
of averages used in the programmable filter changes
the filter bandwidth. With a higher number of
averages, the bandwidth is reduced and more noise
is attenuated.
The low-pass filter has notches (or zeros) at the data
output rate and multiples thereof. The sinc
5
part of
the filter produces wide notches at f
CLK
/128 and
multiples thereof. At these frequencies, the filter has
zero gain. Figure 42 shows the response with no
post averaging. Note that in Auto-Scan mode, the
data rate is reduced while retaining the same
frequency response as in Fixed-Channel mode.
With programmable averaging, the wide notches
produced by the sinc
5
filter remain, but a number of
narrow notches are superimposed in the response.
The number of the superimposed notches is
determined by the number of readings
averaged (minus one).
Figure 43. Frequency Response, DRATE[1:0] = 10
Table 3. Data Rates
(1)
DATA RATE AUTO-SCAN DATA RATE FIXED-CHANNEL –3dB BANDWIDTH
DRATE[1:0] Num_Ave
(2)
MODE (SPS)
(3)
MODE (SPS) (Hz)
11 1 23739 125000 25390
10 4 15123 31250 12402
01 16 6168 7813 3418
00 64 1831 1953 869
(1) f
CLK
= 16MHz, Chop = 0, and Delay = 0.
(2) Num_Ave is the number of averages performed by the digital filter second stage.
(3) In Auto-Scan mode, the data rate listed is for a single channel; the effective data rate for multiple channels (on a per-channel basis) is
the value shown in Figure 42 and Figure 43 divided by the number of active channels in a scan loop.
18
Submit Documentation Feedback
Page 19
www.ti.com
ALIASING
DRDY 1 2
Step Input
Data Not Settled Settled Data
DRDY 1 2 6
Step Input
Data Not Settled Settled Data
NOISE PERFORMANCE
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
Frequency (MHz)
Gain (dB)
4 80 12 16
DRATE[1:0] = 11
125kSPS
Fixed−Channel Mode
SETTLING TIME
ENOB +
lnǒFSRńRMS Noise
Ǔ
ln(2)
(5)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
input. For most modes of operation, the analog input
must be stable for one complete conversion cycle to
The digital filter low-pass characteristic repeats at
provide settled data. In Fixed-Channel mode
multiples of the modulator rate of f
CLK
/2. Figure 44
(DRATE[1:0] = 11), the input must be stable for five
shows the response plotted out to 16MHz at the data
complete conversion cycles.
rate of 125kSPS (Fixed-Channel mode). Notice how
the responses near DC, 8MHz, and 16MHz are the
same. The digital filter will attenuate high-frequency
noise on the ADS1258 inputs up to the frequency
where the response repeats. However, noise or
frequency components present on the analog input
where the response repeats will alias into the
passband. For most applications, an anti-alias filter is
recommended to remove the noise. A simple
first-order input filter with a pole at 200kHz provides
Figure 45. Asynchronous Step-Input Settling
–34dB rejection at the first image frequency.
Time (DRATE[1:0] = 10, 01, 00)
Referring to Figure 42 and Figure 43 , frequencies
present on the analog input above the Nyquist rate
(sample rate/2) are first attenuated by the digital filter
and then will alias into the passband.
Figure 46. Asynchronous Step-Input Settling
Time (Fixed-Channel Mode, DRATE[1:0] = 11)
The ADS1258 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased by reducing the data rate,
noise drops correspondingly. See Table 4 for
Input-Referred Noise, Noise-Free Resolution, and
Figure 44. Frequency Response Out to 16MHz
Effective Number of Bits (ENOB). The noise
performance of low-level signals can be improved
substantially by using external gain. Note that when
Chop = 1, the data rate is reduced by 2x and the
noise is reduced by 1.4x.
The design of the ADS1258 provides fully-settled
data when scanning through the input channels in
ENOB is defined in Equation 5 :
Auto-Scan mode. The DRDY flag asserts low when
the data for each channel is ready. It may be
necessary to use the automatic switch time delay
feature to provide time for settling of the external
where FSR is the full-scale range.
buffer and associated components after channel
switching. When the converter is started (START pin
The data for the Noise-Free Resolution (bits) is
transitions high or Start Command) with stable
calculated in the same way as ENOB, except
inputs, the first converter output is fully settled. When
peak-to-peak noise is used.
applying asynchronous step inputs, the settling time
As seen in the illustration of Noise vs V
REF
is somewhat different. The step-input settling time
(Figure 9 ), the converter noise is relatively constant
diagrams (Figure 45 and Figure 46 ) show the
versus the reference voltage. Optimum
converter step response with an asynchronous step
signal-to-noise ratio of the converter is achieved by
using higher reference voltages (V
REF MAX
= AVDD –
AVSS).
19
Submit Documentation Feedback
Page 20
www.ti.com
EXTERNAL MULTIPLEXER LOOP
SWITCH TIME DELAY
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Table 4. Noise Performance
(1)
DATA RATE EFFECTIVE
DATA RATE FIXED-CHANNEL INPUT-REFERRED NOISE-FREE NUMBER
AUTO-SCAN MODE MODE NOISE RESOLUTION OF BITS
DRATE[1:0] (SPS) (SPS) (µV
RMS
) (Bits) (ENOB)
11 23739 125000 12 16.8 19.5
10 15123 31250 7.9 17.4 20.1
01 6168 7813 4.5 18.2 20.9
00 1831 1953 2.8 18.9 21.6
(1) V
REF
= 4.096V, f
CLK
= 16MHz, Chop = 0, Delay = 0, Inputs shorted, and 2048 sample size.
Table 5. Effective Data Rates with Switch-Time Delay (Auto-Scan Mode)
(1)
TIME DELAY TIME DELAY
DLY[2:0] (128/f
CLK
periods) ( µ S) DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00
000 0 0 23739 15123 6168 1831
001 1 8 19950 13491 5878 1805
010 2 16 17204 12177 5614 1779
011 4 32 13491 10191 5151 1730
100 8 64 9423 7685 4422 1639
101 16 128 5878 5151 3447 1483
110 32 256 3354 3104 2392 1247
111 48 384 2347 2222 1831 1075
(1) Time delay and data rates scale with f
CLK
. If Chop = 1, the data rates are half those shown. f
CLK
= 16MHz, Auto-Scan Mode.
Use of the switch time delay register reduces the
effective channel data rate. Table 5 shows the actual
data rates derived from Equation 2 , when using the
The external multiplexer loop consists of two
switch time delay feature.
differential multiplexer output pins and two differential
ADC input pins. The user may use external
When pulse converting, where one channel is
components (buffering/filtering, single-ended to
converted with each start pin pulse or each pulse
differential conversion, etc.), forming a signal
command, the application software may provide the
conditioning loop. For best performance, the ADC
required time delay between pulses. However, with
input should be buffered and driven differentially.
Chop = 1, the switch time delay feature may still be
necessary to allow for settling.
To bypass the external multiplexer loop, connect the
ADC input pins directly to the multiplexer output pins,
In estimating the time delay that may be required,
or select internal bypass connection (BYPASS = 0 of
Table 6 lists the time delay-to-time constant ratio (t/ τ )
CONFIG0). Note that the multiplexer output pins are
and the corresponding final settled data in % and
active regardless of the bypass setting.
number of bits.
Table 6. Settling Time
When using the ADS1258 in the Auto-Scan mode,
FINAL SETTLING FINAL SETTLING
where the converter automatically switches from one
t/ τ
(1)
(%) (Bits)
channel to the next, the settling time of the external
1 63 2
signal conditioning circuit becomes important. If the
3 95 5
channel does not fully settle after the multiplexer
5 99.3 7
channel is switched, the data may not be correct.
7 99.9 10
The ADS1258 provides a switch time delay feature
which automatically provides a delay after channel
10 99.995 14
switching to allow the channel to settle before taking
15 99.9999 20
a reading. The amount of time delay required
17 99.999994 24
depends primarily on the settling time of the external
signal conditioning. Additional consideration may be
(1) Multiple time constants can be
approximated by: ( τ
1
2
+ τ
2
2
+ … )½.
needed to account for the settling of the input source
arising from the transient generated from channel
switching.
20
Submit Documentation Feedback
Page 21
www.ti.com
SENSOR BIAS
dV
dt
+
I
SDC
C
(6)
OPEN-SENSOR DETECTION
EXTERNAL DIODE BIASING
80
Ω
AVDD
R
L
R
S
ADCINP
80
Ω
AVSS
ADCINN
MUXOUTP
MUXOUTN
I
SDC
I
SDC
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
The time to charge the external capacitance is given
in Equation 6 :
An integrated current source provides a means to
bias an external sensor (for example, a diode
junction); or, it verifies the integrity of a sensor or
sensor connection. When the sensor fails to an open
It is also important to note that the low impedance
condition, the current sources drive the inputs of the
(65k Ω ) of the direct ADC inputs or the impedance of
converter to positive full-scale. The biasing is in the
the external signal conditioning loads the current
form of differential currents (programmable 1.5 µ A or
sources. This low impedance limits the ability of the
24 µ A), connected to the output of the multiplexer.
current source to pull the inputs to positive full-scale
for open-channel detection.
Figure 47 shows a simplified diagram of ADS1258
input structure with the external sensor modeled as a
resistance R
S
between two input pins. The two 80 Ω
series resistors, R
MUX
, model the ADS1258 internal
For open-sensor detection, set the biasing to either
resistances. R
L
represents the effective input
1.5 µ A or 24 µ A. Then select the channel and read the
resistance of the ADC input or external buffer. When
output code. When a sensor opens, the positive
the sensor bias is enabled, they source I
SDC
to one
input is pulled to AVDD and the negative input is
selected input pin (connected to the MUXOUTP) and
pulled to AVSS. Because of this configuration, the
sink I
SDC
from the other selected input pin connected
output code trends toward positive full-scale. Note
to the MUXOUTN channel. The signal measured with
that the interaction of the multiplexer resistance with
the biasing enabled equals the total IR drop:
the current source may lead to degradation in
I
SDC
[(2R
MUX
+ RS) ׀ ׀ RL]. Note that when the sensor
converter linearity. It is recommended to enable the
is a direct short (that is, R
S
= 0), there will still be a
current source only periodically to check for open
small signal measured by the ADS1258 when the
inputs and discard the associated data.
biasing is enabled: I
SDC
[2R
MUX
׀ ׀ RL].
The current source is connected to the output of the
multiplexer. For unselected channels, the current
The current source can be used to bias external
source is not connected. This configuration means
diodes for temperature sensing. Scan the
that when a new channel is selected, the current
appropriate channels with the current source set to
source charges stray sensor capacitance, which may
24µA. Re-scan the same channels with the current
slow the rise of the sensor voltage. The automatic
source set to 1.5µA. The difference in diode voltage
switch time delay feature can be used to apply an
readings resulting from the two bias currents is
appropriate time delay before a conversion is started
directly proportional to temperature.
to provide fully settled data (see the Switch Time
Delay section).
Note that errors in current ratio, diode and cable
resistance, or the non-ideality factor of the diode can
lead to errors in temperature readings. These effects
can be compensated by characterization or by
calibrating the diode at known temperatures.
Figure 47. Sensor Bias Structure
21
Submit Documentation Feedback
Page 22
www.ti.com
EXTERNAL CHOPPING
GPIO Pin
GPIO Data (read)
GPIO Data (write)
GPIO Control
POWER-DOWN INPUT ( PWDN)
ADC
Multiplexer
(chopping)
AINn
AINn
MUXOUTP
MUXOUTN
ADCINP
Optional
Signal
Conditioning
ADCINN
POWER-UP TIMING
GPIO DIGITAL PORT (GPIOx)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
the level of the pins. When reading the GPIOD
register, the data returned is the level of the pins,
The modulator of the ADS1258 incorporates a
whether they are programmed as inputs or outputs.
chopping front-end which removes offset errors,
As inputs, a write to the GPIOD has no effect. As
providing excellent offset and offset drift
outputs, a write to the GPIOD sets the output value.
performance. However, offset and offset drift
originating from external signal conditioning are not During Standby and Power-Down modes, the GPIO
removed by the modulator. The ADS1258 has an remains active. If configured as inputs, they must be
additional chopping feature that removes external driven (do not float). If configured as outputs, they
offset errors (CHOP = 1). continue to drive the pins. The GPIO pins are set as
inputs after power-on or after a reset. Figure 49
With external chopping enabled, the converter takes
shows the GPIO port structure.
two readings in succession on the same channel.
The first reading is taken with one polarity and the
second reading is taken with the opposite polarity.
The converter averages the two readings, canceling
the offset, as shown in Figure 48 . With chopping
enabled, the effective reading is reduced to half of
the nominal reading rate.
Note that since the inputs are reversed under control
of the ADS1258, a delay time may be necessary to
provide time for external signal conditioning to fully
settle before the second phase of the reading
sequence starts (see the Switch Time Delay section).
Figure 49. GPIO Port Pin
The PWDN pin is used to control the power-down
mode of the converter. In power-down mode, all
internal circuitry is deactivated including the oscillator
and the clock output. Hold PWDN low for at least two
f
CLK
cycles to engage power-down. The register
settings are retained during power-down. When the
Figure 48. External Chopping
pin is returned high, the converter requires a
wake-up time before readings can be taken, as
shown in the Power-Up Timing section. Note that in
External chopping can be used to significantly
power-down mode, the inputs of the ADS1258 must
reduce total offset errors (to less than 10 µ V) and
still be driven and the device continues to drive the
offset drift over temperature (to less than 0.2 µ V/ ° C).
outputs.
Note that chopping must be disabled (CHOP = 0) to
take the internal monitor readings.
When powering up the device or taking the PWDN
pin high to wake the device, a wake-up time is
The ADS1258 has eight dedicated pins for
required before readings can be taken. When using
General-Purpose Digital I/O (GPIO). The digital I/O
the internal oscillator, the wake-up time is composed
pins are individually configurable as either inputs or
of the oscillator start-up time and the PLL lock time,
as outputs through the GPIOC (GPIO-Configure)
and if the supplies are also being powered, there is a
register. The GPIOD (GPIO-Data) register controls
reset interval time of 2
18
f
CLK
cycles. Note that CLKIO
is not valid during the wake-up period, as shown in
Figure 50 .
22
Submit Documentation Feedback
Page 23
www.ti.com
POWER-UP SEQUENCE
Reset Input ( RESET)
CLKIO
Device Ready
t
WAKE
3.2V, typical
CLKSEL
or
AVDD−AVSS
(1)
or
PWDN
NOTE: (1) Shownwith DVDD stable.
Clock Select Input (CLKSEL)
Clock Input/Output (CLKIO)
Start Input (START)
CLKIO
DeviceReady
t
WAKE
3.2V,typical
or
AVDD−AVSS
(1)
PWDN,
CLKSEL
NOTE:(1)ShownwithDVDDstable.
Data Ready Output ( DRDY)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
The analog and digital supplies should be applied
before any analog or digital input is driven. The
power supplies may be sequenced in any order. The
internal master reset signal is generated from the
analog power supply (AVDD – AVSS), when the
level reaches approximately 3.2V. The power-up
master reset signal is functionally the same as the
Reset Command and the RESET input pin.
When RESET is held low for at least two f
CLK
cycles,
all registers are reset to their default values and the
digital filter is cleared. When RESET is released
high, the device is ready to convert data.
Figure 50. Device Wake Time with
Internal Oscillator
This pin selects the source of the system clock: the
crystal oscillator or an external clock. Tie CLKSEL
When using the device with an external clock, the
low to select the crystal oscillator. When using an
wake-up time is 2/f
CLK
periods when waking up with
external clock (applied to the CLKIO pin), tie
the PWDN pin and 218/f
CLK
periods when powering
CLKSEL high.
the supplies, all after a valid CLKIO is applied, as
shown in Figure 51 .
This pin serves either as a clock output or clock
input, depending on the state of the CLKSEL pin.
When using an external clock, apply the clock to this
pin and set the CLKSEL pin high. When using the
internal oscillator, this pin has the option of providing
a clock output. The CLKENB bit of register CONFIG0
enables the clock output (default is enabled).
The START pin is an input that controls the ADC
process. When the START pin is taken high, the
converter starts converting the selected input
channels. When the START pin is taken low, the
conversion in progress runs to completion and the
converter is stopped. The device then enters one of
Figure 51. Device Wake Time with External Clock
the two idle modes (see the Idle Modes section).
(See Conversion Control for details of using the
Table 7 summarizes the wake-up times using the
START pin.)
internal oscillator and the external clock operations.
Table 7. Wake-Up Times
The DRDY pin is an output that asserts low to
t
WAKE
t
WAKE
indicate when new channel data is available to read
INTERNAL EXTERNAL
(the previous conversion data is lost). DRDY returns
CONDITION OSCILLATOR
(1)
CLOCK
high after the first falling edge of SCLK during a data
PWDN or CLKSEL t
OSC
2/f
CLK
read operation. If the data is not read (no SCLK
AVDD – AVSS t
OSC
+ 218/f
CLK
218/f
CLK
pulses), DRDY remains low until new channel data is
available once again. DRDY then pulses high, then
(1) Wake-up times for the internal oscillator
low to indicate new data is available; see Figure 52 .
operation are typical and may vary
depending on crystal characteristics and
layout capacitance. The user should
verify the oscillator start-up times (t
OSC
=
oscillator start-up time).
23
Submit Documentation Feedback
Page 24
www.ti.com
INTERNAL SYSTEM READINGS
Analog Power-Supply Reading (VCC)
Total Analog Supply Voltage(V
)
+
Code
786432
(7)
DRDY
DRDY
SCLK
SCLK
DRDY with SCLK
DRDY without SCLK
t
DRDYPLS
t
DRDYPLS
=
1
f
CLK
Output Data Scaling and Over-Range
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
DRDY is usually connected to an interrupt of a and the output clips when:
controller, DSP, or connected to a controller port pin
|V
IN
| ≥ 1.0 6 × V
REF
.
for polling in a software loop. Channel data can be
read without the use of DRDY. Read the data using
Table 8 summarizes the ideal output codes versus
the register format read and check the Status Byte
input signals.
when the NEW bit = 1, which indicates new channel
data.
The analog power-supply voltage of the ADS1258
can be monitored by reading the VCC register. The
supply voltage is routed internal to the ADS1258 and
is measured and scaled using an internal reference.
The supply readback channel outputs the difference
between AVDD and AVSS (AVDD – AVSS), for both
single and dual configurations. Note that it is
required to disable chopping (CHOP = 0) prior to
taking this reading.
The scale factor of Equation 7 converts the code
value to volts:
When the power supply falls below the minimum
specified operating voltage, the full operation of the
ADS1258 cannot be ensured. Note that when the
Figure 52. DRDY Timing
total analog supply voltage falls to below
(See Figure 2 for the DRDY Pulse)
approximately 4.3V the returned data is set to zero.
The SUPPLY bit in the status byte is then set. The
bit is cleared when the total supply voltage rises
approximately 50mV.
The ADS1258 is scaled such that the output data
The digital supply (DVDD) may be monitored by
code resulting from an input voltage equal to ± V
REF
looping-back the supply voltage to an input channel.
has a margin of 6. 6% before clipping. This
A resistor divider may be required for bipolar supply
architecture allows operation of applied input signals
operation to reduce the DVDD level to within the
at or near full-scale without overloading the
range of the analog supply.
converter.
Specifically, the device is calibrated so that:
1LSB = V
REF
/780000h,
Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL V
IN
(ADCINP – ADCINN) IDEAL OUTPUT CODE
(1)
DESCRIPTION
≥ +1.0 6 V
REF
7FFFFFh Maximum Positive Full-Scale Before Output Clipping
+V
REF
780000h VIN= +V
REF
+1.0 6 V
REF
/(2
23
– 1) 000001h +1LSB
0 000000h Bipolar Zero
–1.0 6 V
REF
/(2
23
– 1) FFFFFFh –1LSB
–V
REF
87FFFFh VIN= –V
REF
≤ – 1.0 6 V
REF
× (2
23/223
– 1) 800000h Maximum Negative Full-Scale Before Output Clipping
(1) Excludes effects of noise, linearity, offset, and gain errors.
24
Submit Documentation Feedback
Page 25
www.ti.com
Gain Reading (GAIN)
Device GainǒVńV
Ǔ
+
Code
7864320
(8)
Temperature(°C) +
ƪ
Temp Reading(mV) * 168,000mV
394mVń°C
ƫ
) 25°C
Offset Reading (OFFSET)
Reference Reading (REF)
CONVERSION CONTROL
External Reference(V
)
+
Code
786432
(9)
START Pin
Temperature Reading (TEMP)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
temperature closely. Note also that self-heating of
the ADS1258 causes a higher reading than the
In this configuration, the external reference is
temperature of the surrounding PCB. Note that it is
connected both to the analog input and to the
required to disable chopping (CHOP = 0) prior to
reference input of the ADC. The data from this
taking this reading.
register indicates the gain of the device.
The scale factor of Equation 10 converts the
The following scale factor (Equation 8 ) converts the
temperature reading to ° C. Before using the
code value to device gain:
equation, the temperature reading code must first be
scaled to µ V.
To correct the device gain error, the user software
can divide each converter data value by the device
(10)
gain. Note that this corrects only for gain errors
originating within the ADC; system gain errors
because of an external gain stage error or because
The differential output of the multiplexer is shorted
of reference errors are not compensated. Note that it
together and set to a common-mode voltage of
is required to disable chopping (CHOP = 0) also prior
(AVDD – AVSS)/2. Ideally, the code from this
to taking this reading.
register function is 0h, but varies because of the
noise of the ADC and offsets stemming from the
ADC and external signal conditioning. This register
In this configuration, the external reference is
can be used to calibrate or track the offset of the
connected to the analog input and an internal
ADS1258 and external signal conditioning. The chop
reference is connected to the reference of the ADC.
feature of the ADC can automatically remove offset
The data from this register indicates the magnitude
and offset drift from the external signal conditioning;
of the external reference voltage.
see the External Chopping section.
The scale factor of Equation 9 converts the code
value to external reference voltage:
The conversions of the ADS1258 are controlled by
the START pin. Conversions begin when the START
pin is taken high and conversions are stopped when
This readback function can be used to check for
the START pin is taken low. For continuous
missing or an out-of-range reference. If the reference
conversions, tie the START pin high. The START pin
input pins are floating (not connected), internal
can also be tied low and the conversions controlled
biasing pulls them to the AVSS supply. This causes
by the PULSE convert command. The PULSE
the output code to tend toward '0'. Bypass capacitors
convert command converts one channel (only) for
connected to the external reference pins may slow
each command sent. In this way, channel
the response of the pins when open. When reading
conversions can be stepped without the need to
this register immediately after power-on, verify that
toggle the START pin.
the reference has settled to ensure an accurate
reading. Note that it is required to disable chopping
(CHOP = 0) prior to taking this reading.
As shown in Figure 53 , when the START pin is taken
high, conversions start beginning with the current
channel. The device continues to convert all of the
The ADS1258 contains an on-chip temperature
programmed channels, in a continuous loop, until the
sensor. This sensor uses two internal diodes with
START pin is taken low. When this occurs, the
one diode having a current density of 16x of the
conversion in process completes, and the device
other. The difference in current densities of the
enters the standby or sleep mode waiting for a new
diodes yields a difference voltage that is proportional
start condition. When DRDY asserts low, the
to absolute temperature.
conversion data is ready. The order in which channel
As a result of the low thermal resistance of the
data is converted is described in Table 10 . When the
package to the printed circuit board (PCB), the
last selected channel in the program list has been
internal device temperature tracks the PCB
converted, the device continues conversions starting
with the highest priority channel. If there is only one
channel selected in the Auto-Scan mode, the
25
Submit Documentation Feedback
Page 26
www.ti.com
GPIO Linked START Pin Control
Initial Delay
DRDY
STARTPin
Data Ready, Index to Next Channel
IdleIdle Mode Converting
Pulse Convert Command
Initial Delay
Fully−Settled Data
DRDY
Start
Condition
DRDY
START Pin
Pulse Convert
Command
Converting ConvertingIdle
Data Ready, Index to Next Channel
or
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
converter remains fixed on one channel. A write
operation to any of the multiplexer channel select
The START pin can be contolled directly by software
registers sets the channel pointer to the highest
by connecting externally a GPIO port pin to the
priority channel (see Table 11 ). In Fixed-Channel
START pin. (Note that an external pull-down resistor
mode, the channel pointer remains fixed.
is recommended to keep the GPIO from floating until
the GPIO is configured as an output). For this mode
of control, the START pin is effectively controlled by
writing to the GPIO Data Register (GPIOD), with the
write operation setting or resetting the appropriate
bit. The data takes effect on the eighth falling edge of
the data byte write. The START pin can then be
controlled by the serial interface.
As seen in Figure 55 , when a start convert condition
Figure 53. Conversion Control, Auto-Scan Mode
occurs, the first reading from ADS1258 is delayed for
a number of clock cycles. This delay allows fully
settled data to occur at the first data read. Data
reads thereafter are available at the full data rate.
Figure 54 also shows the start of conversions with
The number of clock cycles delayed before the first
the rising edge of the START pin. If the START pin is
reading is valid depends on the data rate setting, and
taken high, and then low prior completion of the
whether exiting the Standby or Sleep Mode. Table 9
conversion cycle ( DRDY asserts low), only the
lists the delayed clock cycles versus data rate.
current channel is converted and the device enters
the standby or sleep modes waiting for a new start
condition. The same function of conversion control is
possible using the Pulse Convert command (with the
START pin low). In this operation, the data from one
channel is converted with each Pulse Convert
command. The Pulse convert command takes effect
when the command byte is completely shifted in
(eighth falling edge of SCLK). After conversion, if
more than one channel is enabled (Auto-Scan
mode), the converter indexes to the next selected
channel after completing the conversion.
Figure 55. Start Condition to First Data
Figure 54. Pulse Conversion, Auto-Scan Mode
Table 9. Start Condition to DRDY Delay, Chop = 0, DLY[2:0] = 000
INITIAL DELAY (Standby Mode) INITIAL DELAY (Sleep Mode)
(f
CLK
cycles) (f
CLK
cycles)
DRATE[1:0] Fixed-Channel Auto-Scan Fixed-Channel Auto-Scan
11 802 708 866 772
10 1186 1092 1250 1156
01 2722 2628 2786 2692
00 8866 8772 8930 8836
26
Submit Documentation Feedback
Page 27
www.ti.com
OPERATING MODES
CONVERTING MODES
Fixed-Channel Mode
Auto-Scan Mode
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
The channels are selected for measurement in
registers MUXDIF, MUXSG0, MUXSG1, and
SYSRED. When any of these registers are written,
The operating modes of the ADS1258 are defined in
the internal channel pointer is set to the channel
three basic states: Converting Mode, Idle Mode, and
address with the highest priority (see Table 11 ).
Power-Down mode. In Converting mode, the device
DRDY asserts low when the channel data is ready;
is actively converting channel data. The device
see Figure 54 and Figure 53 . At the same time, the
power dissipation is the highest in this mode. This
converter indexes to the next selected channel and,
mode is divided into two sub-modes: Auto-Scan and
if the START pin is high, starts a new channel
Fixed-Channel.
conversion. Otherwise, if pulse converting, the
The next mode is the Idle mode. In this mode, the
device enters the Idle mode.
device is not converting channel data. The device
For example, if channels 3, 4, 7, and 8 are selected
remains active, waiting for input to start conversions.
for measurement in the list, the ADS1258 converts
The power consumption is reduced from that of the
the channels in that order, skipping all other
Converting mode. This mode also has two
channels. After channel 8 is converted, the device
sub-modes: Standby and Sleep.
starts over, beginning at the top of the channel list,
The last mode is Power-Down mode. In this mode,
channel 3.
all functions of the converter are disabled to reduce
The following guidelines can be used when selecting
power consumption to a minimum.
input channels for Auto-Scan measurement:
1. For differential measurements, adjacent input
pins (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, etc.) are
The ADS1258 has two converting modes: Auto-Scan
pre-set as differential pairs. Even number
and Fixed-Channel. In Auto-Scan mode, the
channels from each pair represent the positive
channels to be measured are pre-selected in the
input to the ADC and odd number channels within
address register settings. When a convert condition
a pair represent the negative input (for example,
is present, the converter automatically measures and
AIN0/AIN1: AIN0 is the positive channel, AIN1 is
sequences through the channels either in a
the negative channel.)
continuous loop or pulse-step fashion, depending on
2. For single-ended measurements use AIN0
the trigger condition.
through AIN15 as single-ended inputs and
In Fixed-Channel mode, the channel address is
AINCOM is the shared common input among
selected in the address register settings prior to
them. Note: AINCOM does not need to be at
acquiring channel data. When a convert condition is
ground potential. For example, AINCOM can be
present, the device converts a single channel, either
tied to VREFP or VREFN; or any potential
continuously or in pulse-step fashion, depending on
between (AVSS – 100mV) and (AVDD + 100mV).
the trigger condition. The data rate in this mode is
3. Combinations of differential, single-ended inputs,
higher than in Auto-Scan Mode since the input
and internal system registers can be used in a
channels are not indexed for each reading.
scan.
The selection of converting modes is set with bit
MUXMOD of register CONFIG0.
In this mode, any of the 16 analog input channels
(AIN0–AIN15) can be selected for the positive ADC
The ADS1258 provides 16 analog inputs, which can
input and any analog input channels can be selected
be configured in combinations of eight differential
for the negative ADC input. New channel
inputs or 16 single-ended inputs, and provides an
configurations must be selected by the MUXSCH
additional five internal system measurements. Taken
register prior to converting a different channel. Note
together, the device allows a total of 29 possible
that the AINCOM input and the internal system
channel combinations. The converter automatically
registers cannot be referenced in this mode.
scans and measures the selected channels, either in
a continuous loop or pulse-step fashion, under the
control of the START pin or Start command software.
27
Submit Documentation Feedback
Page 28
www.ti.com
IDLE MODES
Data Input (DIN) and Data Output (DOUT)
POWER-DOWN MODE
SPI Bus Sharing
SERIAL INTERFACE
COMMUNICATION PROTOCOL
Chip Select ( CS)
Reading DATA
Serial Clock (SCLK) Operation
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
or write operations in progress will terminate and the
SPI interface resets. This timeout feature can be
When the START pin is taken low, the device
used to recover lost communication when a serial
completes the conversion of the current channel and
interface transmission is interrupted or inadvertently
then enters one of the Idle modes, Standby or Sleep.
glitched.
In the Standby mode, the internal biasing of the
converter is reduced. This state provides the fastest
wake-up response when re-entering the run state. In
Operation
Sleep mode, the internal biasing is reduced further to
provide lower power consumption than the Standby The data input pin (DIN) is used to input data to the
mode. This mode has a slower wake-up response ADS1258. The data output pin (DOUT) is used to
when re-entering the Converting mode (see Table 9 ). output data from the ADS1258. Data on DIN is
Selection of these modes is set under bit IDLMOD of shifted into the converter on the rising edge of SCLK
register CONFIG1. while data is shifted out on DOUT on the falling edge
of SCLK. DOUT is tri-stated when CS is high to allow
multiple devices to share the line.
In power-down mode, both the analog and digital
circuitry are completely disabled.
The ADS1258 can be connected to a shared SPI
bus. DOUT tri-states when CS is deselected (high).
When the ADS1258 is connected to a shared bus,
The ADS1258 is operated via an SPI-compatible
data can be read only by the Channel Data Read
serial interface by writing data to the configuration
command format.
registers, using commands to control the converter
and finally reading back the channel data. The
interface consists of four signals: CS, SCLK, DIN,
Communicating to the ADS1258 involves shifting
and DOUT.
data into the device (via the DIN pin) or shifting data
out of the device (via the DOUT pin) under control of
the SCLK input.
CS is an input that is used to select the device for
serial communication. CS is active low. When CS is
high, read or write commands in progress are
DRDY goes low to indicate that new conversion data
aborted and the serial interface is reset. Additionally,
is ready. The data may be read via a direct data read
DOUT tri-states and inputs on DIN are ignored.
(Channel Data Read Direct) or the data may be read
DRDY indicates when data is ready, independent of
in a register format (Channel Data Read Register). A
CS.
direct data read requires the data to be read before
The converter may be operated using CS to actively
the next occurrence of DRDY or the data will be
select and deselect the device, or with CS tied low
corrupted. This type of data read requires
(always selected). CS must stay low for the entire
synchronization with DRDY to avoid this conflict.
read or write operation. When operating with CS tied
When reading data in the register format, the data
low, the number of SCLK pulses must be carefully
may be read at any time without concern to DRDY.
controlled to avoid false command transmission.
The NEW bit of the STATUS byte indicates that the
data register has been refreshed with new converter
data since the last read operation. The data is shifted
out MSB first after the STATUS byte.
The serial clock (SCLK) is an input which is used to
clock data into (DIN) and out of (DOUT) the
It should be noted that on system power-up, if the
ADS1258. This input is a Schmitt-trigger input that
ADS1258 interface signals are floating or undefined,
has a high degree of noise immunity. However, it is
the interface could wake in an unknown state. This
recommended to keep SCLK as clean as possible to
condition is remedied by resetting the interface in
prevent glitches from inadvertently shifting the data.
three ways: toggle the RESET pin low then high;
Data is shifted into DIN on the rising edge of SCLK
toggle the CS pin high then low; or hold SCLK
and data is shifted out of DOUT on the falling edge
inactive for 2
18
+ 4096 f
CLK
cycles.
of SCLK. If SCLK is held inactive for 4096 or 256
f
CLK
cycles (SPIRST bit of register CONFIG0), read
28
Submit Documentation Feedback
Page 29
www.ti.com
Channel Data Read Direct
COMMAND DESCRIPTION
Channel Data Read Command
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
NOTES: (1)OptionalforAuto-Scanmode,disabledforFixed-Channelmode.SeeTable13,StatusByte.
(2)Afterthechanneldatareadoperation, mustbetoggledoranSPItimeoutmustoccurbeforesendingcommands.
(3)NoSCLKactivity.
CS
(3)
DRDY
CS
SCLK
DOUT
DIN
(holdinactive)
StatusByte
(1)
DataByte1(MSB) DataByte3(MSB)
(2)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Channel data can be accessed from the ADS1258 in
Commands may be sent to the ADS1258 with CS
two ways: Direct data read or Data read with register
tied low. However, after the Channel Data Read
format. With Direct read, the DIN input pin is held
Direct operation, it is necessary to toggle CS or an
inactive (high or low) for at least the first three SCLK
SPI timeout must occur to reset the interface before
transitions. When the first three bits are 000 or 111,
sending a command.
the device detects a direct data read and channel
data is output. After the device defects this read
format, commands are ignored until either CS is
To read channel data in this mode (register format),
toggled, an SPI timeout occurs or the device is reset.
the first three bits of the command byte to be shifted
The Channel Data Read Command does not have
into the device are 001. The MUL bit must be set
this requirement.
because this command is a multiple byte read. The
Concurrent with the first SCLK transition, channel
remaining bits are don’t care but still must be clocked
data is output on the DOUT output pin. A total of 24
to the device. During this time, ignore any data that
or 32 SCLK transitions complete the data read
appear on DOUT until the command completes. This
operation. The number of shifts depend on whether
data should be ignored. Beginning with the eighth
the status byte is enabled. The data must be
SCLK falling edge (command byte completed), the
completely shifted out before the next occurrence of
MSB of the channel data is restarted on DOUT. The
DRDY or the remaining data will be corrupted. It is
user clocks the data on the following rising edge of
recommended to monitor DRDY to synchronize the
SCLK. A total of 40 SCLK transitions complete the
start of the read operation to avoid data corruption.
data read operation. Unlike the Direct read mode,
Before DRDY asserts low, the MSB of the Status
the channel data can be read during a DRDY
byte or the MSB of the data is output on DOUT ( CS
transition without data corruption. This mode is
= '0'), as shown in Figure 56 . In this format, reading
recommended when DRDY is not used and the data
the data a second time within the same DRDY frame
is polled to detect for the occurrence of new data or
returns data = 0.
when CS is tied low to avoid the necessity for an SPI
timeout that otherwise occurs when reading data
directly. This option avoids conflicts with DRDY, as
shown in Figure 57 .
Figure 56. Channel Data Read Direct (No Command)
29
Submit Documentation Feedback
Page 30
www.ti.com
CS
SCLK
DIN Command Byte 1 Don’t Care Don’t Care
(1)
DOUT
(1) After the prescribed number of registers are read, thenone or moreadditional commands canbe issued in succession.
(2) Four bytes for channel data register read. See Table 13, Status Byte. One or more bytes for register data read, depending on MULbit.
NOTE:
Don’t Care Data
(2)
Data
(2)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Register Read Command
CONTROL COMMANDS
Pulse Convert Command
Reset Command
Register Write Command
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Figure 57. Register and Channel Data (Register Format) Read
Beginning with the eighth SCLK rising edge
(command byte completed), the MSB of the data is
shifted in. The remaining seven SCLK rising edges
To read register data, the first three bits of the
complete the write to a single register. If MUL = '1',
command byte to be shifted into the device are 010.
the data from the next register can be written by
These bits are followed by the multiple register read
supplying additional SCLKs. The operation
bit (MUL). If MUL = '1', then multiple registers can be
terminates when the last register is accessed
read in sequence beyond the desired register. If
(address = 09h), as shown in Figure 58 .
MUL = '0', only data from the addressed register can
be read. The last four bits of the command word are
the beginning register address bits. During this time,
the invalid data may appear on DOUT until the
command is completed. This data should be ignored.
Beginning with the eighth falling edge of SCLK
(See Conversion Control)
(command byte completed), the MSB of the register
data is output on DOUT. The remaining eight SCLK
transitions complete the read of a single register. If
MUL = '1', the data from the next register can be
The Reset command resets the ADC. All registers
read in sequence by supplying additional SCLKs.
are reset to their default values. A conversion in
The operation terminates when the last register is
process will continue but will be invalid when
accessed (address = 09h); see Figure 57 .
completed ( DRDY low). This conversion data should
be discarded. Note that the SPI interface may
require reset for this command, or any command, to
function. To ensure device reset under a possible
To write register data, the first three bits of the
locked SPI interface condition, do one of the
command byte to be shifted into the device are 011.
following: 1) toggle CS high then low and send the
These bits are followed by the multiple register read
reset command; or 2) hold SCLK inactive for 256/f
CLK
bit (MUL). If MUL = '1', then multiple registers can be
or 4096/f
CLK
and send the reset command. The
written in sequence beyond the desired register. If
control commands are illustrated in Figure 59 .
MUL = '0', only data from the addressed register can
be written. The remaining four bits of the command
word are the beginning register address bits. During
this time, the invalid data may appear on DOUT until
the command is completed. This data should be
ignored.
30
Submit Documentation Feedback
Page 31
www.ti.com
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN Command Byte Register Data
(1)
Register Data
(1)(2)
(1) One or more bytes depending on MULbit.
(2) After the prescribed number of registers are read, then one ormore additional commands can be issued in succession.
NOTE:
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN Command 1 Command 2
(1)
Command 3
(1)
NOTE: (1) Oneor more commandscan be issued in succession.
CHANNEL DATA
STATUS BYTE
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Figure 58. Register Write Operation
Figure 59. Control Command Operation
The data read operation outputs either four bytes (one byte for status and three bytes for data), or three bytes
for data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see
Table 13 , Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three
bytes are the data bytes. The MSB (Data23) of the data is shifted out first.
Table 10. CHANNEL DATA FORMAT
BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0
2 MSB Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16
3 MSB-1 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8
4 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0
BIT STATUS.7, NEW
The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit
remains set indefinitely until the channel data is read. When the channel data is read again before the converter
updates with new data, the previous data is output and the NEW bit is cleared. If the channel data is not read
before the next conversion update, the data from the previous conversion is lost. As shown in Figure 60 , the
NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in
software, the user reads data at a rate faster than the converter's data rate. The user then polls the NEW bit to
detect for new channel data.
0 = Channel data has not been updated since the last read operation.
1 = Channel data has been updated since the last read operation.
31
Submit Documentation Feedback
Page 32
www.ti.com
DRDY
NEW Bit
Data Reads
(register format)
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Figure 60. NEW Bit Operation
BIT STATUS.6 OVF
When this bit is set, this indicates the differential voltage applied to the ADC inputs have exceeded the range of
the converter |V
IN
| > 1.0 6V
REF
. During over-range, the output code of the converter clips to either positive FS
(V
IN
≥ 1.0 6 × V
REF
) or negative FS (V
IN
≤ – 1.0 6× V
REF
). This bit, with the MSB of the data, can be used to
detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital
filter, the absence of this bit does not assure that the modulator of the ADC has not saturated due to possible
transient input overload conditions.
BIT STATUS.5 SUPPLY
This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The supply bit is
set when the value falls below 4.3V (typically) and is reset when the value rises 50mV higher (typically). The
output data of the ADC may not be valid under low power-supply conditions.
BITS CHID[4:0] CHANNEL ID BITS
The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode,
the Channel ID bits are undefined. See Table 11 for the channel ID, the measurement priority, and the channel
description for Auto-Scan Mode.
32
Submit Documentation Feedback
Page 33
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
BITS DATA[23:0] OF DATA BYTES
The ADC output data are 24 bits wide (DATA[23:0]). DATA23 is the most significant bit (MSB) and DATA0 is the
least significant bit (LSB). The data is coded in binary twos complement format.
Table 11. Channel ID and Measurement Order (Auto-Scan Mode)
BITS CHID[4:0] PRIORITY CHANNEL DESCRIPTION
00h 1 (Highest) DIFF0 (AIN0–AIN1) Differential 0
01h 2 DIFF1 (AIN2–AIN3) Differential 1
02h 3 DIFF2 (AIN4–AIN5) Differential 2
03h 4 DIFF3 (AIN6–AIN7) Differential 3
04h 5 DIFF4 (AIN8– AIN9) Differential 4
05h 6 DIFF5 (AIN10–AIN11) Differential 5
06h 7 DIFF6 (AIN12–AIN13) Differential 6
07h 8 DIFF7 (AIN14–AIN15) Differential 7
08h 9 AIN0 Single-Ended 0
09h 10 AIN1 Single-Ended 1
0Ah 11 AIN2 Single-Ended 2
0Bh 12 AIN3 Single-Ended 3
0Ch 13 AIN4 Single-Ended 4
0Dh 14 AIN5 Single-Ended 5
0Eh 15 AIN6 Single-Ended 6
0Fh 16 AIN7 Single-Ended 7
10h 17 AIN8 Single-Ended 8
11h 18 AIN9 Single-Ended 9
12h 19 AIN10 Single-Ended 10
13h 20 AIN11 Single-Ended 11
14h 21 AIN12 Single-Ended 12
15h 22 AIN13 Single-Ended 13
16h 23 AIN14 Single-Ended 14
17h 24 AIN15 Single-Ended 15
18h 25 OFFSET OFFSET
1Ah 26 VCC AVDD – AVSS Supplies
1Bh 27 TEMP Temperature
1Ch 28 GAIN Gain
1Dh 29 (Lowest) REF External Reference
33
Submit Documentation Feedback
Page 34
www.ti.com
COMMAND AND REGISTER DEFINITIONS
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Commands are used to read channel data, access the configuration registers, and control the conversion
process. If the command is a register read or write operation, one or more data bytes follow the command byte.
If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation
(see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data
Read direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data
read by command does not require CS to be toggled.
The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and
the Register Address Bits (A[3:0]); see the Command Byte register.
Command Byte
7 6 5 4 3 2 1 0
C2 C1 C0 MUL A3 A2 A1 A0
Bits C[2:0] — Command Bits
These bits code the command within the command byte.
C[2:0] DESCRIPTION COMMENTS
000 Channel Data Read Direct (no command) Toggle CS or allow SPI timeout before sending command
001 Channel Data Read Command (register format) Set MUL = 1; status byte always included in data
010 Register Read Command
011 Register Write Command
100 Pulse Convert Command MUL, A[3:0] are don't care
101 Reserved
110 Reset Command MUL, A[3:0] don't care
111 Channel Data Read Direct (no command) Toggle CS or allow SPI timeout before sending command
Bit 4 MUL: Multiple Register Access
0 = Disable Multiple Register Access
1 = Enable Multiple Register Access
This bit enables the multiple register access. This option allows writing or reading more than one register in a
single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register
access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1258 automatically
increments the register address for each register data byte subsequently read or written. The multiple register
read or write operations complete after register address = 09h (device ID register) has been accessed.
The multiple register access is terminated in one of three ways:
1. The user takes CS high. This action resets the SPI interface.
2. The user holds SCLK inactive for 4096 f
CLK
cycles. This action resets the SPI interface.
3. Register address = 09h has been accessed. This completes the command and the ADS1258 is then ready
for a new command. Note for the Channel Data Read command, this bit must be set to read the four data
bytes (one status byte and three data bytes).
A[3:0] Register Address Bits
These bits are the register addresses for a register read or write operation; see Table 12 .
34
Submit Documentation Feedback
Page 35
www.ti.com
REGISTERS
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Table 12. Register Map
ADDRESS REGISTER DEFAULT
Bits A[3:0] NAME VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h CONFIG0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0
01h CONFIG1 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0
02h MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0
03h MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8
06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET
07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0
08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h)
7 6 5 4 3 2 1 0
0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0
Default = 0Ah.
Bit 7 Must be 0 (default)
Bit 6 SPIRST SPI Interface Reset Timer
This bit sets the number of f
CLK
cycles in which SCLK is inactive the SPI interface will reset. This
places a lower limit on the frequency of SCLK in which to read or write data to the device. The SPI
interface only is reset and not the device itself. When the SPI interface is reset, it is ready for a new
command.
0 = Reset when SCLK inactive for 4096f
CLK
cycles (256µs, f
CLK
= 16MHz) (default).
1 = Reset when SCLK inactive for 256f
CLK
cycles (16µs, f
CLK
= 16MHz).
Bit 5 MUXMOD
This bit sets either the Auto-Scan or Fixed-Channel mode of operation.
0 = Auto-Scan Mode (default)
In Auto-Scan mode, the input channel selections are eight differential channels (DIFF0–DIFF7) and 16
single-ended channels (AIN0–AIN15). Additionally, five internal monitor readings can be selected.
These selections are made in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. In this mode,
settings in register MUXSCH have no effect. See the Auto-Scan section for more details.
1 = Fixed-Channel Mode
In Fixed-Channel mode, any of the analog input channels may be selected for the positive
measurement channel, and any of the analog input may be selected for the negative measurement
channel. The inputs are selected in register MUXSCH. In this mode, registers MUXDIF, MUXSG0,
MUXSG1, and SYSRED have no effect. Note that it is not possible to select the internal monitor
readings in this mode.
Bit 4 BYPAS
This bit selects either the internal or external connection from the multiplexer output to the ADC input.
0 = ADC inputs use internal multiplexer connection (default).
1 = ADC inputs use external ADC inputs (ADCINP and ADCINN).
Note that the Temperature, V
CC
, Gain, and Reference internal monitor readings automatically use the
internal connection, regardless of the BYPAS setting. The Offset reading uses the setting of BYPAS.
35
Submit Documentation Feedback
Page 36
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Bit 3 CLKENB
This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal
oscillator and PLL circuit.
0 = Clock output on CLKIO disabled.
1 = Clock output on CLKIO enabled (default).
Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit
has no effect.
Bit 2 CHOP
This bit enables the chopping feature on the external multiplexer loop.
0 = Chopping Disabled (default)
1 = Chopping Enabled
The chopping feature corrects for offset originating from components used in the external multiplexer
loop; see the External Chopping section.
Note that for Internal System readings (Temperature, VCC, Gain, and Reference), the CHOP bit must
be 0.
Bit 1 STAT Status Byte Enable
When reading channel data from the ADS1258, a status byte is normally included with the conversion
data. However, in some ADS1258 operating modes, the status byte can be disabled. Table 13 , Status
Byte, shows the modes of operation and the data read formats in which the status byte can be
disabled.
0 = Status Byte Disabled
1 = Status Byte Enabled (default)
Table 13. Status Byte
CHANNEL DATA CHANNEL DATA
MODE READ COMMAND READ DIRECT
Auto-Scan Always Enabled Enabled/Disabled by STAT Bit
Fixed-Channel Always Enabled (Byte is Undefined) Always Disabled
Bit 0 Must be 0
36
Submit Documentation Feedback
Page 37
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h)
7 6 5 4 3 2 1 0
IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0
Default = 83h.
Bit 7 IDLMOD
This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode
offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle
Modes section.
0 = Select Standby Mode
1 = Select Sleep Mode (default)
Bits DLY[2:0]
6–4 These bits set the amount of time the converter will delay after indexing to a new channel but before
starting a new conversion. This value should be set large enough to allow for the full settling of
external filtering or buffering circuits used between the MUXOUTP, MUXOUTN, and ADCINP,
ADCINN pins; see the Switch Time Delay section. (default = 000)
Bits SBCS[1:0]
3–2 These bits set the sensor bias current source.
0 = Sensor Bias Current Source Off (default)
1 = 1.5µA Source
3 = 24µA Source
Bits DRATE[1:0]
1–0 These bits set the data rate of the converter. Slower reading rates yield increased resolution; see
Table 4 . The actual data rates shown in the table can be slower, depending on the use of Switch Time
Delay or the Chop feature. See the Switch Time Delay section. The reading rate scales with the
master clock frequency.
DATA RATE DATA RATE
AUTO-SCAN MODE FIXED-CHANNEL MODE
DRATE[1:0] (SPS) (SPS)
11 23739 125000
10 15123 31250
01 6168 7813
00 1831 1953
f
CLK
= 16MHz, Chop = 0, Delay = 0.
37
Submit Documentation Feedback
Page 38
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h)
7 6 5 4 3 2 1 0
AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0
Default = 00h.
This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The
MUXMOD bit in register CONFIG0 must be set to '1'. In this mode, bits AINN[3:0] select the analog input
channel for the negative ADC input, and bits AINP[3:0] select the analog input channel for the positive ADC
input. See the Fixed-Channel Mode section.
MUXDIF: MULTIPLEXER DIFFERENTIAL INPUT SELECT REGISTER (Address = 03h)
7 6 5 4 3 2 1 0
DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
Default = 00h.
MUXSG0: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 0 (Address = 04h)
7 6 5 4 3 2 1 0
AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
Default = FFh.
MUXSG1: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 1 (Address = 05h)
7 6 5 4 3 2 1 0
AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8
Default = FFh.
SYSRED: SYSTEM READING SELECT REGISTER (Address = 06h)
7 6 5 4 3 2 1 0
0 0 REF GAIN TEMP VCC 0 OFFSET
Default = 00h.
These four registers select the input channels and the internal readings for measurement in Auto-Scan mode.
For differential channel selections (DIFF0 … DIFF7), adjacent input pins (AIN0/AIN1, AIN2/AIN3, etc.) are
pre-set as differential inputs. All single-ended inputs are measured with respect to the AINCOM input. AINCOM
may be set to any level within ± 100mV of the analog supply range. Channels not selected are skipped in the
measurement sequence. Writing to any of these four registers resets the internal channel pointer to the
channel with the highest priority (see Table 11 ). Note that the bits indicated as '0' must be set to 0.
0 = Channel not selected within a reading sequence.
1 = Channel selected within a reading sequence.
38
Submit Documentation Feedback
Page 39
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h)
7 6 5 4 3 2 1 0
CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0
Default = FFh.
This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port
pins are inputs and as such they should not be left floating. See the GPIO Digital Port section.
0 = GPIO is an output; 1 = GPIO is an input (default).
CIO[7:0] GPIO Configuration
bit 7 CIO7, Digital I/O Configuration Bit for Pin GPIO7
bit 6 CIO6, Digital I/O Configuration Bit for Pin GPIO6
bit 5 CIO5, Digital I/O Configuration Bit for Pin GPIO5
bit 4 CIO4, Digital I/O Configuration Bit for Pin GPIO4
bit 3 CIO3, Digital I/O Configuration Bit for Pin GPIO3
bit 2 CIO2, Digital I/O Configuration Bit for Pin GPIO2
bit 1 CIO1, Digital I/O Configuration Bit for Pin GPIO1
bit 0 CIO0, Digital I/O Configuration Bit for Pin GPIO0
GPIOD: GPIO DATA REGISTER (Address = 08h)
7 6 5 4 3 2 1 0
DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
Default = 00h.
This register is used to read and write data to the GPIO port pins. When reading this register, the data returned
corresponds to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As
outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. See the
GPIO Digital Port section.
0 = GPIO is logic low (default); 1 = GPIO is logic high.
DIO[7:0] GPIO Data
bit 7 DIO7, Digital I/O Data bit for Pin GPIO7
bit 6 DIO6, Digital I/O Data bit for Pin GPIO6
bit 5 DIO5, Digital I/O Data bit for Pin GPIO5
bit 4 DIO4, Digital I/O Data bit for Pin GPIO4
bit 3 DIO3, Digital I/O Data bit for Pin GPIO3
bit 2 DIO2, Digital I/O Data bit for Pin GPIO2
bit 1 DIO1, Digital I/O Data bit for Pin GPIO1
bit 0 DIO0, Digital I/O Data bit for Pin GPIO0
ID: DEVICE ID REGISTER (Address = 09h)
7 6 5 4 3 2 1 0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Default = 8Bh.
ID[7:0] ID Bits
Factory-programmed ID bits. Read-only.
39
Submit Documentation Feedback
Page 40
www.ti.com
APPLICATIONS
HARDWARE CONSIDERATIONS
Input AINx
AVDD
BAT54SWTI
AVSS
10k
Ω
typ.
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
The following summarizes the design and layout
considerations when using the ADS1258:
a. Power Supplies: The converter accepts a single
+5V supply (AVDD = +5V and AVSS = AGND) or
dual, bipolar supplies (typically AVDD = +2.5V,
AVSS = –2.5V). Dual supply operation
accommodates true bipolar input signals, within a
± 2.5V range. Note that the maximum negative
input voltage to the multiplexer is limited to AVSS
Figure 61. Input Overload Protection
– 100mV, and the maximum positive input
voltage is limited to AVDD + 100mV. The range
d. ADC Inputs: The external multiplexer loop of the
for the digital power supply (DVDD) is 2.7V to
ADS1258 allows for the inclusion of signal
5.25V. For all supplies, use a 10 µ F tantalum
conditioning between the output of the multiplexer
capacitor, bypassed with a 0.1 µ F ceramic
and the input of the ADC. Typically, an amplifier
capacitor, placed close to the device pins.
is used to provide gain, buffering, and/or filtering
Alternatively, a single 10 µ F ceramic capacitor can
to the input signal. For best performance, the
be used. The supplies should be relatively free
ADC inputs should be driven differentially. A
from noise and should not be shared with devices
differential in/differential out or a
that produce voltage spikes (such as relays, LED
single-ended-to-differential driver is recom-
display drivers, etc.). If a switching power supply
mended. If the driver uses higher supply voltages
is used, the voltage ripple should be low (< 2mV).
than the device itself (for example, ± 15V),
The analog and digital power supplies may be
attention should be paid to power-supply
sequenced in any order.
sequencing and potential over-voltage fault
b. Analog (Multiplexer) Inputs: The 16-channel
conditions. Protection resistors and/or external
analog input multiplexer can accommodate 16
clamp diodes may be used to protect the ADC
single-ended inputs, eight differential input pairs,
inputs. A 1nF or higher capacitor should be used
or combinations of either. These options permit
directly across the ADC inputs.
freedom in choosing the input channels. The
e. Reference Inputs: It is recommended to use a
channels do not have to be used consecutively.
10 µ F tantalum with a 0.1 µ F ceramic capacitor
Unassigned channels are skipped by the device.
directly across the reference pins, VREFP and
In the Fixed-Channel mode, any of the analog
VREFN. The reference inputs should be driven by
inputs (AIN0 to AIN15) can be addressed for the
a low-impedance source. For rated performance,
positive input and for the negative input. The
the reference should have less than 3 µ V
RMS
full-scale range of the device is 2.1 3V
REF
, but the
broadband noise. For references with higher
absolute analog input voltage is limited to 100mV
noise, external filtering may be necessary. Note
beyond the analog supply rails. Input signals
that when exiting the sleep mode, the device
exceeding the analog supply rails (for example,
begins to draw a small current through the
± 10V) must be divided prior to the multiplexer
reference pins. Under this condition, the transient
inputs.
response of the reference driver should be fast
c. Input Overload Protection: Overdriving the
enough to settle completely before the first
multiplexer inputs may affect the conversions of
reading is taken, or simply discard the first
other channels. In the case of input overload,
several readings.
external Schottky diode clamps and series
f. Clock Source: The ADS1258 requires a clock
resistor are recommended, as shown in Figure
signal for operation. The clock can originate from
61.
either the crystal oscillator or from an external
clock source. The internal oscillator uses a PLL
circuit and an external 32.768kHz crystal to
generate a 15.7MHz master clock. The PLL
requires a 22nF capacitor from the PLLCAP pin
to AVSS. The crystal and load capacitors should
be placed close to the pins as possible and kept
away from other traces with AC components. A
buffered output of the 15.7MHz clock can be
40
Submit Documentation Feedback
Page 41
www.ti.com
CONFIGURATION GUIDE
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
used to drive other converters or controllers. An
external clock source can be used up to 16MHz.
Configuration of the ADS1258 involves setting the
For best performance, the clock of the SPI
configuration registers via the SPI interface. After the
interface controller and the converter itself should
device is configured for operation, channel data is
be on the same domain. This configuration
read from the device through the same SPI interface.
requires that the ratio of the SCLK to device clock
The following is a suggested procedure for
must be limited to 1,1/2,1/4, 1/8, etc.
configuring the device:
g. Digital Inputs: It is recommended to source
1. Reset the SPI Interface: Before using the SPI
terminate the digital inputs and outputs of the
interface, it may be necessary to recover the SPI
device with a 50 Ω (typical) series resistor. The
interface. To reset the interface, set CS high or
resistors should be placed close to the driving
disable SCLK for 4096 (256) f
CLK
cycles.
end of the source (output pins, oscillator, logic
2. Stop the Converter: Set the START pin low to
gates, DSP, etc). This placement helps to reduce
stop the converter. Although not necessary for
the ringing and overshoot on the digital lines.
configuration, this command stops the channel
h. Hardware Pins: START, DRDY, RESET, and
scanning sequence which then points to the first
PWDN. These pins allow direct pin control of
channel after configuration.
the ADS1258. The equivalent of the START
3. Reset the Converter: The reset pin can be
and DRDY pins is provided via commands
pulsed low or a Reset command can be sent.
through the SPI interface; these pins may be
Although not necessary for configuration,
left unused. The device also has a RESET
reset re-initializes the device into a known
command. The PWDN pin places the ADC
state.
into very low-power state where the device is
inactive.
4. Configure the Registers: The registers are
configured by writing to them either sequentially
i. SPI Interface: The ADS1258 has an
or as a group. The user may configure the
SPI-compatible interface. This interface
software in either mode. Any write to the
consists of four signal lines: SCLK, DIN,
Auto-Scan channel-select registers resets the
DOUT, and CS. When CS is high, the DIN
channel pointer to the channel of highest priority.
input is ignored and the DOUT output
tri-states. See Chip Select ( CS) for more
5. Verify Register Data: The register data may be
details. The SPI interface can be operated in
read back for verification of device
a minimum configuration without the use of
communications.
CS (tie CS low; see the Serial Interface and
6. Start the Converter: The converter can be
Communication Protocol sections).
started with the Start pin or with a Pulse Convert
j. GPIO: The ADS1258 has eight, user-
command sent through the interface.
programmable digital I/O pins. These pins are
7. Read Channel Data: The DRDY asserts low
controlled by register settings. The register
when data is ready. The channel data can be
setting is default to inputs. If these pins are not
read at that time. If DRDY is not used, the
used, tie them high or low (do not float input pins)
updated channel data can be checked by reading
or configure them as outputs.
the NEW bit in the status byte. The status byte
k. QFN Package: See Application Note SLUA271 ,
also indicates the origin of the channel data. If the
QFN/SON PCB Attachment for PCB layout
data for a given channel is not read before DRDY
recommendations, available for download at
asserts low again, the data for that channel is lost
www.ti.com . The exposed thermal pad of the
and replaced with new channel data.
ADS1258 should be connected electrically to
AVSS.
41
Submit Documentation Feedback
Page 42
www.ti.com
DIGITAL INTERFACE CONNECTIONS
DIN
DOUT
DRDY
SCLK
CS
(1)
ADS1258
SPISIMO
SPISOMI
XINT1
SPICLK
SPISTA
TMS320R2811
(1) CS maybe tied low.
GPIO Connections
DIN
DOUT
DRDY
SCLK
CS
(1)
ADS1258
(1) CS maybe tied low.
P1.3
P1.2
P1.0
P1.6
P1.4
MSP430
GPIOx
(Input)
GPIOx
(Output)
ADS1258
4.7k
Ω
10k
Ω
Key Pad
3.3V
3.3V
470
LED Indicator
DIN
DOUT
DRDY
SCLK
CS
(1)
ADS1258
(1) CS maybe tied low.
MOSI
MISO
INT
SCK
IO
MSC12xx or
68HC11
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
The ADS1258 SPI-compatible interface easily
connects to a wide variety of microcontrollers and
DSPs. Figure 62 shows the basic connection to TI's
MSP430 family of low-power microcontrollers.
Figure 63 shows the connection to microcontrollers
with an SPI interface such as the 68HC11 family, or
TI's MSC12xx family . Note that the MSC12xx
includes a high-resolution ADC; the ADS1258 can be
used to provide additional channels of measurement
or add higher-speed connections. Finally, Figure 64
shows how to connect the ADS1258 to a TMS320x
DSP.
Figure 64. Connection to a TMS320R2811 DSP
The ADS1258 has eight general purpose
input/output (GPIO) pins. Each pin can be configured
as an input or an output. Note that pins configured as
inputs should not float. The pins can be used to read
key pads, drive LED indicator, etc., by reading and
writing the GPIO data register (GPIOD). See
Figure 65 .
Figure 62. Connection to MSP430 Microcontroller
Figure 65. GPIO Connections
Figure 63. Connection to Microcontrollers with an
SPI Interface
42
Submit Documentation Feedback
Page 43
www.ti.com
ANALOG INPUT CONNECTIONS
100
Ω
10k
Ω
9.09k
Ω
10k
Ω
OPA3 50
OPA3 65
OPA3 65
ADS1258
47
Ω
10k
Ω
2.2nF
+2.5V
+2.5V
MU XOUTN
MU XOUTP
ADCINP
ADCINN
−
2.5V
+2.5V
−
2.5V
+2.5V
−
2.5V
AIN15
AINCOM
REFP
REFN
AIN0
AVSS AVDD
±
10V
9.09k
Ω
±
10V
50
Ω
AINx
20m A Input
1k
Ω
1k
Ω
+2.5V
−
2.5V
0.1µF
100µF 0.1µF
0.47µF
+
10µF
+
REF3125
0.1µF
+
10µF
−
2.5V
0.1µF
+
10µF
…
…
NOTE: 0.1µF ca pacitors not shown.
47
Ω
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
When using Auto-Scan mode to sequence through
the channels, the switch time delay feature
Figure 66 shows the ADS1258 interfacing to
(programmable by registers) can be used to provide
high-level ± 10V inputs, commonly used in industrial
additional settling time of the external components.
environments. In this case, bipolar power supplies
are used, avoiding the need for input signal Figure 67 illustrates the ADS1258 interfacing to
level-shifting otherwise required when a single multiple pressure sensors having a resistor bridge
supply is used. The input resistors serve both to output. Each sensor is excited by the +5V single
reduce the level of the 10V input signal to within the supply that also powers the ADS1258 and likewise is
ADC range and also protect the inputs from used as the ADS1258 reference input; the 6% input
inadvertent signal over-voltage up to 30V. The overrange capability accommodates input levels at or
external amplifiers convert the single-ended inputs to above V
REF
. The ratiometric connection provides
a fully differential output to drive the ADC inputs. cancellation of excitation voltage drift and noise. For
Driving the inputs differentially maintains good best performance, the +5V supply should be free
linearity performance. The 2.2nF capacitor at the from glitches or transients. The 5V supply input
ADC inputs is required to bypass the ADC sampling amplifiers (two OPA365 s) form a differential
currents. The 2.5V reference, REF3125 , is filtered input/differential output buffer with the gain set to 10.
and buffered to provide a low-noise reference input The chop feature of the ADS1258 is used to reduce
to the ADC. The chop feature of the ADC can be offset and offset drift to very low levels. The 2.2nF
used to reduce offset and offset drift of the capacitor at the ADC inputs is required to bypass the
amplifiers. ADC sampling currents. The 47 Ω resistors isolate
the op-amp outputs from the filter capacitor.
For ± 1V input signals, the input resistor divider can
be removed and replaced with a series protection
resistor. For 20mA input signals, the input resistor
divider is replaced by a 50 Ω resistor, connected from
each input to AINCOM.
Figure 66. Multichannel, ± 10V Single-Ended Input, Bipolar Supply Operation
43
Submit Documentation Feedback
Page 44
www.ti.com
2k
Ω
47
Ω
R2= 10k
Ω
R2= 10k
Ω
ADS1258
2.2nF
+5V
+5V
47
Ω
AIN0
AINCOM
MUXOUTN
MUXOUTP
ADCINP
ADCINN
2k
Ω
AIN1
2k
Ω
AIN14
2k
Ω
AIN15
REFP
REFN
AVSS AVDD
R1= 2.2k
Ω
10µF+0.1µF
0.1µF
+
10µF
OPA365
OPA365
RFI
RFI
RFI
RFI
RFI
RFI
NOTE: G =1 + 2R2/R1. Match for goodCMRR.
0.1µF capacitor not shown.
…
…
…
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Figure 67. Bridge Input, Single-Supply Operation
44
Submit Documentation Feedback
Page 45
www.ti.com
ADS1258
SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from C Revision (June 2006) to D Revision ................................................................................................... Page
• Changed statement about DOUT tri-states and inputs on DIN and SCLK; deleted SCLK reference ................................ 28
• Added section on SPI Bus Sharing .................................................................................................................................... 28
• Added note 3 to Figure 56 to indicate period of no SCLK activity ...................................................................................... 29
• Changed SPI Interface paragraph ...................................................................................................................................... 41
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from B Revision (December 2005) to C Revision .......................................................................................... Page
• Changed to "23.7kSPS/Channel" from "23.7kSPS" ............................................................................................................. 1
• Added "per channel" to end of first sentence ....................................................................................................................... 1
• Added "32.768kHz" to external oscillator on front page block diagram ................................................................................ 1
• Added "f
CLK
= 15.729MHz (internal clock)" to condition ........................................................................................................ 3
• Added "f
CLK
= 15.729MHz (internal clock)" to condition ........................................................................................................ 7
• Changed Figure 38 CLKENB bit gate connection .............................................................................................................. 16
• Changed to "trends toward" from "will be" in Open Sensor Detection paragaph ............................................................... 21
• Added optional signal conditioning to Figure 48 ................................................................................................................. 22
• Added paragraph and Equation 10 on scaling factor ......................................................................................................... 25
• Changed location of Table 9 cross reference ..................................................................................................................... 28
• Added "Highest" and "Lowest" to Priority column ............................................................................................................... 33
• Deleted MUXOUTP and MUXOUTN from Bit 4 paragraph description .............................................................................. 35
• Changed SPI Interface paragraph ...................................................................................................................................... 41
• Added paragraph on autoscan and switch time delay feature ........................................................................................... 43
• Deleted sentence referring to the chop feature enabled and data rate set to maximum ................................................... 43
45
Submit Documentation Feedback
Page 46
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
ADS1258IRTCR ACTIVE QFN RTC 48 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1258IRTCRG4 ACTIVE QFN RTC 48 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1258IRTCT ACTIVE QFN RTC 48 250 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1258IRTCTG4 ACTIVE QFN RTC 48 250 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status valuesare defined as follows:
ACTIVE: Product device recommendedfor new designs.
LIFEBUY: TI has announcedthat the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has beenannounced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinuedthe production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latestavailability information and additional product content details.
TBD: The Pb-Free/Green conversionplan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TIPb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sbdo not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not beavailable for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on anannual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2006
Addendum-Page 1
Page 47
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 1
Page 48
Device Package Pins Site Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
ADS1258IRTCR RTC 48 TAI 330 16 7.3 7.3 1.5 12 16 PKGORN
T2TR-MS
P
ADS1258IRTCT RTC 48 TAI 330 16 7.3 7.3 1.5 12 16 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
ADS1258IRTCR RTC 48 TAI 342.9 336.6 28.58
ADS1258IRTCT RTC 48 TAI 342.9 336.6 28.58
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 2
Page 49
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
Page 50
Page 51
Page 52
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Telephony www.ti.com/telephony
Low Power www.ti.com/lpw Video & Imaging www.ti.com/video
Wireless
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
Loading...