750 MHz to 1150 MHz Quadrature
V
V
Demodulator with Fractional-N PLL and VCO
FEATURES
IQ demodulator with integrated fractional-N PLL
LO frequency range: 750 MHz to 1150 MHz
Input P1dB: 12.5 dBm
Input IP3: 25 dBm
Noise figure (DSB): 14.3 dB
Voltage conversion gain: 5.1 dB
Quadrature demodulation accuracy
Phase accuracy: 0.3°
Amplitude accuracy: 0.05 dB
Baseband demodulation: 275 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
ADRF6801
GENERAL DESCRIPTION
The ADRF6801 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 3.0 GHz to 4.6 GHz. A
divide-by-4 quadrature divider divides the output frequency of
the VCO down to the required local oscillator (LO) frequency
to drive the mixers in quadrature. Additionally, an output buffer
can be enabled that generates an f
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
The ADRF6801 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
/2 signal for external use.
VCO
FUNCTIONAL BLOCK DIAGRAM
LOSEL
CCLO
CCLO
GND
34
LON
LOP
GND
DATA
CLK
GND
REFIN
GND
MUXOUT
35
37
38
MUX
1
VCC1
FRACTION
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
TEMP
SENSOR
3.3V LDO
2
DECL3
11
12
13
14
LE
15
6
7
8
SPI
INTERFACE
×2
÷2
÷4
17
10
VCC2
36
MODULUS
–
+
FREQUENCY
DETECTOR
16
GND
BUFFER
CTRL
INTEGER
REG
N COUNTER
PHASE
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAUL T ),
750µA,
1000µA
4
3
GND
CPOUT
5
RSET
BUFFER
BUFFER
9
DECL2
MUX
DIVIDER
VCO
CORE
39
VTUNE
OR
÷2
÷1
ADRF6801
VCO LDO2.5V LDO
40
DECL1
QUAD
÷2
Figure 1.
18
QBBP
IBBNIBBP
3233
19
QBBN
GND
31
20
GND
30
29
28
27
26
25
24
23
22
21
GND
VCCBB
GND
VCCRF
RFIN
GNDRF
GND
GND
VCCBB
GND
09576-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
ADRF6801
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Synthesizer/PLL.......................................................................... 12
Complementary Cumulative Distribution Functions (CCDF)
....................................................................................................... 13
Circuit Description......................................................................... 14
LO Quadrature Drive................................................................. 14
V-to-I Converter......................................................................... 14
Mixers .......................................................................................... 14
Emitter Follower Buffers ........................................................... 14
Bias Circuitry .............................................................................. 14
Register Structure....................................................................... 14
Applications Information.............................................................. 21
Basic Connections...................................................................... 21
Supply Connections................................................................... 21
Synthesizer Connections........................................................... 21
I/Q Output Connections........................................................... 22
RF Input Connections ............................................................... 22
Charge Pump/VTUNE Connections ...................................... 22
LO Select Interface ..................................................................... 22
External LO Interface ................................................................ 22
Setting the Frequency of the PLL............................................. 22
Register Programming............................................................... 22
EVM Measurements .................................................................. 23
Evaluation Board Layout and Thermal Grounding................... 24
ADRF6801 Software .................................................................. 28
Characterization Setups................................................................. 30
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
1/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADRF6801
SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; f
settings use the recommended values shown in the Register Structure section, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT AT 900 MHz RFIN pins
Internal LO Frequency Range With VCO amplitude = 63 (R6 [DB15 to DB10]) 750 1125 MHz
With VCO amplitude = 24 (R6 [DB15 to DB10]) 750 1150 MHz
Input Return Loss Measured at 900 MHz <−20 dB
Input P1dB 12.5 dBm
Second-Order Input Intercept (IIP2) −5 dBm each tone >65 dBm
Third-Order Input Intercept (IIP3) −5 dBm each tone 25 dBm
Noise Figure Double sideband from RF to either I or Q output 14.3 dB
With a −10 dBm interferer 5 MHz away 18.9 dB
LO-to-RF Leakage At 1×LO frequency, 50 Ω termination at the RF port −75 dBm
I/Q BASEBAND OUTPUTS IBBP, IBBN, QBBP, QBBN pins
Voltage Conversion Gain 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN) 5.1 dB
Demodulation Bandwidth 1 V p-p signal 3 dB bandwidth 275 MHz
Quadrature Phase Error 0.3 Degrees
I/Q Amplitude Imbalance 0.05 dB
Output DC Offset (Differential) ±5 mV
Output Common-Mode Voltage V
Gain Flatness Any 5 MHz (<100 MHz) 0.2 dB p-p
Maximum Output Swing Differential 450 Ω load 4 V p-p
Differential 200 Ω load 2.4 V p-p
Maximum Output Current Each pin 12 mA p-p
LO INPUT/OUTPUT LOP, LON
Output Level
Input Level Externally applied 2×LO, PLL disabled 0 dBm
Input Impedance Externally applied 2×LO, PLL disabled 50 Ω
VCO Operating Frequency With VCO amplitude = 63 (R6 [DB15 to DB10]) 3000 4500 MHz
With VCO amplitude = 24 (R6 [DB15 to DB10]) 3000 4600 MHz
SYNTHESIZER SPECIFICATIONS
Channel Spacing f
PLL Bandwidth
SPURS
Reference Spurs f
f
f
f
= 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, R
REF
Into a differential 50 Ω load, LO buffer enabled (LO
= 450 differential, all register and PLL
LOAD
− 2.4 V
POS
−2.5 dBm
frequency = 900 MHz, output frequency = 1800 MHz)
All synthesizer specifications measured with
recommended settings provided in Figure 33 through
Figure 39
= 26 MHz; modulus = 2047 25 kHz
PFD
Can be adjusted with off-chip loop filter component
values and R
= 900 MHz, f
f
LO
at BB outputs with f
= 26 MHz, f
REF
/2 −107.8 dBc
PFD
× 2 −89.1 dBc
PFD
× 3 −94.2 dBc
PFD
SET
= 26 MHz, f
REF
= 50 MHz
BB
= 26 MHz −91.6 dBc
PFD
= 26 MHz, measured
PFD
130 kHz
Rev. 0 | Page 3 of 36
ADRF6801
Parameter Test Conditions/Comments Min Typ Max Unit
PHASE NOISE (USING 130 kHz LOOP FILTER)
= 900 MHz, f
f
LO
= 26 MHz, f
REF
at BB outputs with f
= 50 MHz
BB
= 26 MHz, measured
PFD
1 kHz offset −99.5 dBc/Hz
10 kHz offset −107.8 dBc/Hz
100 kHz offset −106.6 dBc/Hz
500 kHz offset −126.7 dBc/Hz
1 MHz offset −131.7 dBc/Hz
5 MHz offset −143.5 dBc/Hz
10 MHz offset −150.5 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.16 °rms
PHASE NOISE (USING 2.5 kHz LOOP FILTER)
= 900 MHz, f
f
LO
= 26 MHz, f
REF
at BB outputs with f
= 50 MHz
BB
= 26 MHz, measured
PFD
1 kHz offset −71.3 dBc/Hz
10 kHz offset −88.3 dBc/Hz
100 kHz offset −114.1 dBc/Hz
500 kHz offset −129.5 dBc/Hz
1 MHz offset −138.6 dBc/Hz
5 MHz offset −150.2 dBc/Hz
10 MHz offset −150.3 dBc/Hz
PLL FIGURE OF MERIT (FOM) Measured with f
Measured with f
= 26 MHz, f
REF
= 104 MHz, f
REF
= 26 MHz −215.4 dBc/Hz/Hz
PFD
= 26 MHz −220.9 dBc/Hz/Hz
PFD
Phase Detector Frequency 20 26 40 MHz
REFERENCE CHARACTERISTICS REFIN, MUXOUT pins
REFIN Input Frequency Usable range 10 160 MHz
REFIN Input Capacitance 4 pF
MUXOUT Output Level VOL (lock detect output selected) 0.25 V
V
(lock detect output selected) 2.7 V
OH
REFOUT Duty Cycle 50 %
CHARGE PUMP
Pump Current 500 μA
Output Compliance Range 1 2.8 V
LOGIC INPUTS CLK, DATA, LE pins
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INH/IINL
1.4 3.3 V
INH
0 0.7 V
INL
0.1 μA
Input Capacitance, CIN 5 pF
POWER SUPPLIES VCC1, VCC2, VCCLO, VCCBB, VCCRF pins
Voltage Range (5 V) 4.75 5 5.25 V
Supply Current (5 V) Normal Rx mode, internal LO 262 mA
Rx mode, internal LO with LO buffer enabled 288 mA
Rx mode, using external LO input (internal VCO, PLL shut
down)
Supply Current (5 V) Power-down mode 20 mA
Rev. 0 | Page 4 of 36
157 mA
ADRF6801
C
TIMING CHARACTERISTICS
VS = 5 V, unless otherwise noted.
Table 2.
Parameter Limit at T
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
Timing Diagram
LOCK
MIN
to T
(B Version) Unit Test Conditions/Comments
MAX
t
4
t
5
DATA
t
2
DB23 (MSB) DB22 DB2
LE
t
1
LE
t
3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
t
7
09576-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 36
ADRF6801
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage, VCC1, VCC2, VCCLO,
VCCBB, and VCCRF (V
Digital I/O, CLK, DATA, and LE −0.3 V to +3.6 V
RFIN 16 dBm
θJA (Exposed Paddle Soldered Down) 30°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
)
S1
−0.5 V to +5.5 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 36
ADRF6801
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ND
31 GND
40 DECL1
39 VTUNE
38 LOP
37 LON
36 LOSEL
35 G
34 VCCLO
32 IBBN
33 IBBP
VCC1 1
DECL3 2
CPOUT 3
GND 4
RSET 5
REFIN 6
GND 7
MUXOUT 8
DECL2 9
VCC2 10
ENABLE
VCO
LDO
PHASE DETECTOR
CHARGE PUMP
×
2
÷2
÷4
2.5V
LDO
FRACTION
AND
MUX
SCALE
BLEED
VCO
BAND
CURRENT
CAL/SET
PROGRAMABLE
DIVIDER
THIRD-ORDER
MODULUS
6
6
SDM
BUFFER
CTRL
VCO
3000MHz
TO
4600MHz
MUX
PRESCALER
÷2
INTEGER
DIV
CTRL
DIV
÷1
OR
÷2
QUADRATURE
÷2
30 GND
29 VCCBB
28 GND
27 VCCRF
26 RFIN
25 GNDRF
24 GND
23 GND
22 VCCBB
21 GND
SERIAL PORT
LE 14
GND 11
CLK 13
DATA 12
GND 15
LO 17
GND 16
VCC
N 19
QBBP 18
GND 20
QBB
08817-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC1 The 5 V Power Supply Pin for VCO and PLL (VCC1).
2 DECL3 Decoupling Node for the 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
3 CPOUT Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
4, 7, 11, 15, 16, 20, 21,
GND Connect these pins to a low impedance ground plane.
23, 24, 28, 30, 31, 35
Rev. 0 | Page 7 of 36
ADRF6801
Pin No. Mnemonic Description
5 RSET
6 REFIN Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz.
8 MUXOUT
9 DECL2 Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
10 VCC2 The 5 V power supply pin for the 2.5 V LDO.
12 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
13 CLK
14 LE
17, 34 VCCLO The 5 V Power Supply for the LO Path Blocks.
18, 19 QBBP, QBBN Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
22, 29 VCCBB The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks.
25 GNDRF Ground Return for RF Input Balun.
26 RFIN Single-Ended, Ground Referenced 50 Ω, RF Input.
27 VCCRF The 5 V Power Supply for the RF Input Section of the Demodulator Blocks.
32, 33 IBBN, IBBP Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
36 LOSEL
37, 38 LON, LOP
39 VTUNE
40 DECL1
EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1
mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this
mode, no external R
(I
) can be externally tweaked according to the following equation where the resulting value is in
NOMINAL
is required. If DB18 is set to 1, the four nominal charge pump currents
SET
units of ohms.
⎡
=
R
⎢
SET
⎣
I
NOMINAL
⎤
×
I
4.217
CP
⎥
8.37
−
⎦
Multiplexer Output. This output can be programmed to provide the reference output signal or
the lock detect signal. The output is selected by programming the appropriate register.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit
word.
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is
set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The
externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set
low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set
high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and
the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.
Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds
to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
Connect a 10 μF capacitor between this pin and ground as close to the device as possible
because this pin serves as the VCO supply and loop filter reference.
Rev. 0 | Page 8 of 36
ADRF6801
A
R
A
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, unless otherwise noted. LO = 750 MHz to 1150 MHz.
16
14
IP1dB
12
10
8
GAIN
6
4
2
CONVERSION GAIN (dB) AND I NPUT P1dB (dBm)
0
750 800 850 900 950 1000 1050 1100 1150
TA = +85°C
TA = +25°C
TA = –40°C
LO FR EQUENCY (MHz)
Figure 4. Conversion Gain and Input P1dB vs. LO Frequency
35
33
TA = +85°C
31
T
= +25°C
A
T
= –40°C
29
27
25
23
INPUT IP3 (dBm)
21
19
17
15
A
750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz)
Figure 5. Input IP3 vs. LO Frequency
1.0
0.8
0.6
0.4
0.2
TCH (dB)
0
–0.2
–0.4
IQ GAIN MISM
–0.6
–0.8
–1.0
TA = +85°C
T
= +25°C
A
T
= –40°C
A
750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz)
Figure 6. IQ Gain Mismatch vs. LO Frequency
09576-004
09576-005
09576-006
80
75
70
65
INPUT IP2 (dBm)
60
55
50
750 800 850 900 950 1000 1050 1100 1150
TA = +85°C
TA = +25°C
TA = –40°C
I CHANNEL
Q CHANNEL
LO FREQ UENCY (MHz )
Figure 7. Input IP2 vs. LO Frequency
20
19
18
TA = +85°C
T
17
16
15
14
NOISE FI GURE (dB)
13
12
11
10
750 800 850 900 950 10 00 1050 1 10 0 1150
= +25°C
A
T
= –40°C
A
LO FREQ UENCY (MHz)
Figure 8. Noise Figure vs. LO Frequency
5
4
TA = +85°C
T
3
2
1
0
–1
TURE PHASE ERROR (Degrees)
–2
–3
–4
IQ QUAD
–5
750 800 850 900 950 1000 1050 1100 1150
= +25°C
A
T
= –40°C
A
LO FREQUENCY (MHz)
Figure 9. IQ Quadrature Phase Error vs. LO Frequency
09576-007
09576-008
09576-009
Rev. 0 | Page 9 of 36
ADRF6801
–
–
–
50
–55
–60
–65
–70
–75
–80
LO-TO-RF F E E DTHROUGH (dBm)
–85
–90
750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz)
Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off
35
–40
–45
–50
–55
–60
–65
LO-TO-BB FEE DTHROUGH (dBV rms)
–70
1
0
–1
–2
–3
–4
NORMALIZE D BASE BAND
–5
FREQUENCY RES PONSE (dB)
–6
–7
1 10 100
09576-010
BASEBAND FREQUENCY (MHz)
09576-013
Figure 13. Normalized Baseband Frequency Response vs. Baseband
Frequency
80
70
60
TA = +85°C
= +25°C
T
50
40
30
AND INPUT IP3 ( dBm)
20
INPUT P1dB (dBm), INPUT IP2 (d Bm),
10
A
= –40°C
T
A
I CHANNEL
Q CHANNEL
IIP2
IIP3
IP1dB
–75
750 800 850 900 950 1000 1050 1100 1150
LO FREQ UENCY (MHz )
09576-011
Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off
30
–35
–40
–45
–50
–55
–60
RF-TO-BB FEEDTHROUGH (dBc)
–65
–70
750 800 850 900 950 1000 1050 1100 1150
RF FREQUENC Y (MHz)
09576-012
Figure 12. RF-to-BB Feedthrough vs. RF Frequency
0
5 101520253035404550
BASEBAND FREQUENCY (MHz)
09576-014
Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency
34
32
30
28
26
24
22
20
18
NOISE FI GURE (dB)
16
14
12
10
–35 –30 –25 –20 –15 –10 –5 0 5
INPUT BLOCKE R P OWER (dBm)
09576-015
Figure 15. Noise Figure vs. Input Blocker Level,
= 900 MHz (RF Blocker 5 MHz Offset)
f
LO
Rev. 0 | Page 10 of 36
ADRF6801
A
T
0
2.0
–5
–10
–15
–20
–25
–30
RF INPUT RET URN L OSS (dB)
–35
–40
750 800 850 900 950 1000 1050 1100 1150
RF FREQUENC Y ( MHz )
Figure 16. RF Input Return Loss vs. RF Frequency
0
–2
–4
L
–6
–8
–10
LOP, LON DIFFERENTI
12
OUTPUT RET URN LOSS (dB)
–14
1.9
1.8
1.7
1.6
1.5
VPTAT VOLTAGE (V )
1.4
1.3
1.2
–40 –15 10 35 60 85
09576-016
TEMPERATURE (°C)
09576-019
Figure 19. VPTAT vs. Temperature
3.5
3.0
2.5
AGE (V)
2.0
1.5
VTUNE VOL
1.0
TA = +85°C
TA = +25°C
TA = –40°C
–16
1500 1600 1700 1800 1900 2000 2100 2200 2300
LOP, LON OUTPUT FREQUENCY (MHz)
Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output
Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun
400
380
360
340
320
300
280
CURRENT (mA)
260
240
220
200
750 800 850 900 950 1000 1050 1100 1150
LO FREQ UENCY (MHz )
TA = +85°C
T
= +25°C
A
T
= –40°C
A
Figure 18. 5 V Supply Currents vs. LO Frequency,
LO Output Enabled
0.5
09576-017
750 800 850 900 950 1000 1050 1 100 1150
LO FREQUENCY (MHz)
09576-020
Figure 20. VTUNE vs. LO Frequency
09576-018
Rev. 0 | Page 11 of 36
ADRF6801
–
–
–
A
–
–
SYNTHESIZER/PLL
VS = 5 V. See the Register Structure section for recommended settings used. External loop filter bandwidths of ~130 kHz and 2.5 kHz
used (see plots within this section for annotations), f
40
–60
–80
–100
–120
PHASE NOISE (dBc/Hz)
–140
–160
1k 10k 100k 1M 10M
2.5kHz LO OP FILTER
BANDWIDTH
OFFSE T FREQUENCY (Hz)
Figure 21. Phase Noise vs. Offset Frequency, f
Filter Bandwidths of 2.5 kHz and 130 kHz
70
–75
–80
–85
TA = +85°C
T
= +25°C
A
T
= –40°C
A
1 × PFD FREQ UENCY
3 × PFD FREQ UENCY
0.5 × PFD FR EQUENCY
TA = +85°C
T
= +25°C
A
T
= –40°C
A
130kHz LOOP FILTER
BANDWIDTH
= 900 MHz, Shown for Loop
LO
REF
= f
= 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted.
PFD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
TED PHASE NOISE (°rms)
0.3
0.2
INTEGR
0.1
0
750 800 850 900 950 1000 1050 1100 1150
09576-021
LO FREQUENCY (MHz)
TA = +85°C
T
= +25°C
A
= –40°C
T
A
Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted), Using
Loop Filter Bandwidth of 130 kHz
50
1kHz
OFFSET
–70
–90
10kHz
OFFSET
1kHz OFFS ET
09576-024
–90
–95
–100
PLL REFERENCE SPURS ( dBc)
–105
–110
750 800 850 900 950 1000 1050 1100 1150
LO FREQ UENCY (MHz)
Figure 22. PLL Reference Spurs vs. LO Frequency, Using Loop Filter
Bandwidth of 130 kHz
PLL REFERENCE SPURS ( d Bc)
70
–75
–80
–85
–90
–95
–100
–105
–110
TA = +85°C
T
= +25°C
A
T
= –40°C
A
750 800 850 900 950 1000 1050 1100 1150
LO FREQ UE NCY (M Hz )
2 × PFD FREQ UE NCY
4 × PFD FREQ UE NCY
Figure 23. PLL Reference Spurs vs. LO Frequency, Using Loop Filter
Bandwidth of 130 kHz
–110
10kHz
OFFSET
–130
PHASE NOISE (dBc/Hz)
09576-022
5MHz
OFFSET
–150
–170
750 800 850 900 950 1000 1050 1100 1150
130kHz LOO P FILTER BANDWIDTH
2.5kHz LOO P FILTER BANDWIDTH
5MHz
OFFSET
LO FREQ UE NCY (M Hz )
TA = +85°C
T
= +25°C
A
T
= –40°C
A
09576-025
Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets),
Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
90
–100
100kHz OFF S E T
–110
–120
–130
–140
PHASE NOISE (dBc/Hz)
–150
–160
750 800 850 900 950 1000 1050 1100 1 150
09576-023
1MHz OFFSET
1MHz OFF SE T
130kHz LOO P FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
LO FREQ UE NCY (M Hz )
100kHz OFFS E T
TA = +85°C
T
= +25°C
A
T
= –40°C
A
09576-026
Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets), Shown
for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
Rev. 0 | Page 12 of 36
ADRF6801
A
A
A
A
A
A
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF)
VS = 5 V, fLO = 900 MHz, fBB = 4.5 MHz.
100
90
80
70
60
50
40
30
TIVE DIS T RIBUTION PERCE NTAGE (%)
20
10
CUMUL
0
024681012141618
GAIN
GAIN (dB) AND INPUT P1dB ( dBm)
TA = +85°C
T
= +25°C
A
T
= –40°C
A
Figure 27. Gain and Input P1dB
100
90
TA = +85°C
80
T
= +25°C
A
T
= –40°C
70
60
50
40
30
TIVE DIS T RIBUTION P ERCENTAGE (%)
20
10
CUMUL
0
A
I CHANNEL
Q CHANNEL
15 17 19 21 23 25 27 29 31 33 35
INPUT IP3 (dBm)
Figure 28. Input IP3
100
90
80
70
60
50
40
30
TIVE DIS T RIBUTION PE RCENTAGE (%)
20
10
CUMUL
0
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
TA = +85°C
T
= +25°C
A
T
= –40°C
A
IQ GAIN MISMATCH (dB)
Figure 29. IQ Gain Mismatch
IP1dB
09576-027
09576-028
09576-029
100
90
80
70
60
50
40
30
TIVE DIS T RIBUTION PERCE NTAGE (%)
20
10
CUMUL
0
60 62 64 66 68 70 72 74 76 78 80
TA = +85°C
T
= +25°C
A
T
= –40°C
A
I CHANNEL
Q CHANNEL
INPUT IP2 (dBm)
Figure 30. Input IP2
100
90
80
70
60
50
40
30
TIVE DIS T RIBUTION P ERCENTAGE (%)
20
10
CUMUL
0
4 6 8 1012141618202224
TA = +85°C
T
= +25°C
A
T
= –40°C
A
NOISE FI GURE (dB)
Figure 31. Noise Figure
100
90
80
70
60
50
40
30
TIVE DIS T RIBUTION PERCE NTAGE (%)
20
10
CUMUL
0
–5 –4 –3 –2 –1 0 1 2 3 4 5
TA = +85°C
T
= +25°C
A
T
= –40°C
A
IQ QUADRATURE PHASE ERROR (Degrees)
Figure 32. IQ Quadrature Phase Error
09576-030
09576-131
09576-132
Rev. 0 | Page 13 of 36
ADRF6801
CIRCUIT DESCRIPTION
The ADRF6801 integrates a high performance IQ demodulator
with a state-of-the-art fractional-N PLL. The PLL also integrates
a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions, the demodulator LO divider functions,
and optimization functions, as well as allowing for an externally
applied LO.
The ADRF6801 uses a high performance mixer core that results
in an exceptional input IP3 and input P1dB, with a very low output
noise floor for excellent dynamic range.
LO QUADRATURE DRIVE
A signal at 2× the desired mixer LO frequency is delivered to
a divide-by-2 quadrature phase splitter followed by limiting
amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The RF input signal is applied to an on-chip balun which then
provides both a ground referenced, 50 Ω single-ended input
impedance and a differential voltage output to a V-to-I converter
that converts the differential voltages to differential output currents.
These currents are then applied to the emitters of the Gilbert
cell mixers.
MIXERS
The ADRF6801 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential I and Q signals
off chip. The output impedance is set by on-chip 12 Ω series
resistors that yield a 24 Ω differential output impedance for each
baseband port. The fixed output impedance forms a voltage divider
with the load impedance that reduces the effective gain. For example,
a 500 Ω differential load has ~0.5 dB lower effective gain than
with a high (10 kΩ) differential load impedance.
The common-mode dc output levels of the emitter followers are set
from VCCBB via the voltage drop across the mixer load resistors,
the V
of the output emitter follower, and the voltage drop
BE
across the 12 Ω series resistor.
BIAS CIRCUITRY
There are several band gap reference circuits and three low
dropout regulators (LDOs) in the ADRF6801 that generate the
reference currents and voltages used by different sections. The
first of the LDOs is the 2.5 V LDO, which is always active and
provides the 2.5 V supply rail used by the internal digital logic
blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9)
for the user to provide external decoupling.
The second LDO is the VCO LDO, which acts as the positive
supply rail for the internal VCO. The VCO LDO output is
connected to DECL2 (Pin 40) for the user to provide external
decoupling. The VCO LDO can be powered down by setting
Register 6, DB18 = 0, which allows the user to save power when
not using the VCO.
The third LDO is the 3.3 V LDO, which acts as the 3.3 V
positive supply rail for the reference input, phase frequency
detector, and charge pump circuitry. The 3.3 V LDO output is
connected to DECL3 (Pin 2) for the user to provide external
decoupling. The 3.3 V LDO can be powered down by setting
Register 6, DB19 = 0, which allows the user to save power when
not using the VCO. The demodulator also has a bias circuit that
supplies bias current for the mixer V-to-I stage, which then sets
the bias for the mixer core. The demodulator bias cell can also
be shut down by setting Register 5, DB7 = 0.
REGISTER STRUCTURE
The ADRF6801 provides access to its many programmable
features through a 3-wire SPI control interface that is used to
program the seven internal registers. The minimum delay and
hold times are shown in the timing diagram (see Figure 2). The
SPI provides digital control of the internal PLL/VCO as well as
several other features related to the demodulator core, on-chip
referencing, and available system monitoring functions. The
MUXOUT pin provides a convenient, single-pin monitor output
signal that can be used to deliver a PLL lock-detect signal or an
internal voltage proportional to the local junction temperature.
Note that internal calibration for the PLL must run when the
ADRF6801 is initialized at a given frequency. This calibration is run
automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 must always be programmed
last. For ease of use, starting the initial programming with
Register 7 and then programming the registers in descending
order, ending with Register 0, is recommended. Once the PLL
and other settings are programmed, the user can change the
PLL frequency simply by programming Register 0, Register 1,
or Register 2 as necessary.
Rev. 0 | Page 14 of 36
ADRF6801
DIVIDE
MODE
DB23 DB22 DB 21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB 4 DB3 DB2 DB1 DB0
0000000000000DMID6ID5ID4ID3ID2ID1ID0C3(0)C2(0)C1(0)
DM
DIVIDE MODE
0
FRACTIONAL ( DE FAULT)
1
INTEGER
INTEGER DI V IDE RATIO CO NTROL BITS
Figure 33. Integer Divide Control Register (R0)
Register 0—Integer Divide Control
With R0[2:0] set to 000, the on-chip integer divide control register
is programmed as shown in Figure 33. The internal VCO
frequency (f
f
VCO
) equation is
VCO
= f
× (INT + (FRAC/MOD)) × 2 (1)
PFD
where:
f
is the output frequency of the internal VCO.
VCO
INT is the preset integer divide ratio value (21 to 123 for integer
mode, 24 to 119 for fractional mode).
MOD is the preset fractional modulus (1 to 2047).
FRAC is the preset fractional divider ratio value (0 to MOD − 1).
ID6 ID5 ID4 ID3 ID2 ID1 ID0
0010101
0010110
0010111
0011000
... ... ... ... ... ... ...
... ... ... ... ... ... ...
0111000
... ... ... ... ... ... ...
... ... ... ... ... ... ...
1110111
1111000
1111001
1111010
1111011
DIVIDE RATI O
21 (INTEGER MODE ONLY)
22 (INTEGER MODE ONLY)
23 (INTEGER MODE ONLY)
24
...
...
56 (DEFAULT )
...
...
119
120 (INTEGER MODE ONLY)
121 (INTEGER MODE ONLY)
122 (INTEGER MODE ONLY)
123 (INTEGER MODE ONLY)
The integer divide ratio sets the INT value in Equation 1. The
INT, FRAC, and MOD values make it possible to generate output
frequencies that are spaced by fractions of the PFD frequency.
Note that the demodulator LO frequency is given by f
LO
Divide Mode
Divide mode determines whether fractional mode or integer mode
is used. In integer mode, the VCO output frequency, f
calculated by
f
= f
VCO
× (INT) × 2 (2)
PFD
= f
VCO
VCO
, is
/4.
09576-031
Rev. 0 | Page 15 of 36
ADRF6801
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset
fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RAT I O
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)
CONTROL BIT S
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
0 0000000001
0 0000000010
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1000000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1111111111
MODULUS VALUE
1
2
...
...
1536 (DEFAULT)
...
...
2047
Figure 34. Modulus Divide Control Register (R1)
Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.
FRACTIONAL DI V I DE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000000000FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0C3(0)C2(1)C1(0)
FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0
0 0000000000
0 0000000001
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
0 1100000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
Figure 35. Fractional Divide Control Register (R2)
CONTRO L BITS
FRACTIONAL VAL UE
0
1
...
...
768 (DEFAUL T )
...
...
<MOD
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ- modulator dither control register is programmed as shown in Figure 36. The dither restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHER
MAGNITUDE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITHER
ENABLE
DITHER RESTART VALUE CONTROL BITS
09576-032
09576-033
DITH1 DITH0
00
01
10
11
DEN
DITHER ENABLE
0
DISABLE
1
ENABLE (DEFAULT, RECOMME NDED)
DITHER MAGNIT UDE
15 (DEFAULT)
7
3
1 (RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
00000000000000001
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
11111111111111111
Figure 36. Σ-Δ Modulator Dither Control Register (R3)
Rev. 0 | Page 16 of 36
DITHER R E START
VALUE
0x00001 (DEFAULT)
...
...
0x1FFFF
09576-034
ADRF6801
θ
Register 4—Charge Pump, PFD, and Reference Path Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
reference path control register is programmed as shown in
Figure 37.
The charge pump current is controlled by the base charge
pump current (I
current multiplier (I
) and the value of the charge pump
CP, BASE
).
CP, MULT
The base charge pump current can be set using an internal or
external resistor (according to Bit DB18 of Register 4). When
using an external resistor, the value of I
can be varied
CP, BASE
according to
×
I
SET
[]
=
⎢
250
⎣
R
4.217
⎡
⎤
,
BASECP
⎥
⎦
8.37
−
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, or 4) of the charge pump base current. The
multiplying value (I
) is equal to 1 plus the value of the
CP, MULT
DB11 and DB10 bits in Register 4.
The PFD phase offset multiplier (θ
), which is set by Bit
PFD, OFS
DB16 to Bit DB12 of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by
OFSPFD
,
5.22[deg]Φ
=
I
MULTCP
,
Finally, the phase offset can be either positive or negative
depending on the value of the DB17 bit in Register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×,
1×, 0.5×, or 0.25×. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The ADRF6801 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals. The
default mode provides a lock-detect output that allows users to
verify when the PLL has locked to the target frequency. In addition,
several other internal signals can be routed to the MUXOUT pin as
described in Figure 37.
Rev. 0 | Page 17 of 36
ADRF6801
PATH
CHARGE
PUMP
OUPUT MUX
SOURCE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)
INPUT REF
SOURCE
REF
PDF
PHASE
OFFSET
POLARITY
PFD PHASE OFFSET
MULTIPLIER VALUE
CHARGE
PUMP
CURRENT
MULTIPLIER
CP
CNTL
SRC
CHARGE
PUMP
CONTROL
PFD EDGE
SENSITIVITY
PFD ANTI-
BACKLASH
DELAY
CONTROL BITS
CPP1 CPP0
00
01
10
11
CPB4 CPB3 CPB2 CPB1 CPB0
00000
00001
... ... ... ... ...
00110
... ... ... ... ...
01010
... ... ... ... ...
11111
PE1
0
1
CPC1 CPC0
00
01
10
11
CPS
CHARGE PUMP CONT ROL SOURCE
0
CONTROL BASED ON STATE OF DB7/DB8 (CP CO NTROL)
1
CONTROL FROM PFD (DE FAULT)
CHARGE PUMP
CURRENT MULTIPLIER
1
2 (DEFAULT, RECOMMENDED)
3
4
CHARGE PUMP
CONTROL
BOTH ON
PUMP DOWN
PUMP UP
TRISTATE (DEFAULT)
PFD PHASE OFFSET MULTIPLIER
0 × 22.5°/ I
CP, MULT
1 × 22.5°/ I
CP, MULT
...
6 × 22.5°/ I
...
10 × 22.5°/I
...
31 × 22.5°/I
CP, MULT
CP, MULT
CP, MULT
(RECOMMENDED)
(DEFAULT)
PAB1 PAB0
00
01
10
11
REFERENCE PATH E DGE
PE0
SENSITIVITY
0
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
1
DIVIDER PATH EDG E
SENSITIVITY
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
PFD ANTIBACKLASH
DELAY
0ns (DEFAULT,
RECOMMENDED)
0.5ns
0.75ns
0.9ns
RMS2 RMS1 RMS0
000
001
010
011
100
101
110
111
PFD PHASE OFFSET POLARITY
CPBD
NEGATIVE
0
POSITIVE (DEFAULT, RECOMMENDED)
1
CHARGE PUMP CURRENT
CPM
REFERENCE SOURCE
INTERNAL (DEFAULT)
0
EXTERNAL
1
RS1 RS0
00
01
10
11
INPUT REFERE NCE
PATH SOURCE
2 × REFERENCE I NP UT
REFERENCE INPUT (DE F AULT)
0.5 × REFERENCE INPUT
0.25 × REFERENCE INPUT
OUTPUT MUX S OURCE
LOCK DETECT (DEFAULT)
VPTAT
BUFFERED VERSION OF REFERENCE INPUT
BUFFERED VERSION OF 0.5 × REFERENCE INPUT
BUFFERED VERSION OF 2 × REFERENCE INPUT
TRISTATE
BUFFERED VERSION OF 0.25 × F
RESERVED (DO NOT USE)
REF
Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)
Rev. 0 | Page 18 of 36
09576-035
ADRF6801
Register 5—LO Path and Demodulator Control
Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in
divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed in Figure 38.
LO
LO
OUTPUT
CONTROL BITS
DRIVER
CTRL
ENABLE
LO OUTPUT DRIVER
LDRV
ENABLE
DRIVER OFF ( DE FAULT)
0
DRIVER ON
1
LXL
LO IN/OUT CONTROL
LO OUTP UT ( DE FAULT)
0
1
LO INPUT
DIVIDE RATI O
÷ 1
÷ 2 (DEFAULT,
NECESSARY FOR V CO USE)
09576-036
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
00000000000 0
0 0 0 0 0 LDIV LXL LDRV C3(1) C2(0) C1(1)
Figure 38. LO Path and Demodulator Control Register (R5)
DEMOD
BIAS
ENABLE
DMBE
DMBE
0
1
LO
FIRST
IN/OUT
DIVIDER
DB6 DB5 DB4 DB3 DB2 DB1 DB0
LDIV
0
1
DEMOD BIAS ENABL E
DISABLE
ENABLE (DEFAULT)
Rev. 0 | Page 19 of 36
ADRF6801
Register 6—VCO Control and Enables
With R6[2:0] set to 110, the VCO control and enables register is
programmed as shown in Figure 39.
VCO band selection is normally selected based on BANDCAL
calibration; however, the VCO band can be selected directly using
Register 6. The VCO BS SRC determines whether the BANDCAL
calibration determines the optimum VCO tuning band or if the
external SPI interface is used to select the VCO tuning band
based on the value of the VCO band select.
The VCO amplitude can be controlled through Register 6. The
VCO amplitude setting can be controlled between 0 and 31
decimal, with a default value of 24.
The internal VCO can be disabled using Register 6. The internal
VCO LDO can be disabled if an external clean 3.0 V supply is
available.
The internal charge pump can be disabled through Register 6.
Normally, the charge pump is enabled.
CHARGE
PUMP
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB23
000
ENABLE
3.3V
VCO LDO
LDO
ENABLE
ENABLE
CPEN L 3EN VCO EN VCO SW VC5
LVEN
VCO
ENABLE
VCO
SWITCH
VCO SW
0
1
VCO SWITCH CONTROL FROM SPI
REGULAR (DEF AULT)
BAND CAL
VCO
VCO AMPLITUDE
VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
VC5 VC4 VC3 VC2 VC1
00000
... ... ... ... ...
00100
... ... ... ... ...
10111
... ... ... ... ...
11111
BS
CSR
VBS5 VBS4 VBS3 VBS2 VBS1
00000
... ... ... ... ...
10000
... ... ... ... ...
11111
VBSRC
VCO BAND CAL AND SW SOURCE CONTROL
0
BAND CAL (DEFAULT )
SPI
1
VCO BAND SELECT
VCO AMPLITUDE
VC0
0
0
...
...
8 (DEFAULT)
0
...
...
47
1
...
...
63 (RECOMMENDE D)
1
VBS0
0
...
0
...
1
CONTROL BI T S
VCO BAND SELECT
FROM SPI
0
...
32 (DEFAULT )
...
63
L3EN 3 .3V LDO ENABL E
0
1
CHARGE PUMP ENABLE
CPEN
DISABLE
0
ENABLE (DEFAUL T)
1
VCO EN
0
1
LVEN VCO LDO ENABLE
DISABLE
0
ENABLE (DEFAUL T)
1
DISABLE
ENABLE (DEFAULT)
VCO ENABLE
DISABLE
ENABLE (DEFAUL T)
09576-037
Figure 39. VCO Control and Enables (R6)
Rev. 0 | Page 20 of 36
ADRF6801
V
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The basic circuit connections for a typical ADRF6801 application
are shown in Figure 40.
SUPPLY CONNECTIONS
The ADRF6801 has several supply connections and on-board
regulated reference voltages that should be bypassed to ground
using low inductance bypass capacitors located in close proximity
to the supply and reference pins of the ADRF6801. Specifically
Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, Pin 29, Pin 34,
and Pin 40 should be bypassed to ground using individual bypass
capacitors. Pin 40 is the decoupling pin for the on-board VCO
LDO, and for best phase noise performance, several bypass
capacitors ranging from 100 pF to 10 µF may help to improve
phase noise performance. For additional details on bypassing the
supply nodes, see the evaluation board schematic in Figure 42.
CHARGE PUMP
LOO P FILTER
SYNTHESIZER CONNECTIONS
The ADRF6801 includes an on-board VCO and PLL for LO
synthesis. An external reference must be applied for the PLL to
operate. A 1 V p-p nominal external reference must be applied
to Pin 6 through an ac coupling capacitor. The reference is
compared to an internally divided version of the VCO output
frequency to create a charge pump error current to control and
lock the VCO. The charge pump output current is filtered and
converted to a control voltage through the external loop filter
that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™
can be a helpful tool when designing the external charge pump
loop filter. The typical Kv of the VCO, the charge pump output
current magnitude, and PFD frequency should all be considered
when designing the loop filter. The charge pump current magnitude
can be set internally or with an external RSET resistor connected to
Pin 5 and ground, along with the internal digital settings applied to
the PLL (see the Register 4—Charge Pump, PFD, and Reference
Path Control section for more details).
+5
+5V
EXTERNAL
REFERENCE
MONITOR
OUTPUT
+5V
OPEN
R2
SPI CONTROL
40 39 38 37 36 35 34 33 32 31
LOP
1
2
3
4
5
6
7
8
9
10
VCC1
DECL3
CPOUT
GND
RSET
REFIN
GND
MUXOUT
DECL2
VCC2
DECL1
VTUNE
GND
DATA
11
12 13 14 15 16 17 18 19 20
LON
CLK
LE
GND
LOSEL
ADRF6801
GND
GND
IF I-OUTPUT
BALUN
IBBN
IBBP
VCCLO
VCCLO
QBBP
+5V
GND
30
GND
29
VCCBB
GND
28
27
VCCRF
26
RFIN
GNDRF
25
24
GND
GND
23
VCCBB
22
21
GND
QBBN
GND
+5V
IF Q-OUTPUT
BALUN
IF I-OUTPUT
+5V
RF INPUT
+5V
IF Q-OUTPUT
09576-041
Figure 40. Basic Connections
Rev. 0 | Page 21 of 36
ADRF6801
I/Q OUTPUT CONNECTIONS
The ADRF6801 has I and Q baseband outputs. Each output
stage consists of emitter follower output transistors with a low
differential impedance of 24 Ω and can source up to 12 mA p-p
differentially. A Mini-Circuits TCM9-1+ balun is used to transform a single-ended 50 Ω load impedance into a nominal 450 Ω
differential impedance.
RF INPUT CONNECTIONS
The ADRF6801 is to be driven single-ended and can be either dc
coupled or ac coupled. There is an on-chip ground referenced
balun that converts the applied single-ended signal to a differential
signal that is then input to the RF V-to-I converter.
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6801 uses a loop filter to create the VTUNE voltage
for the internal VCO. The loop filter in its simplest form is an
integrating capacitor. It converts the current mode error signal
coming out of the CPOUT pin into a voltage to control the VCO
via the VTUNE voltage. The stock filter on the evaluation
board has a bandwidth of 130 kHz. The loop filter contains
seven components, four capacitors, and three resistors. Changing
the values of these components changes the bandwidth of the loop
filter. Note that to obtain the approximately 2.5 kHz loop bandwidth, the user can change the values of the following components
on the evaluation board to as follows: C14 = 0.1 µF, R10 = 68 Ω,
C15 = 4.7 µF, R9 = 270 Ω, C13 = 47 nF, R60 = 0 Ω, C4 = open.
LO SELECT INTERFACE
The ADRF6801 has the option of either monitoring a scaled
version of the internally generated LO (LOSEL pin driven high
at 3.3 V) or providing an external LO source (LOSEL pin driven
low to ground, the LDRV bit in Register 5 set low, and the LXL bit
in Register 5 set high). See the Pin Configuration and Function
Descriptions section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6801 provides the option to use an external signal
source for the LO into the IQ demodulating mixer core. It is
important to note that the applied LO signal is divided down
by either 2 or 4 depending on the LO path divider bit, LDIV, in
Register 5, prior to the actual IQ demodulating mixer core. The
divider is determined by the register settings in the LO path
and mixer control register (see the Register 5—LO Path and
Demodulator Control section). The LO input pins (Pin 37 and
Pin 38) present a broadband differential 50 Ω input impedance.
The LOP and LON input pins must be ac-coupled. This is achieved
on the evaluation board via a Mini-Circuits TC1-1-13+ balun with
a 1:1 impedance ratio. When not in use, the LOP and LON pins
can be left unconnected.
SETTING THE FREQUENCY OF THE PLL
The frequency of the VCO/PLL, once locked, is governed by the
values programmed into the PLL registers, as follows:
f
= f
PLL
× 2 × (INT + FRAC/MOD)
PFD
where:
f
is the frequency at the VCO when the loop is locked.
PLL
is the frequency at the input of the phase frequency detector.
f
PFD
INT is the integer divide ratio programmed into Register 0.
MOD is the modulus divide ratio programmed into Register 1.
FRAC is the fractional value programmed into Register 2.
The practical lower limit of the reference input frequency is
determined by the combination of the desired f
and the maximum
PLL
programmable integer divide ratio of 119 and reference input
frequency multiplier of 2. For a maximum f
> ~f
f
REF
/(119 × 2 × 2), or 9.7 MHz.
PLL
of 4600 MHz,
PLL
A lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with logic high signifying that the
loop is locked.
When the internal VCO is used, the actual LO frequency is
f
= f
/4
LO
PLL
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and
charge pump, it must be programmed once before programming
the PLL frequency (Register 0, Register 1, and Register 2).
The registers should be programmed starting with the highest
register (Register 7) first and then sequentially down to Register 0
last. When Register 0, Register 1, or Register 2 is programmed,
an internal VCO calibration is initiated that must execute when
the other registers are set. Therefore, the order must be Register 7,
Register 6, Register 5, Register 4, Register 3, Register 2, Register 1,
and then Register 0. Whenever Register 0, Register 1, or Register 2
is written to, it initializes the VCO calibration (even if the value
in these registers does not change). After the device has been
powered up and the registers configured for the desired mode of
operation, only Register 0, Register 1, or Register 2 must be
programmed to change the LO frequency.
If none of the register values is changing from their defaults,
there is no need to program them.
Rev. 0 | Page 22 of 36
ADRF6801
EVM MEASUREMENTS
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver has
all constellation points at their ideal locations; however, various
imperfections in the implementation (such as magnitude imbalance,
noise floor, and phase imbalance) cause the actual constellation
points to deviate from their ideal locations.
In general, a demodulator exhibits three distinct EVM limitations
vs. received input signal power. As signal power increases, the
distortion components increase. At large enough signal levels,
where the distortion components due to the harmonic nonlinearities in the device are falling in-band, EVM degrades
as signal levels increase. At medium signal levels, where the
demodulator behaves in a linear manner and the signal is well
above any notable noise contributions, the EVM has a tendency to
reach an optimal level determined dominantly by either quadrature
accuracy and I/Q gain match of the demodulator or the precision
of the test equipment. As signal levels decrease, such that the
noise is the major contribution, the EVM performance vs. the
signal level exhibits a decibel-for-decibel degradation with
decreasing signal level. At lower signal levels, where noise proves
to be the dominant limitation, the decibel EVM proves to be
directly proportional to the SNR.
The basic test setup to test EVM for the ADRF6801 consisted
of an Agilent E4438C, which was used as a signal source. The
900 MHz modulated signal was driven single ended into the
RFIN SMA connector of the ADRF6801 evaluation board. The
IQ baseband outputs were taken differentially into two AD8130
difference amplifiers to convert the differential signals into singleended signals. A Hewlett Packard 89410A VSA was used to sample
and calculate the EVM of the signal. The ADRF6801 IQ baseband output pins were presented with a 450 Ω differential load
impedance.
The ADRF6801 shows excellent EVM performance for 16 QAM.
Figure 41 shows the EVM of the ADRF6801 being better than
−40 dB over a RF input range of about +35 dB for the 16 QAM
modulated signal at a 10 MHz symbol rate. The pulse shaping
filter’s roll-off (alpha) was set to 0.35.
0
–5
–10
–15
–20
–25
EVM (dB)
–30
–35
–40
–45
–65 –55 –45 –35 –25 –15 –5 5 15
INPUT POWER (dBm)
Figure 41. EVM vs. Input Power, EVM Measurements at f
= 0 MHz (that is, Direct Down Conversion); 16 QAM; Symbol Rate = 10 MHz
f
IF
= 900 MHz;
RF
09576-042
Rev. 0 | Page 23 of 36
ADRF6801
EVALUATION BOARD LAYOUT AND THERMAL GROUNDING
An evaluation board is available for testing the ADRF6801. The
evaluation board schematic is shown in Figure 42. Ta b le 5 provides
the component values and suggestions for modifying the
component values for the various modes of operation.
3P3V_SENSE
VCC
VCC_SENSE
OSC_3P3V
OUTPU T_EN
LO_EXTERN
VCC4
1
3
5
7
3P3V1
VCC4
R7
0Ω
C9
100pF
0.1µF
R58
OPEN
LEGEND
NET NAME
TEST POINT
SMA INP UT/OUTPUT
2
4
6
J1
8
109
R38
CP
0Ω
R37
0Ω
C10
2P5V
REFIN
REFOUT
10µF
C11
0.1µF
R14
49.9Ω
2P5V_LDO
C3
VCC2
C31
1nF
R16
C17
0.1µF
GND
GND1
GND2
0Ω
3P3V_SENSE
2P5V_LDO
VCO_LDO
C14
22pF
R11
OPEN
R49
OPEN
R8
R18
0Ω
R17VCC
0Ω
C19
0.1µF
2.7nF
VCO_LDO
R15
0Ω
VCO_LDO
0Ω
VTUNE
R10
3kΩ
C15
C16
100pF
C12
100pF
C18
100pF
C2
10µF
OPEN
R2
0Ω
10kΩ
R1
OPEN
R
9
6.8pF
100pF
C33
P1
C13
LO_EXTERN
C1
VCC1
1
2
DECL3
3
CPOUT
4
5
6
REFIN
GND
7
8
MUXOUT
9
DECL2
10
VCC2
DATA
R30
0Ω
GND
RSET
R55
4
1nF
C6 C5
LOP
S1
R56
R33
10kΩ
0Ω
LO
5
2
T1
13
1nF
LON
GND
LOSEL
VCCLO
VCC
10kΩ
VTUNE
R59
OPEN
6
0
R
10kΩ
C4
22pF
R12
0Ω
40 39 38 37 36 35 34 33 32 31
DECL1
VTUNE
ADRF6801
VCCLO
LE
GND
DATA
11
12 13 14 15 16 17 18 19 20
R51
OPEN
CLK
C32
OPEN
12345
6789
GND
CLK
OPEN
R36
0Ω
GND
LE
C34
R52
OPEN
R57
0Ω
R50
OPEN
R35
0Ω
DIG_GND
VCC_LO
R6
0Ω
C8
100pFC70.1µF
GND
IBBP
IBBN
VCCBB
VCCRF
GNDRF
VCCBB
QBBN
QBBP
GND
R19
OPEN
C21
100pF
GND
GND
RFIN
GND
GND
GND
30
29
28
27
26
25
24
23
22
21
R20
0Ω
R24
0Ω
VCC_LO
R53
0Ω
C20
0.1µF
R34
OPEN
R45
0Ω
R46
0Ω
R47
0Ω
R48
0Ω
S2
VCC_LO
VCC_RF
R29 R32
OPEN
C26
100pF
C22 C23
100pF
OUTPU T_EN
R27
0Ω
R44
OPEN
R41
C24
100pF
C28
10µF
R26
0Ω
R28
0Ω
R25
0Ω
R54
10kΩ
OPEN
VCC_LO1
R4
0Ω
P2
R5
0Ω
C30
0.1µF
C27
0.1µF
VCC_BB1
0.1µF
R21
0Ω
P3
R22
0Ω
VCC_BB
VCC
VCC_RF
VCC_RF
C25
0.1µF
C29
0.1µF
VCC
0Ω
T2
2
VCC_BB
2
4513
T3
3
VCC_LO
VCC_BB
4
51
VCC4
R31
0Ω
R40
0Ω
RFIN
R43
0Ω
OPEN
OPEN
R39
OPEN
R23
OPEN
R42
R13
0Ω0Ω
VCC_SENSE
VCC
R3
IBBP
IOUT_S E
IBBN
QBBP
QOUT_SE
QBBN
09576-044
Figure 42. Evaluation Board Schematic
Rev. 0 | Page 24 of 36
ADRF6801
The package for the ADRF6801 features an exposed paddle on
the underside that should be well soldered to an exposed
opening in the solder mask on the evaluation board. Figure 43
illustrates the dimensions used in the layout of the ADRF6801
footprint on the ADRF6801 evaluation board (1 mil. = 0.0254 mm).
Note the use of nine via holes on the exposed paddle. These
ground vias should be connected to all other ground layers on
the evaluation board to maximize heat dissipation from the device
package. Under these conditions, the thermal impedance of the
ADRF6801 was measured to be approximately 30°C/W in still air.
0.012
0.050
0.025
0.020
Figure 43. Evaluation Board Layout Dimensions for the ADRF6801 Package
0.177
0.232
0.035
0.168
9576-046
Figure 44. ADRF6801 Evaluation Board Top Layer
09576-043
Figure 45. ADRF6801 Evaluation Board Bottom Layer
Table 5. Evaluation Board Configuration Options
Component Function Default Condition
VCC, VCC2, VCC4, VCO_LDO, VCC_LO,
VCC_LO1, VCC_RF, VCC_BB1, 3P3V1,
2P5V, CLK, DATA, LE, CP, DIG_GND,
GND, GND1, GND2
Power supply, ground and other test points.
Connect a 5 V supply to VCC.
VCC, VCC2, VCC4, VCC_LO, VCC_RF, VCC_BB1,
VCC_LO1, VCO_LDO, 3P3V1, 2P5V =
Components Corporation TP-104-01-02,
CP, LE, CLK, DATA =
Components Corporation TP-104-01-06,
GND, GND1, GND2, DIG_GND =
Components Corporation TP-104-01-00
R1, R6, R7, R8, R13, R15, R17, R18,
R24, R25, R26, R27, R29, R31, R32,
R36, R49
Power supply decoupling. Shorts or power supply
decoupling resistors.
R1, R6, R7, R8 = 0 Ω (0402),
R13, R15, R17 = 0 Ω (0402),
R18, R24, R25, R26, R27 = 0 Ω (0402),
R29, R31, R32 = 0 Ω (0402),
R36 = 0 Ω (0402),
R49 = open (0402)
Rev. 0 | Page 25 of 36
09576-047
ADRF6801
Component Function Default Condition
C1, C2, C3, C7, C8, C9, C10, C11, C12,
C16, C17, C18, C19, C20, C21, C22,
C23, C24, C25, C26, C27, C28
T1, C5, C6
R16, R14, R58, C31
R2, R9, R10, R11, R12, R37, R38, R59,
R60, C4, C14, C15, C13
R3, R4, R5, R21, R22, R23, R39, R40,
R41, R42, R43, R44, R45, R46, R47,
R48, C29, C30, T2, T3, P2, P3
R28
R30, R35, R50, R51, R52, R57, C32,
C33, C34, P1
R33, R55, R56, S1
The capacitors provide the required decoupling of
the supply-related pins.
External LO path. The T1 transformer provides
single-ended-to-differential conversion. C5 and C6
provide the necessary ac coupling.
REFIN input path. R14 provides a broadband 50 Ω
termination followed by C31, which provides the
ac coupling into REFIN. R16 provides an external
connectivity to the MUXOUT feature described in
Register 4. R58 provides option for connectivity to
the P1-6 line of a 9-pin D-sub connector for dc
measurements.
Loop filter component options. A variety of loop filter
topologies is supported using component
placements C4, C13, C14, C15, R9, R10, and R60. R38
and R59 provide connectivity options to numerous
test points for engineering evaluation purposes. R2
provides resistor programmability of the charge
pump current (see Register 4 description). R37
connects the charge pump output to the loop filter.
R12 references the loop filter to the VCO_LDO. Default
values on board provide a loop filter bandwidth of
roughly 130 kHz using a 26 MHz PFD frequency.
IF I/Q output paths. The T2 and T3 baluns provide a
9:1 impedance transformation; therefore, with a 50 Ω
load on the single-ended IOUT/QOUT side, the center
tap side of the balun presents a differential 450 Ω
to the ADRF6806. The center taps of the baluns are
ac grounded through C29 and C30. The baluns create
a differential-to-single-ended conversion for ease
of testing and use, but an option to have straight
differential outputs is achieved via populating R3,
R39, R23, and R42 with 0 Ω resistors and removing
R4, R5, R21, and R22. P2 and P3 are differential
measurement test points (not to be used as jumpers).
RF input interface. R28 provides the single-ended
RF input path to the on-chip RF input balun.
Serial port interface. A 9-pin D-sub connector (P1)
is provided for connecting to a host PC or control
hardware. Optional RC filters can be installed on
the CLK, DATA, and LE lines to filter the PC signals
through R50 to R52 and C32 to C34. CLK, DATA, and
LE signals can be observed via test points for debug
purposes. R58 provides a connection to the MUXOUT
for sensing lock detect through the P1 connector.
LO select interface. The LOSEL pin, in combination
with the LDRV and LXL bits in Register 5, controls
whether the LOP and LON pins operate as inputs or
outputs. A detailed description of how the LOSEL pin,
LDRV bit, and the LXL bit work together to control
the LOP and LON pins is found in Table 4 under the
LOSEL pin description. Using the S1 switch, the
user can pull LOSEL to a logic high (VCC/2) or a logic
low (ground). Resistors R55 and R56 form a resistor
divider to provide a logic high of VCC/2. LO select
can also be controlled through Pin 9 of J1. The 0 Ω
jumper, R33, must be installed to control LOSEL via J1.
Rev. 0 | Page 26 of 36
C1, C8, C10, C12 = 100 pF (0402),
C16, C18, C21, C22 = 100 pF (0402),
C24, C26 = 100 pF (0402),
C7, C9, C11 = 0.1 μF (0402),
C17, C19, C20, C23 = 0.1 μF (0402),
C25, C27 = 0.1 μF (0402),
C3, C2 = 10 μF (0603), C28 = 10 μF (3216)
C5, C6 = 1 nF (0603),
T1 = TC1-1-13+ Mini-Circuits
R14 = 49.9 Ω (0402),
R16 = 0 Ω (0402),
R58 = open (0402),
C31 = 1 nF (0603)
R12, R37, R38 = 0 Ω (0402),
R59 = open (0402),
R9, R60 = 10 kΩ (0402),
R10 = 3 kΩ (0402),
R2, R11 = open (0402),
C13 = 6.8 pF (0402),
C4, C14 = 22 pF (0402),
C15 = 2.7 nF (1206)
R4, R5, R21, R22, = 0 Ω (0402),
R40, R43, R45, R46 = 0 Ω (0402),
R47, R48 = 0 Ω (0402),
R3, R23, R39, R41, R42, R44 = open (0402),
C29, C30, = 0.1 μF (0402),
T2, T3 = TCM9-1+ Mini-Circuits,
P2, P3 = Samtec SSW-102-01-G-S
R28 = 0 Ω (0402)
R30, R35, R57 = 0 Ω (0402),
R50, R51, R52 = open (0402),
C32, C33, C34 = open (0402),
P1 = Tyco Electronics 5747840-3
R33 = 0 Ω (0402),
R55, R56 = 10 kΩ (0402),
S1 = Samtec TSW-103-08-G-S
ADRF6801
Component Function Default Condition
J1
R19, R20, R34, R53, R54, S2 Provides ground connection for Pin 16.
Engineering test points and external control. J1 is a
10-pin connector connected to various important
points on the evaluation board that the user can
measure or force voltages upon.
J1 = Molex Connector Corp. 10-89-7102
R20, R53 = 0 Ω (0402),
R34, R54 = open (0402),
R19 = open, S2 = open
Rev. 0 | Page 27 of 36
ADRF6801
ADRF6801 SOFTWARE
The ADRF6801 evaluation board can be controlled from PCs
using a USB adapter board, which is also available from Analog
Devices, Inc. The USB adapter evaluation documentation and
ordering information can be found on the EVAL-ADF4XXXZ-USB
product page. The basic user interfaces are shown in Figure 46 and
Figure 47.
The software allows the user to configure the ADRF6801 for
various modes of operation. The internal synthesizer is controlled
by clicking on any of the numeric values listed in RF Section.
Attempting to program Ref Input Frequency, PFD Frequency,
VCO Frequency (2×LO), LO Frequency, or other values in RF
Section launches the Synth Form window shown in Figure 47.
Usi ng Synth Form, the user can specify values for Local Oscillator
Frequency (MHz) and External Reference Frequency (MHz).
The user can also enable the LO output buffer and divider options
from this menu. After setting the desired values, it is important
to click Upload all registers for the new setting to take effect.
09576-048
Figure 46. Evaluation Board Software Main Window
Rev. 0 | Page 28 of 36
ADRF6801
09576-049
Figure 47. Evaluation Board Software Synth Form Window
Rev. 0 | Page 29 of 36
ADRF6801
CHARACTERIZATION SETUPS
Figure 48 to Figure 50 show the general characterization bench
setups used extensively for the ADRF6801. The setup shown in
Figure 48 was used to do the bulk of the testing. An automated
Agilent VEE program was used to control the equipment over the
IEEE bus. This setup was used to measure gain, input P1dB, output
P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature
accuracy, and supply current. The evaluation board was used to
perform the characterization with a Mini-Circuits TCM9-1+ balun
on each of the I and Q outputs. When using the TCM9-1+ balun
below 5 MHz (the specified 1 dB low frequency corner of the
balun), distortion performance degrades; however, this is not
the ADRF6801 degrading, merely the low frequency corner of
the balun introducing distortion effects. Through this balun,
the 9-to-1 impedance transformation effectively presented a 450 Ω
differential load at each of the I and Q channels. The losses of the
output baluns were de-embedded from all measurements.
To do phase noise and reference spur measurements, the setup
shown in Figure 50 was used. Phase noise was measured at the
baseband output (I or Q) at a baseband carrier frequency of
50 MHz. The baseband carrier of 50 MHz was chosen to allow
phase noise measurements to be taken at frequencies of up to
20 MHz offset from the carrier. The noise figure was measured
using the setup shown in Figure 49 at a baseband frequency
of 10 MHz.
Rev. 0 | Page 30 of 36
ADRF6801
IEEE
R&S SMA100
SIGNAL GE NE RATOR
IEEE
IEEE
IEEE
IEEE
R&S SMT03 SIGNAL GENERATOR
R&S SMT03 SIGNAL GENERATOR
IEEE
AGILENT MXA
SPECTRUM ANALYZER
IEEE
IEEE
(FOR I
AGILENT E3631A
POWER SUPPLY
AGILENT DM M
MEAS.)
SUPPLY
RF1
AGILENT 11636A
POWER DIVIDER
(USED AS COMBINER)
RF2
HP 8508A
VECTOR
VOLTMETER
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
IEEE
IEEE
3dB
3dB
3dB
CH A
CH B
10-PIN
CONNECTION
(+5V V
DC MEASURE)
9-PIN D-SUB CONNECTION
(VCO AND PLL P ROGRAMMING)
POS
,
MINI-CIRCUITS
ZHL-42W AMPLIFIER
(SUPPLIED WITH +15V dc
FOR OPERAT ION)
3dB
RF
RF SWITCH MATRIX
I CH
6dB 3dB
RF
ADRF6801
EVALUATIO N BOARD
6dB
REF
REF
Q CH
6dB
IEEE
IEEE
09576-050
Figure 48. General Characterization Setup
Rev. 0 | Page 31 of 36
ADRF6801
IEEE
AGILENT 8665B
LOW NOISE SYN
SIGNAL G ENERATOR
REF
RF1
IEEE
IEEE
E
IEEE
AGILENT E3631A
POWER SUPPLY
AGILENT 346B
NOISE SOURCE
AGILENT N8974A
NOISE FI GURE ANALYZER
AGILENT DM M
(FOR I
SUPPLY
MEAS.)
10MHz
LOW-PASS FILTER
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
IEEE
I CH
6dB 3dB 6dB
10-PIN
CONNECTION
DC MEASURE )
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING )
(+5V V
POS
1,
3dB
RF
RF SWIT CH M ATRIX
RF
ADRF6801
EVALUATION BOARD
6dB
REF
Q CH
IEEE
Figure 49. Noise Figure Characterization Setup
Rev. 0 | Page 32 of 36
IEEE
09576-051
ADRF6801
IEEE
R&S SMA100
SIGNAL GENERATOR
IEEE
IEEE
IEEE
IEEE
AGILENT E5052 SIGNAL SOURCE
E
IEEE
AGILENT E3631A
POWER SUPPLY
IEEE
IE
R&S SMA100
SIGNAL GENERATOR
ANALYZER
AGILENT MXA
SPECTRUM ANALYZ ER
AGILENT DM M
(FOR I
SUPPLY
MEAS.)
100MHz
LOW-PASS FILTER
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
IEEE
(VCO AND PLL PROGRAMMING )
RF1
10-PIN
CONNECTION
DC MEASURE )
9-PIN D-SUB CONNECTION
(+5V V
POS
1,
3dB
RF
RF SWIT CH M ATRIX
I CH
6dB 3dB 6dB
RF
ADRF6801
EVALUATION BOARD
6dB
REF
Q CH
REF
IEEE
IEEE
IEEE
09576-052
Figure 50. Phase Noise Characterization Setup
Rev. 0 | Page 33 of 36
ADRF6801
OUTLINE DIMENSIONS
PIN 1
INDICATOR
1.00
0.85
0.80
12° MAX
SEATING
PLANE
6.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
5.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.60 MAX
0.50
BSC
0.50
0.40
0.30
0.08
0.60 MAX
31
30
EXPOSED
(BOT TOM VIEW)
21
20
40
1
PAD
10
11
4.50
REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER T O
THE PIN CONFIGURATIO N AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
INDICATOR
4.25
4.10 SQ
3.95
0.25 MIN
072108-A
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Ordering
Model1 Temperature Range Package Description Package Option
ADRF6801ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 750
ADRF6801-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.
Quantity
Rev. 0 | Page 34 of 36
ADRF6801
NOTES
Rev. 0 | Page 35 of 36
ADRF6801
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09576-0-1/11(0)
Rev. 0 | Page 36 of 36
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