Datasheet ADRF6602 Datasheet (ANALOG DEVICES)

1550 MHz to 2150 MHz Rx Mixer with

V

Integrated Fractional-N PLL and VCO

FEATURES

Rx mixer with integrated fractional-N PLL RF input frequency range: 1000 MHz to 3100 MHz Internal LO frequency range: 1550 MHz to 2150 MHz Input P1dB: 14.8 dBm Input IP3: 30 dBm IIP3 optimization via external pin SSB noise figure

IP3SET pin open: 13.8 dB

IP3SET pin at 3.3 V: 15 dB Voltage conversion gain: 6.5 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Cellular base stations

GENERAL DESCRIPTION

The ADRF6602 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a f can be divided or multiplied and then applied to the PLL phase frequency detector (PFD).

LODRV_EN

input to the mixer. The reference input

LO

CC1

36

LON

37

38

LOP

16

PLL_EN

DATA

CLK

REF_IN

MUXOUT

12 13 14

LE

6

8

SPI

INTERFACE

×2

MUX

÷2 ÷4

FRACTION

TEMP

SENSOR

7 11 15 20 21 23 24 25 28 30 31 35

FUNCTIONAL BLOCK DIAGRAM

CC2VCC_LOVCC_MIXVCC_V2IVCC_LO

MODULUS

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

– +

N COUNTER

PHASE

FREQUENCY

DETECTOR

GND

INTEGER

REG

21 TO 123

Figure 1.

ADRF6602

The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter.

The loop filter output is then applied to an integrated VCO. The VCO output at 2× f programmable PLL divider. The programmable PLL divider is controlled by a Σ- modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047.

The active mixer converts the single-ended 50  RF input to a 200 Ω differential IF output. The IF output can operate up to 500 MHz.

The ADRF6602 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range.

Table 1.

Internal LO

Part No.

Range

ADRF6601 750 MHz 300 MHz 450 MHz

1160 MHz 2500 MHz 1600 MHz

ADRF6602 1550 MHz 1000 MHz 1350 MHz

2150 MHz 3100 MHz 2750 MHz

ADRF6603 2100 MHz 1100 MHz 1450 MHz

2600 MHz 3200 MHz 2850 MHz

ADRF6604 2500 MHz 1200 MHz 1600 MHz

2900 MHz 3600 MHz 3200 MHz

2717101 22

34

BUFFER

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA (DEFAUL T ) ,

750µA, 1000µA

54

R

SET

is applied to an LO divider, as well as to a

LO

±3 dB RF Balun Range

ADRF6602

INTERNAL L O RANGE 1550MHz TO 2150MHz

DIV

2:1

BY

MUX

2, 1

VCO

CORE

3

CP VTUNE

IFP

191839

IFN

NC

32 33

NC

3.3V LDO

2.5V LDO

VCO LDO

IN

2

9

40

26

29

±1 dB RFIN Balun Range

DECL3P3

DECL2P5

DECLVCO

RF

IN

IP3SET

08545-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADRF6602

REVISION HISTORY

9/10—Rev. B to Rev. C

Changes to Features Section............................................................ 1

Changes to Table 2 ............................................................................ 3

Changes to Table 3 and Table 4 ....................................................... 4

Changes to Table 6 ............................................................................ 6

Changes to Typical Performance Characteristics Section ........... 9

Added Spurious Performance Section ......................................... 15

Changes to Programming the ADRF6602 Section .................... 20

Added AC Test Fixture Section and Figure 47 ........................... 23

Changes to Evaluation Board Control Software Section ........... 24

7/10—Rev. A to Rev. B

Changes to Table 1 ............................................................................ 1

Changes to Table 6 ............................................................................ 6

Changes to Figure 20 ...................................................................... 14

Changes to Figure 21 ...................................................................... 17

Changes to Figure 22 ...................................................................... 18

Changes to Figure 23 ...................................................................... 19

Rev. C | Page 2 of 32

4/10—Rev. 0 to Rev. A

Added Table 1 .................................................................................... 1

Changes to Figure 1 ........................................................................... 1

Change to Synthesizer/PLL Specifications Section ....................... 4

Change to Table 3 .............................................................................. 4

Changes to Initializing Sequence Section ................................... 15

Changes to Figure 16 ...................................................................... 12

Changes to Figure 17 ...................................................................... 13

Changes to Figure 19 ...................................................................... 14

Changes to Figure 21 ...................................................................... 17

Changes to Figure 24 ...................................................................... 20

1/10—Revision 0: Initial Version

ADRF6602

SPECIFICATIONS

RF SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; f using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

INTERNAL LO FREQUENCY RANGE 1550 2150 MHz RF INPUT FREQUENCY RANGE ±3 dB RF input range 1000 3100 MHz RF INPUT AT 1410 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −9 dB

Input P1dB 15.5 dBm

Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 54.0 dBm

Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 33.5 dBm

Single-Side Band Noise Figure IP3SET = 3.3 V 15.2 dB

IP3SET = open 14.1 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −45 dBm

RF INPUT AT 1760 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −15 dB

Input P1dB 15 dBm

Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 53.5 dBm

Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 30.8 dBm

Single-Side Band Noise Figure IP3SET = 3.3 V 14.9 dB

IP3SET = open 13.5 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −43 dBm

RF INPUT AT 2010 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) <(−20) dB

Input P1dB 14.8 dBm

Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 60 dBm

Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 29.5 dBm

Single-Side Band Noise Figure IP3SET = 3.3 V 15.8 dB

IP3SET = open 14.9 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −45 dBm

IF OUTPUT

Voltage Conversion Gain Differential 200 Ω load 6.5 dB

IF Bandwidth Small signal 3 dB bandwidth 500 MHz

Output Common-Mode Voltage External pull-up balun or inductors required 5 V

Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/0.5 dB

Gain Variation Over full temperature range 1.2 dB

Output Swing Differential 200 Ω load 2 V p-p

Differential Output Return Loss Measured through 4:1 balun −12 dB

LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, internal PLL disabled

Frequency Range 250 6000 MHz

Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −7 dBm

Input Level (LO as Input) −6 0 +6 dBm

Input Impedance 50 Ω

= 153.6 MHz; f

REF

= 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized

PFD

Rev. C | Page 3 of 32

ADRF6602

SYNTHESIZER/PLL SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; f

= 140 MHz; IIP3 optimized using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted.

f

IF

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO

Frequency Range Internally generated LO 1550 2150 MHz Figure of Merit1 P

Reference Spurs f f f

PFD

>f PHASE NOISE fLO = 1550 MHz to 2150 MHz, f

1 kHz to 10 kHz offset −92 dBc/Hz

100 kHz offset −103 dBc/Hz

500 kHz offset −122 dBc/Hz

1 MHz offset −128 dBc/Hz

5 MHz offset −140 dBc/Hz

10 MHz offset −147 dBc/Hz

20 MHz offset −150 dBc/Hz

Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.3

PFD Frequency 20 40 MHz REFERENCE CHARACTERISTICS REF_IN, MUXOUT pins

REF_IN Input Frequency 12 160 MHz

REF_IN Input Capacitance 4 pF

MUXOUT Output Level VOL (lock detect output selected) 0.25 V

V

MUXOUT Duty Cycle 50 % CHARGE PUMP

Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1 mA 500 μA

Output Compliance Range 1 2.8 V

1

The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10Log10(f

power = 10 dBm (500 V/μs slew rate) with a 40 MHz f

f

REF

LOGIC INPUT AND POWER SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; f using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted.

= 153.6 MHz; f

REF

= 0 dBm −220.5 dBc/Hz

REF_IN

power = 4 dBm; f

REF

= 38.4 MHz; high-side LO injection;

PFD

= 38.4 MHz /4 −105 dBc

−80 dBc

PFD

= 38.4 MHz

PFD

°rms

(lock detect output selected) 2.7 V

OH

) – 20Log10(fLO/f

. The FOM was computed at 50 kHz offset.

PFD

= 153.6 MHz; f

REF

PFD

= 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized

PFD

). The FOM was measured across the full LO range, with f

PFD

= 80 MHz,

REF

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

LOGIC INPUTS CLK, DATA, LE

Input High Voltage, V

Input Low Voltage, V

Input Current, I

1.4 3.3 V

INH

0 0.7 V

INL

0.1 μA

INH/IINL

Input Capacitance, CIN 5 pF POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range 4.75 5 5.25 V

Supply Current PLL only 97 mA External LO mode (internal PLL disabled, LO output buffer off, IP3SET pin = 3.3 V) 168 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 277 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 263 mA Power-down mode 30 mA

Rev. C | Page 4 of 32

ADRF6602

TIMING CHARACTERISTICS

VCC2 = 5 V ± 5%.

Table 5.

Parameter Limit Unit Description

t1 20 ns min LE setup time t2 10 ns min DATA-to-CLK setup time t3 10 ns min DATA-to-CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK-to-LE setup time t7 20 ns min LE pulse width

Timing Diagram

CLK

t

4

t

5

DATA

DB23 (MSB) DB22

t

1

LE

t

2

t

3

DB2 DB1

(CONTROL BIT C2)(CONTROLBIT C3)

DB0 (LSB)

(CONTROLBIT C1)

t

6

t

7

08545-002

Figure 2. Timing Diagram

Rev. C | Page 5 of 32

ADRF6602

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Supply Voltage, VCC1, VCC2, VCC_LO,

VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE −0.3 V to +3.6 V IFP, IFN −0.3 V to VCC_V2I + 0.3 V RFIN 16 dBm LOP, LON 13 dBm θJA (Exposed Paddle Soldered Down) 35°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

−0.5 V to +5.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. C | Page 6 of 32

ADRF6602

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRV_EN

ND

CC_LO

NC

V

G

LO

LON

LOP

VTUNE

DECLVCO

37

38

39

40

PIN 1

1VCC1

INDICATOR

2DECL3P3

3CP

GND

4

R

5

SET

REF_IN

6 7

GND

8

MUXOUT

VCC2

9

10

DECL2P5

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE SHOULD BE SOLDEREDTO A LOW I M P EDANCE GROUND PLANE.

ADRF6602

TOP VIEW

(Not to S cale)

11

12

13

14 LE

CLK

GND

DATA

Figure 3. Pin Configuration

GND

NC 32

31

33

34

35

36

30 GND 29 IP3SET 28 GND 27 VCC_V2I

RF

26

IN

25

GND 24 GND 23 GND 22 VCC_MIX 21

GND

15

17

16

18

19

20

IFP

IFN

GND

PLL_EN

VCC_LO

08545-003

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC1

Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 2 DECL3P3 Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 3 CP Charge Pump Output Pin. Connect to VTUNE through loop filter. 4, 7, 11, 15, 20,

GND Ground. Connect these pins to a low impedance ground plane. 21, 23, 24, 25, 28, 30, 31, 35

5 R

SET

Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external R

is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I

SET

can be externally adjusted according to the following equation:

×

I

4.217

⎛ ⎜

=

R

SET

⎜

I

NOMINAL

⎝

⎞

CP

⎟ ⎟ ⎠

37.8

−

6 REF_IN Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. 8 MUXOUT

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect

signal. The output is selected by programming the appropriate register. 9 DECL2P5 Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 10 VCC2

Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. 13 CLK

Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE

Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the

eight registers. The relevant latch is selected by the three control bits of the 24-bit word. 16 PLL_EN

PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is

automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the

internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be

used to switch modes. 17, 34 VCC_LO

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes.

NOMINAL

)

Rev. C | Page 7 of 32

ADRF6602

Pin No. Mnemonic Description

22 VCC_MIX

26 RFIN RF Input (Single-Ended, 50 Ω). 27 VCC_V2I

29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. 32, 33 NC No Connection. 36 LODRV_EN

37, 38 LON, LOP

39 VTUNE

40 DECLVCO Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.

LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. External LO drive frequency must be 1× LO. This pin should not be left floating.

Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins.

VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.5 V to 2.5 V.

Rev. C | Page 8 of 32

ADRF6602

TYPICAL PERFORMANCE CHARACTERISTICS

RF FREQUENCY SWEEP

CDAC = 0x0, internally generated high-side LO, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted.

5

IP3SET = OPEN IP3SET = 3.3V

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

1410 1510 1610 1710 1810 1910 2010

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 4. Gain vs. RF Frequency

90

IP3SET = OPEN IP3SET = 3.3V

80

70

60

INPUT IP2 (dBm)

50

40

30

1410 1510 1610 1710 1810 1910 2010

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 5. Input IP2 vs. RF Frequency

20

IP3SET = OPEN

19

IP3SET = 3.3V

18 17 16 15 14 13 12 11 10

9 8 7

NOISE FIGURE (dB)

6 5 4 3 2 1 0 1410 1510 1610 1710 1810 1910 2010

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 6. Noise Figure vs. RF Frequency

08545-104

08545-105

08545-106

45

IP3SET = OPEN IP3SET = 3.3V

40

35

30

INPUT IP3 (dBm)

25

20

1410 1510 1610 1710 1810 1910 2010

RF FREQUENCY ( MHz)

Figure 7. Input IP3 vs. RF Frequency

20

IP3SET = OPEN IP3SET = 3.3V

19

18

17

16

15

14

INPUT P1dB (dBm)

13

12

11

10

1410 1510 1610 1710 1810 1910 2010

RF FREQUENCY ( MHz)

Figure 8. Input P1dB vs. RF Frequency

TA = +85°C TA = +25°C TA = –40°C

08545-107

08545-108

Rev. C | Page 9 of 32

ADRF6602

IF FREQUENCY SWEEP

CDAC = 0x0, internally generated swept low-side LO, fRF = 1960 MHz, RFIN = −5 dBm, unless otherwise noted.

5

IP3SET = OPEN IP3SET = 3.3V

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

25 4003753503253002752502252001751501257550 100

IF FREQ UENCY ( MHz)

Figure 9. Gain vs. IF Frequency

90

IP3SET = OPEN IP3SET = 3.3V

80

70

60

INPUT IP2 (dBm)

50

40

30

25 4003753503253002752502252001751501257550 100

IF FREQ UENCY ( MHz)

Figure 10. Input IP2 vs. IF Frequency, RFIN = −5 dBm

20

IP3SET = OPEN IP3SET = 3.3V

18

16

14

12

10

8

NOISE FIGURE (dB)

6

4

2

0

25 4003753503253002752502252001751501257550 100

IF FREQ UENCY ( MHz)

Figure 11. Noise Figure vs. IF Frequency

TA = +85°C TA = +25°C TA = –40°C

08545-110

08545-111

08545-112

45

IP3SET = OPEN IP3SET = 3.3V

40

35

30

25

20

INPUT IP3 (dBm)

15

10

5

25 4003753503253002752502252001751501257550 100

IF FREQ UENCY ( MHz)

Figure 12. Input IP3 vs. IF Frequency, RFIN = −5 dBm

20

IP3SET = OPEN IP3SET = 3.3V

18

16

14

12

10

8

INPUT P1dB (dBm)

6

4

2

0

25 4003753503253002752502252001751501257550 100

IF FREQ UENCY ( MHz)

Figure 13. Input P1dB vs. IF Frequency

TA = +85°C TA = +25°C TA = –40°C

08545-113

08545-114

Rev. C | Page 10 of 32

ADRF6602

–

0

IP3SET = OPEN

–5

IP3SET = 3.3V –10 –15 –20 –25 –30 –35 –40 –45

LO-TO - IF FEEDT HROUGH (dBm)

–50 –55 –60

1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

TA = +85°C TA = +25°C TA = –40°C

Figure 14. LO-to-IF Feedthrough vs. LO Frequency,

LO Output Turned Off, CDAC = 0x0

30

IP3SET = OPEN

IP3SET = 3.3V –40

–50

–60

–70

LO-TO-RF LEAKAGE ( dBm)

–80

TA = +85°C TA = +25°C TA = –40°C

08545-115

0

–2

–4

–6

–8

–10

–12

RETURN LOSS (d B)

–14

–16

–18

–20

1400 230022002100200019001800170016001500

LO FREQUENCY (MHz )

08545-117

Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)

350

300

250

200

150

RESISTANCE (Ω)

100

50

RESISTANCE

CAPACITANCE

3.5

3.0

2.5

2.0

1.5

1.0

0.5

CAPACITANCE (pF)

–90

1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off

0

–10

–20

–30

–40

–50

RETURN LOSS (d B)

–60

–70

–80

1400 230022002100200019001800170016001500

RF FREQUENCY ( MHz)

Figure 16. RF Input Return Loss vs. RF Frequency

0

50 500450400350300250200150100

08545-109

IF FREQUENCY (MHz )

0

08545-118

Figure 18. IF Differential Output Impedance (R Parallel C Equivalent)

35

IP3SET = OPEN IP3SET = 3.3V

30

25

20

NOISE FIGURE (dB)

15

10

–60 0–10–20–30–40–50

08545-116

CW BLOCKER LE V E L (dBm)

08545-200

Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level,

LO Frequency = 2105 MHz, RF Frequency = 1965 MHz

Rev. C | Page 11 of 32

ADRF6602

0

IP3SET = OPEN

–5

IP3SET = 3.3V –10 –15 –20 –25 –30 –35 –40 –45

RF-TO-IF ISOLATION (dBc)

–50 –55 –60

1300 1500 1700 1900 2100 2300

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

08545-119

Figure 20. RF-to-IF Leakage vs. RF Frequency, High-Side LO, IF = 140 MHz,

LO Output Turned Off

0

IP3SET = OPEN

IP3SET = 3.3V

–1

–2

–3

–4

–5

–6

–7

–8

LO OUTP UT AMPLIT UDE ( dBm)

–9

–10

1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

TA = +85°C TA = +25°C TA = –40°C

08545-120

Figure 21. LO Output Amplitude vs. LO Frequency

20

15

10

5

0

–5

–10

–15

FREQUENCY DEVIATION FROM 1960MHz ( M Hz )

–20

0 25020015010050

TIME (ns)

08545-222

Figure 22. Frequency Deviation from LO Frequency at

LO = 1.97 GHz to 1.96 GHz vs. Lock Time

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VTUNE VOLTAGE (V)

1.5

1.0

0.5

0 1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

TA = +85°C TA = +25°C TA = –40°C

Figure 23. VTUNE vs. LO Frequency

350

300

250

200

SUPPLY CURRENT ( mA)

150

100

IP3SET = OPEN IP3SET = 3.3V

1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

TA = +85°C TA = +25°C TA = –40°C

Figure 24. Supply Current vs. LO Frequency

2.0

1.9

1.8

1.7

1.6

1.5

1.4

VPTAT VOLTAGE (V)

1.3

1.2

1.1

1.0

IP3SET = OPEN IP3SET = 3.3V

–55 –35 –15 5 25 45 65 85 105

TEMPERATURE ( °C)

Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open)

08545-122

08545-123

08545-124

Rev. C | Page 12 of 32

ADRF6602

Complementary cumulative distribution function (CCDF), fRF = 1960 MHz, fIF = 140 MHz.

100

DISTRIBUTION PERCENTAG E (%)

IP3SET = OPEN IP3SET = 3.3V

90

80

70

60

50

40

30

20

10

0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

GAIN (dB)

Figure 26. Gain

100

DISTRIBUTION PERCENTAG E (%)

IP3SET = OPEN IP3SET = 3.3V

90

80

70

60

50

40

30

20

10

0

40 45 50 55 60 65 70 75 80

INPUT IP2 (dBm)

Figure 27. Input IP2

100

IP3SET = OPEN

90

80

70

60

50

40

30

20

DISTRIBUTION PERCENTAG E (%)

10

0

11 12 13 14 15 16 17 18

NOISE FI GURE (dB)

Figure 28. Noise Figure

TA = +85°C TA = +25°C TA = –40°C

08545-125

08545-126

08545-127

100

DISTRIBUTION PERCENTAG E (%)

IP3SET = OPEN IP3SET = 3.3V

90

80

70

60

50

40

30

20

10

0

20 22 24 26 28 30 32 34 36

INPUT IP3 (dBm)

Figure 29. Input IP3

100

DISTRIBUTION PERCENTAG E (%)

IP3SET = OPEN IP3SET = 3.3V

90

80

70

60

50

40

30

20

10

0

9 10111213141516 1817

INPUT P1dB (dBm)

Figure 30. Input P1dB

100

DISTRIBUTION PERCENTAG E (%)

IP3SET = OPEN IP3SET = 3.3V

90

80

70

60

50

40

30

20

10

0

–55 –53 –51 –49 –47 –45 –43 –41 –39 –37 –35

LO FEEDTHROUGH (dBm)

Figure 31. LO Feedthrough to IF, LO Output Turned Off

TA = +85°C TA = +25°C TA = –40°C

08545-128

08545-129

08545-130

Rev. C | Page 13 of 32

ADRF6602

–

Measured at IF output, CDAC = 0x0, IP3SET = open, internally generated high-side LO, f RF

= −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.

IN

80

LO FREQUENCY = 2134.4MHz

–90

–100

–110

–120

LO FREQUENCY = 1558.4MHz

–130

PHASE NOISE (d Bc/Hz)

–140

–150

–160

1k 10k 100k 1M 10M 100M

OFFSET FREQUENCY (Hz)

Figure 32. Phase Noise vs. Offset Frequency

75

2× PFD FREQUENCY

4× PFD FREQUENCY

SPURRS LEVEL (dBc)

–80

–85

–90

–95

–100

–105

TA = +85°C TA = +25°C TA = –40°C

08545-131

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

INTEGRATE D P HAS E NOISE (°rms)

0.1

0 1550 1650 1750 1850 1950 2050 2150

80

–90

–100

–110

–120

–130

PHASE NOISE (d Bc/Hz)

–140

–150

= 153.6 MHz, f

REF

LO FREQUENCY (MHz )

= 38.4 MHz,

PFD

TA = +85°C TA = +25°C TA = –40°C

Figure 35. Integrated Phase Noise vs. LO Frequency

TA = +85°C TA = +25°C TA = –40°C

OFFSET = 1kHz

OFFSE T = 100kHz

OFFSET = 5MHz

08545-133

–110

1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)

75

3× PFD FREQUENCY

1× PFD FREQUENCY

1550 1650 1750 1850 1950 2050 2150

LO FREQUENCY (MHz )

SPURRS LEVEL (dBc)

–80

–85

–90

–95

–100

–105

–110

TA = +85°C TA = +25°C TA = –40°C

0.25× PF D FREQUENCY

Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)

–160

1550 1650 1750 1850 1950 2050 2150

08545-132

LO FREQUENCY (MHz )

08545-134

Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)

80

–90

–100

–110

–120

–130

PHASE NOISE (d Bc/Hz)

–140

–150

–160

1550 1650 1750 1850 1950 2050 2150

08545-232

OFFSE T = 10kHz

OFFSET = 1MHz

LO FREQUENCY (MHz )

TA = +85°C TA = +25°C TA = –40°C

08545-135

Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)

Rev. C | Page 14 of 32

ADRF6602

SPURIOUS PERFORMANCE

(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than −125 dBc are shown.

LO = 1550 MHz, RF = 1410 MHz (horizontal axis is m, vertical axis is n), and RF

0 1 2

N

3 4 5 6 7

0 1 2 3 4

−95.78 −36.11 −38.06 −43.03

−27.96 0.00 −75.14 −44.01 −81.04

−80.82 −84.22 −70.69 −83.52 −90.50

−105.61 −93.37 −112.15 −84.67 −121.89

−120.72 −121.95 −123.15 −120.95 −123.77

−122.11 −122.03 −122.97 −123.53

−122.02 −121.46 −122.62

−122.03 −121.44

M

LO = 1900 MHz, RF = 1760 MHz (horizontal axis is m, vertical axis is n), and RF

0 1 2 −69.90 −80.06 −71.05 −86.55 −95.26

N

3 −105.85 −107.79 −104.24 −78.66 −121.43 4 5 6 7

0 1 2 3 4

−96.17 −35.62 −23.14 −51.42

−23.66 0.00 −63.13 −40.94 −68.37

−122.72 −121.39 −122.69 −124.20

M

−122.78 −122.48 −117.55

LO = 2150 MHz, RF = 2010 MHz (horizontal axis is m, vertical axis is n), and RF

0 1 2 −76.22 −77.24 −75.74 −80.30 −87.09

N

3 4 5 6 7

0 1 2 3 4

−94.96 −36.89 −22.24 +9.56 +9.56

−21.91 0.00 −69.83 −31.34 +9.56

−97.36 −101.06 −76.16 −121.60

−122.66 −122.37 −120.59 −125.16

M

−122.76 −121.11 −124.51

power = −10 dBm.

IN

power = −10 dBm.

IN

−122.39 −123.67

power = −10 dBm.

IN

−122.63 −122.41

−119.57

−122.93

Rev. C | Page 15 of 32

ADRF6602

REGISTER STRUCTURE

This section provides the register maps for the ADRF6602. The three LSBs determine the register that is programmed.

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000000000000DMID6ID5ID4ID3ID2ID1ID0C3(0)C2(0)C1(0)

DIVIDE

MODE

DIVIDE MODE

DM

FRACTIONAL ( DEFAULT)

0

INTEGER

1

ID6 ID5 ID4 ID3 ID2 ID1 ID0 0010101 0010110 0010111 0011000

... ... ... ... ... ... ...

0111000

... ... ... ... ... ... ...

1110111 1111000 1111001 1111010 1111011

INTEGER DI VIDE RATIO CONTRO L BITS

INTEGER DI VIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 (DEFAULT ) ... ... 119 120 (INTEG E R MODE ONLY ) 121 (INTEG E R MODE ONLY ) 122 (INTEG E R MODE ONLY ) 123 (INTEG E R MODE ONLY )

Figure 38. Register 0—Integer Divide Control Register Map

08545-004

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RESERVED

0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 0 0000000001 0 0000000010

... ... ... ... ... ... ... ... ... ... ...

1 1000000000

... ... ... ... ... ... ... ... ... ... ...

1 1111111111

Figure 39. Register 1—Modulus Divide Control Register Map

Rev. C | Page 16 of 32

MODULUS VALUE

CONTROL BITS

MODULUS VALUE 1 2 ... ... 1536 (DEFAULT ) ... ... 2047

08545-005

ADRF6602

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FRACTIONAL V ALUERESERVED

0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)

CONTROL BITS

FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 0 0000000000 0 0000000001

... ... ... ... ... ... ... ... ... ... ...

0 1100000000

... ... ... ... ... ... ... ... ... ... ...

FRACTIONAL VALUE MUST BE LESS THAN MO DUL US

Figure 40. Register 2—Fractional Divide Control Register Map

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

DITHER

ENABLE

DEN

DITHER ENABLE

0

DISABLE

1

ENABLE (DEFAUL T, RECOMME NDED)

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 00000000000000001

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

11111111111111111

DITHER RESTART VALUE CONTROL BITS

Figure 41. Register 3—Σ-Δ Modulator Dither Control Register Map

DITH1 DITH0 00 01

10 11

DITHER

MAGNITUDE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DITHER MAGNI TUDE 15 (DEFAULT) 7

3 1 (RECOMME NDED)

FRACTIONAL VALUE 0 1 ... ... 768 (DEFAULT ) ... ... <MDR

DITHER RESTART VALUE

0x00001 (DEFAULT) ... ... 0x1FFFF

08545-006

08545-007

Rev. C | Page 17 of 32

ADRF6602

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

REF OUTPUT MUX SELECT

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

INPUT REF

PATH

CP

CURRENT

REF

SOURCE

PFD POL

PFD PHASE OF FSET

MULTIPLIER

CP

CURRENT

CP

SRC

CP

CONTROL

PFD EDGE CONTROL BITS

PFD ANTI

BACKLASH

DELAY

CPB4 CPB3 CPB2 CPB1 CPB0 00000

00001 00110 01010 10000 11111

CPC1 CPC0 00

01 10 11

CHARGE PUMP CONTRO L SO URCE

CPS

CONTROL BASED ON STATE OF DB7/DB8 (CP CO NTROL)

0

CONTROL F ROM PFD (DEF AULT)

1

CPP1 CPP0 00

01 10 11

PFD PHASE OFFSET MULTIPLIER 0 × 22.5°/ I

1 × 22.5°/ I 6 × 22.5°/ I 10 × 22.5°/I 16 × 22.5°/I 31 × 22.5°/I

CHARGE PUMP CURRENT 250µA

500µA (DEFAULT) 750µA 1000µA

CPMULT CPMULT

(RECOMMENDED)

CPMULT

(DEFAULT)

CPMULT CPMULT CPMULT

PAB0 PAB1 00

01 10 11

REFERENCE PATH EDGE

PE0

SENSITIVITY

0

FALLING EDGE (RECOMMENDED) RISING EDGE (DE F AULT)

1

DIVIDER PAT H EDGE

PE1

SENSITIVITY

0

FALLING EDGE (RECOMMENDED) RISING EDGE (DEFAULT)

1

CHARGE PUMP CONT ROL BOTH ON

PUMP DOWN PUMP UP TRISTATE (DEFAULT)

PFD ANTI BACKLAS H DELAY

0ns (DEFAUL T)

0.5ns

0.75ns

0.9ns

RMS2 RMS1 RMS0 000

001 010 011 100 101 110 111

CPBD 0

1

CHARGE PUMP CURRENT

CPM

REFERENCE SOURCE INTERNAL (DEFAULT)

0

EXTERNAL

1

RS0 RS1 00

01 10 11

REF OUTPUT MUX SELECT LOCK DETECT ( DEF AUL T)

VPTAT REFIN (BUFF ERED)

0.5× REFIN ( BUFFERED) 2× REFIN (BUF FERED) TRISTATE RESERVED RESERVED

INPUT REFERE NCE PATH SOURCE

2× REFIN REFIN (DEFAUL T)

0.5× REFIN

0.25× REFI N

Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map

PFD PHASE OFFSET POLARITY NEGATIVE

POSITIVE (DEFAULT)

Rev. C | Page 18 of 32

08545-008

ADRF6602

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB70DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000000 0

CAP DAC CONTROL BITS

CD3 CD2 CD1 CD0 PLEN LDV1 LXL LDRV C3(1) C2(0) C1(1)

RES

PLLENLO

DIV1LOEXTLODRV

CAPACITOR DAC

CD3 CD2 CD1 CD0

0000 1111

CONTROL FOR IIP3 OPTIMIZATION

MIN MAX

PLEN 0

1

Figure 43. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

3.3V VCO LDO

LDO

ENABLE

DISABLE ENABLE (DEFAUL T)

VCO

LVEN

ENABLE

VCO EN 0

1

VCO

SWITCH

VCO SW 0

1

VCO ENABLE DISABLE

ENABLE (DEFAULT)

VCO AMPLITUDERESERVED

VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

VC[5:0] VCO AMP LITUDE 0x00 0

…. …. 0x18 24 (DEFAULT)

…. …. 0x2B 43

…. …. 0x3F 63 (RECOMMENDED)

VCO SWITCH CONTROL FROM SPI REGULAR (DEF AULT)

BAND CAL

Figure 44. Register 6—VCO Control and VCO Enable Register Map

VCO

BW SW

CTRL

VBSRC 0

1

DB23

000

CPEN 0

1

CHARGE

PUMP

DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CHARGE PUMP ENABLE DISABLE

ENABLE (DEFAUL T)

ENABLE

CPEN L3EN VCO EN VCO SW VC5

L3EN 3.3V LDO ENABL E

DISABLE

0

ENABLE (DEFAUL T)

1

LVEN VCO LDO ENABLE 0

1

LO OUTPUT DRIVER

LDRV

ENABLE DRIVER OFF (DEFAULT)

0

DRIVER ON

1

EXTERNAL LO DRIVE

LXL

ENABLE (PIN 37, PIN 38) INTERNAL LO OUTPUT (DEFAULT)

0

EXTERNAL LO INPUT

1

DIVIDE - B Y - 2 I N L O CH AIN ENABLE

LDV1

DIVIDE BY 1

0

DIVIDE BY 2 (DE FAULT)

1

PLL ENABLE DISABLE

ENABLE (DEFAULT)

VCO BAND SELECT FROM SPI

VBS[5:0] VCO BAND S ELECT FROM SPI 0x00

0x01 ….

0x3F

VCO BW CAL AND SW S OURCE CONTROL BAND CAL (DEFAULT )

SPI

DEFAULT 0x20

CONTROL BITS

08545-009

08545-010

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

MIXER

XVCORES

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0XVCO

B_EN

MBE000000000000000000C3(1)C2(1)C1(1)

MBE

MIXER BIAS ENABLE DISABLE

0

ENABLE (DEFAULT)

1

EXTERNAL VCO

XVCO

INTERNAL VCO ( DE FAULT)

0

EXTERNAL VCO

1

Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map

RESERVED CONTROL BITS

Rev. C | Page 19 of 32

08545-011

ADRF6602

THEORY OF OPERATION

The ADRF6602 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO.

The mixer core within the ADRF6602 is the next generation of an industry-leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output. The high performance active mixer core results in an exceptional IIP3 and IP1dB, with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6602 typically provides IF input P1dB of 14.5 dBm and IIP3 of 30 dBm.

Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port, and by using a resistor to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6602, thus allowing cancellation of third-order distortion with no change in supply current. Connecting a resistor to a 5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current.

The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is INT + (FRAC/MOD), where INT is the integer value, FRAC is the fractional value, and MOD is the modulus value, all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often spurious components close to the fundamental signal. In the ADRF6602, a Σ- modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function.

PROGRAMMING THE ADRF6602

The ADRF6602 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Tabl e 8.

Table 8. Register Functions

Register Function

Register 0 Integer divide control for the PLL Register 1 Modulus divide control for the PLL Register 2 Fractional divide control for the PLL Register 3 Σ-Δ modulator dither control Register 4 PLL charge pump, PFD, reference path control Register 5 PLL enable and LO path control Register 6 VCO control and VCO enable Register 7 Mixer bias enable and external VCO enable

Note that internal calibration for the PLL must be run when the ADRF6602 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed last and in this order: Register 0, Register 1, Register 2.

To program the frequency of the ADRF6602, the user typically programs only Register 0, Register 1, and Register 2. However, if registers other than these are programmed first, a short delay should be inserted before programming Register 0. This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated.

Software is available on the ADRF6602 product page under the Evaluation Boards & Development Kits section that allows easy programming from a PC running Windows XP or Vista.

INITIALIZATION SEQUENCE

To ensure proper power-up of the ADRF6601, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V ±

0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions.

To ensure that the PLL is reset after power-up, follow this procedure:

Disable the PLL by setting the PLEN bit to 0 (Register 5,

1. Bit DB6).

After a delay of >100 ms, set the PLEN bit to 1 (Register 5,

2. Bit DB6).

After this procedure is followed, the other registers should be programmed in this order: Register 7, Register 6, Register 4, Register 3, Register 2, Register 1. Then, after a delay of >100 ms, Register 0 should be programmed.

Rev. C | Page 20 of 32

ADRF6602

LO SELECTION LOGIC

The downconverting mixer in the ADRF6602 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer.

Table 9. LO Selection Logic

Pins1 Register 5 Bits1 Outputs

Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO

0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal

1

X = don’t care.

The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Ta b le 9 .

Rev. C | Page 21 of 32

ADRF6602

APPLICATIONS INFORMATION

BASIC CONNECTIONS FOR OPERATION

Figure 46 shows the schematic for the ADRF6602 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 µF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 46.

The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC.

A peak-to-peak differential swing on RF for a sine wave input) results in an IF output power of 3.8 dBm.

The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should

VCC RED

+5V

C7

0.1µF (0402)

VCC1

RED

S1

OPEN

R56

(0402)

LO IN/OUT

R55 OPEN (0402)

0Ω

TC1-1-13+

REF_IN

REFOUT

4

3

51

T8

(0402)

R70

49.9Ω (0402)

R16

0Ω

(0402)

LODRV_EN

C5

1nF

(0402)

C6

1nF

(0402)

C31 1nF

REF_IN

MUXOUT

LON

LOP

R6 0Ω (0402)

C8 100pF (0402)

34 27 17 10 1

36

37

38

ADRF6602

×2

6

8

MUX

÷2 ÷4

of 1 V (0.353 V rms

IN

C25

0.1µF (0402)

R26 0Ω (0402)

C24 100pF (0402)

VCC_MIXVCC_V2IVCC_LO

FRACTION

THIRD-ORDER

INTERPOLATOR

TEMP

SENSOR

7 11 15 20 21 23 24 25 28 30 31 35

C23

0.1µF (0402)

R25 0Ω (0402)

C22 100pF (0402)

VCC_LO VCC2 VCC1

22

MODULUS

REG

FRACTIONAL

N COUNTER

21 TO 123

–

PHASE

+

FREQUENCY

DETECTOR

CP

TEST

POINT

(ORANGE)

C20

0.1µF (0402)

R25 0Ω (0402)

C21 100pF (0402)

INTEGER

REG

R38

0Ω

(0402)

C14

22pF

(0603)

C43

10µF

(0603)

R37

0Ω

(0402)

R11 OPEN (0402)

OPEN (0402)

R17 0Ω (0402)

Figure 46. Basic Connections for Operation of the ADRF6602

VCC

S2

C19

0.1µF (0402)

C18 100pF (0402)

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA

R

SET

R2 OPEN (0402)

R9 10kΩ

(0402)

R10

3.0kΩ (0603)

C15

2.7nF (1206)

C2

be ac-coupled and terminated with a 50 Ω resistor as shown in Figure 46. The reference signal, or a divided-down version o the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin.

The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options sectio

Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary.

P1

R54 10kΩ (0402)

R65 10kΩ

R1

0Ω

(0402)

100pF (0402)

R7 0Ω (0402)

BUFFER

(0402)

C13

6.8pF (0603)

C1

R53

10kΩ

(0402)

C9

0.1µF (0402)

C10 100pF (0402)

1 2 3 4 5 6 7 8 9

R19

0Ω

R20

(0402)

0Ω

(0402)

DIVIDER

÷2

DIV

2:1

BY

MUX

2, 1

VCO

CORE

VTUNE

CP

R62 0Ω (0402)

C40 22pF (0603)

R12 0Ω (0402)

R35 0Ω (0402)

DECLVCO

VTUNE

R63 OPEN (0402)

R30 0Ω (0402)

PLL_EN

R57 0Ω (0402)

CLK

DATA

1316 12

14

SPI

INTERFACE

VCC

+5V

LE

19184039354

9-PIN DSUB

R36 0Ω (0402)

IFNIFP

C34 OPEN (0402)

C33 OPEN (0402)

C32 OPEN (0402)

DECL2P5

9

DECL3P3

2

26

29

R59 (0402) C29

0.1µF (0402)

RF

IN

IP3SET

0Ω

R52 OPEN (0402)

R51 OPEN (0402)

R50 OPEN (0402)

C16 100pF (0402)

C12 100pF (0402)

R28

0Ω

(0402)

R27

0Ω

(0402)

124

35

R43

0Ω

(0402)

R18

0Ω

(0402)

R8 0Ω

(0402)

RFIN

C27

0.1µF (0402)

RFOUT

n.

C17

0.1µF (0402)

C11

0.1µF (0402)

C42 10µF (0603)

C41 OPEN (0603)

f

08545-024

Rev. C | Page 22 of 32

ADRF6602

A

AC TEST FIXTURE

Characterization data for the ADRF6602 was taken under very strict test conditions. All possible techniques were used to achieve optimum accuracy and to remove degrading effects of

RF1 AGIL E NT N5181A

HP 11636A

POWER DIVIDER

RF2 AGIL E NT N5181A

REF_IN AGILENT N5181A

REF_IN

DRF6602 CHARACTERIZ ATION RACK DIAGRAM. ALL INSTRUMEN TS ARE CONTR OLLED BY A LAB COMPUTER VIA A USB TO GPIB CONTROLLER, DAISY CHAINED TO EACH INDIVI DUAL INSTRUME NT .

the signal generation and measurement equipment. Figure 47 shows the typical AC test set up used in the characterization of the ADRF6602.

RF

IN

ADRF6602

EVALUATION BOARD

IF_OUT

ROHDE & SCHWARTZ

FSEA30

AGILENT 34401A SET T O IDC

(SET FO R S UPPLY CURRENT)

5V dc VIA

10-PIN DC HEADER

AGILENT 34980A WITH THREE 34921 MODULES

AND ONE 34950 MODULE

5V dc MEASURED F OR SUPPLY CURRENT

10-PIN DC HEADER

9-PIN CONTRO LLER DSUB AND

GND VIA 10-PIN DC HEADER

3.3V dc VIA 10-PIN DC HEADER

AGILENT E3631A 25V SET TO

3.3V, 6V SE T T O 5V. RETURNS ARE

JUMPERED TOGETHER

08545-047

Figure 47. ADRF6602 AC Test Set Up

Rev. C | Page 23 of 32

ADRF6602

EVALUATION BOARD

Figure 50 shows the schematic of the RoHS-compliant evaluation board for the ADRF6602. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material.

The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6—VCO Control and VCO Enable (Default: 0x1E2106) section).

Additional configuration options for the evaluation board are described in Ta ble 1 0.

EVALUATION BOARD CONTROL SOFTWARE

Software to program the ADRF6602 is available for download on the ADRF6602 product page under the Evaluation Boards & Development Kits section. To install the software

Download and extract the zip file:

1. ADRF6x0x_3p0p0_XP_install.exe file.

Follow the instructions in the read me file..

2.

The evaluation board can be connected to the PC using a PC parallel port or a USB port. These options are selectable from the opening menu of the software interface (see Figure 48). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port.

To connect the evaluation board to a USB port, a USB adapter board (EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices. This board connects to the PC using a standard USB cable with a USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6602 evaluation board.

8545-025

Figure 48. Control Software Opening Menu

Figure 49 shows the main menu of the control software with the default settings displayed.

Rev. C | Page 24 of 32

ADRF6602

08545-026

Figure 49. Main Screen of the ADRF6602 Evaluation Board Software

Rev. C | Page 25 of 32

ADRF6602

V

SCHEMATIC AND ARTWORK

CC

T7

1

GND2

1

GND1

1

GND

VCC

1

VCC_BB

VCC_LO

VCC_RF

11A22A3

P1-T7

AGND

9J1

6J1

7J1

8J1

10J1

AGND

VCO_LDO

2P5V_LDO

3P3V_LDO

VCC_SENSE

LO_EXTERN

2J1

3J1

4J1

5J1

1J1

AGND

OUT

VCC

AGND

0

R43

461

T3

TC4-1W

3

2

VCC_SENSE

0

SNS1

SNS

C28

AGND

0

R32

0

R31

0

R29

AGNDAGND

6A

10UF

LO

AGND

VCC_LO

0

R69

AGND

P4-T7

44A55A6

T8

3A

1

VCC_LO

P1-T7

4

2

0

R6

NC

153

P3-T7

LO_EXTERN

P3-T7

P4-T7

R66

0

R67

R68

0DNI

IP3SET

OUTPUT_EN

C7

0.1UF

AGND AGND

C8

100PF

VCC_BB

C27

0.1UF

TBD

R27

R60

TBD

1

IP3SET

AGND

0

R33

1NF

C6 C5

1NF

R56

10K

AGND

2

VCC

1

VCC1

3

10K

R55

AGND

1

S1

VCC_RF

1

VCC_RF

C25

0.1UF

0

R26

C24

100PF

AGND AGND

272829

30

GND

IP3SET

GND

31323334353637383940

NC

VCC_V2I

NC

VCC_LO

GND

LODRV_EN

LON

LOP

VTUNE

DECLVCO

P1-6

0

R63

R72

100K

AGND

VTUNE

0

R62

22PF

C40

10K

R65R9

C13

6.8PF

10K

3K

C15

R10

C14

22PF

0

R37

0

R38

1

CP

0

R12

2.7NF

DNI

R11

100PF

C10

0

R7

0.1UF

C9

1

VCC4

VCC

C1

100PF

0

R1

C2

0.1UF

VCO_LDO

1

AGND

R49

VCO_LDO

R8

AGND AGND

1

3P3V1

VCC1

123456789

AGND

10UF

C43

AGND

DNI

AGND

C12

100PF

0

C11

0.1UF

AGND

OSC_3P3V

C41

10UF

AGND

DECL3P3CPGND

0

R15

1

C4

OSC_3P3V

R59

0

VCC

R44

AGND

C29

0.1UF

AGND

RFIN

0

R28

AGND

VCC_BB

1

C23

VCC_BB1

0.1UF

0

R25

AGND AGND

C22

100PF

DNI

IFP

AGND

R47

C35

DNI

L1

TBD

VCC

IFN

AGND

0

R48

C36

DNI

L2

TBD

VCC

DNI

R58

VCC_LO

22

23

242526

IN

GND

RF

AGND

21

PAD

GND

E-PAD

VCC_MIX

GND

AGND

IFN

IFP

VCC_LO

PLL_EN

Z1

SET

R

REF_IN

GND

MUXOUT

R2

DNI

AGND

GND

LE

CLK

DATA

GND

DECL2P5

VCC2

10

AGND

P1-1

TBD

0

13 14 17 19

R35

11 12 15 16 18 20

R19

C32

100PFDNI

AGND

P1-1

1

R50

1KD NI

P1

123456789

CLK

C16

100PF

0

R18

C17

0.1UF

1

2P5V

10UF

C42

R71

0

R16

2P5V_LDO

AGND

REFOUT

DNI

R14

Y1

10PF

22000PF

C3

C31

1000PF

AGND

R70

49.9

AGND

REFIN

1

VCC_LO1

0

R34

0

R20

1

DATA

0

R57

R30

P1-6

AGNDAGND

C20

0.1UF

0

R24

C21

100PF

OUTPUT_EN

R54

3

1

2

S2

AGND

100PFDNI

C33

1

0

DIG_GND

R36

AGND

R51

1KDNI

1

VCC

AGND

R53

10K 10K

1

C34

100PFDNI

AGND

R52

1KDNI

AMP745781-4

100PF

C18

AGND

1

VCC2

AGND

0

R17

0.1UF

C19

AGND

VCC

08545-023

CC5

LE

3P3V_LDO

Figure 50. Evaluation Board Schematic

Rev. C | Page 26 of 32

ADRF6602

08545-013

Figure 51. Evaluation Board Layout (Bottom)

Figure 52. Evaluation Board Layout (Top)

08545-012

Rev. C | Page 27 of 32

ADRF6602

EVALUATION BOARD CONFIGURATION OPTIONS

Table 10.

Default Condition/

Component Description

S1, R55, R56, R33

LO IN/OUT SMA Connector

REFIN SMA Connector

REFOUT SMA Connector

CP Test Point

R37, C14, R9, R10, C15, C13, R65, C40

R11, R12

R62, R63, VTUNE SMA Connector

R2 R RFIN SMA Connector

T3

LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information).

LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input connector.

Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 Ω.

Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2× REFIN, REFIN/2, and REFIN/4; temperature sensor output voltage; and lock detect indicator.

Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise.

Loop filter. Loop filter components.

Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 Ω resistor in R11.

Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector.

pin. This pin is unused and should be left open. R2 = open (0402)

SET

RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6602 is ac-coupled, so no bias is necessary.

IF output. The differential IF output signals from the ADRF6602 (IFP and IFN) are converted to a single-ended signal by T3.

Option Settings

S1 = R55 = open (not installed), R56 = R33 = 0 Ω, LODRV_EN = 0 V

LO input

Lock detect

R12 = 0 Ω (0402), R11 = open (0402)

R62 = 0 Ω (0402), R63 = open (0402)

R3 = R23 = open (0402)

Rev. C | Page 28 of 32

ADRF6602

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.08

0.50

BSC

0.50

0.40

0.30

0.60 MAX

31

30

EXPOSED

(BOTTOM VIEW)

21

20

40

1

PAD

10

11

4.50 REF

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION O F THIS DATA SHEET.

PIN 1 INDICATOR

4.25

4.10 SQ

3.95

0.25 MIN

072108-A

Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADRF6602ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 ADRF6602-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. C | Page 29 of 32

ADRF6602

NOTES

Rev. C | Page 30 of 32

ADRF6602

NOTES

Rev. C | Page 31 of 32

ADRF6602

NOTES

registered trademarks are the property of their respective owners. D08545-0-9/10(C)

D08545-0-9/10(C)

Rev. C | Page 32 of 32

Datasheet ADRF6602 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

RF SPECIFICATIONS

SYNTHESIZER/PLL SPECIFICATIONS

LOGIC INPUT AND POWER SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

RF FREQUENCY SWEEP

IF FREQUENCY SWEEP

SPURIOUS PERFORMANCE

REGISTER STRUCTURE

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

THEORY OF OPERATION

PROGRAMMING THE ADRF6602

INITIALIZATION SEQUENCE

LO SELECTION LOGIC

APPLICATIONS INFORMATION

BASIC CONNECTIONS FOR OPERATION

AC TEST FIXTURE

EVALUATION BOARD

EVALUATION BOARD CONTROL SOFTWARE

SCHEMATIC AND ARTWORK

EVALUATION BOARD CONFIGURATION OPTIONS

OUTLINE DIMENSIONS

ORDERING GUIDE