Datasheet ADRF6601 Datasheet (ANALOG DEVICES)

750 MHz to 1160 MHz Rx Mixer with

V

Integrated Fractional-N PLL and VCO

FEATURES

Rx mixer with integrated fractional-N PLL RF input frequency range: 300 MHz to 2500 MHz Internal LO frequency range: 750 MHz to 1160 MHz Input P1dB: 14.5 dBm Input IP3: 31 dBm IIP3 optimization via external pin SSB noise figure

IP3SET pin open: 13.5 dB

IP3SET pin at 3.3 V: 14.6 dB Voltage conversion gain: 6.7 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Cellular base stations

GENERAL DESCRIPTION

The ADRF6601 is a high dynamic range active mixer with an integrated phase-locked loop (PLL) and a voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a f can be divided or multiplied and then applied to the PLL phase frequency detector (PFD).

LODRV_EN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

input to the mixer. The reference input

LO

CC1

36

LON

37

38

LOP

PLL_EN

DATA

CLK

REF_IN

MUXOUT

16

12

13

14

LE

6

8

SPI

INTERFACE

×2

MUX

÷2

÷4

FRACTION

TEMP

SENSOR

7 11 15 20 21 23 24 25 28 30 31 35

FUNCTIONAL BLOCK DIAGRAM

CC2VCC_LOVCC_MIXVCC_V2IVCC_LO

PHASE

INTEGER

N COUNTER

21 TO 123

MODULUS

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

– +

FREQUENCY

DETECT OR

GND

REG

Figure 1.

ADRF6601

The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter.

The loop filter output is then applied to an integrated VCO. The VCO output at 2 × f programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta (Σ-) modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047.

The active mixer converts the single-ended 50  RF input to a 200 Ω differential IF output. The IF output can operate up to 500 MHz.

The ADRF6601 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range.

Table 1.

Internal LO

Part No.

Range

ADRF6601 750 MHz 300 MHz 450 MHz 1160 MHz 2500 MHz 1600 MHz

ADRF6602 1550 MHz 1000 MHz 1350 MHz

2150 MHz 3100 MHz 2750 MHz

ADRF6603 2100 MHz 1100 MHz 1450 MHz

2600 MHz 3200 MHz 2850 MHz

ADRF6604 2500 MHz 1200 MHz 1600 MHz

2900 MHz 3600 MHz 3200 MHz

2717101 22

34

BUFFER

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA (DEFAULT ),

750µA, 1000µA

54

R

SET

is applied to an LO divider, as well as to a

LO

±3 dB RF Balun Range

ADRF6601

INTERNAL LO RANGE

750MHz TO 1160M Hz

DIV

2:1

BY

MUX

4, 2, 1

VCO

CORE

3

CP VTUNE

IFP

NC

191839

IFN

32 33

3.3V LDO

2.5V LDO

VCO LDO

NC

IN

2

9

40

26

29

±1 dB RFIN Balun Range

DECL3P3

DECL2P5

DECLVCO

RF

IN

IP3SET

08546-001

ADRF6601

REVISION HISTORY

3/11—Rev. 0 to Rev. A

Changes to Features Section, General Description Section, and

Table 1 ............................................................................................ 1

Changes to Table 2............................................................................ 3

Changes to Conditions Statement and the Figure of Merit,

Reference Spurs, and Phase Noise Parameters, Table 3;

Changes to Conditions Statement and the Supply Current

Parameter, Table 4 ........................................................................ 4

Changes to Table 6............................................................................ 6

Changes to Table 7............................................................................ 7

Replaced Typical Performance Characteristics Section .............. 9

Added Spurious Performance Section......................................... 15

Changes to Figure 44 and Figure 45............................................. 19

Changes to Theory of Operation Section.................................... 20

Added AC Test Fixture Section and Figure 47;

Renumbered Sequentially ......................................................... 23

Changes to Evaluation Board Control Software Section........... 24

Changes to Table 10........................................................................ 28

1/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

ADRF6601

SPECIFICATIONS

RF SPECIFICATIONS

VS = 5 V, ambient temperature (TA) = 25°C, f using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

INTERNAL LO FREQUENCY RANGE 750 1160 MHz RF INPUT FREQUENCY RANGE ±3 dB RF input range 300 2500 MHz RF INPUT AT 610 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −11.1 dB Input P1dB 14.8 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 67.4 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 33.4 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 13.3 dB

IP3SET = open 12.5 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −55.5 dBm

RF INPUT AT 910 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −16.7 dB Input P1dB 14.5 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 55.3 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 30.9 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 14.6 dB

IP3SET = open 13.5 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −48 dBm

RF INPUT AT 1020 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −16.8 dB Input P1dB 14.8 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 60.9 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 32.2 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 14.8 dB

IP3SET = open 13.5 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −49 dBm

IF OUTPUT

Voltage Conversion Gain Differential 200 Ω load 6.7 dB IF Bandwidth Small signal 3 dB bandwidth 500 MHz Output Common-Mode Voltage External pull-up balun or inductors required 5 V Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/0.5 dB Gain Variation Over full temperature range 1.2 dB Output Swing Differential 200 Ω load 2 V p-p Differential Output Return Loss Measured through 4:1 balun −15.5 dB

LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, internal PLL disabled

Frequency Range 250 6000 MHz Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −6 dBm Input Level (LO as Input) −6 0 +6 dBm Input Impedance 50 Ω

= 153.6 MHz, f

REF

= 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized

PFD

Rev. A | Page 3 of 32

ADRF6601

SYNTHESIZER/PLL SPECIFICATIONS

VS = 5 V, ambient temperature (TA) = 25°C, f

= 140 MHz, IIP3 optimized using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.

f

IF

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO

Frequency Range Internally generated LO 750 1160 MHz

Figure of Merit1 P

Reference Spurs f f f >f PHASE NOISE fLO = 750 MHz to 1160 MHz, f

1 kHz to 10 kHz offset −99 dBc/Hz

100 kHz offset −108 dBc/Hz

500 kHz offset −127 dBc/Hz

1 MHz offset −135 dBc/Hz

5 MHz offset −147 dBc/Hz

10 MHz offset −151 dBc/Hz

20 MHz offset −153 dBc/Hz

Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.14

PFD Frequency 20 40 MHz REFERENCE CHARACTERISTICS REF_IN, MUXOUT pins

REF_IN Input Frequency 12 160 MHz

REF_IN Input Capacitance 4 pF

MUXOUT Output Level VOL (lock detect output selected) 0.25 V

V

MUXOUT Duty Cycle 50 % CHARGE PUMP

Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1 mA 500 μA

Output Compliance Range 1 2.8 V

1

The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(f

power = 10 dBm (500 V/μs slew rate) with a 40 MHz f

and f

REF

= 153.6 MHz, f

REF

= 0 dBm −222 dBc/Hz/Hz

REF_IN

= 38.4 MHz

PFD

/4 −107 dBc

PFD

−83 dBc

PFD

−88 dBc

PFD

power = 4 dBm, f

REF

= 38.4 MHz

PFD

= 38.4 MHz, high-side LO injection,

PFD

°rms

(lock detect output selected) 2.7 V

OH

) – 20 log 10(fLO/f

. The FOM was computed at 50 kHz offset.

PFD

). The FOM was measured across the full LO range with f

PFD

= 80 MHz,

REF

LOGIC INPUT AND POWER SPECIFICATIONS

VS = 5 V, ambient temperature (TA) = 25°C, f using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

LOGIC INPUTS CLK, DATA, LE

Input High Voltage, V

Input Low Voltage, V

Input Current, I

1.4 3.3 V

INH

0 0.7 V

INL

0.1 μA

INH/IINL

Input Capacitance, CIN 5 pF POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range 4.75 5 5.25 V

Supply Current PLL only 97 mA External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off) 184 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 294 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off ) 281 mA Power-down mode 30 mA

= 153.6 MHz, f

REF

= 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized

PFD

Rev. A | Page 4 of 32

ADRF6601

TIMING CHARACTERISTICS

VS = 5 V ± 5%.

Table 5.

Parameter Limit Unit Description

t1 20 ns min LE setup time t2 10 ns min DATA-to-CLK setup time t3 10 ns min DATA-to-CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK-to-LE setup time t7 20 ns min LE pulse width

Timing Diagram

CLK

t

4

t

5

DATA

DB23 (MSB) DB22

t

1

LE

t

2

t

3

DB2 DB1

(CONTROL BIT C2)(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

08546-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 32

ADRF6601

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Supply Voltage, VCC1, VCC2, VCC_LO,

VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE, LODRV_EN,

PLL_EN VTUNE 0 V to 3.3 V IFP, IFN −0.3 V to VCC_V2I + 0.3 V RFIN 16 dBm LOP, LON, REF_IN 13 dBm θJA (Exposed Paddle Soldered Down) 35°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

−0.5 V to +5.5 V

−0.3 V to +3.6 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 32

ADRF6601

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRV_EN

ND

NC

VCC_LO

G

LO

LON

LOP

VTUNE

DECLVCO

37

38

39

40

PIN 1

1VCC1

INDICATOR

2DECL3P3 3CP

GND

4 5 6 7 8 9

ADRF6601

TOP VIEW

(Not to Scale)

11

12

13

14

LE

CLK

GND

DATA

R

SET

REF_IN

GND

MUXOUT

DECL2P5

10

VCC2

NOTES

1. NC = NO CONNECT. DO NOT CONNECT THIS PIN.

2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PL ANE.

Figure 3. Pin Configuration

GND

NC

32

31

33

34

35

36

30 GND 29 IP3SET 28 GND 27 VCC_V2I

RF

26

IN

25

GND 24 GND 23 GND 22 VCC_MIX 21

GND

15

17

16

18

19

20

ND

IFP

IFN

GND

G

PLL_EN

VCC_LO

08546-003

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC1

Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 2 DECL3P3 Decoupling Node for the 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 3 CP Charge Pump Output Pin. Connect to VTUNE through the loop filter. 4, 7, 11, 15, 20,

GND Ground. Connect these pins to a low impedance ground plane. 21, 23, 24, 25, 28, 30, 31, 35

5 R

SET

Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external R

is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I

SET

can be externally adjusted according to the following equation:

=

R

SET

6 REF_IN

Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-

⎛ ⎜ ⎜ ⎝

I

NOMINAL

⎞

CP

⎟ ⎟ ⎠

37.8

−

×

I

4.217

biased and should be ac-coupled.

8 MUXOUT

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect

signal. The output is selected by programming the appropriate register. 9 DECL2P5 Decoupling Node for the 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 10 VCC2

Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. 13 CLK

Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE

Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the

eight registers. The relevant latch is selected by the three control bits of the 24-bit word. 16 PLL_EN

PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is

automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the

internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be

used to switch modes. 17, 34 VCC_LO

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes.

Rev. A | Page 7 of 32

NOMINAL

)

ADRF6601

Pin No. Mnemonic Description

22 VCC_MIX

26 RFIN RF Input (single-ended, 50 Ω). 27 VCC_V2I

29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. 32, 33 NC No Connection. 36 LODRV_EN

37, 38 LON, LOP

39 VTUNE

40 DECLVCO

EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.

LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high if the PLEN bit (DB6 in Register 5) is set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency must be 1× LO. This pin has an internal 100 kΩ pull-down resistor.

Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins.

VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.5 V to 2.5 V.

Decoupling Node for the VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground.

Rev. A | Page 8 of 32

ADRF6601

TYPICAL PERFORMANCE CHARACTERISTICS

RF FREQUENCY SWEEP

CDAC = 0x0, internally generated high-side LO, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted.

5

IP3SET = OPEN IP3SET = 3.3V

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

610 660 710 760 810 860 910 960 1010

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 4. Gain vs. RF Frequency

08546-004

45

40

35

30

25

20

INPUT IP3 (dBm)

15

10

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C TA = +25°C TA = –40°C

5

610 660 710 760 810 860 910 960 1010

RF FREQUENCY ( MHz)

Figure 7. Input IP3 vs. RF Frequency

08546-007

90

80

70

60

INPUT IP2 (dBm)

50

40

30

IP3SET = OPEN IP3SET = 3.3V

610 660 710 760 810 860 910 960 1010

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 5. Input IP2 vs. RF Frequency

20

18

16

14

12

10

NOISE FIGURE (dB)

IP3SET = OPEN IP3SET = 3.3V

8

6

4

2

0

610 660 710 760 810 860 910 960 1010

RF FREQUENCY ( MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 6. Noise Figure vs. RF Frequency

20

18

16

14

12

10

INPUT P1dB (dBm)

08546-005

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C

8

6

4

2

0

610 660 710 760 810 860 910 960 1010

RF FREQUENCY ( MHz)

TA = +25°C TA = –40°C

08546-008

Figure 8. Input P1dB vs. RF Frequency

08546-006

Rev. A | Page 9 of 32

ADRF6601

IF FREQUENCY SWEEP

CDAC = 0x0, internally generated swept low-side LO, fRF = 1960 MHz, RFIN = −5 dBm, unless otherwise noted.

5

IP3SET = OPEN

4

IP3SET = 3.3V

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 9. Gain vs. IF Frequency

08546-009

45

40

35

30

25

20

INPUT IP3 (dBm)

15

10

IP3SET = OPEN IP3SET = 3.3V

5

25 4003753503253002752502252001751501257550 100

IF FREQUENCY (MHz)

Figure 12. Input IP3 vs. IF Frequency, RF

TA = +85°C TA = +25°C TA = –40°C

= −5 dBm

IN

08546-012

90

80

70

60

INPUT IP2 (dBm)

50

40

30

NOISE FIGURE (dB)

IP3SET = OPEN IP3SET = 3.3V

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

Figure 10. Input IP2 vs. IF Frequency, RF

20

18

16

14

12

10

IP3SET = OPEN IP3SET = 3.3V

8

6

4

2

0

25 4003753503253002752502252001751501257550 100

IF FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

= −5 dBm

IN

TA = +85°C TA = +25°C TA = –40°C

Figure 11. Noise Figure vs. IF Frequency

20

18

16

14

12

10

INPUT P1dB (dBm)

08546-010

IP3SET = OPEN IP3SET = 3.3V

8

6

4

2

0

25 4003753503253002752502252001751501257550 100

IF FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

08546-013

Figure 13. Input P1dB vs. IF Frequency

08546-011

Rev. A | Page 10 of 32

ADRF6601

–

0

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

LO-TO -IF FEE DTHROUGH (dBm)

–60

–65

–70

IP3SET = OPEN IP3SET = 3.3V

750 800 850 900 950 1000 1050 1100 1150

LO FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 14. LO-to-IF Feedthrough vs. LO Frequency,

LO Output Turned Off, CDAC = 0x0

30

–40

–50

–60

–70

LO-RF LEAKAGE (dBm)

–80

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C TA = +25°C TA = –40°C

08546-014

0

–5

–10

–15

–20

–25

RETURN LOSS (d B)

–30

–35

–40

500 1300120011001000900800700600

LO FREQUENCY (MHz)

08546-017

Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)

350

300

250

200

150

RESISTANCE (Ω)

100

50

RESISTANCE

CAPACITANCE

3.5

3.0

2.5

2.0

1.5

1.0

0.5

CAPACITANCE (pF )

–90

750 1000 1050 1100 1150950900850800

LO FREQUENCY (MHz)

Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off

0

–5

–10

–15

–20

–25

RETURN LOSS (d B)

–30

–35

–40

500 1300120011001000900800700600

RF FREQUENCY (M Hz)

Figure 16. RF Input Return Loss vs. RF Frequency

0

50 500450400350300250200150100

08546-015

IF FREQUENCY (MHz)

0

08546-018

Figure 18. IF Differential Output Impedance (R Parallel C Equivalent)

35

30

25

20

NOISE FIGURE (dB)

15

10

08546-016

IP3SET = OPEN IP3SET = 3.3V

–60 –50 –40 –30 –20 –10 0

CW BLOCKER LEVEL (dBm)

08546-019

Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level,

LO Frequency = 1055 MHz, RF Frequency = 915 MHz

Rev. A | Page 11 of 32

ADRF6601

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

RF-TO-IF ISOLATION (dBc)

–55

–60

–65

–70

0

550 1350125011501050950850750650

IP3SET = OPEN IP3SET = 3.3V

RF FREQUENCY (M Hz)

TA = +85°C TA = +25°C TA = –40°C

08546-020

Figure 20. RF-to-IF Isolation vs. RF Frequency, High-Side LO, IF = 140 MHz,

LO Output Turned Off

0

IP3SET = OPEN IP3SET = 3.3V

750 800 850 900 950 1000 1050 1100 1150

LO FREQUENCY (MHz)

LO OUTPUT AMPLIT UDE (dBm)

–10

–1

–2

–3

–4

–5

–6

–7

–8

–9

TA = +85°C TA = +25°C TA = –40°C

08546-021

Figure 21. LO Output Amplitude vs. LO Frequency

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VTUNE VOLTAGE (V)

1.5

1.0

0.5

0

750 80 0 850 900 950 1000 1050 1100 1150

LO FREQUE NCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 23. VTUNE vs. LO Frequency

350

300

250

200

SUPPLY CURRENT (mA)

150

100

750 1150110010501000950900850800

IP3SET = OPEN IP3SET = 3.3V

LO FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

Figure 24. Supply Current vs. LO Frequency

08546-023

08546-024

20

15

10

5

0

–5

–10

–15

FREQUENCY DEVIATION F ROM 920MHz (M Hz)

–20

0 50 100 150 200 250

TIME (µs)

Figure 22. Frequency Deviation from 910 MHz vs. Time

(Demonstrates LO Frequency Settling Time from 920 MHz to 910 MHz)

08546-022

Rev. A | Page 12 of 32

2.0

1.9

1.8

1.7

1.6

1.5

1.4

VPTAT VOLTAGE (V)

1.3

1.2

1.1

1.0

IP3SET = OPEN IP3SET = 3.3V

–55 –35 –15 5 25 45 65 85 105

TEMPERATURE (° C)

Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open)

08546-025

ADRF6601

Complementary cumulative distribution function (CCDF), fRF = 2140 MHz, fIF = 140 MHz.

100

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

0

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C TA = +25°C TA = –40°C

–1.0–1.5–2.0 –0.5 0 0. 5 1.0 1.5 2.0 3.02.5

GAIN (dB)

08546-026

Figure 26. Gain

100

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C TA = +25°C TA = –40°C

0

24 26 28 30 32 34 36 38 40

INPUT IP3 (dBm)

Figure 29. Input IP3

08546-029

100

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C TA = +25°C TA = –40°C

0

50 55 60 65 70 75 80

INPUT IP2 (dBm)

Figure 27. Input IP2

100

IP3SET = OPEN

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

0

11 12 13 14 15 16 17109

NOISE FI GURE (dB)

TA = +85°C TA = +25°C TA = –40°C

Figure 28. Noise Figure

100

IP3SET = OPEN

90

IP3SET = 3.3V

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

0

08546-027

10 11 12 13 1 4 15 16 1817

INPUT P1dB (dBm)

TA = +85°C TA = +25°C TA = –40°C

08546-030

Figure 30. Input P1dB

100

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

08546-028

IP3SET = OPEN IP3SET = 3.3V

TA = +85°C TA = +25°C TA = –40°C

0

–90 –80 –70 –60 –50 –40 –30

LO FEEDTHROUGH (dBm)

08546-031

Figure 31. LO Feedthrough to IF, LO Output Turned Off

Rev. A | Page 13 of 32

ADRF6601

–

Measured at IF output, CDAC = 0x0, IP3SET = open, internally generated high-side LO, f RF

= −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.

IN

80

–90

LO FREQ UENCY = 1155.2MHz

–100

–110

–120

–130

PHASE NOISE (d Bc/Hz)

LO FREQUENCY = 752MHz

–140

–150

–160

1k 10k 100k 1M 10M 100M

OFFSET FREQUENCY (Hz)

Figure 32. Phase Noise vs. Offset Frequency

TA = +85°C TA = +25°C TA = –40°C

08546-032

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

INTEGRATE D PHASE NOISE ( °rms)

0.05

0

750 800 850 900 950 1000 1 050 1100 1150

= 153.6 MHz, f

REF

LO FREQUENCY (MHz)

= 38.4 MHz,

PFD

TA = +85°C TA = +25°C TA = –40°C

Figure 35. Integrated Phase Noise vs. LO Frequency

08546-035

75

OFFSET AT 2× PFD FREQUENCY

–80

–85

–90

–95

SPURS LEVEL (dBc)

–100

–105

–110

OFFSET AT 4× PFD FREQUENCY

TA = +85°C TA = +25°C TA = –40°C

750 850 950 1050 1150800 900 1000 1100

LO FREQUENCY (MHz)

08546-033

Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)

75

OFFSET AT 3× PFD FREQUENCY

–80

–85

–90

–95

SPURS LEVEL (dBc)

–100

–105

–110

OFFSET AT 1× PFD FREQUENCY

0.25× PFD FREQUENCY

750 850 950 1050 1150800 900 1000 1100

LO FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

08546-034

Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)

90

OFFSE T = 1kHz

OFFSE T = 100kHz

OFFSET = 5MHz

LO FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

08546-036

PHASE NOISE (dBc/Hz)

–100

–110

–120

–130

–140

–150

–160

750 1150110010501000950900850800

Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)

100

–105

–110

–115

–120

–125

–130

–135

PHASE NOISE (dBc/Hz)

–140

–145

–150

750 800 850 900 950 1000 1050 1100 1150

OFFSET = 10kHz

OFFSET = 1MHz

LO FREQUENCY (MHz)

TA = +85°C TA = +25°C TA = –40°C

08546-037

Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)

Rev. A | Page 14 of 32

ADRF6601

SPURIOUS PERFORMANCE

(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than −125 dBc are shown.

LO = 750 MHz, RF = 610 MHz (horizontal axis is m, vertical axis is n), and RF

0 1 2

N

3 4 5 6 7

0 1 2 3 4

−115.74 −63.28 −31.83 −54.52 −33.54

−49.49 0.0 −64.58 −24.09 −71.52

−48.77 −42.49 −75.23 −60.35 −67.88

−81.30 −71.27 −103.32 −73.13 −110.05

−83.02 −91.24 −105.20 −88.27 −113.66

−103.16 −111.19 −114.25 −108.4 −115.31

−110.88 −112.83 −112.85 −113.85 −113.55

−110.87 −108.26 −112.91 −111.93 −113.64

M

LO = 1050 MHz, RF = 910 MHz (horizontal axis is m, vertical axis is n), and RF

0 −113.23 −57.96 −27.78 −58.01 1 −34.12 0.0 −58.72 −27.14 −84.94 2 −49.76 −47.19 −57.30 −68.48 −65.03

N

3 −73.54 −74.12 −102.24 −72.99 −108.62 4 5 6 7

0 1 2 3 4

−102.66

−108.79 −107.57

−110.79 −108.34 −107.38

−109.87 −109.71 −108.58

−110.29 −100.07 −99.75 −112.69

M

−110.94 −110.16 −115.35

power = 0 dBm.

IN

power = 0 dBm.

IN

−40.34

−112.44 −113.78

−110.01

Rev. A | Page 15 of 32

ADRF6601

REGISTER STRUCTURE

This section provides the register maps for the ADRF6601. The three LSBs determine the register that is programmed.

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000000000000DMID6ID5ID4ID3ID2ID1ID0C3(0)C2(0)C1(0)

DM

0

1

ID6 ID5 ID4 ID3 ID2 ID1 ID0

0010101

0010110

0010111

0011000

... ... ... ... ... ... ...

0111000

... ... ... ... ... ... ...

1110111

1111000

1111001

1111010

1111011

DIVIDE MODE

FRACTIONAL (DEFAULT)

INTEGER

INTEGER DI VIDE RATIO CONTROL BITS

INTEGER DIVIDE RATIO

21 (INTEG ER MODE ONL Y)

22 (INTEG ER MODE ONL Y)

23 (INTEG ER MODE ONL Y)

24

...

56 (DEFAULT)

...

119

120 (INTEGER MODE ONL Y)

121 (INTEGER MODE ONL Y)

122 (INTEGER MODE ONL Y)

123 (INTEGER MODE ONL Y)

Figure 38. Register 0—Integer Divide Control Register Map

08546-038

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RESERVED

0 0 0 0 0 0 0 0 0 0 MD10 M D9 M D8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)

MD10MD9MD8MD7MD6MD5MD4MD3MD2MD1MD0

0 0000000001

0 0000000010

... ... ... ... ... ... ... ... ... ... ...

1 1000000000

... ... ... ... ... ... ... ... ... ... ...

1 1111111111

Figure 39. Register 1—Modulus Divide Control Register Map

Rev. A | Page 16 of 32

MODULUS VALUE

CONTROL BI TS

MODULUS VALUE

1

2

...

1536 (DEFAULT )

...

2047

8546-039

ADRF6601

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FRACTIONAL VALUERESERVED

0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 F D2 FD1 F D0 C3(0) C2(1) C1(0)

CONTROL BI TS

FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0

0 0000000000

0 0000000001

... ... ... ... ... ... ... ... ... .. . ...

0 1100000000

... ... ... ... ... ... ... ... ... .. . ...

FRACTIONAL VALUE MUST BE LESS THAN MO DULUS

Figure 40. Register 2—Fractional Divide Control Register Map

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 DITH1 DITH0 DE N DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DITH1 DITH0 00 01

10

11

DITHER

MAGNITUDE

DITHER MAGNITUDE 15 (DEFAULT ) 7

3

1 (RECOMMENDED)

DITHER

ENABLE

DEN 0 1

DITHER RESTART VALUE CONTROL BITS

DITHER ENABLE DISABLE ENABLE (DEFAULT, RECOMMENDED)

FRACTIONAL VALUE

0

1

...

768 (DEFAULT )

...

<MDR

08546-040

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

00000000000000001

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

11111111111111111

DITHER RESTART VALUE

0x00001 (DEFAULT )

... ... 0x1FFFF

08546-041

Figure 41. Register 3—Σ-Δ Modulator Dither Control Register Map

Rev. A | Page 17 of 32

ADRF6601

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

REF OUP UT

MUX SELECT

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

INPUT REF

PATH

CP

CURRENT

REF

SOURCE

PFD

POL

PFD PHASE OFFSET

MULTIPLIER

CP

CURRENT

CP

SRC

CP

CONTROL

PFD EDGE CONTROL BITS

PFD ANTI

BACKLASH

DELAY

CPB4 CPB3 CPB2 CPB1 CPB0

0000 0 0000 1 0011 0 0101 0 1000 0 1111 1

CPC1 CPC0

00 01 10 11

CHARGE PUMP CONTROL SOURCE

CPS

CONTROL BASE D ON STATE OF DB7/DB8 (CP CO NTROL)

0

CONTROL FRO M PFD (DEFAUL T)

1

CPP1 CPP0

00 01 10 11

PFD PHASE OFF SET MULTIPLIER

0 × 22.5°/I 1 × 22.5°/I 6 × 22.5°/I 10 × 22.5°/I 16 × 22.5°/I 31 × 22.5°/I

CHARGE PUMP CURRENT

250µA 500µA (DEFAUL T) 750µA 1000µA

CPMULT CPMULT

(RECOMMENDED)

CPMULT

(DEFAULT)

CPMULT CPMULT CPMULT

PAB0 PAB1

00 01 10 11

REFERENCE PATH EDGE

PE0

SENSITIVITY

0

FALLING EDGE RISING EDG E (DEFAULT )

1

DIVIDER PATH EDGE

PE1

SENSITIVITY

0

FALLING EDGE RISING EDG E (DEFAULT )

1

CHARGE PUMP CONT ROL

BOTH ON PUMP DOWN PUMP UP TRISTATE (DEFAULT)

PFD ANTI BACKLASH DELAY

0ns (DEFAULT)

0.5ns

0.75ns

0.9ns

RMS2 RMS1 RMS0

000 001 010 011 100 101 110 111

CPBD

0 1

CHARGE PUMP CURRENT

CPM

REFERENCE SOURCE INTERNAL (DEF AULT)

0

EXTERNAL

1

RS0 RS1

00 01 10 11

REF OUTPUT MUX SELECT

LOCK DETECT (DEFAULT) VPTAT REF_IN (BUFFERED)

0.5× REF_IN ( BUFFERED) 2× REF_IN (BUFFERED) TRISTATE RESERVED RESERVED

INPUT REFERENCE PATH SOURCE

2× REF_IN REF_IN (DEFAULT)

0.5× REF_IN

0.25× REF_IN

Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map

PFD PHASE OFFSET POLARITY

NEGATIVE POSITIVE (DEFAULT)

Rev. A | Page 18 of 32

08546-042

ADRF6601

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7

00000000000 0

CAP DAC

CD3 CD2 CD1 CD0 PLEN LDV1 L XL LDRV C3(1) C2(0) C1(1)

RES

LDV2

PLLENLO

DIV1LOEXTLODRV

DB6 DB5 DB4 DB3 DB2 DB1 DB0

CONTRO L BIT S

CAPACITOR DAC

CD3 CD2 CD1 CD0

0000

... ... ... ...

1111

CONTROL F OR IIP3 OPTIMIZATION

MIN ... MAX

Figure 43. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

DB23

CPEN

0 1

CHARGE

PUMP

DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

000

CHARGE PUMP ENABLE

DISABLE ENABLE (DEFAULT)

ENABLE

L3EN 3.3V LDO ENABLE

DISABLE

0

ENABLE (DEFAULT)

1

LVEN VCO LDO ENABLE

0 1

3.3V VCO LDO

LDO

ENABLE

CPEN L3EN VCO EN VCO SW VC5

DISABLE ENABLE (DEFAULT)

LVEN

VCO

ENABLE

VCO EN

0 1

VCO

SWITCH

VCO SW

0 1

VCO SWIT CH CONTROL FROM SPI

REGULAR (DEFAUL T) BAND CAL

VCO ENABLE

DISABLE ENABLE (DEFAULT)

Figure 44. Register 6—VCO Control and VCO Enable Register Map

VCO

VCO AMPLITUDERESERVED

VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

VC[5:0] VCO AMPLITUDE

0x00 0 …. ….

0x18 24 (DEFAULT) …. ….

0x2B 43 …. ….

0x3F 63 (RECOMMENDE D)

BW SW

CTRL

VBSRC

0 1

LO OUTPUT DRIVER

LDRV

ENABLE

DRIVER OFF (DEFAULT)

0

DRIVER ON

1

EXTERNAL LO DRIVE

LXL

ENABLE (PIN 37, PIN 38)

INTERNAL LO OUTPUT (DEFAULT)

0

EXTERNAL LO INPUT

1

DIVIDE-BY-2 I N LO CHAIN E NABLE

LDV1

DIVIDE BY 1

0

DIVIDE BY 2 (DEFAULT)

1

PLEN

PLL ENABLE

DISABLE

0

ENABLE (DEFAULT)

1

VCO BAND SELECT FROM SPI

VBS[5:0] VCO BAND SELECT FROM SPI

0x00 0x01

….

0x20 ….

0x3F

VCO BW CAL AND SW SOURCE CONTRO L

BAND CAL (DEFAULT ) SPI

DEFAULT

CONTROL BI TS

08546-043

08546-044

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

MIXER

XVCORES

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0XVCO

B_EN

MBE0 0 00000000000000 00C3(1)C2(1)C1(1)

MBE

MIXER BIAS ENABL E ENABLE (DEFAULT)

0

DISABLE

1

EXTERNAL VCO

XVCO

INTERNAL VCO (DEFAULT)

0

EXTERNAL VCO

1

Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map

RESERVED CONTROL BITS

Rev. A | Page 19 of 32

08546-045

ADRF6601

THEORY OF OPERATION

The ADRF6601 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO.

The mixer core within the ADRF6601 is the next generation of an industry-leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output voltage by external bias inductors. The mixer bias current is also sourced through these external inductors. The high performance active mixer core results in an exceptional IIP3 and IP1dB with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6601 typically provides an IF input P1dB of

14.5 dBm and an IIP3 of 31 dBm.

Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port and by using a resistor to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6601, thus allowing cancellation of third-order distortion with no change in supply current. Connecting a resistor to a 5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current.

The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than to be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is

INT + (FRAC/MOD)

where:

INT is the integer value. FRAC is the fractional value. MOD is the modulus value.

The INT, FRAC, and MOD values are all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often spurious components close to the fundamental signal. In the ADRF6601, a Σ- modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function.

Table 8. ADRF6601 Register Functions

Register Function

Register 0 Integer divide control for the PLL Register 1 Modulus divide control for the PLL Register 2 Fractional divide control for the PLL Register 3 Σ-Δ modulator dither control Register 4 PLL charge pump, PFD, reference path control Register 5 PLL enable and LO path control Register 6 VCO control and VCO enable Register 7 Mixer bias enable and external VCO enable

Note that internal calibration for the PLL must be run when the ADRF6601 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed in the order specified in the Initialization Sequence section.

To program the frequency of the ADRF6601, the user typically programs only Register 0, Register 1, and Register 2. However, if registers other than these are programmed first, a short delay should be inserted before programming Register 0. This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated.

Software is available on the ADRF6601 product page under the Evaluation Boards & Kits section that allows easy programming from a PC running Windows XP or Vista.

INITIALIZATION SEQUENCE

To ensure proper power-up of the ADRF6601, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V ±

0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions.

To ensure that the PLL is reset after power-up, follow this procedure:

Disable the PLL by setting the PLEN bit to 0 (Register 5,

1. Bit DB6).

After a delay of >100 ms, set the PLEN bit to 1 (Register 5,

2. Bit DB6).

After this procedure is complete, the other registers should be programmed in the following order: Register 7, Register 6, Register 4, Register 3, Register 2, Register 1. Then, after a delay of >100 ms, Register 0 should be programmed.

PROGRAMMING THE ADRF6601

The ADRF6601 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Tabl e 8 .

Rev. A | Page 20 of 32

ADRF6601

LO SELECTION LOGIC

The downconverting mixer in the ADRF6601 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer.

Table 9. LO Selection Logic

Pins1 Register 5 Bits1 Outputs

Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO

0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal

1

X = don’t care.

The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Ta b le 9 .

Rev. A | Page 21 of 32

ADRF6601

APPLICATIONS INFORMATION

BASIC CONNECTIONS FOR OPERATION

Figure 46 shows the schematic for the ADRF6601 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 µF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 46.

The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC.

A peak-to-peak differential swing on RF for a sine wave input) results in an IF output power of 4.7 dBm.

The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should

VCC RED

+5V

VCC1

RED

R55 OPEN (0402)

S1

OPEN

(0402)

LO IN/OUT

R56

0Ω

REF_IN

REFOUT

4

51

T8

TC1-1-13+

R70

49.9Ω

(0402)

R16

(0402)

LODRV_EN

3

(0402)

C31 1nF

(0402)

0Ω

C5

1nF

C6

1nF

REF_IN

MUXOUT

LON

LOP

34 22 17 10 1

36

37

38

ADRF6601

×2

6

÷2

÷4

8

of 1 V (0.353 V rms

IN

C7

C25

0.1µF

(0402)

R6

R26

0Ω

(0402)

C8

C24

100pF

(0402)

VCC_MIXVCC_V2IVCC_LO

27

FRACTIO N

REG

THIRD-ORDER

FRACTIONAL

INTERPO LATOR

MUX

TEMP

SENSOR

1174 2015 2321 2524 3038 3531

Figure 46. Basic Connections for Operation of the ADRF6601

C23

C20

0.1µF

(0402)

R25 0Ω (0402)

(ORANG E)

R24 0Ω (0402)

C22

C21

100pF

(0402)

VCC_LO VCC2 VCC1

N COUNTER

21 TO 123

–

PHASE

+

FREQUENCY

DETECTOR

CP

TEST

POINT

INTEGER

REG

R38

0Ω

(0402)

C14

22pF

(0603)

C43

10µF

(0603)

MODULUS

R37

0Ω

(0402)

R11 OPEN (0402)

R17 0Ω (0402)

R9 10kΩ

OPEN (0402)

be ac-coupled and terminated with a 50 Ω resistor as shown in Figure 46. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin.

The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options section.

Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary.

P1

89

R57 0Ω (0402)

CLK

DATA

13 12

SPI

INTERFACE

1840393

VCC

+5V

195

LE

14

9-PIN DSUB

R36 0Ω (0402)

IFNIFP

DECL2P5

9

DECL3P3

2

RF

26

IP3SET

29

R59

0Ω

(0402)

C29

0.1µF (0402)

C34 OPEN (0402)

C33 OPEN (0402)

C32 OPEN (0402)

IN

C16 100pF (0402)

C12 100pF (0402)

R28

0Ω

(0402)

R27

(0402)

14

2

3

R52 OPEN (0402)

R51 OPEN (0402)

R50 OPEN (0402)

(0402)

0Ω

(0402)

5

R18

R43

0Ω

R8 0Ω

RFIN

C27

0.1µF (0402)

0Ω

VCC

R54 10kΩ (0402)

S2

R53

10kΩ

(0402)

C19

C9

0.1µF

(0402)

R7 0Ω (0402)

C18

C10

100pF

(0402)

BUFFER

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA ( DEFAULT), 750µA, 1000µA

R

SET

R2 OPEN (0402)

R65 10 kΩ

(0402)

R10

3.0kΩ

C13

(0603)

6.8pF

C15

(0603)

2.7nF (1206)

R1 0Ω

(0402)

C2

C1 100pF (0402)

R20

0Ω

(0402)

C40 22pF (0603)

R12 0Ω (0402)

2 4 61357

R19

0Ω

(0402)

DIVIDER

÷2

DIV

2:1

MUX

4, 2, 1

VCO

CORE

VTUNE

CP

R62 0Ω (0402)

BY

R35 0Ω (0402)

DECLVCO

R63 OPEN (0402)

R30 0Ω (0402)

PLL_EN

16

VTUNE

C17

0.1µF (0402)

C11

0.1µF (0402)

RFOUT

C42 10µF (0603)

C41 OPEN (0603)

08546-046

Rev. A | Page 22 of 32

ADRF6601

A

AC TEST FIXTURE

Characterization data for the ADRF6601 was taken under very strict test conditions. All possible techniques were used to achieve optimum accuracy and to remove degrading effects of

ALL INSTRUMENTS ARE CONTROLLED BY A LAB COMPUTER VIA A USB TO GPIB CONTROLLER, DAISY CHAINED TO EACH INDIVIDUAL INSTRUMENT.

RF1 AGILENT N5181A

HP 11636A

POWER DIVI DER

RF2 AGILENT N5181A

REF_IN AGILENT N5181A

REF_IN

DRF6601 CHARACTERIZATI ON RACK DIAGRAM.

the signal generation and measurement equipment. Figure 47 shows the typical ac test setup used in the characterization of the ADRF6601.

RF

IN

ADRF6601

EVALUATION BOARD

IF_OUT

ROHDE & SCHWARTZ

FSEA30

AGILENT 34401A SET TO IDC

(SET FOR SUPPLY CURRENT)

5V dc VIA

10-PIN DC HEADER

AGILENT 34980A WITH THREE 34921 MODUL ES

AND ONE 34950 MODULE

5V dc MEASURED FOR SUPPLY CURRENT

10-PIN DC HEADER

9-PIN CONTRO LLER DSUB AND

GND VIA 10-PIN DC HEADER

3.3V dc VI A 10-PIN DC HEADER

AGILENT E3631A 25V SET TO

3.3V, 6V SET TO 5V. RETURNS ARE

JUMPERED TOGETHER

08546-047

Figure 47. ADRF6601 AC Test Setup

Rev. A | Page 23 of 32

ADRF6601

EVALUATION BOARD

Figure 50 shows the schematic of the RoHS-compliant evaluation board for the ADRF6601. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material.

The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6—VCO Control and VCO Enable (Default: 0x1E2106) section).

Additional configuration options for the evaluation board are described in Ta bl e 10 .

EVALUATION BOARD CONTROL SOFTWARE

Software to program the ADRF6601 is available for download from the ADRF6601 product page under the Evaluation Boards & Kits section. To install the software

Download and extract the zip file:

1. ADRF6x0x_3p0p0_XP_install.exe file.

Follow the instructions in the read me file.

2.

The evaluation board can be connected to the PC using a PC USB port.

To connect the evaluation board to a USB port, a USB adapter board (EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices.

This board connects to the PC using a standard USB cable with a USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the EVAL-ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6601 evaluation board.

Figure 48. Control Software Opening Menu

Figure 49 shows the main window of the control software with the default settings displayed.

08546-053

Rev. A | Page 24 of 32

ADRF6601

08546-049

Figure 49. Main Window of the ADRF6601 Evaluation Board Software

Rev. A | Page 25 of 32

ADRF6601

SCHEMATIC AND ARTWORK

T7

GND2

GND1

GND

VCC

1

VCC

VCC_BB

VCC_LO

VCC_RF

AGNDAGND

6A

11A22A3

P1-T7

1

AGND

VCC_SENSE

SNS1

SNS

0

R32

0

R31

0

R29

LO

AGND

P4-T7

44A55A6

T8

3A

153

P3-T7

P4-T7

P1-6

9J1

10J1

VCO_LDO

LO_EXTERN

C28

AGND

10UF

AGND

0

R69

VCC_LO

P1-T7

4

2

NC

LO_EXTERN

P3-T7

0

R72

VTUNE

5J1

6J1

7J1

8J1

2P5V_LDO

3P3V_LDO

0

R66

R67

R68

0 DNI

IP3SET

OUTPUT_EN

VCC_LO

1

C7

0.1UF

0

R6

AGND AGND

C8

100PF

R63

100K

AGND

10K

R65R9

10K

0

R38

1

CP

1J1

2J1

3J1

4J1

AGND

TC4-1W

3

VCC

AGND

VCC_SENSE

0

IP3SE T

0

R33

1NF

C6 C5

1NF

3K

R10

R56

10K

AGND

2

VCC

1

VCC1

0

R62

22PF

C40

C13

6.8PF

C15

2.7NF

C14

22PF

0

R37

VCC4

1

3

S1

10K

R55

0

R12

VCO_LDO

1

DNI

AGND

R11

100PF

C10

0

R7

AGND AGND

0.1UF

C9

1

VCC

AGND

OUT

0

R43

VCC_BB

TBD

R27

1

IP3SET

AGND

0

R1

VCO_LDO

1

3P3V1

VCC_RF

C27

0.1UF

R60

TBD

AGND AGND

AGND

31323334353637383940

INBB IPBB

GND

LON LOP

AGND

100PF

C1

AGND

C43

C2

0.1UF

AGND

R49

DNI

AGND

C12

100PF

0

R8

AGND

C11

0.1UF

AGND

C41

10UF

2

461

T3

VCC_RF

1

C25

0.1UF

0

R26

C24

100PF

27

28

29

30

VCCRF

GNDRF

IP3SET

GNDBB

VCC_LO

LOEXTEN

VCO_IN

VCO_LDO

3P3_LDO

VCC

CPOUT

GNDCP

123456789

10UF

0

C4

R15

1

OSC_3P3V

AGND

26

RFIN

Z1

RSET

R2

AGND

22000PF

RFIN

0

R28

24

25

RFRTNNCGNDRF

REF_IN

REFGND

DNI

Y1

10PF

C3

R59

0

VCC

R44

AGND

GNDBB IFN IFP VCC_LO OUTPUTEN GNDDIG LE CLK DATA GNDDIG

DNI

IFP

AGND

R47

C35

DNI

L1

TBD

VCC

AGND

0

13 14 17 19

11 12 15 16 18 20

0

AGND

R35

R19

C32

100PF DNI

AGND

P1-11

1

R50

1K DNI

P1

CLK

C16

100PF

0

R18

C17

0.1UF

1

2P5V

10UF

C42

2P5V_LDO

AGND

0

R48

C36

L2

VCC

DNI

R58

VCC_LO1

0

R34

0

R20

1

DATA

0

R30

P1-6

2345678

AGND

R17

AGND

1

VCC2

AGND

IFN

1

R57

VCC

AGND

DNI

TBD

VCC_LO

AGNDAGND

C20

0.1UF

0

R24

C21

100PF

OUTPUT_EN

R54

3

1

2

S2

AGND

100PF DNI

C33

1

0

DIG_GND

R36

9

AMP745781-4

100PF

C18

0

0.1UF

C19

AGND

R51

1K DNI

AGND

1

VCC

AGND

R53

10K 10K

1

C34

100PF DNI

AGND

R52

1K DNI

AGND

C29

0.1UF

AGND

VCC_BB

1

C23

VCC_BB1

0.1UF

0

R25

AGND AGND

C22

100PF

22

23

21

PAD

E-PAD

GNDRF

VCCBB

2P5_LDO

REFOUT/LOCK

VCC

10

AGND

P1-1

TBD R71

R16

REFOUT

DNI R14

C31

1000PF

AGND

R70

49.9

REFIN

08546-050

VCC5

LE

3P3V_LDO

Figure 50. Evaluation Board Schematic

Rev. A | Page 26 of 32

ADRF6601

08546-051

Figure 51. Evaluation Board Layout (Bottom)

Figure 52. Evaluation Board Layout (Top)

08546-052

Rev. A | Page 27 of 32

ADRF6601

EVALUATION BOARD CONFIGURATION OPTIONS

Table 10.

Default Condition/

Component Description

S1, R55, R56, R33

LO IN/OUT SMA Connector

REFIN SMA Connector

REFOUT SMA Connector

CP Test Point

R37, C14, R9, R10, C15, C13, R65, C40

R11, R12

R62, R63, VTUNE SMA Connector

R2 R RFIN SMA Connector

T3

LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information).

LO input/output. An external 1× LO or 2× LO signal can be applied to this single-ended input connector.

Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 Ω.

Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REF_IN, 2× REF_IN, REF_IN/2, and REF_IN/4; temperature sensor output voltage; and lock detect indicator.

Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise.

Loop filter. Loop filter components.

Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 Ω resistor in R11.

Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector.

pin. This pin is unused and should be left open. R2 = open (0402)

SET

RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6601 is ac-coupled; therefore, no bias is necessary.

IF output. The differential IF output signals from the ADRF6601 (IFP and IFN) are converted to a single-ended signal by T3.

Option Settings

S1 = R55 = open (not installed), R56 = R33 = 0 Ω, LODRV_EN = 0 V

LO input

Lock detect

R12 = 0 Ω (0402), R11 = open (0402)

R62 = 0 Ω (0402), R63 = open (0402)

R3 = R23 = open (0402)

Rev. A | Page 28 of 32

ADRF6601

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50 BSC

0.50

0.40

0.30

0.08

0.60 MAX

31

30

EXPOSED

(BOTTOM VIEW)

21

20

40

1

PAD

10

11

4.50 REF

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION O F THIS DAT A SHEET.

PIN 1 INDICATOR

4.25

4.10 SQ

3.95

0.25 MIN

072108-A

Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADRF6601ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 ADRF6601-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. A | Page 29 of 32

ADRF6601

NOTES

Rev. A | Page 30 of 32

ADRF6601

NOTES

Rev. A | Page 31 of 32

ADRF6601

NOTES

Rev. A | Page 32 of 32

Datasheet ADRF6601 Datasheet (ANALOG DEVICES)

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

RF SPECIFICATIONS

SYNTHESIZER/PLL SPECIFICATIONS

LOGIC INPUT AND POWER SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

RF FREQUENCY SWEEP

IF FREQUENCY SWEEP

SPURIOUS PERFORMANCE

REGISTER STRUCTURE

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

THEORY OF OPERATION

INITIALIZATION SEQUENCE

PROGRAMMING THE ADRF6601

LO SELECTION LOGIC

APPLICATIONS INFORMATION

BASIC CONNECTIONS FOR OPERATION

AC TEST FIXTURE

EVALUATION BOARD

EVALUATION BOARD CONTROL SOFTWARE

SCHEMATIC AND ARTWORK

EVALUATION BOARD CONFIGURATION OPTIONS

OUTLINE DIMENSIONS

ORDERING GUIDE