Ultracompact SC70 and SOT-23-3 packages
Temperature coefficient: 40 ppm/°C (maximum)
2× the temperature coefficient improvement over the
LM4040
Pin compatible with the LM4040/LM4050
Initial accuracy: ±0.2%
Low output voltage noise: 18 μV p-p @ 2.5 V output
No external capacitor required
Operating current range: 50 μA to 15 mA
Industrial temperature range: −40°C to +85°C
APPLICATIONS
Portable, battery-powered equipment
Automotive
Power supplies
Data acquisition systems
Instrumentation and process control
Energy measurement
Figure 1. 3-Lead SC70 (KS) and 3-Lead SOT-23-3 (RT)
GENERAL DESCRIPTION
Designed for space-critical applications, the ADR525/ADR530/
ADR550 are high precision shunt voltage references, housed in
ultrasmall SC70 and SOT-23-3 packages. These references feature
low temperature drift of 40 ppm/°C, an initial accuracy of better
than ±0.2%, and ultralow output noise of 18 μV p-p.
Available in output voltages of 2.5 V, 3.0 V, and 5.0 V, the
advanced design of the ADR525/ADR530/ADR550 eliminates
the need for compensation by an external capacitor, yet the
references are stable with any capacitive load. The minimum
operating current increases from a mere 50 μA to a maximum
of 15 mA. This low operating current and ease of use make
these references ideally suited for handheld, battery-powered
applications.
A trim terminal is available on the ADR525/ADR530/ADR550
to allow adjustment of the output voltage over a ±0.5% range,
without affecting the temperature coefficient of the device. This
feature provides users with the flexibility to trim out small
system errors.
For better initial accuracy and wider temperature range, see the
ADR5040/ADR5041/ADR5043/ADR5044/ADR5045 family at
www.analog.com.
TRIM
3
04501-001
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Change to Ordering Guide............................................................ 14
11/03—Revision 0: Initial Version
Rev. F | Page 2 of 12
Page 3
ADR525/ADR530/ADR550
SPECIFICATIONS
ADR525 ELECTRICAL CHARACTERISTICS
IIN = 50 μA to 15 mA, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage V
Grade A 2.490 2.500 2.510 V
Grade B 2.495 2.500 2.505 V
Initial Accuracy V
Grade A ±0.4% −10 +10 mV
Grade B ±0.2% −5 +5 mV
Temperature Coefficient1 TCVO −40°C < TA < +85°C
Grade A 25 70 ppm/°C
Grade B 15 40 ppm/°C
Output Voltage Change vs. IIN ∆VR IIN = 0.1 mA to 15 mA 1 mV
−40°C < TA < +85°C 4 mV
I
Dynamic Output Impedance (∆VR/∆IR) IIN = 0.1 mA to 15 mA 0.2 Ω
Minimum Operating Current IIN −40°C < TA < +85°C 50 μA
Voltage Noise e
Turn-On Settling Time tR 2 μs
Output Voltage Hysteresis ∆V
1
Guaranteed by design, but not production tested.
OUT
OERR
= 1 mA to 15 mA, −40°C < TA < +85°C 2 mV
IN
0.1 Hz to 10 Hz 18 μV p-p
N p-p
IIN = 1 mA 40 ppm
OUT_HYS
ADR530 ELECTRICAL CHARACTERISTICS
IIN = 50 μA to 15 mA, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage V
Grade A 2.988 3.000 3.012 V
Grade B 2.994 3.000 3.006 V
Initial Accuracy V
Grade A ±0.4% −12 +12 mV
Grade B ±0.2% −6 +6 mV
Temperature Coefficient1 TCVO −40°C < TA < +85°C
Grade A 25 70 ppm/°C
Grade B 15 40 ppm/°C
Output Voltage Change vs. IIN ∆VR IIN = 0.1 mA to 15 mA 1 mV
−40°C < TA < +85°C 4 mV
I
Dynamic Output Impedance (∆VR/∆IR) IIN = 0.1 mA to 15 mA 0.2 Ω
Minimum Operating Current IIN −40°C < TA < +85°C 50 μA
Voltage Noise e
Turn-On Settling Time tR 2 μs
Output Voltage Hysteresis ∆V
1
Guaranteed by design, but not production tested.
OUT
OERR
= 1 mA to 15 mA, −40°C < TA < +85°C 2 mV
IN
0.1 Hz to 10 Hz 22 μV p-p
N p-p
IIN = 1 mA 40 ppm
OUT_HYS
Rev. F | Page 3 of 12
Page 4
ADR525/ADR530/ADR550
ADR550 ELECTRICAL CHARACTERISTICS
IIN = 50 μA to 15 mA, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage V
Grade A 4.980 5.000 5.020 V
Grade B 4.990 5.000 5.010 V
Initial Accuracy V
Grade A ±0.4% −20 +20 mV
Grade B ±0.2% −10 +10 mV
Temperature Coefficient1 TCVO −40°C < TA < +85°C
Grade A 25 70 ppm/°C
Grade B 15 40 ppm/°C
Output Voltage Change vs. IIN ∆VR IIN = 0.1 mA to 15 mA 1 mV
−40°C < TA < +85°C 5 mV
I
Dynamic Output Impedance (∆VR/∆IR) IIN = 0.1 mA to 15 mA 0.2 Ω
Minimum Operating Current IIN −40°C < TA < +85°C 50 μA
Voltage Noise e
Turn-On Settling Time tR 2 μs
Output Voltage Hysteresis ∆V
1
Guaranteed by design, but not production tested.
OUT
OERR
= 1 mA to 15 mA, −40°C < TA < +85°C 2 mV
IN
0.1 Hz to 10 Hz 38 μV p-p
N p-p
IIN = 1 mA 40 ppm
OUT_HYS
Rev. F | Page 4 of 12
Page 5
ADR525/ADR530/ADR550
ABSOLUTE MAXIMUM RATINGS
Ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 5.
Parameter Rating
Reverse Current 25 mA
Forward Current 20 mA
Storage Temperature Range −65°C to +150°C
Industrial Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Package Type θ
3-Lead SC70 (KS) 580.5 177.4 °C/W
3-Lead SOT-23-3 (RT) 270 102 °C/W
1
θJA is specified for worst-case conditions, such as for devices soldered on
circuit boards for surface-mount packages.
1
θJC Unit
JA
ESD CAUTION
Rev. F | Page 5 of 12
Page 6
ADR525/ADR530/ADR550
PARAMETER DEFINITIONS
TEMPERATURE COEFFICIENT
Temperature coefficient is defined as the change in output
voltage with respect to operating temperature changes and is
normalized by the output voltage at 25°C. This parameter is
expressed in ppm/°C and is determined by the following
equation:
TCV
where:
V
OUT(T2
V
OUT(T1
V
(25°C) = V
OUT
O
) = V
) = V
ppm
⎤
⎡
⎢
⎣
=
⎥
C
°TTV
⎦
OUT
at Temperature 2.
OUT
at Temperature 1.
OUT
at 25°C.
OUT
−
)()(
TVTV
12
OUTOUT
−×°
6
×
10
(1)
)(C)25(
12
THERMAL HYSTERESIS
Thermal hysteresis is defined as the change in output voltage
after the device is cycled through temperatures ranging from
+25°C to −40°C, then to +85°C, and back to +25°C. The
following equation expresses a typical value from a sample of
parts put through such a cycle:
−°=
C)25(
VVV
__
ENDOUTOUTHYSOUT
−°
C)25(
OUT
VV
°
C)25(
_
HYSOUT
[ppm]
V
V
=
where:
V
OUT
V
OUT_END
(25°C) = V
= V
at 25°C.
OUT
at 25°C after a temperature cycle from +25°C to
OUT
−40°C, then to +85°C, and back to +25°C.
_
ENDOUTOUT
(2)
6
×
10
Rev. F | Page 6 of 12
Page 7
ADR525/ADR530/ADR550
TYPICAL PERFORMANCE CHARACTERISTICS
5.5
= 25°C
T
A
5.0
4.5
4.0
3.5
3.0
2.5
2.0
REVERSE VOLTAGE (V)
1.5
1.0
0.5
0
025
MINIMUM OPERATING CURRENT (µA)
Figure 2. Reverse Characteristics and Minimum Operating Current
8
ADR550
ADR530
ADR525
5075100
VIN = 2V/DIV
V
= 1V/DIV
OUT
IIN = 10mA
TIME (µs)
04501-006
4µs/DIV
04501-010
Figure 5. ADR525 Turn-On Response
6
4
2
= +25°C
T
A
0
REVERSE VOLTAGE CHANGE (mV)
= +85°C
T
–2
03
A
612
915
IIN (mA)
Figure 3. ADR525 Reverse Voltage vs. Operating Current
8
7
6
5
4
3
2
REVERSE VOLTAGE CHANGE (mV)
1
0
06
TA = –40°C
39
T
= +25°C
A
IIN (mA)
= +85°C
T
A
1215
Figure 4. ADR550 Reverse Voltage vs. Operating Current
T
= –40°C
A
VIN = 2V/DIV
V
= 1V/DIV
OUT
IIN = 100µA
04501-008
TIME (µs)
4µs/DIV
04501-011
Figure 6. ADR525 Turn-On Response
VIN = 2V/DIV
V
= 2V/DIV
OUT
IIN = 10mA
TIME (µs)
04501-009
4µs/DIV
04501-014
Figure 7. ADR550 Turn-On Response
Rev. F | Page 7 of 12
Page 8
ADR525/ADR530/ADR550
2.5030
VIN = 2V/DIV
IIN = 100µA
TIME (µs)
Figure 8. ADR550 Turn-On Response
∆I = 1mA/DIV
I
= 1mA
IN
10µs/DIV
TIME (µs)
Figure 9. ADR525 Load Transient Response
V
OUT
V
OUT
= 2V/DIV
20µs/DIV
= 50mV/DIV
04501-015
04501-016
2.5025
2.5020
2.5015
2.5010
(V)
2.5005
OUT
V
2.5000
2.4995
2.4990
2.4985
2.4980
–40–1510356085
TEMPERATURE (°C)
Figure 11. Data for Five Parts of ADR525 V
3.0055
3.0050
3.0045
3.0040
3.0035
3.0030
(V)
OUT
3.0025
V
3.0020
3.0015
3.0010
3.0005
3.0000
–40–1510356085
TEMPERATURE (°C)
Figure 12. Data for Five Parts of ADR530 V
over Temperature
OUT
over Temperature
OUT
04501-018
04501-019
5.008
5.006
∆I = 1mA/DIV
= 10mA
I
IN
V
OUT
10µs/DIV
TIME (µs)
Figure 10. ADR550 Load Transient Response
= 50mV/DIV
04501-017
5.004
5.002
5.000
(V)
4.998
OUT
V
4.996
4.994
4.992
4.990
4.988
–40–1510356085
TEMPERATURE (°C)
Figure 13. Data for Five Parts of ADR550 V
over Temperature
OUT
04501-020
Rev. F | Page 8 of 12
Page 9
ADR525/ADR530/ADR550
V
V
V
−
V
THEORY OF OPERATION
The ADR525/ADR530/ADR550 use the band gap concept to
produce a stable, low temperature coefficient voltage reference
suitable for high accuracy data acquisition components and
systems. The devices use the physical nature of a silicon transistor
base-emitter voltage (V
) in the forward-biased operating region.
BE
All such transistors have approximately a −2 mV/°C temperature coefficient (TC), making them unsuitable for direct use as
low temperature coefficient references. Extrapolation of the
temperature characteristics of any one of these devices to
absolute zero (with the collector current proportional to the
absolute temperature), however, reveals that its V
approaches
BE
approximately the silicon band gap voltage. Thus, if a voltage
develops with an opposing temperature coefficient to sum the
, a zero temperature coefficient reference results. The
V
BE
ADR525/ADR530/ADR550 circuit shown in Figure 14 provides
such a compensating voltage (V1) by driving two transistors at
different current densities and amplifying the resultant V
difference (ΔV
The sum of V
, which has a positive temperature coefficient).
BE
and V1 provides a stable voltage reference over
BE
BE
temperature.
+
V1
+
•
Given these conditions, R
voltage (V
the ADR525/ADR530/ADR550, and the output voltage (V
of the ADR525/ADR530/ADR550.
Precision Negative Voltage Reference
The ADR525/ADR530/ADR550 are suitable for applications
where a precise negative voltage is desired. Figure 16 shows the
ADR525 configured to provide a negative output.
S
+ I
I
IN
R
I
IN
L
I
L
ADR550
V
OUT
04501-003
Figure 15. Shunt Reference
is determined by the supply
BIAS
), the load and operating currents (IL and IIN) of
S
)
OUT
VV
S
R
= (3)
BIAS
OUT
II
+
INL
ADR525
–2.5V
R
–
+
∆
V
BE
–
+
BE
–
V–
04501-002
Figure 14. Circuit Schematic
APPLICATIONS
The ADR525/ADR530/ADR550 are a series of precision shunt
voltage references. They are designed to operate without an
external capacitor between the positive and negative terminals.
If a bypass capacitor is used to filter the supply, the references
remain stable.
All shunt voltage references require an external bias resistor (R
between the supply voltage and the reference (see Figure 15).
sets the current that flows through the load (IL) and the
R
BIAS
reference (I
needs to be chosen based on the following considerations:
R
BIAS
• R
). Because the load and the supply voltage can vary,
IN
must be small enough to supply the minimum I
BIAS
current to the ADR525/ADR530/ADR550, even when the
supply voltage is at its minimum value and the load current
is at its maximum value.
• R
must be large enough so that IIN does not exceed
BIAS
15 mA when the supply voltage is at its maximum value
and the load current is at its minimum value.
The trim terminal of the ADR525/ADR530/ADR550 can be
used to adjust the output voltage over a range of ±0.5%. This
allows systems designers to trim small system errors by setting
the reference to a voltage other than the preset output voltage.
An external mechanical or electrical potentiometer can be used
for this adjustment. Figure 17 illustrates how the output voltage
can be trimmed using the AD5273, an Analog Devices, Inc.,
10 kΩ potentiometer.
S
)
ADR530
R
V
OUT
R1
470kΩ
AD5273
POTENTIOMETER
10kΩ
Figure 17. Output Voltage Trim
04501-005
Rev. F | Page 9 of 12
Page 10
ADR525/ADR530/ADR550
V
G
A
V
Stacking the ADR525/ADR530/ADR550 for
User-Definable Outputs
Multiple ADR525/ADR530/ADR550 parts can be stacked to
allow the user to obtain a desired higher voltage. Figure 18 shows
three ADR550s configured to give 15 V. The bias resistor, R
BIAS
, is
chosen using Equation 3; note that the same bias current flows
through all the shunt references in series. Figure 19 shows three
ADR550s stacked to give −15 V. R
is calculated in the same
BIAS
manner as for Figure 18. Parts of different voltages can also be
added together. For example, an ADR525 and an ADR550 can
be added together to give an output of +7.5 V or −7.5 V, as
desired. Note, however, that the initial accuracy error is now the
sum of the errors of all the stacked parts, as are the temperature
coefficients and output voltage change vs. input current.
+
DD
R
+15V
ADR550
ADR550
ADR550
GND
04501-022
Figure 18. +15 V Output with Stacked ADR550s
ADR550
ADR550
ND
ADR550
–15V
R
Adjustable Precision Voltage Source
The ADR525/ADR530/ADR550, combined with a precision low
input bias op amp, such as the AD8610, can be used to output a
precise adjustable voltage. Figure 20 illustrates the implementation
of this application using the ADR525/ADR530/ADR550. The
output of the op amp, V
, is determined by the gain of the circuit,
OUT
which is completely dependent on the resistors, R1 and R2.
V
= V
OUT
(1 + R2/R1)
REF
An additional capacitor, C1, in parallel with R2, can be added to
filter out high frequency noise. The value of C1 is dependent on
the value of R2.
S
R
V
REF
DR5xx
GND
R1
AD8610
R2
C1
(OPTIONAL)
V
= V
OUT
(1+R2/R1)
REF
04501-023
Figure 20. Adjustable Voltage Source
–V
DD
04501-024
Figure 19. −15 V Output with Stacked ADR550s
Rev. F | Page 10 of 12
Page 11
ADR525/ADR530/ADR550
OUTLINE DIMENSIONS
2.20
2.00
1.35
1.25
1.15
1.00
0.80
1.80
21
0.65 BSC
2.40
2.10
1.80
1.10
0.80
0.40
0.10
3
0.10 MAX
COPLANARITY
0.10
0.40
0.25
ALL DIMENSIONS COMPLIANT WITH EIAJ SC70
SEATING
PLANE
0.26
0.10
0.30
0.20
0.10
072809-A
Figure 21. 3-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-3)
Dimensions shown in millimeters
3.04
2.90
2.80
1.40
1.30
1.20
1.02
0.95
0.88
0.100
0.013
SEATING
PLANE
0.60
0.45
3
1
2.05
1.78
2.64
2.10
2
1.03
0.89
0.54
REF
0.60 MAX
0.30 MIN
0.51
0.37
1.12
0.89
GAUGE
PLANE
0.180
0.085
0.25
COMPLIANT TO JEDEC STANDARDS TO -236-AB
Figure 22. 3-Lead Small Outline Transistor Package [SOT-23-3]