Page 1
+5 V Fixed, Adjustable
a
FEATURES
Low-Dropout: 150 mV @ 200 mA
Low Power CMOS: 20 µA Quiescent Current
Shutdown Mode: 0.2 µA Quiescent Current
250 mA Output Current
Pin Compatible with MAX667
Stable with 10 µF Load Capacitor
Low Battery Detector
Fixed +5 V or Adjustable Output
+3.5 V to +16.5 V Input Range
Dropout Detector Output
APPLICATIONS
Handheld Instruments
Cellular Telephones
Battery Operated Devices
Portable Equipment
Solar Powered Instruments
High Efficiency Linear Power Supplies
Low-Dropout Linear Voltage Regulator
ADP667
FUNCTIONAL BLOCK DIAGRAM
OUT
DD
SET
SHDN
LBO
LBI
GND
IN
ADP667
A1
C1
C2
1.255V
REF
50mV
GENERAL DESCRIPTION
The ADP667 is a low-dropout precision voltage regulator that
can supply up to 250 mA output current. It can be used to give
a fixed +5 V output with no additional external components or
can be adjusted from +1.3 V to +16 V using two external resistors. Fixed or adjustable operation is automatically selected via
the SET input. The low quiescent current (20 µA) in conjunc-
tion with the standby or shutdown mode (0.2 µA) makes this
device especially suitable for battery powered systems. The
dropout voltage when supplying 100 µA is only 5 mV allowing
operation with minimal headroom and prolonging the battery
useful life. At higher output current levels the dropout remains
low increasing to just 150 mV when supplying 200 mA. A wide
input voltage range from 3.5 V to 16.5 V is allowable.
Additional features include a dropout detector and a low supply/
battery monitoring comparator. The dropout detector can be
used to signal loss of regulation, while the low battery detector
can be used to monitor the input supply voltage.
The ADP667 is a pin-compatible replacement for the MAX667.
It is specified over the industrial temperature range –40°C to
+85°C and is available in an 8-pin DIP and in narrow surface
mount (SOIC) packages.
TYPICAL OPERATING CIRCUIT
+6V
INPUT
IN
+
OUT
ADP667
GNDSET SHDN
+5V
+
OUTPUT
C1
10µF
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADP667AN –40°C to +85°C 8-Pin Plastic DIP N-8
ADP667AR –40°C to +85°C 8-Lead SOIC SO-8
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
ADP667–SPECIFICATIONS
(VIN = +9 V, GND = 0 V, V
otherwise noted)
= +5 V, C
OUT
= 10 µF, T
L
A
= T
MIN
to T
MAX
unless
Parameter Min Typ Max Units Test Conditions/Comments
Input Voltage, V
IN
Output Voltage, V
OUT
3.5 16.5 V
4.8 5.0 5.2 V V
= 0 V, VIN = 6 V, I
SET
Maximum Output Current 250 mA VIN = +6 V, +4.5 V < V
Quiescent Current
: Shutdown Mode 0.2 1 µAV
I
GND
2 µAT
I
: Normal Mode V
GND
20 25 µAI
20 30 µAI
515 mAI
35 µAI
50 µAI
20 mA I
Dropout Voltage 5 60 mV I
75 mV T
150 250 mV I
350 mV TA = T
Load Regulation 50 100 mV I
250 mV T
Line Regulation 5 10 mV VIN = 6 V to 10 V, I
15 mV TA = T
SET Reference Voltage, V
SET Input Leakage Current, I
SET
SET
1.23 1.255 1.28 V
±0.01 ±10 nA V
±1000 nA T
Output Leakage Current, I
Short-Circuit Current, I
OUT
OUT
0.1 1 µAV
400 mA T
450 mA TA = T
Low Battery Detector Input Threshold, V
LBI Input Leakage Current, I
LBI
1.215 1.255 1.295 V
LBI
±0.01 ±10 nA V
±1000 nA T
Low Battery Detector Output Voltage, V
LBO
0.25 V V
0.40 V TA = T
Shutdown Input Threshold Voltage, V
Shutdown Input Leakage Current, I
SHDN
SHDN
1.5 V
±0.01 ±10 nA V
±1000 nA T
Dropout Detector Output Voltage 0.25 V (V
4.0 (V
Specifications subject to change without notice.
= 2 V, T
SHDN
= T
A
MIN
= 0 V, V
SHDN
= 0 µA
OUT
= 100 µA
OUT
= 200 mA
OUT
T
= T
A
MIN
= 0 µA
OUT
= 100 µA
OUT
= 200 mA
OUT
= 100 µA, TA = +25°C
OUT
= T
A
MIN
= 200 mA, T
OUT
MIN
= 10 mA–200 mA, VIN = 6 V, T
OUT
= T
A
MIN
MIN
= 1.5 V, T
SET
= T
A
MIN
= 2 V
SHDN
= +25°C
A
MIN
= 1.5 V, T
LBI
= T
A
MIN
< 1.215 V, I
LBI
MIN
= 0 V to VIN, T
SHDN
= T
A
MIN
= 0 V, V
SET
V
= 7 V, I
IN
= 0 V, V
SET
VIN = 4.5 V, I
to T
to T
to T
to T
to T
to T
to T
to T
to T
to T
to T
SHDN
OUT
SHDN
OUT
= +25°C
A
MAX
= 0 V, T
SET
MAX
MAX
= +25°C
A
MAX
MAX
OUT
MAX
= +25°C
A
MAX
MAX
= +25°C
A
MAX
= 10 mA, T
LBO
MAX
A
MAX
= 0 V, R
= 10 mA)
= 0 V, R
= 10 mA)
= 10 mA
OUT
< +5.5 V
OUT
= +25°C
A
= 10 mA, T
= +25°C
A
= +25°C
= 100 kΩ
DD
= 100 kΩ
DD
= +25°C
A
= +25°C
A
ABSOLUTE MAXIMUM RATINGS*
(T
= +25°C unless otherwise noted)
A
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18 V
Output Short Circuit to GND Duration . . . . . . . . . . . . . . 1 sec
LBO Output Sink Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
LBO Output Voltage . . . . . . . . . . . . . . . . . . . . . GND to V
OUT
SHDN Input Voltage . . . . . . . . . . . . . . . . –0.3 V (VIN + 0.3 V)
LBI, SET Input Voltage . . . . . . . . . . . . . –0.3 V (V
+ 0.3 V)
IN
Power Dissipation, N-8 . . . . . . . . . . . . . . . . . . . . . . . . 625 mW
(Derate 8.3 mW/°C above +50°C)
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 120°C/W
θ
JA
Power Dissipation, SO-8 . . . . . . . . . . . . . . . . . . . . . . . 450 mW
(Derate 6 mW/°C above +50°C)
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W
θ
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 6000 V
*This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
–2–
REV. 0
Page 3
ADP667
ADP667
IN
SHDN
LBO
LBI
GND
50mV
SET
DD
OUT
1.255V
REF
A1
C1
C2
PIN FUNCTION DESCRIPTION
Mnemonic Function
DD Dropout Detector Output. PNP collector output
GENERAL INFORMATION
The ADP667 contains a micropower bandgap reference voltage
source, an error amplifier A1, two comparators (C1, C2) and a
series PNP output pass transistor.
which sources current as dropout is reached.
V
IN
Voltage Regulator Input.
GND Ground Pin. Must be connected to 0 V.
LBI Low Battery Detect Input. Compared with 1.255 V.
LBO Low Battery Detect Output. Open Drain Output
that goes low when LBI is below the threshold.
SHDN Digital Input. May be used to disable the device
so that the power consumption is minimized.
SET Voltage Setting Input. Connect to GND for +5 V
output or connect to resistive divider for adjustable output.
OUT Regulated Output Voltage. Connect to filter
capacitor.
CIRCUIT DESCRIPTION
The internal bandgap voltage reference is trimmed to 1.255 V
and is used as a reference input to the error amplifier A1. The
feedback signal from the regulator output is supplied to the
other input by an on-chip voltage divider or by two external
resistors. When the SET input is at ground, the internal divider
provides the error amplifier’s feedback signal giving a +5 V output. When SET is at more than 50 mV above ground, comparator C1 switches the error amplifier’s input directly to the SET
pin, and external resistors are used to set the output voltage.
The external resistors are selected so that the desired output
voltage gives 1.255 V at the SET input.
The output from the error amplifier supplies base current to the
PNP output pass transistor which provides output current. Up
to 250 mA output current is available provided that the device
power dissipation is not exceeded.
DIP & SOIC PIN CONFIGURATION
Comparator C2 compares the voltage on the Low Battery Input,
LBI, pin to the internal +1.255 V reference voltage. The output
DD
OUT
LBI
GND
1
2
ADP667
TOP VIEW
3
(Not to Scale)
4
8
IN
7
LBO
6
SET
5
SHDN
from the comparator drives an open drain FET connected to the
Low Battery Output pin, LBO. The Low Battery Threshold
may be set using a suitable voltage divider connected to LBI.
When the voltage on LBI falls below 1.255 V, the open drain
output, LBO, is pulled low.
A shutdown (SHDN) input that can be used to disable the
error amplifier and hence the voltage output is also available.
The supply current in shutdown is less than 1 µA.
TERMINOLOGY
Dropout Voltage: The input/output voltage differential at
which the regulator no longer maintains regulation against further reductions in input voltage. It is measured when the output
decreases 100 mV from its nominal value. The nominal value is
the measured value with V
IN
= V
OUT
+2 V.
Line Regulation: The change in output voltage as a result of a
change in the input voltage. It is specified for a change of input
voltage from 6 V to 10 V.
Load Regulation: The change in output voltage for a change
in output current. It is specified for an output current change
from 10 mA to 200 mA.
Quiescent Current (I
): The input bias current which
GND
flows into the regulator not including load current. It is measured on the GND line and is specified in shutdown and also for
different values of load current.
Figure 1. ADP667 Functional Block Diagram
Shutdown: The regulator is disabled and power consumption
is minimized.
Dropout Detector: An output that indicates that the regulator
is dropping out of regulation.
Maximum Power Dissipation: The maximum total device
dissipation for which the regulator will continue to operate
within specifications.
REV. 0
–3–
Page 4
ADP667
APPLICATIONS INFORMATION
Circuit Configurations
For a fixed +5 V output the SET input should be grounded, and
no external resistors are necessary. This basic configuration is
shown in Figure 2. The input voltage can range from +5.15 V
to +16.5 V, and output currents up to 250 mA are available
provided that the maximum package power dissipation is not
exceeded.
IN
++
OUT
ADP667
GNDSET SHDN
C1
10µF
+5V
OUTPUT
Figure 2. Fixed +5 V Output Circuit
Output Voltage Setting
If the SET input is connected to a resistor divider network, the
output voltage is set according to the following equation:
OUT
SET
R1+ R2
×
R2
R1
R1
V
C1
10µF
OUT
+
where V
= 1.255 V.
SET
V
IN
V
OUT=VSET
IN
ADP667
SHDN
GND
Shutdown Input (SHDN)
The SHDN input allows the regulator to be switched off with a
logic level signal. This will disable the output and reduce the
current drain to a low quiescent (1 µA maximum) current. This
is very useful for low power applications. Driving the SHDN input to greater than 1.5 V places the part in shutdown.
If the shutdown function is not being used, then SHDN should
be connected to GND.
Low Supply or Low Battery Detection
The ADP667 contains on-chip circuitry for low power supply or
battery detection. If the voltage on the LBI pin falls below the
internal 1.255 V reference, then the open drain output LBO will
go low. The low threshold voltage may be set to any voltage
above 1.255 V by appropriate resistor divider selection.
V
BATT
R3 = R4 ×
V
LBI
where R3 and R4 are the resistive divider resistors and V
–1
is
BATT
the desired low voltage threshold.
Since the LBI input leakage current is less than 10 nA, large values may be selected for R3 and R4 in order to minimize loading.
For example, a 6 V low threshold, may be set using 10 MΩ for
R3 and 2.7 MΩ for R4.
The LBO output is an open-drain output that goes low sinking
current when LBI is less than 1.255 V. A pull-up resistor of
10 kΩ or greater may be used to obtain a logic output level with
the pull-up resistor connected to V
V
IN
IN
R3
R4
ADP667
LBI
OUT
LBO
GND SETSHDN
OUT
10kΩ
.
V
OUT
+
C1
10µF
LOW BATTERY
STATUS OUTPUT
Figure 3. Adjustable Output Circuit
The resistor values may be selected by first choosing a value for
R1 and then selecting R2 according to the following equation:
R2 = R1 ×
V
OUT
V
SET
−1
The input leakage current on SET is 10 nA maximum. This
allows large resistor values to be chosen for R1 and R2 with
little degradation in accuracy. For example, a 1 MΩ resistor
may be selected for R1, and then R2 may be calculated accord-
ingly. The tolerance on SET is guaranteed at less than ±25 mV,
so in most applications fixed resistors will be suitable.
Figure 4. Low Battery/Supply Detect Circuit
–4–
REV. 0
Page 5
ADP667
Dropout Detector
The ADP667 features an extremely low dropout voltage making
it suitable for low voltage systems where headroom is limited. A
dropout detector is also provided. The dropout detector output,
DD, changes as the dropout voltage approaches its limit. This is
useful for warning that regulation can no longer be maintained.
The dropout detector output is an open collector output from a
PNP transistor. Under normal operating conditions with the input voltage more than 300 mV above the output, the PNP transistor is off and no current flows out the DD pin. As the voltage
differential reduces to less than 300 mV, the transistor switches
on and current is sourced. This condition indicates that regulation
can no longer be maintained. Please refer to Figure 10 in the
“Typical Performance Characteristics.” The current output can
be translated into a voltage output by connecting a resistor from
DD to GND. A resistor value of 100 kΩ is suitable. A digital
status signal can be obtained using a comparator. The on-chip
comparator LBI may be used if it is not being used to monitor a
battery voltage. This is illustrated in Figure 5.
ADP667
GNDSET SHDN
OUT
LBO
DD
+
C1
10µF
R1
100kΩ
IN
+
V
IN
LBI
R2
10kΩ
+5V
OUTPUT
DROPOUT STATUS OUTPUT
Figure 5. Dropout Status Output
Output Capacitor Selection
An output capacitor is required on the ADP667 to maintain
stability and also to improve the load transient response. Ca-
pacitor values from 10 µF upwards are suitable. All specifica-
tions are tested and guaranteed with 10 µF. Capacitors larger
than 10 µF will further improve the dynamic transient response
characteristics of the regulator. Tantalum or aluminum electrolytics are suitable for most applications. For temperatures below
about –25°C, solid tantalums should be used as many alumi-
num electrolytes freeze at this temperature.
Quiescent Current Considerations
The ADP667 uses a PNP output stage to achieve low dropout
voltages combined with high output current capability. Under
normal regulating conditions the quiescent current is extremely
low. However if the input voltage drops so that it is below the
desired output voltage, the quiescent current increases considerably. This happens because regulation can no longer be main-
tained and large base current flows in the PNP output transistor
in an attempt to hold it fully on. For minimum quiescent current, it is therefore important that the input voltage is maintained higher than the desired output level. If the device is being
powered using a battery that can discharge down below the recommended level, there are a couple of techniques that can be
applied to reduce the quiescent current, but at the expense of
dropout voltage. The first of these is illustrated in Figure 6. By
connecting DD to SHDN the regulator is partially disabled with
input voltages below the desired output voltage and therefore
the quiescent current is reduced considerably.
+
V
IN
IN OUT
ADP667
DD
GNDSET SHDN
47kΩ
R1
+
C1
10µF
+5V
OUTPUT
C2
0.1µF
Figure 6. IQ Reduction 1
Another technique for reducing the quiescent current near dropout is illustrated in Figure 7. The DD output is used to modify
the output voltage so that as V
drops, the desired output volt-
IN
age setpoint also drops. This technique only works when external resistors are used to set the output voltage. With V
than V
, DD has no effect. As VINreduces and dropout is
OUT
IN
greater
reached, the DD output starts sourcing current into the SET
input through R3. This increases the SET voltage so that the
regulator feedback loop does not drive the internal PNP transistor as hard as it otherwise would. As the input voltage continues
to decrease, more current is sourced, thereby reducing the PNP
drive even further. The advantage of this scheme is that it maintains a low quiescent current down to very low values of V
at
IN
which point the batteries are well outside their useful operating
range. The output voltage tracks the input voltage minus the
dropout. The SHDN function is also unaffected and may be
used normally if desired.
V
IN
SHDN
GND
ADP667
DD
SET
R3
1MΩ
R2
1MΩ
R1
332kΩ
IN OUT
+
+
C1
10µF
+5V
OUTPUT
Figure 7. IQ Reduction 2
REV. 0
–5–
Page 6
ADP667–Typical Performance Characteristics
1000
TA = +25°C
100
10
DROPOUT VOLTAGE – mV
1
1
10 100
LOAD CURRENT – mA
Figure 8. Dropout Voltage vs. Load Current
10
V
= 6V
IN
TA = +25°C
1
1000
2.0
TA = +25°C
V
= 6V
IN
= 10µF
C
L
1.5
1.0
∆V – mV
0.5
0.0
0 200
Figure 11. Load Regulation (∆V
V
IN
50 100 150
∆I – mA
OUT
TA = +25°C
vs. ∆I
OUT
)
+10V
+6V
0.1
QUIESCENT CURRENT – mA
0.01
0.01
I
– mA
OUT
100101
10000.1
Figure 9. Quiescent Current vs. Load Current
1000
TA = +25°CTA = +25°C
100mA
100
20mA
10mA
10
DD OUTPUT CURRENT – µA
1
0.00 0.450.05
5mA
2mA
0.10 0.15 0.20 0.25 0.30 0.35 0.40
50mA
I-O DIFFERENCE – mV
V
OUT
CH1 2.00V CH2 200mV M 2.00ms
Figure 12. Dynamic Response to Input Change
OUTPUT
CURRENT
V
OUT
CH1 1.00V CH2 20.0mV M 2.00ms
200mV
0V
100mA
10mA
20mV
0mV
Figure 10. DD Output Current vs. I-O Differential
–6–
Figure 13. Dynamic Response to Load Change
REV. 0
Page 7
ADP667
POWER DISSIPATION
The ADP667 can supply currents up to 250 mA and can operate with input voltages as high as 16.5 V, but not simultaneously.
It is important that the power dissipation and hence the internal
die temperature be maintained below the maximum limits. Power
Dissipation is the product of the voltage differential across the
regulator times the current being supplied to the load. The
maximum package power dissipation is given in the Absolute
Maximum Ratings. In order to avoid excessive die temperatures,
these ratings must be strictly observed.
= (VIN– V
P
D
OUT
) (IL)
The die temperature is dependent on both the ambient temperature and on the power being dissipated by the device. The inter-
nal die temperature must not exceed 125°C. Therefore, care
must be taken to ensure that, under normal operating conditions, the die temperature is kept below the thermal limit.
T
= TA + PD (
J
θ
)
JA
This may be expressed in terms of power dissipation as follows:
P
= (TJ– TA)/(
D
θ
)
JA
where:
T
= Die Junction Temperature (°C)
J
T
= Ambient Temperature (°C)
A
P
= Power Dissipation (W)
D
θ
= Junction to Ambient Thermal Resistance (°C/W)
JA
If the device is being operated at the maximum permitted ambi-
ent temperature of 85°C, the maximum power dissipation per-
mitted is:
P
(max) = (TJ (max) – TA)/(
D
P
(max) = (125 – 85)/(θ
D
= 40/
θ
JA
θ
)
JA
)
JA
where:
θ
= 120°C/W for the 8-pin DIP (N-8) package
JA
θ
= 170°C/W for the 8-pin SOIC (SO-8) package
JA
Therefore, for a maximum ambient temperature of 85°C:
P
(max) = 333 mW for N-8
D
P
(max) = 235 mW for SO-8
D
At lower ambient temperatures the maximum permitted power
dissipation increases accordingly up to the maximum limits
specified in the absolute maximum specifications.
The thermal impedance (θ
) figures given are measured in still
JA
air conditions and are reduced considerably where fan assisted
cooling is employed. Other techniques for reducing the thermal
impedance include large contact pads on the printed circuit
board and wide traces. The copper will act as a heat exchanger
thereby reducing the effective thermal impedance.
High Power Dissipation Recommendations
Where excessive power dissipation due to high input-output
differential voltages and/or high current conditions exists, the
simplest method of reducing the power requirements on the
regulator is to use a series dropper resistor. In this way the
excess power can be dissipated in the external resistor. As an
example, consider an input voltage of +12 V and an output
voltage requirement of +5 V @ 100 mA with an ambient tem-
perature of +85°C. The package power dissipation under these
conditions is 700 mW which exceeds the maximum ratings. By
using a dropper resistor to drop 4 V, the power dissipation
requirement for the regulator is reduced to 300 mW which is
within the maximum specifications for the N-8 package at 85°C.
The resistor value is calculated as R = 4/0.1 = 40 Ω. A resistor
power rating of 400 mW or greater may be used.
40Ω
0.5W
V
12V
IN
1µF
IN
+
C1
OUT
ADP667
GNDSET SHDN
+
C2
10µF
+5V
OUTPUT
Figure 14. Reducing Regulator Power Dissipation
Transient Response
The ADP667 exhibits excellent transient performance as illustrated in the “Typical Performance Characteristics.” Figure 12
shows that an input step from 10 V to 6 V results in a very small
output disturbance (50 mV). Adding an input capacitor would
improve this even more.
Figure 13 shows how quickly the regulator recovers from an
output load change from 10 mA to 100 mA. The offset due to
the load current change is less than 1 mV.
Monitored µP Power Supply
Figure 15 shows the ADP667 being used in a monitored µP
supply application. The ADP667 supplies +5 V for the microprocessor. Monitoring the supply, the ADM705 will generate a
reset if the supply voltage falls below 4.65 V. Early warning of
an impending power fail is generated by a power fail comparator
on the ADM705. A resistive divider network samples the preregulator input voltage so that failing power is detected while
the regulator is still operating normally. An interrupt is generated so that a power-down sequence can be completed before
power is completely lost. The low dropout voltage on the
ADP667 maximizes the available time to carry out the powerdown sequence. The resistor divider network R1 and R2 should
be selected so that the voltage on PFI is 1.25 V at the desired
warning voltage.
UNREGULATED
DC
R1
R2
IN
ADP667
GND SET SHDN
V
CC
RESET
ADM705
PFI
GND
OUT
PFO
+5V
+
10µF
V
CC
RESET
µP
INTERRUPT
Figure 15.µP Regulator with Supply Monitoring and Early
Power-Fail Warning
REV. 0
–7–
Page 8
ADP667
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.0098 (0.25)
0.0040 (0.10)
8
1
0.430 (10.92)
0.348 (8.84)
0.100
(2.54)
BSC
5
4
0.070 (1.77)
0.045 (1.15)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
8-Lead Narrow-Body SOIC
(SO-8)
5
4
0.0192 (0.49)
0.0138 (0.35)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
8
1
0.1968 (5.00)
0.1890 (4.80)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.0196 (0.50)
0.0099 (0.25)
8
°
0
°
0.195 (4.95)
0.115 (2.93)
x 45
0.0500 (1.27)
0.0160 (0.41)
C2015–18–4/95
°
–8–
PRINTED IN U.S.A.
REV. 0
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