Datasheet ADP5587 Datasheet (ANALOG DEVICES)

QWERTY Keypad Controller

ADP5587

18

17

19

21

23

22

20

24

CONTROL

REGISTERS

CONTROL

INTERFACE

R7R6R5R4R3R2R1R0C0C1C2C3C4C5C6

C7

C9

C8

GND

V

CC

SCL

SDA

RST

INT

3 4 5 6 7 8 9 10 11 12 13 14 15 161 2

ADP5587

08612-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Data Sheet

FEATURES

18-GPIO port expander or 10 × 8 keypad matrix GPIOs configurable as GPIs, GPOs, and keypad rows or

columns

2

I

C interface with auto-increment

1.65 V to 3.6 V operation Keypad lock capability Open-drain interrupt output Key press and key release interrupts GPI interrupt with level programmability Programmable pull-ups Key event counter with overflow interrupt 275 μs debounce on the reset line and GPIs 1 μA typical idle current 55 μA typical polling current 4 mm × 4 mm LFCSP package Small 2 mm x 2 mm WLCSP package, 0.4 mm pitch Multiple I

2

C addresses available for the LFCSP package to

allow multiple port expanders on the same bus

Mobile I/O Expander and

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

APPLICATIONS

Keypad and I/O expander designed for QWERTY type phones

that require a large keypad matrix

GENERAL DESCRIPTION

The ADP5587 is an I/O port expander and keypad matrix designed for QWERTY type phones that require a large keypad matrix and expanded I/O lines. I/O expander ICs are used in mobile platforms as a solution to the limited number of GPIOs available in the main processor.

In its small 2 mm × 2 mm package, the ADP5587 contains enough power to handle all key scanning and decoding and to flag the processor of key presses and releases via the I interface and interrupt. The ADP5587 frees the main microprocessor from the need to monitor the keypad, thereby minimizing current drain and increasing processor bandwidth. The ADP5587 is also equipped with a buffer/FIFO and key event counter to handle and keep track of up to 10 unprocessed key or GPI events with overflow wrap and interrupt capability.

The ADP5587 has keypad lock capability with an option to trigger or not trigger an interrupt at key presses and releases.

2

C

All communication to the main processor is done using one interrupt line and two I

2

C-compatible interface lines. The ADP5587 can be configured as a keypad matrix of up to 8 rows × 10 columns (a maximum of 80 keys).

When the ADP5587 is used for smaller keypad matrices, unused row and column pins can be reconfigured to act as generalpurpose inputs or outputs. R0 to R7 denote the row pins of the matrix, whereas C0 to C9 denote the column pins. At power-up, all rows and columns default to GPIs and must be programmed to function as part of the keypad matrix or as GPOs.

Two options for I

2

C addresses exist for the LFCSP package to reduce the chance of port contention and allow up to two ADP5587 ICs to operate on the same I

2

C bus (see the Ordering

Guide).

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

ADP5587 Data Sheet

REVISION HISTORY

1/12—Rev. C to Rev. D

Changes to Table 11 .......................................................................... 9

Changes to Table 25 ........................................................................ 18

7/11—Rev. B to Rev. C

Changes to Features and General Description,

2

I

C Address Options ........................................................................ 1

Changes to the I

Figure 16, Figure, 17, and Figure 18 ............................................. 14

Changes to Ordering Guide .......................................................... 23

5/10—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Table 8 ............................................................................ 6

2

C Programming and Digital Control Section,

Typical Performance Characteristics ..............................................7

Theory of Operation .........................................................................8

Keypad Operation .........................................................................8

General-Purpose Inputs and Outputs ..................................... 12

I2C Programming and Digital Control ........................................ 14

Registers ....................................................................................... 15

Register Descriptions ................................................................. 16

Applications Information .............................................................. 21

Applications Overview .............................................................. 21

Keypad Current .......................................................................... 21

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

3/10—Rev. 0 to Rev. A

Added WLCSP Information ........................................ Throughout

Added Typical Performance Characteristics Section ................... 7

Updated Outline Dimensions, Changes to Ordering Guide .... 23

12/09—Revision 0: Initial Version

Rev. D | Page 2 of 24

Data Sheet ADP5587

With One Key Press

ICC

VCC = 1.8 V, TA = −40°C to +85°C

55

90

μA

SPECIFICATIONS

TA = TJ = −40°C to +85°C, unless otherwise noted.

DC CHARACTERISTICS

Table 1. General DC Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY VOLTAGE

VCC Input Voltage Range VCC 1.65 3.6 V Supply Current1 ICC VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C 1 10 μA

ICC VCC = 3.0 V, TA = −40°C to +85°C 100 200 μA With GPI Low (Pull-Up Enabled)2 ICC VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C 20 50 μA With GPI Low (Pull-Up Disabled) ICC VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C 2 10 μA With One GPO Active3 ICC VCC = 1.8 V, TA = −40°C to +85°C 50 μA

OSCILLATOR CURRENT

Oscillator Current (Enabled) ICC VCC = 1.8 V to 3.0 V 40 μA

1

Operating current measured with I/Os defaulting as GPIs, with all pull-ups enabled and all inputs open.

2

With one GPI low.

3

Load = 100 kΩ.

Table 2. I/O DC Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

INPUT LOGIC LEVELS (SCL, SDA,

Logic Low Input Voltage VIL 1.8 V ≤ VIO ≤ 3.0 V 0.3 × VCC V Logic High Input Voltage VIH 1.8 V ≤ VIO ≤ 3.0 V 0.7 × VCC V Schmitt Trigger Hysteresis V Input Leakage Current V

OUTPUT LOGIC LEVELS (C0 to C9, R0 to R7)

Logic Low Output Voltage VOL I Output High Voltage VOH I

OUTPUT LOGIC LEVELS (

INT

Output Low Voltage VOL I

Output High Voltage VOH 1.8 V ≤ VCC ≤ 3.0 V 0.7 × VCC V Logic High Leakage Current V

PULL-UP RESISTANCE FOR GPIOs (C0 to C9, R0 to R7)2 R

1

Power-up default current. All I/Os default to GPIs and are open; C8 and C9 default to GPIs; I2C is idle.

2

GPIO internal pull-ups are approximately 100 kΩ.

, C0 to C9, R0 to R7)1

RST

0.10 V

HYST

1.8 V ≤ VIO ≤ 3.0 V −1 +1 µA

I-LEAKAGE

= 1 mA 0.40 V

SINK

= 1 mA VCC − 0.3 V V

SOURCE

, SDA)

= 3 mA,

SINK

1.8 V ≤ V

1.8 V ≤ VCC ≤ 3.0 V 0.1 1 µA

O-LEAKAG E

100 kΩ

PULL-UP

≤ 3.0 V

CC

0.40 V

Table 3. Capacitance Loading1

Parameter Symbol Min Typ Max Unit

I/O Input Capacitance CIN 1 10 pF I/O Output Loading Capacitance C Capacitive Load for Each Bus Line C

1

Guaranteed by design.

2

CB = total capacitance of one bus line in picofarads.

50 pF

OUT

2

400 pF

B

Rev. D | Page 3 of 24

ADP5587 Data Sheet

Setup Time for Stop Condition

tSU,

0.6

μs

SDA

SCL

S

S = START CONDITION Sr = REPEATED S TART CONDITION P = STOP CONDITION

Sr P S

t

LOW

t

R

t

HD, DAT

t

HIGH

t

SU, DAT

t

F

t

F

t

SU, STA

t

HD, STA

t

SP

t

SU, STO

t

BUF

t

R

08612-002

AC CHARACTERISTICS

Table 4. General AC Characteristics1

Parameter Symbol Min Typ Max Unit

Delay from Reset Deassertion to I2C Access R Keypad Unlock Timer T Keypad Interrupt Mask Timer T Debounce TD 275 μs

1

Guaranteed by design.

Table 5. I2C AC Electrical Characteristics1

Parameter Symbol Min Ty p Max Unit

SCL Clock Frequency f SCL High Time t SCL Low Time t Data Setup Time tSU, Data Hold Time tHD, Setup Time for Repeated Start tSU, Hold Time for Start/Repeated Start tHD, Bus Free Time for Stop and Start t

Rise Time for SCL and SDA2 tR 20 + 0.1 CB 300 ns Fall Time for SCL and SDA2 tF 20 + 0.1 CB 300 ns Pulse Width of Suppressed Spike tSP 0 50 μs

1

Guaranteed by design.

2

tR and tF are measured between 0.3 × VCC and 0.7 × VCC.

60 μs

STD

7 sec

KUT

31 sec

KIMT

400 kHz

SCL

0.6 μs

HIGH

1.3 μs

LOW

100 ns

DAT

0 0.9 μs

DAT

0.6 μs

STA

0.6 μs

STA

1.3 μs

BUF

STO

2

Figure 2. I

C Interface Timing Diagram

Rev. D | Page 4 of 24

Data Sheet ADP5587

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

VCC −0.3 V to + 4.0 V R0 to R7, C0 to C9 −0.3 V to VCC + 0.3 V SCL −0.3 V to VCC + 0.3 V SDA −0.3 V to VCC + 0.3 V

−0.3 V to VCC + 0.3 V

RST

−0.3 V to VCC + 0.3 V

INT GND −0.3 V to +0.3 V Operating Ambient Temperature Range −40°C to +85°C Operating Junction Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C ESD Machine Model ±200 V ESD Human Body Model ±2000 V ESD Charged Device Model ±1000 V Soldering Condition JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

24-Lead LFCSP_WQ 57.8 9.4 °C/W Maximum Power 600 N/A mW 25-Ball WLCSP 46 N/A °C/W Maximum Power 600 N/A mW

ESD CAUTION

Rev. D | Page 5 of 24

ADP5587 Data Sheet

08612-003

2

1

3 4 5 6

18 17 16 15 14 13

R2

R3

R4

R5

R6

R7

C4

NOTES

1. EXPOSED

PAD MUST BE CONNECTED

TO GROUND.

C5

C6

C7

C8

C9

8

9

10

11

7

R0

C0

C1

C2

12 C3

R1

20

19

21

RST

GND

VCC

22

SDA

23

SCL

24

INT

ADP5587

TOP

VIEW

(Not to S cale)

INT

RST

TOP VIEW

(BALL SIDE DO WN)

Not to Scale

08612-004

1

A

B

C

D

E

2 3 4

BALL A1 CORNER

C6 C1 R2 R7

VCC C7 C2 NC R6

SDA C8 C3 R1 R5

SCL C9 C4 R0 R4

GND C5 C0 R3

NOTES

1. NC = NO CONNECT.

5

6

A4

R2

GPIO, Row 2 in the Keypad Matrix.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. LFCSP Pin Configuration

Table 8. Pin Function Descriptions

LFCSP Pin No.

WLCSP Pin No.

1 A5 R7 GPIO, Row 7 in the Keypad Matrix. 2 B5 R6 GPIO, Row 6 in the Keypad Matrix. 3 C5 R5 GPIO, Row 5 in the Keypad Matrix. 4 D5 R4 GPIO, Row 4 in the Keypad Matrix. 5 E5 R3 GPIO, Row 3 in the Keypad Matrix.

N/A B4 N/A No Connect (NC) 7 C4 R1 GPIO, Row 1 in the Keypad Matrix. 8 D4 R0 GPIO, Row 0 in the Keypad Matrix. 9 E4 C0 GPIO, Column 0 in the Keypad Matrix. 10 A3 C1 GPIO, Column 1 in the Keypad Matrix. 11 B3 C2 GPIO, Column 2 in the Keypad Matrix. 12 C3 C3 GPIO, Column 3 in the Keypad Matrix. 13 D3 C4 GPIO, Column 4 in the Keypad Matrix. 14 E3 C5 GPIO, Column 5 in the Keypad Matrix. 15 A2 C6 GPIO, Column 6 in the Keypad Matrix. 16 B2 C7 GPIO, Column 7 in the Keypad Matrix. 17 C2 C8 GPIO, Column 8 in the Keypad Matrix. 18 D2 C9 GPIO, Column 9 in the Keypad Matrix. 19 E2 GND Ground. 20 A1

21 B1 VCC Supply Voltage, 1.65 V to 3.6 V. 22 C1 SDA I2C Serial Data. The open drain requires an external pull-up resistor. 23 D1 SCL I2C Clock. 24 E1

EP N/A EPAD Exposed Pad. The exposed pad must be connected to ground.

Figure 4. WLCSP Pin Configuration

Mnemonic Description

Hardware Reset (Active Low). This pin resets the device to the power default conditions. The reset

RST

pin must be driven low for a minimum of 50 μs to be valid and to prevent false resets due to ESD glitches or noise in the system. If not used,

Processor Interrupt, Active Low, Open Drain. This pin can be pulled up to 2.7 V or 1.8 V for selection

INT

must be tied high with a pull-up resistor.

RST

flexibility in the processor GPIO supply group.

Rev. D | Page 6 of 24

Data Sheet ADP5587

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

I

CC

CURRENT (µA)

08612-017

VCC AT 1.8V

VCC AT 3.0V

140

120

100

80

60

40

20

0

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

INPUT/OUTPUT V

OH

(mV)

08612-019

VCC AT 1.8V

VCC AT 3.0V

60

50

40

30

20

10

0 –40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

INPUT/OUTPUT V

OL

(mV)

08612-018

VCC AT 1.8V

V

CC

AT 3.0V

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 SUPPLY VOLTAGE (V)

STANDBY CURRENT ( µ A)

08612-020

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise specified.

Figure 5. Standby (ICC) Current vs. Temperature

Figure 6. Input/Output VOH vs. Temperature (Source Current = 1 mA)

Figure 7. Input/Output VOL vs. Temperature (Sink Current = 1 mA)

Figure 8. Supply Voltage vs. Standby Current

Rev. D | Page 7 of 24

ADP5587 Data Sheet

CONTROL

REGISTERS

CONTROL

INTERFACE

R7R6R5R4R3R2R1R0C0C1C2C3C4C5C6

C7

C9

C8

A0A1

A2A3

A4

A5A6

A7

B0B1B2B3B4B5B6B7 C0C1C2C3C4C5C6C7 D0D1D2D3D4D5D6D7 E0E1E2E3E4E5E6E7 F0F1F2F3F4F5F6F7 G0G1G2G3G4G5G6G7 H0H1H2H3H4H5H6H7

I0I1I2I3I4I5I6I7

J0J1J2J3J4J5J6J7

SCL

SDA

RST

INT

V

CC

GND

V

CC

SCL SDA

19

21

23

22

18

17

20

24

1

2 3

4

5 6

7 8

9

10 11 12 13 14 15 16

ADP5587

RST

INT

08612-005

THEORY OF OPERATION

Figure 9. Typical Operating Circuit

The ADP5587 is a GPIO expander that can be configured either as an 18 I/O port expander or as a 10 column × 8 row keypad matrix (80 keys maximum). It is ideal for cellular phone designs and other portable devices that require a large extended keypad and/or expanded I/Os. When smaller size keypads are required, unused GPIOs in the keypad matrix can be used as I/Os (GPOs and GPIs). All GPIOs (rows and columns) default to GPIs at power-up with pull-ups and debounce enabled.

KEYPAD OPERATION

Any number of rows and columns, up to 10 columns × 8 rows, can be configured to be part of the keypad matrix. The rows and columns that make up the keypad matrix must be configured by setting the corresponding bits in Register 0x1D to Register 0x1F. Key presses and releases appear in the key event table/registers with a decimal value of 1 (0x01 hexadecimal or 0000001 binary) through a decimal value of 80 (0x50 hexadecimal or 1010000 binary). See Ta b l e 9 for key event number assignments. The keypad, in idle mode, is configured with columns driven low and rows as inputs configured high with pull-up resistors.

Rev. D | Page 8 of 24

Table 9. Key Event Number Assignment Table

Row C0 C1 C2 C3 C4 C5 C6 C7 C8 C9

1 2 3 4 5 6 7 8 9 10

R0

11 12 13 14 15 16 17 18 19 20

R1

21 22 23 24 25 26 27 28 29 30

R2

31 32 33 34 35 36 37 38 39 40

R3

41 42 43 44 45 46 47 48 49 50

R4

51 52 53 54 55 56 57 58 59 60

R5

61 62 63 64 65 66 67 68 69 70

R6

71 72 73 74 75 76 77 78 79 80

R7

When one key press or multiple key presses (short between column and row) occur, the internal state machine checks the row pins to determine which one is driven low and then triggers an internal interrupt. The state machine then starts a key scan cycle to determine which columns are involved in the key press. After a key has been pressed for 25 ms, the state machine sets the appropriate key number in the key event status register with the key-pressed bits set (the MSB in the key event register) in the order detected. The state machine then sets the KE_INT bit in Register 0x02. If the KE_IEN field in Register 0x01 is set, an interrupt is sent to the host processor.

Data Sheet ADP5587

KEYPAD SCAN AND DECODE

D0_PULL

J7

I7

H7

G7

F7

E7

D7

C7

B7

A7

J6

I6

H6

G6

F6

E6

D6

C6

B6

A6

J5

I5

H5

G5

F5

E5

D5

C5

B5

A5

J4

I4

H4

G4

F4

E4

D4

C4

B4

A4

J3

I3

H3

G3

F3

E3

D3

C3

B3

A3

J2

I2

H2

G2

F2

E2

D2

C2

B2

A2

J1

I1

H1

G1

F1

E1

D1

C1

B1

A1

J0

I0

H0

G0

F0

E0

D0

C0

B0

A0

R7 R6 R5 R4 R3 R2 R1

R0

C0 C1 C2 C3 C4 C5 C6 C7 C9C8

10 × 8 KEYPAD MATRIX

V

CC

D1_PULL

D2_PULL

D3_PULL

D4_PULL

D5_PULL

D6_PULL

D7_PULL

08612-006

NOTES:

1. Dx_PULL STANDS FOR GPIO PULL-UP .

B1

Pressed

2

1 J 0 0101101

Key E4 released

To prevent glitches or narrow press times registering as valid key presses, the key scanner requires the key to be pressed for two scan cycles. The key scanner has a sampling period of 25 ms; therefore, the key must be pressed and held for at least 25 ms to register as pressed. If the key is continuously pressed, the key scanner continues to sample every 25 ms. If a pressed key is released for 25 ms or greater, the state machine sets the appropriate key number in the key event status register with the key-pressed bits cleared in the order detected. Because the release of a key is not necessarily in sync with the key scan sampling period, it may take between 25 ms and 50 ms for a key to register as released. After the key is registered as released, the key scanner returns to idle mode. Figure 10 shows the row and column pins connected to a typical 10 × 8, 80-switch keypad matrix.

bits display the binary representation of the keys that are pressed or released.

The first read of any of the FIFO registers displays the first event that happened and its status. Subsequent reads of the same register replace the register data with the next event that happens. If tracking of all the events is important, it is best to use a single register per event. After all the events in the FIFO are read, reading of any of the event registers yields a zero value.

Table 10 and Tabl e 11 show the event sequences as they are logged in and read from the FIFO. The 10 FIFO registers are labeled A through J, and the keys are labeled A0 through J7.

Table 10. Example of Event Sequence

Key Pressed/Released Status Key Event Counter

A0 Pressed 1

A0 Released 3 C2 Pressed 4 B1 Released 5 D3 Pressed 6 C2 Released 7 E4 Pressed 8 E4 Released 9 D3 Released 10

Key Event Tracking

The 10 key event registers are set to act as a FIFO, meaning that reading any of the 10 key event registers yields the key events in the order the keys were pressed and released.

Tracking of key events is done with the help of the key event counter (the KEC field in Register 0x03) and the FIFO/key event registers (Register 0x04 through Register 0x0D). The KEC count increases as keys are pressed and released; up to 10 events can be logged in the counter. The FIFO/key event registers, on the other hand, display the key events and their status (pressed or released) as they are read out of the FIFO. The FIFO registers contain eight bits, with the MSB dedicated as the status bit (1 indicates a press and 0 indicates a release); the remaining seven

Figure 10. Keypad Decode Configuration

Table 11. Interpretation of FIFO Event Reading

Key Event Counter

Key Event Register Read

Key Event Register Content (Binary)

1

Key Event Register Interpretation

10 N/A N/A N/A 9 D 1 0000001 Key A0 pressed 8 E 1 0001100 Key B1 pressed 7 C 0 0000001 Key A0 released 6 F 1 0010111 Key C2 pressed 5 G 0 0001100 Key B1 released 4 A 1 0100010 Key D3 pressed 3 B 0 0010111 Key C2 released 2 H 1 0101101 Key E4 pressed

0 I 0 0100010 Key D3 released

1

The MSB indicates a key press or key release in the key event register: 1 = key

press; 0 = key release.

Key Event Overflow

The ADP5587 is equipped with an overflow feature to handle key events beyond the FIFO capacity. When all events are filled, any additional events set the OVR_FLOW_INT bit in Register 0x02; if the OVR_FLOW_IEN bit in Register 0x01 is set, the host processor is also interrupted when overflow occurs. When the FIFO is not full, new events are added as the last events.

The OVR_FLOW_M bit in Register 0x01 sets the mode of operation during overflows. Clearing the OVR_FLOW_M bit causes new incoming events to be discarded, and setting this bit rolls over and overwrites old data with new data starting at the first event.

Rev. D | Page 9 of 24

ADP5587 Data Sheet

KEYPAD MODE

KEC

REG. 0x1D

THROUGH REG . 0x1F

REG. 0x03

READ KE(s) TO CLEAR

INT DRIVE

KE_INT

REG. 0x02

WRITE 1 TO CLEAR

KE_IEN

REG. 0x01

AND

08612-007

START

MASK TIMER = 0

KEY PRESS

DETECTED

NO

YES

NO

YES

NO

YES

NO

YES

NO

YES

NO

GENERATE

KE INTERRUPT

START MASK TIMER

MASK TIMER

EXPIRES

MASK TIMER

EXPIRES

GENERATE

KEYLOCK I NTERRUPT

FIRST UNLOCK

KEY DETECTED

SECOND UNLO CK

KEY DETECTED

START UNLOCK1 TO UNL OCK2

UNLOCK1

TO

UNLOCK2

TIMER EXPIRES

KEY PRESS

DETECTED

START UNLOCK1 TO UNL OCK2

FIRST UNLOCK KEY DETECTED

GENERATE

KEYLOCK I NTERRUPT

SECOND UNLO CK

KEY DETECTED

UNLOCK1 TO

UNLOCK2

TIMER EXPIRES

NO

08612-008

Auto-Increment

The ADP5587 features automatic increment during I2C read access, which allows the user to increment the address pointer without the need to send a read command for subsequent addresses. This minimizes processor intervention and, therefore, saves processor bandwidth and current drain. Bit 7 of Register 0x01 must be set to initiate auto-increment (see Figure 17 for the full write and read sequence).

Key Event Interrupt

On a key event (KE) interrupt, the processor reads the interrupt status register to determine the cause of the interrupt. If the KE_INT bit in Register 0x02 is set, the processor reads the key event count from the KEC [3:0] field in Register 0x03 to determine the number of events. After reading all the events from the

FIFO, it then reads the KEC field again (in Register 0x03) to make sure that no new events have come in. After all the events are read, the KEC field is decremented to zero (KEC = 0), and the KE_INT bit can be cleared by writing a 1 to it. Both key presses and key releases are capable of generating key event interrupts. The KE_INT bit cannot be cleared, and the

INT

cannot be deasserted, until the FIFO is cleared of all events.

Figure 11. Key Event Interrupt Generation

Figure 12. Keypad Lock Interrupt Mask Timer Flowchart

Rev. D | Page 10 of 24

Data Sheet ADP5587

KEY EVENT INTERRUPT

KEYLOCK I NTERRUPT

OVERFLOW INTERRUPT

GPIO INTERRUPT

INT

OR

INTERRUPT CONFIGURATION

OVR_FLOW_

IEN

K_LCK_IM GPI_IEN KE_IEN

GPIEM_

CFG

KEYPAD LOCK INTERRUPT MAS K TIMER

K_LCK_EN

INT

LOGIC

V

CC

08612-009

Keypad Lock/Unlock Feature

The ADP5587 has a locking feature that allows the user to lock the keypad or GPIs (configured to be part of the event table). When enabled, the keypad lock can prevent generation of key event interrupts and prevent key events from being recorded in the key event table. This feature comprises the Unlock Key 1 and Unlock Key 2 registers (Register 0x0F and Register 0x10, respectively), the keypad lock interrupt mask and keypad unlock timers (Register 0x0E), and the LCK1, LCK2, and keylock enable (K_LCK_EN) bits (Register 0x03).

The unlock keys can be programmed with any value of the keys in the keypad matrix or any GPI event values that are part of the key event table. When the keypad lock interrupt mask timer is enabled, the user must press two specific keys before a keylock interrupt is generated or keypad events are recorded. After the keypad is locked (set Bit 6, Register 0x03, to enable the lock), the first time that the user presses any key, a key event interrupt is generated. No additional interrupt is generated unless both unlock key sequences are correct.

If the correct unlock keys are not pressed before the mask timer expires, the state machine starts over. The first key event interrupt is generated to allow the software to see that the user has pressed a key so that the host can turn on the LCD and display the unlock message. The host then reads the lock status register to see if the keypad is unlocked. After the first key event

interrupt, the state machine does not interrupt the processor again unless the correct sequence is keyed. The state machine is reset if the correct sequences are not keyed before the keypad lock interrupt mask timer expires.

The state of the keypad lock interrupt mask bit (Register 0x01, Bit 2) in the configuration register determines whether the interrupt pin is asserted when the keylock interrupt status bit (Register 0x02, Bit 2) is set. Setting the keylock interrupt mask bit causes the

INT

pin to be asserted when the keylock interrupt status bit is set in Register 0x02; clearing that bit masks the interrupt, causing the interrupt pin not to respond to the keylock interrupt status bit. The mask interrupt timer should be set for the time that it takes for the LCD to dim or turn off so that, if a key is pressed, the backlight is set to bright mode again or reset to turn on the LCD.

When the unlock mask interrupt timer equals 0, only the correct unlock sequence can generate an interrupt. Disabling the unlock mask interrupt timer allows the processor to remain undisturbed for situations in which the user, for example, has the phone in a pocket or purse and the keys are constantly pressed. The flowchart in Figure 11 shows the interaction of interrupt enable, key event counter, key event interrupt status, and interrupt generation.

INT

Figure 13.

Rev. D | Page 11 of 24

Pin Drive

ADP5587 Data Sheet

DEBOUNCE

GPIOx

Dx_DIR

Dx_OUT

Dx_IN

Dx_IN_DBNC

Dx_PULL

V

CC

V

CC

08612-010

NOTES:

1. Dx_IN STANDS FOR ANY OF THE 18 GPIOs CONFIG URE D AS GPIs.

2. Dx_OUT STANDS FOR ANY O F THE 18 GPIOs CONFI GURED AS GPO s.

3. Dx_IN_DBNC STANDS FOR GPI DE BOUNCE.

4. Dx_DIR STANDS FOR GPIO DIRECTI ON.

5. Dx_PULL S TANDS FOR GP IO PULL - UP .

Dx_IN

Dx_IN_IEN

REG. 0x23

THROUGH

REG. 0x25

Dx_IN_ISTAT

REG. 0x11 THROUGH REG. 0x13

READ TWICE

TO CLEAR

GPI_INT

REG. 0x02

WRITE 1

TO CLEAR

REG. 0x01

INT DRIVE

INTERRUPT

CONDITION

DECODE

Dx_ILVL

REG. 0x26

THROUGH

REG. 0x28

AND

08612-011

NOTES:

1. Dx_IN STANDS FOR ANY OF THE 18 GPIOs CONFIG URE D AS GPIs.

2. Dx_ILVL STANDS FOR GPIO INTERRUPT LEVEL.

3. Dx_IN_IEN S TANDS FOR GP I INTERRUPT ENABLE.

4. Dx_IN_STAT STANDS FO R GPI INT E RRUP T STATUS.

5. GPI_INT STANDS FOR GPI INTERRUPT.

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

GENERAL-PURPOSE INPUTS AND OUTPUTS

The ADP5587 supports up to 18 programmable GPIOs that can be configured to address a variety of uses. Figure 14 shows the makeup of a typical GPIO block where GPIOx represents any of the 18 I/O lines.

Figure 14. Typical GPIO B lock

General-Purpose Inputs (GPI)

The ADP5587 allows the user to configure all or some of its GPIOs as general-purpose inputs (GPIs). After the GPIOs are configured as GPIs, the user can choose to also turn on pull-up resistors and interrupt generation capability, thus reducing the amount of software monitoring and processor interaction and saving p ower.

The programmed level of the GPI interrupt determines the active level of the GPI pin. For example, if a GPI interrupt level is programmed as high, a high on that pin is considered active and meets the interrupt requirement. If the interrupt is programmed as low, a low on that pin is considered active and meets the interrupt requirement.

GPI data status and interrupt status are reflected in the GPIO interrupt status and data status registers (Register 0x11 through Register 0x16). Caution is necessary during software implementation because an interrupt may be set immediately after the registers are s et . To prevent this, the correct logic levels must be present at the GPIs, and the GPIO interrupt level must be set before GPIO interrupt enable or GPI event FIFO enable registers are set. Figure 15 shows the interrupt generation scheme, where Dx represents any one of the 18 GPIOs.

Figure 15. GPIO Interrupt Generation

GPI Events

A column or row configured as a GPI can be programmed to be part of the key event table and is, therefore, also capable of generating a key event interrupt. A key event interrupt caused by a GPI follows the same process flow as a key event interrupt caused by a key press or key release. GPIs configured as part of the key event table allow single key switches and other GPI interrupts to be monitored. As part of the event table, GPIs are represented by a decimal value of 97 (0x61 hexadecimal or 1100001 binary) through a decimal value of 114 (0x72 hexadecimal or 1110010 binary). See Table 12 and Ta b l e 13 for GPI event number assignments for rows and columns, respectively.

Table 12. GPI Event Number Assignments for Rows

R0 R1 R2 R3 R4 R5 R6 R7

97 98 99 100 101 102 103 104

Table 13. GPI Event Number Assignments for Columns

105 106 107 108 109 110 111 112 113 114

For a GPI that is set as active high and is enabled in the key event table, the state machine adds an event to the event count and event tables whenever that GPI goes high. If the GPI is set to active low, a transition from high to low is considered a press and is also added to the event count and event table. After the interrupt state is met, the state machine internally sets an interrupt for the opposite state programmed in the register to prevent polling for the released state, thereby saving current. After the released state is achieved, it is added to the event table. The press and release are still indicated by Bit 7 in the event register (Register 0x04 through Register 0x0D). The GPI events can also be used as unlocked sequences.

When the GPI_EM_REGx bit in Register 0x20 through Register 0x22 is set, GPI events are not tracked when the keypad is locked. The GPIEM_CFG bit (Register 0x01, Bit 6) must be cleared for the GPI events to be tracked in the event counter and event table when the keypad is locked.

Rev. D | Page 12 of 24

Data Sheet ADP5587

8 × 7

C0 to C7, R0 to R6

56

R7, C8, C9

3

275 Microsecond Interrupt Configuration

The ADP5587 gives the user the flexibility of deasserting the interrupt for 275 μs while there is a pending event. When the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already asserted results in a 275 μs deassertion. When the INT_CFG bit is cleared, the processor interrupt remains asserted if the host tries to clear the interrupt. This feature is particularly useful for software development and edge triggering applications.

Debouncing

The ADP5587 has a 275 μs debounce time for GPIOs configured as GPIs and rows in keypad scanning mode. The reset line always has a 275 μs debounce time.

Table 14. Device Configuration

Keypad GPIO

Matrix Active Pins Number of Keys Available GPIO Number of GPIOs

10 × 8 C0 to C9, R0 to R7 80 0 0 8 × 8 C0 to C7, R0 to R7 64 C8, C9 2

General-Purpose Outputs (GPOs)

The ADP5587 allows the user to configure all or some of its GPIOs as GPOs. These GPOs can be used as extra enables for the host processor or simply as trigger outputs. When configured as an output (GPO), a digital buffer drives the pin to 0 V for a 0 and to V

for a 1. To se t any GPIO as a GPO, make sure that

CC

the corresponding bits in Register 0x1D through Register 0x1F are set for GPIO mode; then use Register 0x23 through Register 0x25 to set the corresponding bits for GPO mode.

Power-On Reset

For built-in power-up initialization for applications lacking a power-on reset signal, a reset pin,

RST

, allows the user to reset the registers to default values in the event of a brownout or other reset condition.

8 × 6 C0 to C7, R0 to R5 48 R6, R7, C8, C9 4 8 × 5 C0 to C7, R0 to R4 40 R5 to R7, C8, C9 5 7 × 7 C0 to C6, R0 to R6 49 R7, C7 to C9 4 7 × 6 C0 to C6, R0 to R5 42 R6, R7, C7 to C9 5 7 × 5 C0 to C6, R0 to R4 35 R5 to R7, C7 to C9 6 6 × 6 C0 to C5, R0 to R5 36 R6, R7, C6 to C9 6 6 × 5 C0 to C5, R0 to R4 30 R5 to R7, C6 to C9 7 6 × 4 C0 to C5, R0 to R3 24 R4 to R7, C6 to C9 8 … … … … … 0 × 0 None 0 R0 to R7, C0 to C9 18

Rev. D | Page 13 of 24

ADP5587 Data Sheet

SUBADDRESS

CHIP ADDRESS

1

ST 0 1 1 0 1 0 0 0 0 0 SP

0 = WRIT E

ADP5587 ACK

ADP5587 RECEIVES D ATA

ADP5587 ACK

0

08612-012

1

DEFAULT WRITEADDRESS IS 0x68. OPTION 1 WRI TE ADDRE S S IS 0x60.

SUBADDRESSCHIP ADDRESS

1

CHIP ADDRESS

2

ST 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 ST 0 1 1 0 1 0 0 0 1 SP

1 = READ

ADP5587 NO ACK

ADP5587 SENDS DATA

ADP5587 ACK

0 = WRIT E

0 1

08612-013

1

DEFAULT WRITEADDRESS IS 0x68. OPTION 1 WRI TE ADDRE S S IS 0x60.

2

DEFAULT READ ADDRE S S IS 0x69. OPTION 1 READ ADDRESS IS 0x61.

READ START ADDR

CHIP ADDRESS CHIP ADDRESS

1

ST 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 ST 0 1 1 0 1 0 0 0 0

1 = READ

ADP5587 ACK

ADP5587 SENDS DATA 1

ADP5587 ACK

0 = WRIT E

0 1

ADP5587 NO ACK

1

ADP5587 SENDS DATA N

...

ST

STOP

START

08612-014

1

DEFAULT READ ADDRE S S IS 0x69. OPTION 1 READ ADDRESS IS 0x61.

I2C PROGRAMMING AND DIGITAL CONTROL

The ADP5587 provides full I2C software programmability to facilitate its adoption in various product architectures. All register programming is done via the I package has two options for I

The default part option I

2

C addressing.

2

C write address is located at 0x68

2

C bus. The LFCSP

(0b01101000), and the read address is at 0x69 (0b 01101001).

The ADP5587ACPZ-1-R7 has the I

2

C write address at 0x60 (0b

01100000) and the read address at 0x61 (0b 01100001).

All communication to the ADP5587 is performed via its I

2

Ccompatible serial interface. Figure 16 shows a typical write sequence for programming an internal register. The cycle begins with a start condition followed by the chip write address. The ADP5587 acknowledges the chip write address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5587 acknowledges the register address byte by pulling the data line low. The data

byte to be written is sent next. The ADP5587 acknowledges the data byte by pulling the data line low, and a stop condition completes the sequence.

Figure 17 shows a typical read sequence for reading back an internal register. The cycle begins with a start condition followed by the chip write address. The ADP5587 acknowledges the chip write address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5587 acknowledges the register address byte by pulling the data line low. The cycle continues with a repeat start followed by the chip read address. The ADP5587 acknowledges the chip read address byte by pulling the data line low. The ADP5587 places the contents of the previously addressed register on the bus for readback. There is no acknowledge following the readback data byte, and a stop condition completes the cycle.

Figure 16. I

Figure 17. I

Figure 18. I

2

C Write Sequence

2

C Read and Write Sequences

2

C Read Auto-Increment

Rev. D | Page 14 of 24

Data Sheet ADP5587

0x0A

KEY_EVENTG

Key Event Register G

0x1B

GPIO_INT_EN2

GPIO interrupt enable

REGISTERS

The general behavior of registers is as follows:

• All registers are 0 on reset.

• All registers are read/write unless otherwise specified.

• Unused bits are read as 0.

Table 15.

Address Register Name Description

0x00 DEV_ID Device ID 0x01 CFG Configuration Register 1 0x02 INT_STAT Interrupt status register 0x03 KEY_LCK_EC_STAT Keylock and event counter register 0x04 KEY_EVENTA Key Event Register A 0x05 KEY_EVENTB Key Event Register B 0x06 KEY_EVENTC Key Event Register C 0x07 KEY_EVENTD Key Event Register D 0x08 KEY_EVENTE Key Event Register E 0x09 KEY_EVENTF Key Event Register F

0x0B KEY_EVENTH Key Event Register H 0x0C KEY_EVENTI Key Event Register I 0x0D KEY_EVENTJ Key Event Register J 0x0E KP_LCK_TMR Keypad Unlock 1 timer to Keypad Unlock 2 timer 0x0F UNLOCK1 Unlock Key 1 0x10 UNLOCK2 Unlock Key 2 0x11 GPIO_INT_STAT1 GPIO interrupt status 0x12 GPIO_INT_STAT2 GPIO interrupt status 0x13 GPIO_INT_STAT3 GPIO interrupt status 0x14 GP IO_DAT_STAT1 GPIO data status, read twice to clear 0x15 GP IO_DAT_STAT2 GPIO data status, read twice to clear 0x16 GP IO_DAT_STAT3 GPIO data status, read twice to clear 0x17 GPIO_DAT_OUT1 GPIO data out 0x18 GPIO_DAT_OUT2 GPIO data out 0x19 GPIO_DAT_OUT3 GPIO data out 0x1A GPIO_INT_EN1 GPIO interrupt enable

• Interrupt bits are cleared by writing 1 to the flag; writing 0

or reading the flag has no effect, with the exception of the key press, key release, and GPIO interrupt status registers, which are cleared on a read.

0x1C GPIO_INT_EN3 GPIO interrupt enable 0x1D KP_GPIO1 Keypad or GPIO selection 0x1E KP_GPIO2 Keypad or GPIO selection 0x1F KP_GPIO3 Keypad or GPIO selection 0x20 GPI_EM_REG1 GPI Event Mode 1 0x21 GPI_EM_REG2 GPI Event Mode 2 0x22 GPI_EM_REG3 GPI Event Mode 3 0x23 GPIO_DIR1 GPIO data direction 0x24 GPIO_DIR2 GPIO data direction 0x25 GPIO_DIR3 GPIO data direction 0x26 GPIO_INT_LVL1 GPIO level detect 0x27 GPIO_INT_LVL2 GPIO level detect 0x28 GPIO_INT_LVL3 GPIO level detect 0x29 DEBOUNCE_DIS1 Debounce disable

Rev. D | Page 15 of 24

ADP5587 Data Sheet

0x2E

GPIO_PULL3

GPIO pull disable

Field

Bits

Description

OVR_FLOW_IEN

3

Overflow interrupt enable.

Address Register Name Description

0x2A DEBOUNCE_DIS2 Debounce disable 0x2B DEBOUNCE_DIS3 Debounce disable 0x2C GPIO_PULL1 GPIO pull disable 0x2D GPIO_PULL2 GPIO pull disable

REGISTER DESCRIPTIONS

Table 16. DEV_ID—Register 0x00 (Device ID)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DEV_ID Device ID[3:0], MFG ID[7:4] MFID3 MFID2 MFID1 MFID0 DID3 DID2 DID1 DID0

Table 17. CFG—Register 0x01 (Configuration Register 1)

AUTO_INC 7 I2C auto-increment. Burst read is supported; burst write is not supported.

1: I2C auto-increment is on.

2

0: I

C auto-increment is off.

GPIEM_CFG 6 GPI event mode configuration.

1: GPI events are not tracked when the keypad is locked. 0: GPI events are tracked when the keypad is locked.

OVR_FLOW_M 5 Overflow mode.

1: overflow mode is on; register overflow data shifts in, starting at the last event and losing first event data. 0: overflow mode is off; register overflow data is lost.

INT_CFG 4 Interrupt configuration.

1: processor interrupt is deasserted for 275 μs and is reasserted with pending key events. 0: processor interrupt remains asserted when host tries to clear interrupt while there is a pending key event.

1: overflow interrupt is enabled. 0: overflow interrupt is disabled.

K_LCK_IM 2 Keypad lock interrupt mask.

1: keypad lock interrupt is enabled. 0: keypad lock interrupt is disabled.

GPI_IEN 1 GPI interrupt enable.

1: GPI interrupt is enabled. 0: GPI interrupt is disabled.

KE_IEN 0 Key events interrupt enable.

1: key events interrupt is enabled. 0: key events interrupt is disabled.

Rev. D | Page 16 of 24

Data Sheet ADP5587

KEY_EVENTI

Key Event Register I status (KE[6:0] = key number),

KI7

KI6

KI5

KI4

KI3

KI2

KI1

KI0

Table 18. INT_STAT—Register 0x02 (Interrupt Status Register)

Field Bits Description

Not Used [7:4] N/A OVR_FLOW_INT1 3 Overflow interrupt status. When set, write 1 to clear.

1: overflow interrupt is detected. 0: overflow interrupt is not detected.

K_LCK_INT2 2 Keylock interrupt status. When set, write 1 to clear.

1: keylock interrupt is detected.

GPI_INT

KE_INT

1

2

3

1, 3

1 GPI interrupt status. When set, write 1 to clear.

1, 3

The KE_INT, GPI_INT, and OVR_FLOW_INT bits reflect the status of the interrupts when the interrupt types are enabled even if the processor interrupt is masked. The K_LCK_INT bit is the interrupt to the processor when the keypad lock sequence is triggered. If there is a pending key event or GPI interrupt in their respective registers, KE_INT is not cleared until the FIFO is empty, and GPI_INT is not cleared until the cause of

the interrupt is resolved. The host must write a 1 to the KE_INT and GPI_INT bits to clear them.

0 Key events interrupt status. When set, write 1 to clear.

Table 19. KEY_LCK_EC_STAT—Register 0x03 (Keylock and Event Counter Register)

Field Bits Description

K_LCK_EN [6] 0: lock feature is disabled.

LCK2, LCK1 [5:4] Keypad lock status[1:0] (00 = unlocked; 11 = locked; read-only bits). KEC1 [3:0] Key event count of key event register.

1

The KEC field indicates the key event count of key event registers that have values in the bit (KEC(0000) = 0 events, KEC(0001) = 1 event, KEC(1010) = 10 events). As the

key events are read and cleared, the state machine automatically reduces the event count in KEC.

0: keylock interrupt is not detected.

1: GPI interrupt is detected. 0: GPI interrupt is not detected.

1: key events interrupt is detected. 0: key events interrupt is not detected.

1: lock feature is enabled.

Table 20. KEY_EVENTx—Register 0x04 to Register 0x0D (Key Event Register A to Key Event Register J)1

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

KEY_EVENTA (Register 0x04)

KEY_EVENTB (Register 0x05)

KEY_EVENTC (Register 0x06)

KEY_EVENTD (Register 0x07)

KEY_EVENTE2 (Register 0x08)

KEY_EVENTF (Register 0x09)

KEY_EVENTG (Register 0x0A)

KEY_EVENTH (Register 0x0B)

(Register 0x0C)

KEY_EVENTJ (Register 0x0D)

1

Data in key event registers is provided as a FIFO, where data is sequentially provided on each read, regardless of an event register read. The user can read the

KEY_EVENTA register only for an event count or can read registers sequentially.

2

KE[6:0] reflects the value 1 to 80 for key press events and the value 97 to 114 for GPI events. For KE[7:0], 0 = key released event, 1 = key pressed event. For GPIEM_CFG,

0 reflects a change in the GPI from GPI_INT_LVL = true to GPI_INT_LVL = false; 1 reflects a change in the GPI in which the GPI_INT_LVL condition becomes true.

Key Event Register A status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

Key Event Register B status (KE[6:0] = key number), KP[7 ] = 0: released, 1: pressed (cleared on read)

Key Event Register C status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

Key Event Register D status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

Key Event Register E status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

Key Event Register F status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

Key Event Register G status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

Key Event Register H status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read)

KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register J status (KE[6:0] = key number),

KP[7] = 0: released, 1: pressed (cleared on read)

KA7 KA6 KA5 KA4 KA3 KA2 KA1 KA0

KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0

KC7 KC6 KC5 KC4 KC3 KC2 KC1 KC0

KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

KE7 KE6 KE5 KE4 KE3 KE2 KE1 KE0

KF7 KF6 KF5 KF4 KF3 KF2 KF1 KF0

KG7 KG6 KG5 KG4 KG3 KG2 KG1 KG0

KH7 KH6 KH5 KH4 KH3 KH2 KH1 KH0

KJ7 KJ6 KJ5 KJ4 KJ3 KJ2 KJ1 KJ0

Rev. D | Page 17 of 24

ADP5587 Data Sheet

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Register 0x12)

GPIO interrupt status, cleared on read)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Register 0x15)

when read for inputs)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Table 21. KP_LCK_TMR—Register 0x0E (Keypad Unlock 1 Timer to Keypad Unlock 2 Timer)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

KP_LCK_TMR Keypad Unlock 1 timer to Keypad Unlock 2

1

When the keypad lock interrupt mask timer is enabled, the user must press two specific keys before a keylock interrupt is generated or keypad events are recorded.

After the keypad is locked, the first time that the user presses any key, a key event interrupt is generated. No additional interrupt is generated unless both unlock key sequences are correct; then a keylock interrupt is generated. When the interrupt mask timer is disabled (0), an interrupt is generated only when the correct full unlock sequence is completed.

2

The Unlock 1 timer and Unlock 2 timer keys can be either a key sequence or GPIEM_CFG sequence. The unlock timer keys can be programmed with any value of the

keys in the keypad matrix or any GPI values that are part of the key event table. The keylock enable bit (Bit 6, Register 0x03) must be set to lock the keypad.

timer[2:0] (0: disabled, 1 sec to 7 sec) Keypad Lock Interrupt Mask Timer[7:3]

(0: disabled, 0 sec to 31 sec)

1, 2

Table 22. UNLOCK1—Register 0x0F (Unlock Key 1)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

UNLOCK1 Unlock Key 1[6:0] (contains key number

for Unlock Key 1; 0: disabled)

Table 23. UNLOCK2—Register 0x10 (Unlock Key 2)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

UNLOCK2 Unlock Key 2[6:0] (contains key number

for Unlock Key 2; 0: disabled)

Table 24. GPIO_INT_STATx—Register 0x11 to Register 0x13 (GPIO Interrupt Status)

KIMT7 KIMT6 KIMT5 KIMT4 KIMT3 KLLT2 KLLT1 KLLT0

N/A ULK6 ULK5 ULK4 ULK3 ULK2 ULK1 ULK0

GPIO_INT_STAT1 (Register 0x11)

GPIO_INT_STAT2

GPIO_INT_STAT3 (Register 0x13)

GPIO interrupt status (used to check GPIO interrupt status, cleared on read)

GPIO interrupt status (used to check

GPIO interrupt status (used to check GPIO interrupt status, cleared on read)

R7IS R6IS R5IS R4IS R3IS R2IS R1IS R0IS

C7IS C6IS C5IS C4IS C3IS C2IS C1IS C0IS

N/A N/A N/A N/A N/A N/A C9IS C8IS

Table 25. GPIO_DAT_STATx—Register 0x14 to Register 0x16 (GPIO Data Status)

GP IO_DAT_STAT1 (Register 0x14)

GP IO_DAT_STAT2

GP IO_DAT_STAT3 (Register 0x16)

GPIO data status (shows GPIO state when read for inputs)

GPIO data status (shows GPIO state

GPIO data status (shows GPIO state when read for inputs)

R7DS R6DS R5DS R4DS R3DS R2DS R1DS R0DS

C7DS C6DS C5DS C4DS C3DS C2DS C1DS C0DS

N/A N/A N/A N/A N/A N/A C9DS C8DS

Table 26. GPIO_DAT_OUTx—Register 0x17 to Register 0x19 (GPIO Data Out)

GPIO_DAT_OUT1 (Register 0x17)

GPIO data out (GPIO data to be written to GPIO out driver, inputs are not

R7DO R6DO R5DO R4DO R3DO R2DO R1DO R0DO

affected). This is needed so that the value can be written prior to being set as an output.

GPIO_DAT_OUT2 (Register 0x18)

GPIO data out (GPIO data to be written to GPIO out driver, inputs are not

C7DO C6DO C5DO C4DO C3DO C2DO C1DO C0DO

affected). This is needed so that the value can be written prior to being set as an output.

GPIO_DAT_OUT3 (Register 0x19)

GPIO data out (GPIO data to be written to GPIO out driver, inputs are not

N/A N/A N/A N/A N/A N/A C9DO C8DO

affected). This is needed so that the value can be written prior to being set as an output.

Rev. D | Page 18 of 24

Data Sheet ADP5587

GPI_EM_REG1

GPI Event Mode Register 1

R7_EM

R6_EM

R5_EM

R4_EM

R3_EM

R2_EM

R1_EM

R0_EM

GPI_EM_REG2

GPI Event Mode Register 2

C7_EM

C6_EM

C5_EM

C4_EM

C3_EM

C2_EM

C1_EM

C0_EM

GPI_EM_REG3

GPI Event Mode Register 3

NA

C9_EM

C8_EM

Table 27. GPIO_INT_ENx—Register 0x1A to Register 0x1C (GPIO Interrupt Enable)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GPIO_INT_EN1 (Register 0x1A)

GPIO_INT_EN2 (Register 0x1B)

GPIO_INT_EN3 (Register 0x1C)

Table 28. KP_GPIOx—Register 0x1D to Register 0x1F (Keypad or GPIO Selection)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

KP_GPIO1 (Register 0x1D)

KP_GPIO2 (Register 0x1E)

KP_GPIO3 (Register 0x1F)

Table 29. GPI_EM_REGx—Register 0x20 to Register 0x22 (GPI Event Mode 1 to GPI Event Mode 3)

Register Name Register Description Bit 7 Bit 6 Bit Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GPIO interrupt enable (enables interrupts for GP inputs only)

Keypad or GPIO selection 0: GPIO 1: KP matrix

R7 R6 R5 R4 R3 R2 R1 R0

C7 C6 C5 C4 C3 C2 C1 C0

N/A N/A N/A N/A N/A N/A C9 C8

R7IE R6IE R5IE R4IE R3IE R2IE R1IE R0IE

C7IE C6IE C5IE C4IE C3IE C2IE C1IE C0IE

N/A N/A N/A N/A N/A N/A C9IE C8IE

(Register 0x20)

(Register 0x21)

(Register 0x22)

0: GPI not part of event FIFO 1: GPI part of event FIFO (R0 to R7)

0: GPI not part of event FIFO 1: GPI part of event FIFO (C0 to C7)

0: GPI not part of event FIFO 1: GPI part of event FIFO (C8 to C9)

Table 30. GPIO_DIRx—Register 0x23 to Register 0x25 (GPIO Data Direction)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GPIO_DIR1 (Register 0x23)

GPIO_DIR2 (Register 0x24)

GPIO_DIR3 (Register 0x25)

GPIO data direction 0: input 1: output

R7D R6D R5D R4D R3D R2D R1D R0D

C7D C6D C5D C4D C3D C2D C1D C0D

N/A N/A N/A N/A N/A N/A C9D C8D

Table 31. GPIO_INT_LVLx—Register 0x26 to Register 0x28 (GPIO Level Detect)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GPIO_INT_LVL1 (Register 0x26)

GPIO_INT_LVL2 (Register 0x27)

GPIO_INT_LVL3 (Register 0x28)

GPIO INT level detect 0: low 1: high

R7IL R6IL R5IL R4IL R3IL R2IL R1IL R0IL

C7IL C6IL C5IL C4IL C3IL C2IL C1IL C0IL

N/A N/A N/A N/A N/A N/A C9IL C8IL

Rev. D | Page 19 of 24

ADP5587 Data Sheet

GPIO_PULL2

GPIO pull disable (remove pull-ups from inputs)

C7PD

C6PD

C5PD

C4PD

C3PD

C2PD

C1PD

C0PD

GPIO_PULL3

GPIO pull disable (remove pull-ups from inputs)

N/A

C9PD

C8PD

Table 32. DEBOUNCE_DISx—Register 0x29 to Register 0x2B (Debounce Disable)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DEBOUNCE_DIS1 (Register 0x29)

DEBOUNCE_DIS2 (Register 0x2A)

DEBOUNCE_DIS3 (Register 0x2B)

Table 33. GPIO_PULLx—Register 0x2C to Register 0x2E (GPIO Pull Disable)

Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GPIO_PULL1 (Register 0x2C)

GPIO pull disable (remove pull-ups from inputs) 0: pull enabled 1: pull disabled

Debounce disable (inputs) 0: enabled 1: disabled

R7DD R6DD R5DD R4DD R3DD R2DD R1DD R0DD

C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD

N/A N/A N/A N/A N/A N/A C9DD C8DD

R7PD R6PD R5PD R4PD R3PD R2PD R1PD R0PD

(Register 0x2D)

(Register 0x2E)

0: pull enabled 1: pull disabled

Rev. D | Page 20 of 24

Data Sheet ADP5587

CONTROL

REGISTERS

HOST

PROCESSOR

CONTROL

INTERFACE

R7R6R5R4R3R2R1R0C0C1C2C3C4C5C6

C7

C9

C8

ENABLE 2 (GP O)

BACKLIGHT

ENABLE (GPO)

A0A1A2A3A4A5A6A7 B0B1B2B3B4B5B6B7 C0C1C2C3C4C5C6C7 D0D1D2D3D4D5D6D7 E0E1E2E3E4E5E6E7 F0F1F2F3F4F5F6F7

G0G1G2G3G4G5G6G7

H0H1H2H3H4H5H6H7

I0I1I2I3I4I5I6I7

J0J1J2J3J4J5J6J7

SCL

SDA

V

CC

GND

V

CC

SCL

GPI1

GPI2

SDA RST INT

19

21

23

22

18

17

20

24

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16

V

CC

BACKLIGHT

DRIVER

PWM OUTPUT

ADP5587

V

CC

RST

INT

08612-015

APPLICATIONS INFORMATION

Figure 19. ADP5587 Detailed Application Block Diagram

APPLICATIONS OVERVIEW

The ADP5587 is designed to complement host processors in a variety of ways. Its versatility makes it the ideal solution for mobile platforms that require extended keypads and GPIO expanders. The programmable registers give the designer the flexibility to configure any or all of its GPIOs in a variety of ways. Figure 19 shows a detailed application diagram.

KEYPAD CURRENT

Keypad current drain varies based on how many keys and how

Rev. D | Page 21 of 24

many rows and columns are pressed during multiple key presses. Tab l e 34 shows the typical current drain for a single key press and for two key presses.

Table 34. Typical Current Drain

Number of Key Presses Conditions

1 VCC = 1.8 V to 3.0 V 55 μA 2 VCC = 1.8 V to 3.0 V 100 μA

1

TA = TJ = −40°C to +85°C.

1

Typical Unit

ADP5587 Data Sheet

HOST

PROCESSOR

BACKLIGHT

DRIVER

PWM

BACKLIGHT

EXPANDED

GPIOs

KEYPAD MATRI X

BACKLIGHT ENABLE

ADP5587

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

C0 C1 C2 C3 C4 C5 C6 C7

D0 D1 D2 D3 D4 D5 D6 D7

E0 E1 E2 E3 E4 E5 E6 E7

F0 F1 F2 F3 F4 F5 F6 F7

G0 G1 G2 G3 G4 G5 G6 G7

H0 H1 H2 H3 H4 H5 H6 H7

I0 I1 I2 I3 I4 I5 I6 I7

J0 J1 J2 J3 J4 J5 J6 J7

I2C

RST

INT

08612-016

Figure 20. Integration Block Diagram

Rev. D | Page 22 of 24

Data Sheet ADP5587

0.50

BSC

0.50

0.40

0.30

0.25

0.20

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGD-8.

072809A

BOTTOM VIEWTOP VIEW

EXPOSED

PAD

PIN 1 INDICATOR

4.10

4.00 SQ

3.90

SEATING

PLANE

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

1

24

7

12

13

18

19

6

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

2.20

2.10 SQ

2.00

092209-B

A

B

C

D

E

0.645

0.600

0.555

0.230

0.200

0.170

2.010

1.970 SQ

1.930

1

2

3

45

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

0.287

0.267

0.247

SEATING PLANE

COPLANARITY

0.05

0.40

REF

1.60

REF SQ

0.022 REF

0.395

0.375

0.355

BALL A1

IDENTIFIER

I2C Write

ADP5587ACPZ-R7

−40°C to +85°C

0x68

0x69

24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

CP-24-10

OUTLINE DIMENSIONS

ORDERING GUIDE

Figure 21. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-24-10)

Dimensions shown in millimeters

Figure 22. 25-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-25-4)

Dimensions shown in millimeters

Temperature

Model1

ADP5587ACPZ-1-R7 −40°C to +85°C 0x60 0x61 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 ADP5587ACBZ-R7 −40°C to +85°C 0x68 0x69 25-Ball Wafer Level Chip Scale Package [WLCSP] CB-25-4 ADP5587CP-EVALZ 0x68 0x69 Evaluation Board [LFCSP_WQ] CP-24-10 ADP5587CB-EVALZ 0x68 0x69 Evaluation Board [WLCSP] CB-25-4

1

Z = RoHS Compliant Part.

Range

Address

Package Description

Rev. D | Page 23 of 24

Package Option Write Read

ADP5587 Data Sheet

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners. D08612-0-1/12(D)

Rev. D | Page 24 of 24

Datasheet ADP5587 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC CHARACTERISTICS

AC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

KEYPAD OPERATION

Key Event Tracking

Key Event Overflow

Auto-Increment

Key Event Interrupt

Keypad Lock/Unlock Feature

GENERAL-PURPOSE INPUTS AND OUTPUTS

General-Purpose Inputs (GPI)

GPI Events

275 Microsecond Interrupt Configuration

Debouncing

General-Purpose Outputs (GPOs)

Power-On Reset

I2C PROGRAMMING AND DIGITAL CONTROL

REGISTERS

REGISTER DESCRIPTIONS

APPLICATIONS INFORMATION

APPLICATIONS OVERVIEW

KEYPAD CURRENT

OUTLINE DIMENSIONS

ORDERING GUIDE