Datasheet ADP5065 Datasheet (ANALOG DEVICES)

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Page 1

Fast Charge Battery Manager with Power

Path and USB Compatibility

ADP5065

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

V_WEAK_SET AGND

PGNDx

IIN_EXT

TRK_EXT

SCL SDA

SYS_ON_OK

CHARGER CONTROL

BLOCK

3MHz

BUCK

CFILT

VBUS

AC OR

USB

VINx

PGNDx

ISO_Sx

ISO_Bx BAT_SNS THR

SWx

INDUCTOR

SYSTEM

Li-Ion

ADP5065

09370-001

Data Sheet

FEATURES

3 MHz switch mode charger

1.25 A charge current from dedicated charger Up to 680 mA charging current from 500 mA USB host Operating input voltage from 4.0 V up to 5.5 V Tolerant input voltage −0.5 V to +20 V (USB VBUS) Dead battery isolation FET between battery and

charger output

Battery thermistor input with automatic charger shutdown

for when battery temperature exceeds limits

Compliant with the JEITA Li-Ion battery charging

temperature specification

SYS_EN_OK flag to hold off system turn-on until battery is at

minimum required level for guaranteed system startup due to minimum battery voltage and/or minimum battery charge level requirements

EOC programming with C/20, C/10 and specific current level

selection

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

APPLICATIONS

Digital still cameras Digital video cameras Single cell Li-Ion portable equipment PDA, audio, GPS devices Mobile phones

GENERAL DESCRIPTION

The ADP5065 charger is fully compliant with the USB 2.0, USB 3.0, and USB Battery Charging Specification 1.1 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.

The ADP5065 operates from a 4 V to 5.5 V input voltage range but is tolerant of voltages of up to 20 V. Th is alleviates the concerns about the USB bus spiking during disconnect or connect scenarios.

The ADP5065 also features an internal FET between the dc-todc charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function on connection to a USB power supply.

Based on the type of USB source, which is detected by an external USB detection chip, the ADP5065 can be set to apply the correct current limit for optimal charging and USB compliance.

The ADP5065 comes in a very small and low profile 20-lead WLCSP (0.5 mm pitch spacing) package.

The overall solution requires only five small, low profile external components consisting of four ceramic capacitors (one of which is the battery filter capacitor), one multilayer inductor. In addition to these components, there is one optional dead battery situation default setting resistor. This configuration enables a very small PCB area to provide an integrated and performance enhancing solution to USB battery charging and power rail provision.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

Page 2

ADP5065 Data Sheet

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Recommended Input and Output Capacitance ........................ 5

I2C-Compatible Interface Timing Specifications ..................... 6

Absolute Maximum Ratings ....................................................... 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Temperature Characteristics ..................................................... 11

Typical Waveforms ..................................................................... 13

Theory of Operation ...................................................................... 15

Introduction ................................................................................ 15

Charger Modes............................................................................ 17

Thermal Management ............................................................... 19

Battery Isolation FET ................................................................. 19

Battery Detection ....................................................................... 20

Battery Pack Temperature Sensing .......................................... 22

External Resistor for V_WEAK_SET ...................................... 23

I2C Interface ................................................................................ 24

Charger Operational Flowchart ............................................... 25

I2C Register Map ......................................................................... 26

Applications Information .............................................................. 33

External Components ................................................................ 33

PCB Layout Guidelines .................................................................. 35

Power Dissipation and Thermal Considerations ....................... 37

Charger Power Dissipation ....................................................... 37

Junction Temperature ................................................................ 38

Factory-Programmable Options .................................................. 39

Packaging and Ordering Information ......................................... 40

Outline Dimensions ................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

4/12—Re v.A to Rev. B

Changes to Features Section and General Description Section ........ 1

Changes to Table 1 ............................................................................ 3

Changes to VIN1, VIN2 to PGND1, PGND2 Parameter, Tab l e 4 ... 7

Changes to Introduction Section .................................................. 15

11/11—Rev. 0 to Rev. A

Changes to Figure 10 ...................................................................... 10

Changes to Figure 17 and Figure 18 ............................................. 11

Changes to Figure 41 ...................................................................... 36

10/11—Revision 0: Initial Version

Rev. B | Page 2 of 40

Page 3

Data Sheet ADP5065

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

GENERAL PARAMETERS

Undervoltage Lockout

2.25

2.35

2.45 V Falling threshold, higher of V

and V

Total Input Current

100

Nominal USB initialized current level1

150

USB super speed

300

USB enumerated current level (specification for China)

900

Dedicated charger input

1500

Dedicated wall charger

VINx

15 mA

No battery, no ISO_Sx load, switching 3 MHz

SWxPin Leakage Current

−I

2 µA

= 0 V, TJ = −40°C to +85°C

CHARGING PARAMETERS

Fast Charge Current, CC Mode

1250 mA

> V

+ V

1, 2

Fast Charge Current Accuracy

−7 +5 % Tj = 25°C, I

= 550 mA to 1250 mA

−8 +8 % I

= 550 mA to 1150 mA, fast charge current

−17 +8 % I

= 1250 mA, Tj = 0°C to isothermal regulation

limit (typically Tj = 115°C)

Weak Charge Current

+ 20

When V

< V

1, 3

Dead Battery

Trickle to Weak Charge Threshold

2.4

2.5

2.6 V On BAT_SNS1

Trickle to Weak Charge Threshold

ΔV

90 mV

Weak Battery

Weak to Fast Charge Threshold

2.9

3.0

3.1 V On BAT_SNS

1, 3

Battery Termination Voltage

4.158

4.200

4.242

On BAT_SNS, TJ = 0°C to 115°C1

Battery Overvoltage Threshold

− 0.15

V Relative to CFILT voltage, BAT_SNS rising

Charge Complete Current

52.5 mA

= V

Accuracy

−55 +55 % I

= 32.5 mA, TJ = 0°C to 115°C

Recharge Voltage Differential

260 mV

Relative to V

, BAT_SNS falling1

Switching Frequency

2.8 3 3.2

MHz

Maximum Duty Cycle

93 %

Regulated System Voltage

ISO_STRK

3.21

3.3

3.39 V V

BAT_SNS

< V

TRK_DEAD

, trickle charging mode

PMOS On Resistance

220

285

mΩ

SPECIFICATIONS

−40°C < TJ < 125°C, VIN = 5.0 V, V

4.7 µF, L

= 1 µH, all registers are at default values, unless otherwise noted.

OUT

Table 1.

> 3.0 V, V

ISO_S

HOT

< V

THR

< V

COLD

, V

BAT_ SNS

= 3.6 V, C

= 2.2 µF, C

VIN

= 22 µF, C

DCDC

= 22 µF, C

BAT

CF ILT

UVLO

50 100 150 mV Hysteresis, higher of V

VIN

CFILT

and V

460 475 500 mA USB enumerated current level

Current Consumption

QVIN

Battery, Standby I

(Battery Voltage > V

TRK_DEAD

)

0.22 2 µA TJ = −40°C to +85°C

QISO_B

OUT

CHG

CHG(TOL)

CHG

VIN

CFILT

BAT_SNS

CCDROP

CHG

accuracy is guaranteed at temperatures from

= 0°C to isothermal regulation limit (typically

= 115°C)

CHG

Trickle Charge Current

1, 2

16 20 25 mA

TRK_DEAD

CHG_WEAK

TRK_DEA D

TRK_DEAD

CHG

TRK_DEA D

BAT_SNS

WEAK

Hysteresis

CFILT

BAT_SNS

rising

Weak Battery Threshold Hysteresis ΔV

Battery Termination Voltage Accuracy −0.3 +0.3 % On BAT_SNS, TJ = 25°C, I

Charge Complete Current Threshold

−35 +35 % I

Battery Node Short Threshold Voltage1 V

CHARGER DC-to-DC CONVERTER

Peak Inductor Current I

Load Regulation 5 mV/A DC-to-DC Power

NMOS On Resistance R

WEAK

90 mV

WEAK

TRM

= 52.5 mA1

END

BATOV

END

−25 +25 % I

RCH

2.3 2.4 2.5 V

BAT_S HR

SWCHG

MAX

1500 1750 2000 mA

L(PK)

DS(ON)P

160 210 mΩ

DS(ON)N

CFILT

Rev. B | Page 3 of 40

BAT_SNS

END

TRM

= 72.5 mA or 92.5 mA, TJ = 0°C to 115°C

= 52.5 mA, TJ = 0°C to 115°C

TRM

Page 4

ADP5065 Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Bump to Bump Resistance Between

115

mΩ

Includes bump resistances and battery isolation

Regulated System Voltage

3.15

3.3

3.45 V V

< V

, fast charging CC mode

VINx Input

High Voltage Blocking FET On

340

455

mΩ

IIN = 500 mA

Current, Suspend Mode

1.3

2.5

EN_CHG = low

Input Voltage

Good Threshold

Rising

3.78

3.9

4.0 V

Overvoltage Threshold

5.35

5.42

5.5 V

Overvoltage Threshold Hysteresis

75 mV

Minimum Rise Time for VINx from

µs

Minimum Fall Time for VINx from

4 V to 0 V

µs THERMAL CONTROL

Thermal Early Warning Temperature

130 °C

Thermal Shutdown Temperature

TSD 140 °C

TJ rising

Thermistor Current

10,000 NTC

400

μA

Thermistor Capacitance

100

Resistance Thresholds

Cool to Cold Resistance

24,050

27,300

30,600

Hot Temperature Threshold

60 °C

No battery charging occurs

Hot to Typical Resistance

2990

3310

3640 Ω

Typical to Hot Resistance

2730

3030

3330 Ω

JEITA SPECIFICATION4

Resistance Thresholds

Cool to Cold Resistance

24,050

27,300

30,600

JEITA Cool Temperature

10 °C

Battery charging occurs at 50% of

Resistance Thresholds

Typical to Cool Resistance

15,200

17,800

20,400

JEITA Typical Temperature

°C

Normal battery charging occurs at default/programmed levels

Resistance Thresholds

Warm to Typical Resistance

4710

5400

6100 Ω

Resistance Thresholds

Warm to Hot Resistance

2730

3030

3330 Ω

JEITA Hot Temperature

60 °C

No battery charging occurs

BATTERY ISOLATION FET

ISO_Bx and ISO_Sx Bumps

Battery Supplementary Threshold V

HIGH VOLTAGE BLOCKING FET

DSONISO

ISO_SFC

0 5 10 mV V

THISO

PMOS on resistance; on battery supplement mode, V

TRK_DEA D

ISO_S[1:2]

= 0 V, V

< V

BAT_SNS

ISO_B[1:2]

ISO_B

, V

SYS

= 3.6 V, I

rising

= 500 mA

ISO_B

Resistance

DSONHV

SUSPEND

VIN_OK_RISE

Falling V

3.6 3.67 V

VIN_OK_FALL

VIN_OV

VINx Transition Timing

5 V to 20 V

VIN_RISE

VIN_FALL

Isothermal Charging Temperature T

115 °C

LIM

SDL

110 °C TJ falling THERMISTOR CONTROL

NTC_10k

100,000 NTC I

Cold Temperature Threshold T

Cold to Cool Resistance R

40 μA

NTC_100k

NTC

0 °C No battery charging occurs

NTC_COLD

COLD_FA LL

23,100 26,200 29,400 Ω

COLD_R ISE

NTC_HOT

Resistance Thresholds

HOT_FALL

HOT_RIS E

JEITA Cold Temperature T

Cold to Cool Resistance R

Cool to Typical Resistance R

Typical to Warm Resistance R

JEITA Warm Temperature T

Hot to Warm Resistance R

0 °C No battery charging occurs

JEITA_C OLD

COLD_FA LL

23,100 26,200 29,400 Ω

COLD_R ISE

JEITA_ COOL

programmed level

TYP_FALL

14,500 17,000 19,500 Ω

TYP_RISE

JEITA_TY P

WARM_FALL

WARM_RISE

JEITA_W ARM

4320 4950 5590 Ω

45 °C Battery termination voltage (V

by 100 mV

2990 3310 3640 Ω

HOT_FALL

HOT_RIS E

JEITA_H OT

Rev. B | Page 4 of 40

) is reduced

TRM

Page 5

Data Sheet ADP5065

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Sink Current

Source Current

Battery Threshold

Low

1.8

1.9

2.0 V

No Battery Threshold

3.3 V

≥ 3.7 V, valid after charge complete (see

Figure 38)

Trickle Charge Timer

60 min

Charge Complete Timer

END

7.5 min

BAT_SNS

= V

TRM

, I

CHG

< I

END

Deglitch Timer

tDG 31 ms

Applies to V

, V

, I

, V

Safety Timer

min

Maximum Logic Low Input Voltage

VIL

0.5 V Applies to SCL, SDA, TRK_EXT, IIN_EXT

Pull-Down Resistance

215

350

610

kΩ

Applies to TRK_EXT, IIN_EXT

BATTERY DETECTION

SINK

SOUR CE

BATL

High V

3.4 V

BATH

NOBAT

TRM

3.0 V V

Battery Detection Timer t

333 ms

BATOK

< 3.7 V, valid after charge complete (see

TRM

TIMERS

Start Charging Delay Timer t

Fast Charge Timer t

1 sec

START

TRK

600 min

CHG

TRK

RCH

END

DEAD

Watchdog Timer1 tWD 32 sec

SAFE

Battery Node Short Timer1 t

30 sec

BAT_S HR

LOGIC INPUTS

Maximum Voltage on Digital Inputs V

5.5 V

DIN_MAX

Minimum Logic High Input Voltage VIH 1.2 V Applies to SCL, SDA, TRK_EXT, IIN_EXT

These values are programmable via I2C. Values are given with default register values.

The output current during charging can be limited by I

Programmable via external resistor programming, if required.

JEITA can be enabled or disabled in I2C.

or by the isothermal charging mode.

BUS

RECOMMENDED INPUT AND OUTPUT CAPACITANCE

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITANCE

VINx Capacitance 1.0 µF Effective capacitance CFILT Pin Total External Capacitance 2.0 4.7 5.0 μF Effective capacitance ISO_Sx Pin Total Capacitance 10 50 µF Effective capacitance ISO_Bx Pin Total Capacitance 10 µF Effective capacitance

VIN_OK

Rev. B | Page 5 of 40

Page 6

ADP5065 Data Sheet

I2C-COMPATIBLE INTERFACE2

S = START CONDITION Sr = REPEATED S TART CONDITION P = STOP CONDITION

LOW

SU,DAT

HD,DAT

SU,STA

SU,STO

SPtR

BUF

HIGH

S Sr P S

SDA

SCL

HD,STA

09370-002

I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS

Table 3.

Parameter1 Symbol Min Typ Max Unit

Capacitive Load, Each Bus Line CS 400 pF SCL Clock Frequency f SCL High Time t SCL Low Time t Data Setup Time t Data Hold Time t Setup Time for Repeated Start t Hold Time for Start/Repeated Start t Bus Free Time Between a Stop and a Start Condition t Setup Time for Stop Condition t

SCL

HIGH

LOW

SU DAT

0 0.9 µs

HDDAT

SU STA

HD STA

BUF

SUSTO

Rise Time of SCL/SDA tR 20 300 ns Fall Time of SCL/SDA tF 20 Pulse Width of Suppressed Spike t

Guaranteed by design.

A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2, the I2C timing

diagram.

Timing Diagram

400 kHz

0.6 µs

1.3 µs 100 ns

0.6 µs

1.3 µs

0.6 µs

300 ns

0 50 ns

Figure 2. I

C Timing Diagram

Rev. B | Page 6 of 40

Page 7

Data Sheet ADP5065

VIN1, VIN2 to PGND1, PGND2

−0.5 V to +20 V

Stresses a bove those l isted under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

All Other Pins to AGND −0.3 V to +6 V Continuous Drain Current, Battery Supple-

mentary Mode, from ISO_Bx to ISO_Sx TJ ≤ 85°C 2.2 A

TJ = 125°C 1.1 A Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θJC θJB Unit

20-Lead WLC SP1 46.8 0.7 9.2 °C/W

5 × 4 array, 0.5 mm pitch (2.75 mm × 2.08 mm); based on a JEDEC, 2S2P,

4-layer board with 0 m/sec airflow.

Maximum Power Dissipation

The maximum safe power dissipation in the ADP5065 package is limited by the associated rise in junction temperature (T

) on

the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADP5065. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in the silicon devices that potentially cause failure.

ESD CAUTION

Rev. B | Page 7 of 40

Page 8

ADP5065 Data Sheet

TOP VIEW

(BALL SI DE DOWN)

Not to Scale

2 3 4

BALL A1 CORNER

V_WEAK_SET

SDA

BAT_SNS

VIN1

THR

ISO_B1

ISO_S1

SW1

IIN_EXT

ISO_B2

ISO_S2

PGND1

SCL

TRK_EXT

AGND

SYS_ON_OK

VIN2 SW2 PGND2

CFILT

09370-003

SDA

I/O

I2C-Compatible Interface Serial Data.

THR I Battery Pack Thermistor Connection. If not used, connect a dummy 10 kΩ resistor from THR to GND.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions

No. Mnemonic Typ e1 Description

D3, E3 SW1, SW2 I/O DC-to-DC Converter Inductor Connection. These pins are high current outputs when in charging mode. D1, E1 VIN1, VIN2 I/O Power Connection to USB VBUS. These pins are high current inputs when in charging mode. D4, E4 PGND1,

C2 AGND G Analog Ground. E2 CF ILT I/O 4.7 μF Filter Capacitor Connection. This pin is a high current input/output when in charging mode. C3, C4 ISO_S1, ISO_S2 I/O Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. B3, B4 ISO_B1,

A2 SCL I I2C-Compatible Interface Serial Clock.

A4 IIN_EXT I Set Input Current Limit. This pin sets the input current limit directly. When IIN_EXT = low or high-Z, the

B2 TRK_EXT I Enable Trickle Charge Function. When TRK_EXT = low or high-Z, the trickle charge is enabled. When

C1 B AT_SNS I Battery Voltage Sense Pin. D2 SYS_ON_OK O Battery Okay Open-Drain Output Flag. Active low. This pin enables the system when the battery

A1 V_WEAK_SET I/O External Resistor Setting Pin for V_WEAK threshold. The use of this pin is optional. When not in use,

I is input, O is output, I/O is input/output, and G is ground.

PGND2

ISO_B2

Figure 3. Pin Configuration

G Charger Power Ground. These pins are high current inputs when in charging mode.

I/O Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.

input limit is 100 mA. When IIN_EXT = high, the input limit is 500 mA.

TRK_EXT = high, the trickle charge is disabled.

reaches V

WEAK

connect to GND.

Rev. B | Page 8 of 40

Page 9

Data Sheet ADP5065

100

2.5 2.9 3.3 3.7 4.1 4.5

EFFICIENCY (%)

BATTERY VOLTAGE (V)

VIN INPUT LIMIT 100mA

INPUT LIMIT 500mA

09370-004

0.001 0.01 0.1 1

SYSTEM VOLTAGE (V)

SYSTEM OUTPUT CURRENT ( A)

3.25

3.26

3.27

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

09370-005

700

100

200

300

400

500

600

2.7 3.0 3.3 3.6 3.9 4.2

BATTERY CHARG E CURRE NT (mA)

BATTERY VOLTAGE (V)

09370-006

0.01 0.1 1 SYSTEM OUTPUT CURRENT ( A)

100

EFFICI E NCY ( %)

09370-007

2.7 3.0 3.3 3.6 3.9 4.2 BATTERY VOLTAGE (V)

4.5

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.3

4.1

SYSTEM VOLTAGE (V)

SYSTEM VOLTAGE

BATTERY VOLTAGE

09370-008

2.7 3.0 3.3 3.6 3.9 4.2 BATTERY VOLTAGE (V)

140

100

120

BATTERY CHARG E CURRE NT (mA)

09370-009

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Battery Charger Efficiency vs. Battery Voltage, VIN = 5.0 V

Figure 5. System Voltage Regulation vs. Output Current, VIN = 5.0 V

Figure 7. System Voltage Efficiency vs. Output Current, VIN = 5.0 V

Figure 8. System Voltage vs. Battery Voltage, VIN = 5.0 V, ILIM = 100 mA

Figure 6. USB Compliant Charge Current vs. Battery Voltage,

= 5.0 V, ILIM = 500 mA

Figure 9. USB Limited Battery Charge Current vs. Battery Voltage,

= 5.0 V, ILIM = 100 mA

Rev. B | Page 9 of 40

Page 10

ADP5065 Data Sheet

2.7 3.0 3.3 3.6 3.9 4.2 BATTERY VOLTAGE (V)

100

RON RESISTANCE (mΩ)

09370-010

1 2 3 4 5 6

VIN VOLTAGE (V)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

VIN CURRENT (mA)

09370-011

0 50 100 150

CHARGE TIM E ( M inutes)

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

BATTERY VOLTAGE (V)

CURRENT (A)

BAT_SNS

ISO_B

VIN

09370-012

Figure 10. Battery Isolation FET Resistance vs. Battery Voltage, VIN = 5.0 V,

Load Current = 1.0 A

Figure 11. VINx Current vs. VINx Voltage, Suspend Mode (EN_CHG = 0)

Figure 12. Charge Profile, VIN = 5.0 V, ILIM = 500 mA,

Battery Capacity = 1320 mAh

Rev. B | Page 10 of 40

Page 11

Data Sheet ADP5065

AMBIENT T E M P E RATURE (°C)

VIN OVERVOLTAGE PROTECTION (V)

5.25

5.30

5.35

5.40

5.45

5.50

5.55

5.60

5.65

5.70

5.75

–40 –20 0 20 40 60 80 100 120

09370-013

AMBIENT T E M P E RATURE (°C)

SYSTEM VOLTAGE (V)

–40 –20 0 20 40 60 80 100 120

3.275

3.280

3.285

3.290

3.295

3.300

3.305

3.310

3.315

09370-014

AMBIENT T E M P E RATURE (°C)

INPUT CURRENT LIMIT ( mA)

–40 –20 0 20 40 60 80 100 120

100

150

200

250

300

350

400

450

500

VIN INPUT LIMIT 100mA

INPUT LIMIT 500mA

09370-015

AMBIENT T E M P E RATURE (°C)

TRM

ACCURACY (%)

–40 –20 0 20 40 60 80 100 120

–1.0

1.0

0.5

–0.5

TRM

= 3.50V

TRM

= 3.80V

TRM

= 4.20V

TRM

= 4.42V

09370-016

AMBIENT T E M P E RATURE (°C)

SWITCHING FREQUE NCY ( M Hz )

–40 –20 0 20 40 60 80 100 120

2.90

2.92

2.94

2.96

2.98

3.00

3.02

3.04

3.06

3.08

3.10

09370-017

AMBIENT T E M P E RATURE (°C)

CHARGE CURRENT (A)

–40 –20 0 20 40 60 80 100 120

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

09370-018

TEMPERATURE CHARACTERISTICS

Figure 13. VINx Overvoltage Protection Rising Threshold vs. Ambient

Temperature

Figure 14. System Voltage vs. Ambient Temperature, VIN = 5.0 V, R

LOAD

= 33 Ω

Figure 16. Termination Voltage vs. Ambient Temperature, VIN = 5.0 V, V

Programming 3.50 V, 3.80 V, 4.20 V, and 4.42 V

Figure 17. Switching Frequency vs. Ambient Temperature, VIN = 5.0 V

TRM

Figure 15. Input Current Limit vs. Ambient Temperature, VIN = 5.0 V

= 5.0 V, V

ISO_B

= 3.6 V, I

= 1050 mA

CHG

Rev. B | Page 11 of 40

Figure 18. Fast Charge Current vs. Ambient Temperature,

Page 12

ADP5065 Data Sheet

AMBIENT T E M P E RATURE (°C)

BATTERY L E AKAGE CURRENT (µA)

–40 –20 0 20 40 60 80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0 V

ISO_B

= 2.7V

ISO_B

= 3.6V

ISO_B

= 4.2V

09370-019

AMBIENT T E M P E RATURE (°C)

INPUT CURRENT ( mA)

–40 –20 0 20 40 60 80

1.16

1.18

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

09370-020

AMBIENT T E M P E RATURE (°C)

CHARGE CURRENT (A)

0 20 40 80 12060 100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

09370-021

Figure 19. Battery Leakage Current vs. Ambient Temperature

Figure 20. VINx Quiescent Current vs. Temperature, VIN = 5.0 V,

Suspend Mode (EN_CHG = 0)

Figure 21. Isothermal Regulation of Charge Current vs. Ambient

Temperature, I

= 750 mA, VIN = 5.0 V, V

CHG

ISO_B

= 3.6 V

Rev. B | Page 12 of 40

Page 13

Data Sheet ADP5065

CH1 2.0V CH2 2.0V CH3 200mA CH4 200mA

100µs A CH2 44mA

T 0.00s

ISO_B

ISO_S

VIN

INRUSH

CURRENT

09370-022

CH1 2.0V CH2 2.0V CH3 500mA CH4 500mA

20µs A CH3 40mA

T 0.00s

ISO_B

ISO_S

VIN

09370-023

CH1 2.0V CH2 2.0V CH3 500mA CH4 500mA

100µs A CH3 430mA

T 0.00s

ISO_B

ISO_S

VIN

09370-024

CH1 2.0V CH2 2.0V CH3 200mA CH4 200mA

100µs A CH3 44mA

T 0.00s

ISO_B

ISO_S

VIN

09370-025

CH1 2.0V CH2 2.0V CH3 500mA CH4 500mA

100µs A CH3 40mA

T 0.00s

ISO_B

ISO_S

VIN

09370-026

CH1 2.0V CH2 50.0mV

CH4 500mA

800ns A CH1 2.16V

T –8.0ns

ISO_S

09370-027

TYPICAL WAVEFORMS

Figure 22. Typical Waveforms, VINx Connect From High Impedance to

VBUS, ILIM = 100 mA

Figure 23. Mode Change, Fast Charge to Suspend (EN_CHG from High to

Low), ILIM = 500 mA, R

LOAD

= 33 Ω

Figure 25. Typical Waveforms, VINx Disconnect from VBUS to High

Impedance, ILIM = 100 mA

Figure 26. Mode Change, Suspend to Fast Charge (EN_CHG from Low to

High), ILIM = 500 mA, R

LOAD

= 33 Ω

Figure 24. VINx Current Limit Change from 100 mA to 500 mA,

EN_CHG = High, V

= 5.0 V, R

LOAD

= 33 Ω

Figure 27. Typical Waveforms, Heavy Load, VIN = 5.0 V, I

Rev. B | Page 13 of 40

= 1000 mA

ISO_S

Page 14

ADP5065 Data Sheet

CH4 500mA

200µs A CH4 250mA

T 600.0µs

ISO_S

CH1 100mV

09370-028

CH2 2.0V 100µs A CH2 2.76V

T 0.00s

ISO_B

ISO_S

ISO_B

AND C

ISO_S

INRUSH CURRENT

CH3 2.0A

09370-029

CH1 2.0V CH2 50.0mV

CH4 200mA

800ns A CH1 2.16V

ISO_S

T –8.00ns

09370-030

Figure 28. System Voltage Load Transient, VIN = 5.0 V, No Battery

Figure 29. Battery Connect

Figure 30. Typical Waveforms, Light Load, VIN = 5.0 V, I

= 100 mA

ISO_S

Rev. B | Page 14 of 40

Page 15

Data Sheet ADP5065

THEORY OF OPERATION

INTRODUCTION

The ADP5065 is a fully I2C-programmable charger for singlecell lithium-ion or lithium-polymer batteries suitable for a wide range of portable applications.

The highly efficient switcher dc-to-dc architecture enables higher charging currents as well as a lower temperature charging operation that results in faster charging times because of the following features:

• 3 MHz switch mode charger.

• 1.25 A charge current from dedicated charger.

• Up to 680 mA of charging current from a 500 mA

USB host.

The ADP5065 operates from an input voltage from 4 V to 5.5 V but is tolerant of voltages of up to 20 V. This alleviates the concern about USB bus spiking during disconnection or connection scenarios.

The ADP5065 features an internal FET between the dc-to-dc charger output and the battery. This permits battery isolation and, hence, system powering in a dead battery or no battery scenario, which allows for immediate system function on connection to a USB power supply.

The ADP5065 is fully compliant with the USB 3.0 battery charging specification and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port. Based on the type of USB source, which is detected by an external USB detection device, the ADP5065 can be set to apply the correct current limit for optimal charging and USB compliance. The USB charger permits correct operation under all USB compliant sources such as, wall chargers, host chargers, hub chargers, and standard hosts and hubs.

A processor is able to control the USB charger using the I program the charging current and numerous other parameters including

• Trickle charge current level.

• Trickle charge voltage threshold.

• Weak charge (constant current) charge current level.

• Fast charge (constant current) charge current level.

• Fast charge (constant voltage) charge voltage level at 1%

accuracy.

• Fast charge safety timer period.

• Watchdog safety timer parameters.

• Weak battery threshold detection.

• Charge complete threshold.

• Recharge threshold.

• Charge enable/disable.

• Battery pack temperature detection and automatic charger

shutdown.

C to

Rev. B | Page 15 of 40

Page 16

SW1

SW2

VIN1

VIN2

THR

+ –

NTC CURRENT

CONTROL

COLD COOL

WARM

HOT

NTC

TRICKLE CURRENT SOURCE

CFILT

+ –

BATTERY DETECTION

+ –

TRICKLE

3.4V

1.9V

0.5V

WEAK

+ –

CHARGE CONTROL

CFILT

+ –

EOC

TO SYSTEM

LOAD

+ –

VIN

OVERVOLTAGE

+ –

VIN LIMIT

BATTERY

ISOLATION FET

+ –

VIN GOOD

CFILT – 150mV

+ –

BATTERY OVERVOLTAGE

HIGH VOLTAGE BLOCKING FET

SCL SDA

TO USB VBUS

OR WALL ADAPTER

D4 E4C2

PGND1

PGND2

AGND

IIN_EXT TRK_EXT

V_WEAK_SET

OPTIONAL

+ –

–

THERMAL CONT ROL

SINGLE CELL

Li-Ion

TSD 140ºC

WARNING 130ºC

ISOTHERMAL 115ºC

TSD DOWN 110ºC

SYS_ON_OK

SYSTEM

VOLTAGE OK

LOGIC

0.5V

3.9V

5.42V

HV-FET

CONTROL

3MHz OSC

IND_PEAK_INT

COIL

CURRENT

DETECTION

DC-DC CONTROL

ISO_S1

ISO_S2

ISO_B1

ISO_B2

BATTERY DETECTION SINK

BAT_SNS

C INTERFACE

AND

CONTROL LOGIC

CV-MODE RECHARGE

BATTERY: OPEN SHORT

09370-031

ADP5065 Data Sheet

Figure 31. Block Diagram

Rev. B | Page 16 of 40

Page 17

Data Sheet ADP5065

Trickle charge enabled

The ADP5065 also includes a number of significant features to optimize charging and functionality, including

• Thermal regulation for maximum performance.

• USB host current-limit accuracy: ±5 %.

• Termination voltage accuracy: ±1 %.

• Battery thermistor input with automatic charger shutdown

in the event that the battery temperature exceeds limits. (Compliant with the JEITA L i-Ion battery charging temperature specification.)

• Offloads processor to manage external pin (TRK_EXT)

control to enable/disable trickle charging.

• Direct external pin (IIN_EXT) control of 100 mA or

500 mA input current limit.

• Optional external resistor programming input, V_WEAK_

SE T, which is used for setting the V the battery reaches the V

threshold, the ADP5065 pulls

WEAK

threshold. When

WEAK

down the SYS_EN_OK open-drain output flag. The flag can be used to hold off system turn on until the battery is at the minimum required level for a guaranteed system startup.

CHARGER MODES

Input Current Limit

The VINx input current limit is controlled via an internal I2C ILIM register. The input current limit can also be controlled via the IIN_EXT pin as outlined in Ta b l e 7. Any change in the I default from 100 mA dominates over the pin setting.

Table 7. IIN_EXT Operation

IIN_EXT Function

0 100 mA input current limit or I2C programmed value 1 500 mA input current limit or I2C programmed value

(or reprogrammed I

C value from 100 mA default)

USB Compatibility

The ADP5065 charger provides support for the following connections through the single connector VINx pin.

The ADP5065 features a programmable input current limit to ensure compatibility with the requirements listed in Tabl e 8. The current limit defaults to 100 mA to allow compatibility with a USB host or hub that is not configured.

The I

C register default is 100 mA. An I2C write command to the ILIM register overrides the IIN_EXT pin and the I register default value can be reprogrammed for alternative requirements.

When the input current limiting feature is used, the available input current may be too low for the charger to meet the programmed charging current, I

, and the rate of charge is

CHG

reduced. In this case, the VIN_ILIM flag is set.

When connecting voltage to VINx without having the proper voltage level on the battery side, the HV blocking part is in a state wherein it draws only 1.3 mA (typical) of current until the V

has reached the VIN_OK level.

Table 8. Input Current Compatibility with Standard USB Limits

Mode Standard USB Limit ADP5065 Function

USB (China Only)

100 mA limit for standard USB host or hub

300 mA limit for Chinese USB

100 mA input current limit

or I

C programmed value

300 mA input current limit

or I

C programmed value

specification

USB 2.0 100 mA limit for stan-

dard USB host or hub 500 mA limit for stan-

dard USB host or hub

USB 3.0 150 mA limit for

super speed USB 3.0

100 mA input current limit

or I

C programmed value

500 mA input current limit

or I

C programmed value

150 mA input current limit

or I

C programmed value

host or hub 900 mA limit for

super speed, high

900 mA input current limit

or I

C programmed value speed USB host or hub charger

Dedicated Charger

1500 mA limit for dedicated charger or

1500 mA input current limit

or I

C programmed value low/full speed USB host or hub charger

Trickle Charge Mode

A deeply discharged Li-Ion cell may exhibit a very low cell voltage making it unsafe to charge the cell at high current rates. The

ADP5065 charger uses a trickle charge mode to reset the battery

pack protection circuit and lift the cell voltage to a safe level for fast charging. A cell with a voltage below V the trickle mode current, I

. During trickle charging mode,

TRK_DEAD

is charged with

the CHARGER_STATUS register is set.

During trickle charging, the ISO_Sx node is regulated to V

by the dc-to-dc converter and the battery isolation FET

ISO_STRK

is off, which means the battery is isolated from the system power supply.

Trickle charging can be controlled via the TRK_EXT external pin (see Ta b l e 9). Note that any change in the I

C EN_TRK bit

dominates over the pin setting.

Table 9. TRK_EXT Operation

TRK_EXT Function

1 Trickle charge disabled

Trickle Charge Mode Timer

The duration of trickle charge mode is monitored to ensure the battery is revived from its deeply discharged state. If trickle charge mode runs for longer than 60 minutes without the cell voltage reaching V

, a fault condition is assumed and

TRK_DEAD

charging stops. The fault condition is asserted on the CHARGER_STATUS register, allowing the user to initiate the fault recovery procedure specified in the Fault Recovery section.

Rev. B | Page 17 of 40

Page 18

ADP5065 Data Sheet

Weak Charge Mode (Constant Current)

When the battery voltage exceeds V V

, the charger switches to the intermediate charge mode.

WEAK

TRK_DEAD

but is less than

During the weak charge mode, the battery voltage is too low to allow the full system to power-up. Due to the low level of the battery, the USB transceiver cannot be powered and, therefore, cannot enumerate for more current from a USB host. Consequently, the USB limit remains at 100 mA.

The system microcontroller may or may not be powered by the charger output voltage (V

) depending upon the amount of

ISO_SFC

current required by the microcontroller and/or the system architecture. In this case, the battery charge current (I

CHG_W EAK

) cannot be increased above 20 mA to ensure the microcontroller can still operate (if doing so) nor increased above the 100 mA USB limit. Thus, set the battery charging current as follows:

• Set the default 20 mA via the linear trickle charger branch (to

ensure that the microprocessor remains alive if powered by the main switching charger output, ISO_Sx). Any residual current on the main switching charger output, ISO_Sx, is used to charge the battery at up to the preprogrammed level in the I

C for I

(fast charge current limit) or I

CHG

LIM

(input current limit).

• During weak current mode, other features may prevent the

actual programmed weak charging current from reaching its full programmed value. Isothermal charging mode or input current limiting for USB compatibility may affect the programmed weak charging current value under certain operating conditions. During weak charging, the ISO_Sx node is regulated to V

by the battery isolation FET.

ISO_SFC

Fast Charge Mode (Constant Current)

When the battery voltage exceeds V

TRK_DEAD

and V

WEAK

, the charger switches to fast charge mode, charging the battery with the constant current, I

. During fast charge mode (constant

CHG

current), the CHARGER_STATUS register is set.

During constant current mode, other features may prevent the current, I

, from reaching its full programmed value.

CHG

Isothermal charging mode or input current limiting for USB compatibility may affect the value of I

under certain oper-

CHG

ating conditions. The voltage on ISO_Sx is regulated to stay at V

by the battery isolation FET when V

ISO_SFC

ISO_B

< V

ISO_SFC

Rev. B | Page 18 of 40

Fast Charge Mode (Constant Voltage)

As the battery charges, its voltage rises and approaches the termination voltage, V

. The ADP5065 charger monitors the voltage

TRM

on the BAT_SNS pin to determine when charging should end. However, the internal ESR of the battery pack combined with PCB and other parasitic series resistances creates a voltage drop between the sense point at the BAT_SNS pin and the cell terminal itself. To compensate for this and ensure a fully charged cell, the

ADP5065 enters a constant voltage charging mode when the

termination voltage is detected on the BAT_SNS pin. The

ADP5065 reduces charge current gradually as the cell continues to

charge, maintaining a voltage of V

on the BAT_SNS pin. During

TRM

fast charge mode (constant voltage), the CHARGER_ STAT U S register is set.

Fast Charge Mode Timer

The duration of fast charge mode is monitored to ensure that the battery is charging correctly. If the fast charge mode runs for longer than t reaching V

without the voltage at the BAT_SNS pin

CHG

, a fault condition is assumed and charging stops.

TRM

The fault condition is asserted on the CHARGER_STATUS register allowing the user to initiate the fault recovery procedure specified in the

If the fast charge mode runs for longer than t

Fault Recovery section.

CHG

, and V

TRM

has been reached on the BAT_SNS pin but the charge current has not yet fallen below I

, charging stops. No fault condition is

END

asserted in this circumstance and charging resumes as normal if the recharge threshold is breached.

Watchdog Timer

The ADP5065 charger features a programmable watchdog timer function to ensure charging is under the control of the processor. The watchdog timer starts running when the

ADP5065 charger determines that the processor should be

operational, that is, when the processor sets the RESET_WD bit for the first time or when the battery voltage is greater than the weak battery threshold, V

. When the watchdog timer has

WEAK

been triggered, it must be reset regularly within the watchdog timer period, t

If the watchdog timer expires without being reset while in charger mode, the ADP5065 charger assumes there is a software problem and triggers the safety timer, t

. For more infor-

SAFE

mation see the Safety Timer section.

Page 19

Data Sheet ADP5065

Safety Timer

If the watchdog timer (see the Watchdog Timer section for more information) expires while in charger mode, the ADP5065 charger initiates the safety timer, t programmed charging parameters by this time, the I the default value. Charging continues for a period of t

. If the processor has

SAFE

is set to

LIM

SAFE

, then

the charger switches off and sets the CHARGER_STATUS register.

Charge Complete

The ADP5065 charger monitors the charging current while in constant voltage fast charge mode. If the current falls below I

and remains below I

END

for t

END

, charging stops and the CHDONE flag is set. If the charging current falls below I

for less than t

END

and then rises above I

END

again, the t

END

timer resets.

Recharge

After the detection of charge complete, and the cessation of charging, the ADP5065 charger monitors the BAT_SNS pin as the battery discharges through normal use. If the BAT_SNS pin voltage falls to V

, the charger reactivates charging. Under

RCH

most circumstances, triggering the recharge threshold results in the charger starting directly into fast charge constant voltage mode.

Battery Charging Enable/Disable

The ADP5065 charging function can be disabled by setting the

C EN_CHG bit to low.

THERMAL MANAGEMENT

Isothermal Charging

To assist with the thermal management of the ADP5065 charge r, the battery charger provides an isothermal charging function. As the on-chip power dissipation and die temperature increase, the ADP5065 charger monitors die temperature and limits output current when the temperature reaches T (typically at 115°C). The die temperature is maintained at T through the control of the charging current into the battery. A reduction in power dissipation or ambient temperature may allow the charging current to return to its original value, and the die temperature subsequently drops below T

LIM

isothermal charging, the THERM_LIM flag is set to high.

LIM

. During

LIM

Rev. B | Page 19 of 40

Thermal Shutdown and Thermal Early Warning

The ADP5065 switching charger features a thermal shutdown threshold detector. If the die temperature exceeds T

, the

ADP5065 charger is disabled, and the TSD 140°C bit is set. The ADP5065 charger can be reenabled when the die temperature

drops below the T To reset the TSD 140°C bit, write to the I

falling limit and the TSD 140°C bit is reset.

C Fault Register 0x0D

or cycle the power.

Before die temperature reaches T T

is exceeded. This allows the system to accommodate power

SDL

, the early warning bit is set if

consumption before thermal shutdown occurs.

Fault Recovery

Before performing the following operation, it is important to ensure that the cause of the fault has been rectified.

To recover from a charger fault (when the CHARGER_STATUS equals 110), cycle power on VINx or write high to reset the I

fault bits in the fault register.

BATTERY ISOLATION FET

The ADP5065 charger features an integrated battery isolation FET for power path control. The battery isolation FET isolates a deeply discharged Li-Ion cell from the system power supply in both trickle and fast charge modes, thereby allowing the system to be powered at all times.

When VINx is below V conducting mode.

The battery isolation FET is off during trickle charge mode. When the battery voltage exceeds V FET switches to the system voltage regulation mode. During system voltage regulation mode, the battery isolation FET maintains the V

ISO_SFC

battery voltage exceeds V full conducting mode.

The battery isolation FET supplements the battery to support high current functions on the system power supply.

When voltage on ISO_Sx drops below ISO_Bx, the battery isolation FET enters into full conducting mode.

When voltage on ISO_Sx rises above ISO_Bx, the isolation FET enters regulating mode or full conduction mode, depending on the Li-Ion cell voltage and the dc-to-dc charger mode.

, the battery isolation FET is in full

VIN_OK

, the battery isolation

TRK

voltage on the ISO_Sx pins. When the

, the battery isolation FET is in

ISO_SFC

Page 20

ADP5065 Data Sheet

BATTERY DETECTION

Battery Level Detection

The ADP5065 charger features a battery detection mechanism to detect an absent battery. The charger actively sinks and sources current into the ISO_Bx/BAT_SNS node, and voltage vs. time is detected. The sink phase is used to detect a charged battery, whereas the source phase is used to detect a discharged b atter y.

The sink phase (see Figure 32) sinks I ISO_Bx/ BAT_SNS pins for a time, t below V

when the t

BATL

timer expires, the charger assumes no

BATOK

battery is present, and starts the source phase. If the BAT_SNS exceeds the V

voltage when the t

BATL

charger assumes the battery is present, and begins a new charge cycle.

The source phase sources I BAT_SNS pins for a time, t V

before the t

BATH

BATOK

SOURCE

BATOK

timer expires, the charger assumes that no battery is present. If the BAT_SNS does not exceed the V voltage when the t

timer expires, the charger assumes that a

BATOK

battery is present, and begins a new charge cycle.

current from the

SINK

. If the BAT_SNS pin is

BATOK

timer expires, the

BATOK

current to ISO_Bx or the

. If the BAT_SNS pin exceeds

BATH

Battery (ISO_Bx) Short Detection

A battery short occurs under a damaged battery condition or when the battery protection circuitry is enabled.

On commencing trickle charging, the ADP5065 charger monitors the battery voltage. If this battery voltage does not exceed V

within the specified timeout period, t

BAT_ SHR

, a fault is declared and the charger is stopped by turning the battery isolation FET off but the system voltage is maintained at V

by the linear regulator.

ISO_STRK

The trickle charge branch is active during the battery short scenario, and trickle charge current to the battery is maintained until the 60 minute trickle charge mode timer expires.

After source phase, if the ISO_Bx or BAT_SNS level remains below V

, either the battery voltage is low or the battery node

BATH

can be shorted. As a result of the battery voltage being low, trickle charging mode is initiated (see Figure 33). If the BAT_SNS level remains below V

BAT_ SHR

after t

BAT_ SHR

has elapsed,

the ADP5065 assumes that the battery node is shorted.

Rev. B | Page 20 of 40

Page 21

Data Sheet ADP5065

OPEN

ISO_Bx

SINK PHASE

LOGIC

STATUS

OPEN

SHORT

BAT_OK

BATL

SINK

ISO_Bx

OPEN

LOGIC

STATUS

SOURCE PHASE

BAT_OK

BATH

SOURCE

09370-032

SHORT

SINK PHASE SOURCE P HAS E TRICKLE CHARGE

ISO_Bx

SHORT

ISO_Bx

SHORT

ISO_Bx

LOGIC

STATUS

OPEN

SHORT

BAT_OK

LOGIC

STATUS

SHORT

LOW

BATTERY

BAT_OK

LOGIC

STATUS

SHORT

BAT_SHR

BATL

BATH

BAT_SHR

SOURCE

TRK_DEAD

SINK

09370-033

Figure 32. Battery Detection Sequence

Figure 33. Battery Short Detection Sequence

Rev. B | Page 21 of 40

Page 22

ADP5065 Data Sheet

JEITA Cool Temperature Limit—Reduced Charge Current Levels

BATTERY PACK TEMPERATURE SENSING

Battery Thermistor Input

The ADP5065 charger features battery pack temperature sensing that precludes charging when the battery pack temperature is outside the specified range. The THR pin provides an on and off switching current source, which should be connected directly to the battery pack thermistor terminal. The activation interval of the THR current source is 167 ms.

The battery pack temperature sensing can be controlled by

C using the conditions shown in Tab l e 10. Note that the

C register default setting for EN_THR (Register 0x07) is

0 = temperature sensing off.

Table 10. THR Input Function

Conditions

VINx V

Open or VIN = 0 V to 4.0 V <2.5 V Off Open or VIN = 0 V to 4.0 V >2.5 V Off, controlled by I2C

4.0 V to 5.5 V Don't care Always on

If the battery pack thermistor is not connected directly to the

ADP5065 THR pin, a 10 kΩ (tolerance ±20%) dummy resistor

must be connected between the THR input and GND. Leaving the THR pin open results in a false detection of the battery temperature being <0°C and charging is disabled.

ISO_B

THR Function

The ADP5065 charger monitors the voltage in the THR pin and suspends charging if the current is outside the range of less than 0°C or greater than 60°C. For temperatures greater than 0°C, the THR_STATUS register is set accordingly, and for temperatures lower than 60°C, the THR_STATUS register is, likewise, set accordingly.

The ADP5065 charger is designed for use with an NTC thermistor in the battery pack with a nominal room temperature value of either 10 kΩ at 25°C or 100 kΩ at 25°C, which is selected by a fuse.

The ADP5065 charger is designed for use with an NTC thermistor in the battery pack with a temperature coefficient curve (beta). Fuse-selectable beta programming is supported by eight steps covering a range from 3150 to 4400 (see Tabl e 34).

JEITA Li-Ion Battery Temperature Charging Specification

The ADP5065 is compliant with the JEITA Li-Ion battery charging temperature specifications as outlined in Table 11.

The JEITA function can be enabled via the I

C interface. When the ADP5065 detects a JEITA cool condition, charging current is reduced according to Table 12.

When the ADP5065 identifies a hot or cold battery condition, the ADP5065 takes the following actions:

• Stops charging the battery.

• Connects/enables the battery isolation FET such that the

system power supply node is connected to the battery.

Table 11. JEITA Li-Ion Battery Charging Specification Defaults

Parameter Symbol Conditions Min Max Unit

JEITA Cold Temperature Limits I JEITA Cool Temperature Limits I

No battery charging occurs. 0 °C

JEITA_COLD

Battery charging occurs at approximately 50% of programmed level.

JEITA_COOL

0 10 °C

See Table 12 for specific charging current reduction levels. JEITA Typical Temperature Limits I JEITA Warm Temperature Limits I

Normal battery charging occurs at default/programmed levels. 10 45 °C

JEITA_TYP

JEITA_WARM

Battery termination voltage (V

) is reduced by 100 mV from

TRM

45 60 °C

programmed value. JEITA Hot Temperature Limits I

No battery charging occurs. 60 °C

JEITA_HOT

Table 12. JEITA Reduced Charge Current Levels

ICHG[2:0] (Default) ICHG JEITA (mA)

000 = 550 mA 250 001 = 650 mA 300 010 = 750 mA 350 011 = 850 mA 400 100 = 950 mA 450 101 = 1050 mA 500 110 = 1150 mA 550 111 = 1250 mA 600

Rev. B | Page 22 of 40

Page 23

Data Sheet ADP5065

17.8

2.8 V

2.7 V

EXTERNAL RESISTOR FOR V_WEAK_SET

The ADP5065 charger features a V used for enabling the main PMU system. When battery voltage at the BAT_SNS pin exceeds the V down the SYS_ON_OK open-drain flag.

threshold, which can be

WEAK

level, the ADP5065 pulls

WEAK

The V an external resistor connected between the V_WEAK_SET pin and GND. Recommended resistor values for each threshold are listed in Table 13.

If an external resistor is not used, it is recommended to tie the V_WEAK_SET pin to AGND for V

Table 13. Resistor Values for V_WEAK_SET Pin

Target Resistor Value E24 (kΩ) Actual Threshold (kΩ)

Short to GND Not applicable I2C (3.0 V default) I2C programmed − 100 mV 15 13.2 2.7 V 2.6 V

27 23.5 2.9 V 2.8 V 36 31.0 3.0 V 2.9 V 47 41.3 3.1 V 3.0 V 68 56.2 3.2 V 3.1 V 100 79.7 3.3 V 3.2 V Open 122.4 3.4 V 3.3 V

threshold can be programmed set either by I2C or by

WEAK

to obtain its default value.

WEAK

Voltage

WEAK

(Rising Threshold)

Voltage

WEAK

(Falling Threshold)

Rev. B | Page 23 of 40

Page 24

ADP5065 Data Sheet

I2C INTERFACE

The ADP5065 includes an I2C-compatible serial interface for control of the charging and for a readback of system status registers. The I in read mode.

Register values are reset to the default values, when the supply voltage at the VINx pin falls below the V threshold. The I disconnected and V

ST0010100 0 0 0 SP0 0 0

C chip address is 0x28 in write mode and 0x29

falling voltage

C registers are also reset when the battery is

is 0 V.

ST0010100 0 0 0

VIN_OK

0 = WRITE MASTER STOP

CHIP ADDRESS

ADP5065 ACK

Figure 34. I

0 = WRITE MASTER STOP

CHIP ADDRESS

SUBADDRESS

C Single Register Write Sequence

ADP5065 RECEIVES

DATA TO REGISTER N

See Figure 34 for an example of the I single register. The subaddress content selects which one of the five ADP5065 registers is written to first. The ADP5065 sends an acknowledgement to the master after the 8-bit data byte has been written. The ADP5065 increments the subaddress automatically and starts receiving a data byte to the following register until the master sends an I

Figure 36 shows the I

C read sequence of a single register.

ADP5065 sends the data from the register denoted by the

subaddress and increments the subaddress automatically, sending data from the next register until the master sends an

C stop condition as shown in Figure 37.

ADP5065 RECEIV E S

DATA

ADP5065 ACK

ADP5065 RECEIVES

DATA TO REGISTER N + 1

ADP5065 ACK

C write sequence to a

C stop as shown in Figure 35.

09370-034

ADP5065 RECEIVES

DATA TO LAST REGISTER

ADP5065 ACK

0 = WRITE

ST0010100 0000000110ST0010100 0 1SP0 1

CHIP ADDRESS SUBADDRESS CHIP ADDRESS ADP5065 SENDS DATA

ADP5065 ACK

0 = WRITE

0010100 0 0 0

CHIP ADDRESS S UB ADDRE SS

ADP5065 ACK

S T

ADP5065 ACK

Figure 35. I

Figure 36. I

0010100 01

Figure 37. I

C Multiple Register Write Sequence

ADP5065 ACK

C Single Register Read Sequence

1 = READ MASTER STOP

CHIP ADDRESS ADP5065 SENDS

C Multiple Register Read Sequence

DATA OF RE GISTER N

ADP5065 ACK

MASTER ACK

ADP5065 ACK

1 = READ

ADP5065 ACK

ADP5065 SENDS

DATA OF RE GISTER

N + 1

ADP5065 ACK

0 1

ADP5065 SENDS

DATA OF L AST

MASTER ACK

ADP5065 NO ACK

MASTER ACK

09370-035

09370-036

S P

09370-037

Rev. B | Page 24 of 40

Page 25

Data Sheet ADP5065

VINOK

FAST CHARGE

WATCHDOG

EXPIRED

START

SAFE

BUS

= 100mA

TFAULT/

BAD BATTERY

RUN

BATTERY

DETECTION

IBUSLIM = HIGH

VIN

= I

LIM

THERMLIM = HIGH

TEMP = T

LIM

WATCHDOG

EXPIRED

START

SAFE

BUS

= 100mA

TFAULT/

BAD BATTERY

(SEE TIMER SECTION)

CC-MODE

CHARGING

CV-MODE

CHARGING

CHARGE

COMPLETE

TRICKLE

CHARGE

VINOK

POWER ON RESET

RESET ALL

REGISTERS

RUN

BATTERY

DETECTION

START

EXPIRED

SAFE

TRK

EXPIRED

SAFE

CHG

EXPIRED

BAT_SNS

TRM

BAT_SNS

≤

NOBAT

BAT_SNS

≤

RCH

OUT

< I

END

POWER

DOWN

BAT_SNS

TRK

BAT_SNS

TRK

VIN

< I

LIM

TEMP < T

LIM

09370-038

CHARGER OPERATIONAL FLOWCHART

Figure 38. ADP5065 Operational Flowchart

Rev. B | Page 25 of 40

Page 26

ADP5065 Data Sheet

Addr.

Name

0x04

Charging

C/20 EOC

C/10 EOC

High

ICHG

ITRK_DEAD

0x09

Interrupt

EN_IND_PEAK_INT

EN_THERM_LIM_INT

EN_WD_INT

EN_TSD_INT

EN_THR_INT

EN_BAT_INT

EN_CHG_INT

EN_VIN_INT

Charger

I2C REGISTER MAP

Table 14. I2C Register Map1

Manufac-

0x00

turer and model ID

Silicon

0x01

revision VINx pins

0x02

settings Termina-

0x03

tion settings

current Voltage

0x05

threshold Timer

0x06

settings Functional

0x07

Settings1 Functional

0x08

Settings2

enable Interrupt

0x0A

active

0x0B

Status 1 Charger

0x0C

Status 2 Fault

0x0D

0x10

short

Each blank cell indicates a bit that is not used.

REV

RFU ILIM

VRCH VTRK_DEAD VWEAK

EN_TEND EN_CHG_TIMER CHG_TMR_PERIOD EN_WD WD PERIOD RESET_WD

EN_JEITA DIS_IPK_SD EN_BMON EN_THR EN_EOC EN_TRK EN_CHG

IND_PEAK_INT THERM_LIM_INT WD_INT TSD_INT THR_INT BAT_INT CHG_INT VIN_INT

VIN_OV VIN_OK VIN_ILIM THERM_LIM CHDONE CHARGER_STATUS

BAT_SHR IND_PEAK_INT TSDL 130°C TSD 140°C

MANUF Model

VTRM IEND

(read only)

THR_STATUS IPK_STAT BATTERY_STATUS

TBAT_SHR VBAT_SHR

Rev. B | Page 26 of 40

Page 27

Data Sheet ADP5065

[7:4]

MANUF[3:0]

0001

The 4-bit manufacturer identification bus.

Bit No.

Mnemonic

Access

Default

Description

1111 = 1500 mA.

REGISTER BIT DESCRIPTIONS

Table 15. Manufacturer and Model ID, Register Address 0x00 Bit Descriptions

Bit No. Mnemonic Access Default Description

[3:0] MODEL[3:0] R 1000 The 4-bit model identification bus.

Table 16. Silicon Revision, Register Address 0x01 Bit Descriptions

[7:4] Not Used R [3:0] REV[3:0] R 0011 The 4-bit silicon revision identification bus.

Table 17. VINx Settings, Register Address 0x02 Bit Descriptions

Bit No. Mnemonic Access Default Description

[7:5] Not Used R 4 RFU R/W 0 Reserved for future use. [3:0] ILIM[3:0] R/W 0000 = 100 mA VINx pin input current-limit programming bus. The current into VINx

can be limited to the following programmed values: 0000 = 100 mA. 0001 = 150 mA. 0010 = 200 mA. 0011 = 300 mA. 0100 = 400 mA. 0101 = 500 mA. 0110 = 600 mA. 0111 = 700 mA. 1000 = 800 mA. 1001 = 900 mA. 1010 = 1000 mA. 1011 = 1100 mA. 1100 = 1200 mA. 1101 = 1300 mA. 1110 = 1400 mA.

Rev. B | Page 27 of 40

Page 28

ADP5065 Data Sheet

000111 = 3.64 V.

011000 = 3.98 V.

101001 = 4.32 V.

Table 18. Termination Settings, Register Address 0x03 Bit Descriptions

Bit No. Mnemonic Access Default Description

[7:2] VTRM[5:0] R/W 100011 = 4.20 V Termination voltage programming bus. The values of the float

voltage can be programmed as per the following values: 000000 = 3.50 V. 000001 = 3.52 V. 000010 = 3.54 V. 000011 = 3.56 V. 000100 = 3.58 V. 000101 = 3.60 V. 000110 = 3.62 V.

001000 = 3.66 V. 001001 = 3.68 V. 001010 = 3.70 V. 001011 = 3.72 V. 001100 = 3.74 V. 001101 = 3.76 V. 001110 = 3.78 V. 001111 = 3.80 V. 010000 = 3.82 V. 010001 = 3.84 V. 010010 = 3.86 V. 010011 = 3.88 V. 010100 = 3.90 V. 010101 = 3.92 V. 010110 = 3.94 V. 010111 = 3.96 V.

011001 = 4.00 V. 011010 = 4.02 V. 011011 = 4.04 V. 011100 = 4.06 V. 011101 = 4.08 V. 011110 = 4.10 V. 011111 = 4.12 V. 100000 = 4.14 V. 100001 = 4.16 V. 100010 = 4.18 V. 100011 = 4.20 V. 100100 = 4.22 V. 100101 = 4.24 V. 100110 = 4.26 V. 100111 = 4.28 V. 101000 = 4.30 V.

101010 = 4.34 V. 101011 = 4.36 V. 101100 = 4.38 V. 101101 = 4.40 V. 101110 to 111111 = 4.42 V.

Rev. B | Page 28 of 40

Page 29

Data Sheet ADP5065

Termination current programming bus. The values of the termination 00 = 5 mA.

01 = 140 mV.

Bit No. Mnemonic Access Default Description

[1:0] IEND[1:0] R/W 01 = 52.5 mA

current can be programmed as per the following values: 00 = 32.5 mA. 01 = 52.5 mA. 10 = 72.5 mA. 11 = 92.5 mA.

Table 19. Charging Current, Register Address 0x04 Bit Descriptions

Bit No. Mnemonic Access Default Description

7 C/20 EOC R/W The C/20 bit has priority over the other settings (C/10 EOC and IEND).

6 C/10 EOC R/W

5 Tied high in metal R 1 [4:2] ICHG[2:0] R/W 111 = 1250 mA Fast charge current programming bus. The values of the constant

[1:0] ITRK_DEAD[1:0] R/W 10 = 20 mA Trickle and weak charge current programming bus. The values of the

When this bit is set to high, C/20 programming is used. 27.5 mA minimum value.

The C/10 bit has priority over the other setting (END) but not C/20 EOC.

When this bit is set to high, C/10 programming is used unless C/20 EOC is set to high. 27.5 mA minimum value.

current charge can be programmed as per the following values: 000 = 550 mA. 001 = 650 mA. 010 = 750 mA. 011 = 850 mA. 100 = 950 mA. 101 = 1050 mA. 110 = 1150 mA. 111 = 1250 mA.

trickle and weak charge currents can be programmed as per the following values:

01 = 10 mA. 10 = 20 mA. 11 = 20 mA.

Table 20. Voltage Threshold, Register Address 0x05 Bit Descriptions

Bit No. Mnemonic Access Default Description

7 Not used R [6:5] VRCH[1:0] R/W 11 = 260 mV Recharge voltage programming bus. The values of the recharge

threshold can be programmed as per the following values: 00 = 80 mV.

10 = 200 mV. 11 = 260 mV.

[4:3] VTRK_DEAD[1:0] R/W 01 = 2.5 V Trickle to fast charge dead battery voltage programming bus. The

values of the trickle to fast charge threshold can be programmed as per following values:

00 = 2.4 V. 01 = 2.5 V. 10 = 2.6 V. 11 = 3.3 V.

Rev. B | Page 29 of 40

Page 30

ADP5065 Data Sheet

011 = 3.0 V.

CHG_TMR_PERIOD

R/W

Trickle/fast charge timer period.

EN_THR

R/W 0 When high, the THR current source is enabled even when the

Bit No. Mnemonic Access Default Description

[2:0] VWEAK[1:0] R/W 011 = 3.0 V Weak battery voltage rising threshold.

000 = 2.7 V. 001 = 2.8 V. 010 = 2.9 V.

100 = 3.1 V. 101 = 3.2 V. 110 = 3.3 V. 111 = 3.4 V.

Table 21. Timer Settings, Register Address 0x06 Bit Descriptions

Bit No. Mnemonic Access Default Description

[7:6] Not used 5 EN_TEND R/W 1 When low, this bit disables the charge complete timer (t

ms deglitch timer remains on this function.

4 EN_CHG_TIMER R/W 1 When high, the trickle/fast charge timer is enabled.

0 = 30 sec/300 minutes. 1 = 60 sec/600 minutes.

2 EN_WD R/W 1 When high, the watchdog timer safety timer is enabled.

When low, the watchdog timer is disabled even when BAT_SNS exceeds V

DEAD

1 WD PERIOD R/W 0 Watchdog safety timer period.

0 = 32 sec/40 minutes. 1 = 64 sec/40 minutes.

0 RESET_WD W 0 High resets the watchdog safety timer. Bit is reset automatically.

), and a 31

END

Table 22. Functional Settings1, Register Address 0x07 Bit Descriptions

Bit No. Mnemonic Access Default Description

7 EN_JEITA R/W 0 When low, this bit disables the JEITA Li-Ion temperature battery

6 DIS_IPK_SD R/W 1 When high, this bit disables the automatic shutdown of the device if

5 EN_BMON R/W 0 When high, the battery monitor is enabled even when the voltage at

3 Not used R/W 0 2 EN_EOC R/W 1 When high, end of charge is allowed. 1 EN_TRK R/W 1 When low, trickle charger is disabled and the dc-to-dc converter is

0 EN_CHG R/W 1 When low, the dc-to-dc converter is disabled.

Table 23. Functional Settings2, Register Address 0x08 Bit Descriptions

Bit No. Mnemonic Access Default Description

[7:0] Not used R/W

Table 24. Interrupt Enable, Register Address 0x09 Bit Descriptions

Bit No. Mnemonic Access Default Description

7 EN_IND_PEAK_INT R/W 0 When high, the inductor peak current-limit interrupt is allowed. 6 EN_THERM_LIM_INT R/W 0 When high, the isothermal charging interrupt is allowed. 5 EN_WD_INT R/W 0 When high, the watchdog alarm interrupt is allowed. 4 EN_TSD_INT R/W 0 When high, the overtemperature interrupt is allowed. 3 EN_THR_INT R/W 0 When high, the THR temperature thresholds interrupt is allowed.

charging specification.

four peak inductor current limits are reached in succession. In addition, when high, it only flags the Status Bit IPK_STAT.

the VINx pins is below V

voltage at the VINx pins is below V

enabled.

Rev. B | Page 30 of 40

VIN_OK

Page 31

Data Sheet ADP5065

EN_CHG_INT

R/W 0 When high, the charger mode change interrupt is allowed.

BAT_INT

R 0 When high, this bit indicates an interrupt caused by battery voltage thresholds.

VIN_ILIM

Not applicable

When high, this bit indicates that the current into a VINx pin is

101 = suspend.

Bit No. Mnemonic Access Default Description

2 EN_BAT_INT R/W 0 When high, the battery voltage thresholds interrupt is allowed.

0 EN_VIN_INT R/W 0 When high, the VINx pin voltage thresholds interrupt is allowed.

Table 25. Interrupt Active, Register Address 0x0A Bit Descriptions

Bit No. Mnemonic Access Default Description

7 IND_PEAK_INT R 0 When high, this bit indicates an interrupt caused by an inductor peak current limit. 6 THERM_LIM_INT R 0 When high, this bit indicates an interrupt caused by isothermal charging. 5 WD_INT R 0 When high, this bit indicates an interrupt caused by the watchdog alarm. The watchdog

timer expires within 2 sec or 4 sec depending on the WDPERIOD setting of 32 sec or 64 sec,

respectively. 4 TSD_INT R 0 When high, this bit indicates an interrupt caused by an overtemperature fault. 3 THR_INT R 0 When high, this bit indicates an interrupt caused by THR temperature thresholds.

1 CHG_INT R 0 When high, this bit indicates an interrupt caused by a charger mode change. 0 VIN_INT R 0 When high, this bit indicates an interrupt caused by VINx voltage thresholds.

Table 26. Charger Status 1, Register Address 0x0B Bit Descriptions

Bit No. Mnemonic Access Default Description

7 VIN_OV R Not applicable When high, this bit indicates that the voltage at the VINx pins

exceeds V

6 VIN_OK R Not applicable When high, this bit indicates that the voltage at the VINx pins

exceeds V

VIN_OV

VIN_OK

limited by the high voltage blocking FET and the charger is not running at the full programmed I

CHG

4 THERM_LIM R Not applicable When high, this bit indicates that the charger is not running at the

full programmed I

but is limited by the die temperature.

CHG

3 CHDONE R Not applicable When high, this bit indicates the end of charge cycle has been

reached. This bit latches on, in that it does not reset to low when the

threshold is breached.

RCH

[2:0] CHAGER_STATUS[2:0] R Not applicable Charger status bus.

000 = off. 001 = trickle charge. 010 = fast charge (CC mode). 011 = fast charge (CV mode). 100 = charge complete.

110 = trickle or fast charge timer expired. 111 = battery detection.

Rev. B | Page 31 of 40

Page 32

ADP5065 Data Sheet

Not Used

Not applicable

010 = 4 sec

111 = 180 sec

011 = 2.3 V

Table 27. Charger Status Register 2, Register Address 0x0C Bit Descriptions

Bit No. Mnemonic Access Default Description

[7:5] THR_STATUS[2:0] R Not applicable THR pin status.

000 = off. 001 = battery cold. 010 = battery cool. 011 = battery warm. 100 = battery hot. 111 = thermistor OK.

4 IPK_STAT R Not applicable Peak current limit status bit. Set high if four or more peak inductor

current limits are reached in succession.

[2:0] B ATT E RY_STATUS[2:0] R Battery status bus.

000 = battery monitor off. 001 = no battery. 010 = BAT_SNS < V 011 = V

≤ BAT_SNS < V

TRK

100 = BAT_SNS ≥ V

Table 28. Fault Register, Register Address 0x0D Bit Descriptions1

Bit No. Mnemonic Access Default Description

[7:4] Not Used 3 BAT_SHR R/W 0 When high, a battery short detection has occurred. 2 IND_PEAK_INT R/W 0 When high, an inductor peak current-limit fault has occurred. 1 TSD 130°C R/W 0 When high, the overtemperature (lower) fault has occurred. 0 TSD 140°C R/W 0 When high, the overtemperature fault has occurred.

To reset the fault bits in the fault register, cycle power on VINx or write high to the corresponding I2C bit.

Table 29. Battery Short, Register Address 0x10 Bit Descriptions

Bit No. Mnemonic Access Default Description

[7:5] TBAT_SHR[2:0] R/W 100 = 30 sec Battery short timeout timer:

000 = 1 sec 001 = 2 sec

TRK

WEAK

[4:3] Not used R/W [2:0] V B AT _ S H R[2:0] R/W 100 = 2.4 V Battery short voltage threshold level:

011 = 10 sec 100 = 30 sec 101 = 60 sec 110 = 120 sec

000 = 2.0 V 001 = 2.1 V 010 = 2.2 V

100 = 2.4 V 101 = 2.5 V 110 = 2.6 V 111 = 2.7 V

Rev. B | Page 32 of 40

Page 33

Data Sheet ADP5065

LfV

VVV

OUT

RIPPLE

××

−×

)(

RIPPLE

MAXLOAD

CHGPEAK

III ++=

0 7654321

DC BIAS (V)

CAPACITANCE (µ F)

09370-039

( )

OUT

RIPPLE

CLf

×××π

≈

××

RIPPLE

COUT

ESR ≤

APPLICATIONS INFORMATION

EXTERNAL COMPONENTS

Inductor Selection

The high switching frequency of the ADP5065 buck converter allows for the selection of small chip inductors. Suggested inductors are shown in Tab l e 33.

The peak-to-peak inductor current ripple is calculated using the following equation:

where:

is the ISO_Sx node output voltage.

OUT

is the converter input voltage at the CFILT node.

is the switching frequency.

L is the inductor value.

The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation:

The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation:

= C

EFF

× (1 − TEMPCO) × (1 − TOL)

OUT

where:

is the effective capacitance at the operating voltage.

EFF

TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and C

is 16 μF at 4.2 V, as shown in Figure 39.

OUT

Substituting these values in the equation yields

= 16 μF × (1 − 0.15) × (1 − 0.1) ≈ 12.24 μF

EFF

Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI.

ISO_Sx (V

) and ISO_Bx Capacitor Selection

OUT

To safely obtain stable operation of the ADP5065, the ISO_Sx and ISO_Bx effective capacitance (including temperature and dc bias effects) must not be less than 10 µF at any point during operation. The combined effective capacitance of the ISO_Sx capacitor and the system capacitance must not exceed 50 µF at any point during operation.

Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value,

Figure 39. Murata GRM31CR60J226ME19C DC Characteristic

To guarantee the performance of the charger in various operation modes including trickle charge, constant current charge, and constant voltage charge, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.

The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation:

it is also important to account for the loss of capacitance due to output voltage dc bias.

trics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate

Ceramic capacitors are manufactured with a variety of dielec-

enough to ensure the minimum capacitance over the necessary

Capacitors with lower effective series resistance (ESR) are preferable to guarantee low output voltage ripple, as shown in the following equation:

temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics.

Rev. B | Page 33 of 40

Page 34

ADP5065 Data Sheet

CFILT

SISO

CFILT

SISO

MAXCHGLOAD

CIN

VVV

)(

−

≥

Murata

GRM188R60J475ME84

4.7 μF

6.3 V

0603

Murata

LQH32PN1R0NN0

2.3 A

3.5 × 2.7 × 1.7

VINx Capacitor Selection

According to the USB 2.0 specification, USB peripherals have a detectable change in capacitance on VBUS when they are attached. The peripheral device VBUS bypass capacitance must be at least 1 µF but not larger than 10 µF. The combined capacitance for the VINx and CFILT pins must not exceed 10 µF at any temperature or dc bias condition. Suggestions for a VINx capacitor is given in Table 32.

CFILT Capacitor Selection

CFILT pin serves the ADP5065 as the step-down dc-to-dc converter input capacitor. Maximum input capacitor current is calculated using the following equation:

Table 30. ISO_Sx and ISO_Bx Capacitor Suggestions

Vendor Part Number Value Voltage Size

Murata GRM31CR61A226KE19 22 μF 10 V 1206 Murata GRM31CR60J226ME19 22 μF 6.3 V 1206 TDK C3216X5R0J226M 22 µF 6.3 V 1206 TAIYO -

JMK316ABJ226KL 22 µF 6.3 V 1206

YUDEN

Table 31. CFILT Capacitor Suggestions

Vendor Part Number Value Voltage Size

Murata GRM219R61C475KE15 4.7 μF 16 V 0805

TDK C1608X5R0J475K 4.7 μF 6.3 V 0603 TAIYO -

JMK107ABJ106MA 10 µF 6.3 V 0603

YUDEN

To minimize supply noise, place the input capacitor as close as possible to the CFILT pin of the charger. As with the output capacitor, a low ESR capacitor is recommended.

The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 2 µF and a maximum of 5 µF. A list of suggested capacitors is shown in Tabl e 31.

Table 32. VINx Capacitor Suggestions

Vendor Part Number Value Voltage Size

Murata GRM21BR71E225KA73 2.2 µF 25 0805 Murata GRM188R61E225KA12 2.2 µF 25 0603 TDK C1608X5R1E225K 2.2 µF 25 0603 TAIYO -

TMK107ABJ225MA 2.2 µF 25 0603

YUDEN

Table 33. 1.0 µH Inductor Suggestions

Saturation Current

Vendor Part Number

L −30% Drop

DCR (mΩ) Size Max L × W × H (mm)

Coilcraft XFL3010-102ME 2.4 A 43 3.2 × 3.2 ×1.1

Rev. B | Page 34 of 40

Page 35

Data Sheet ADP5065

D4 E4

CFILT

SW1

SW2

ISO_S1

ISO_S2

ISO_B1

ISO_B2

VDDIO

PGND1

PGND2

AGND

IIN_EXT TRK_EXT

V_WEAK_SET

THR

TO MCU

TO MCU/NC TO MCU/NC

R3/NC

(OPTIONAL)

ADP5065

C1 2.2µF

GRM21BR71E225K

C2 4.7µF

GRM219R61C475K

VIN = 4.5V TO 5.5V

R5 NTC 10kΩ

(OPTIONAL)

10kΩ

CONNECT CLOSE TO

BATTERY

C4 22µF

GRM31CR61A226K

C3 22µF

GRM31CR61A226K

L1 1µH

LQH32PN1R0NN0

VIN1 VIN2

BAT_SNS

SYS_ON_OK

CONTROL

(INPUT CURRENT,

DC-DC)

CHARGE CONTROL

(CHARGE MODE ,

BATTERY ISOLATION)

SCL SDA

VDDIO

TO MCU TO MCU

1.5kΩR21.5kΩ

09370-040

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5065 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines:

• Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas.

• Route the output voltage path away from both the inductor

and SWxnode to minimize noise and magnetic interference.

• Maximize the size of ground metal on the component side

to help with thermal dissipation.

• Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference on sensitive circuit nodes.

Figure 40. Reference Circuit Diagram

Rev. B | Page 35 of 40

Page 36

ADP5065 Data Sheet

8mm

PGND

11.5mm

ADP5065

2.2µF

CFILT

4.7µF

ISO_S

22µF

L 1µH

ISO_B

22µF

09370-041

Figure 41. PCB Layout Suggestion

Rev. B | Page 36 of 40

Page 37

Data Sheet ADP5065

100%×=

OUT

)(

OUT

RMSOUT

×=

POWER DISSIPATION AND THERMAL CONSIDERATIONS

The ADP5065 is a highly efficient USB compliant charger. However, if the device operates at high ambient temperatures and maximum current charging and loading conditions, the junction temperature can reach the maximum allowable operating limit (125°C).

When the temperature exceeds 140°C, the ADP5065 turns off allowing the device to cool down. When the die temperature falls below 110°C and the TSD 140°C fault bit in Register 0x0D is cleared by an I

C write, the ADP5065 resumes normal

operation.

This section provides guidelines to calculate the power dissipated in the device and ensure that the ADP5065 operates below the maximum allowable junction temperature.

The output power of the ADP5065 charger is gived by

= V

× I

OUT

ISO_S

LOAD

+ V

ISO_B

× I

(1)

CHG

where:

is the total output power to the system and battery.

OUT

is the ISO_Sx pin voltage.

ISO_S

is the load current from ISO_Sx node.

LOAD

is the battery voltage.

ISO_B

is the charge current.

CHG

The efficiency of the ADP5065 is given by

(2)

where:

η is the efficiency. P

is the input power.

Power loss is given by

= PIN − P

LOSS

(3a)

OUT

= P

LOSS

(1− η)/η (3b)

OUT

Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and both outputs (ISO_Sx and ISO_Bx). Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 5 to derive the power lost in the inductor and, from this, use Equation 4 to calculate the power dissipation in the ADP5065 charger.

A second method to estimate the power dissipation uses the system voltage and charging efficiency curves provided for the

ADP5065. When the efficiency is known, use Equation 3b to

derive the total power lost in the dc-to-dc converter, isolation FET and inductor; use Equation 5 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 4.

Note that the ADP5065 efficiency curves are typical values and may not be provided for all possible combinations of V and I

To account for these variations, it is necessary to

OU T.

, V

OUT

include a safety margin when calculating the power dissipated in the charger.

CHARGER POWER DISSIPATION

The power loss of the step-down charger is approximated by

= P

LOSS

where:

is the power dissipation of the ADP5065 charger.

DCHG

is the inductor power losses.

The inductor losses are external to the device, and they do not have any effect on the die temperature. Equation 5 estimates the inductor losses without core losses. Some inductor manufacturers provide web tools to estimate power inductor core losses based on inductor type, switching frequency, and ripple current. At a switching frequency of 3 MHz, the core losses can add inductor losses significantly.

≈ I

where:

DCR

is the inductor series resistance.

is the summary of rms load current and charging

OUT(RMS)

current (I

where r is the normalized inductor ripple current.

r = V

where:

L is the inductance. f

is the switching frequency.

D is the duty cycle.

D = V

+ PL (4)

DCHG

× DCRL (5)

OUT(RMS)

+ I

LOAD(RMS)

CHG

(6)

× (1 − D)/(I

OUT

OUT/VIN

(8)

× L × fSW) (7)

OUT

Rev. B | Page 37 of 40

Page 38

ADP5065 Data Sheet

JUNCTION TEMPERATURE

In cases where the ambient temperature, TA, is known, the thermal resistance parameter, θ junction temperature rise. T the formula

= TA + (PD × θJA) (9)

The typical θ

value for the 20-bump WLCSP is 46.8°C/W (see

Tabl e 5). A very important factor to consider is that θ on a 4-layer, 4 in × 3 in, 2.5 oz copper board as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers.

When designing an application for a particular ambient temperature range, calculate the expected ADP5065 power dissipation (P temperature, T

). From this power calculation, the junction

, can be estimated using Equation 9.

, can be used to estimate the

is calculated from TA and PD using

is based

Maximum junction temperature (T from the board temperature (T using the formula

= TA + (PD × θJB) (10)

where θ

is the junction-to-board thermal resistance.

The typical value for the 20-bump WLCSP is 9.2°C/W (see Tabl e 5). θ

is based on a 4-layer, 4 in × 3 in, 2.5 oz copper

board, as per the JEDEC standard.

For a WLCSP device, where possible, remove heat from every current carrying bump (PGNDx, VINx, SWx, ISO_Sx, and ISO_Bx). For example, thermal vias to the board power planes can be placed close to these pins, where available.

The reliable operation of the charger can be achieved only if the estimated die junction temperature of the ADP5065 (Equation 9) is less than 125°C. Reliability and mean time between failures (MTBF) are highly affected by increasing the junction temperature. Additional information about product reliability is available in the ADI Reliability Handbook at the following URL:

www.analog.com/reliability_handbook.

) can also be calculated

) and power dissipation (PD)

Rev. B | Page 38 of 40

Page 39

Data Sheet ADP5065

3500

FACTORY-PROGRAMMABLE OPTIONS

Table 34. ADP5065 Fuse-Selectable Trim Options

Parameter Value ADP5065ACBZ-1-R7 Trim Setting

NTC Thermistor Type 10 kΩ 10 kΩ 100 kΩ NTC Beta 3150 3350 3350

3650 3850 4000 4200 4400

Rev. B | Page 39 of 40

Page 40

ADP5065 Data Sheet

2.75

2.71

2.67

2.08

2.04

2.00

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

BALL 1

IDENTIFIER

0.50

REF

0.660

0.600

0.540

SIDE VIEW

0.270

0.240

0.210

0.360

0.320

0.280

2.00 REF

1.50 REF

COPLANARITY

0.04

SEATING

PLANE

0.390

0.360

0.330

10-04-2011-B

respective owners.

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

Figure 42. 20-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-20-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range (Junction) Package Description Package Option

ADP5065ACBZ-1-R7 −40°C to +125°C 20-Ball Wafer Level Chip Scale Package [WLCSP] CB-20-8 ADP5065CB-EVALZ ADP5065 Evaluation Board

Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

trademarks are the proper ty of their

D09370-0-4/12(B)

www.analog.com/ADP5065

Rev. B | Page 40 of 40

Datasheet ADP5065 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

RECOMMENDED INPUT AND OUTPUT CAPACITANCE

I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Maximum Power Dissipation

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE CHARACTERISTICS

TYPICAL WAVEFORMS

THEORY OF OPERATION

INTRODUCTION

CHARGER MODES

Input Current Limit

USB Compatibility

Trickle Charge Mode

Trickle Charge Mode Timer

Weak Charge Mode (Constant Current)

Fast Charge Mode (Constant Current)

Fast Charge Mode (Constant Voltage)

Fast Charge Mode Timer

Watchdog Timer

Safety Timer

Charge Complete

Recharge

Battery Charging Enable/Disable

THERMAL MANAGEMENT

Isothermal Charging

Thermal Shutdown and Thermal Early Warning

Fault Recovery

BATTERY ISOLATION FET

BATTERY DETECTION

Battery Level Detection

Battery (ISO_Bx) Short Detection

BATTERY PACK TEMPERATURE SENSING

Battery Thermistor Input

JEITA Li-Ion Battery Temperature Charging Specification

EXTERNAL RESISTOR FOR V_WEAK_SET

I2C INTERFACE

CHARGER OPERATIONAL FLOWCHART

I2C REGISTER MAP

REGISTER BIT DESCRIPTIONS

APPLICATIONS INFORMATION

EXTERNAL COMPONENTS

Inductor Selection

VINx Capacitor Selection

CFILT Capacitor Selection

PCB LAYOUT GUIDELINES

POWER DISSIPATION AND THERMAL CONSIDERATIONS

CHARGER POWER DISSIPATION

JUNCTION TEMPERATURE

FACTORY-PROGRAMMABLE OPTIONS

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

ORDERING GUIDE