Datasheet ADP5042 Datasheet (ANALOG DEVICES)

Supervisory, Watchdog and Manual Reset

ADP5042

Rev. A

rights of third parties that may result from its use. Specifications subject to change without notice. No

Trademarks and registered trademarks are the property of their respec tive owners.

Fax: [phone] ©2010-2011 Analog Devices, Inc. All rights reserved.

FPWM

PSM/PWM

MODE

SW
VOUT1
PGND

C6
10µF

V

OUT1

AT

800mA

L1

1µH

EN_BK

BUCK

EN_LDO1

LDO1

(DIGITAL)

EN_LDO2

LDO2

(ANALOG)

SUPERVISOR

MICROPROCESSOR

VIN1

EN3

AVIN

AVIN

EN1

VIN2

VIN3

EN2

AGND

C2
1µF

VOUT2

VOUT3

WSTAT

WDI1
WDI2

nRSTO

V

OUT2

AT

300mA

C4
1µF

V

OUT3

AT

300mA

C5

4.7µF

ON

OFF

ON

OFF

ON

OFF

VIN1 = 2.3V

TO 5.5V

AVIN

R

FILT

= 30Ω

VIN2 = 1.7V

TO 5.5V

MR

C1

1µF

VIN3 = 1.7V

TO 5.5V

C3

1µF

08811-001

Data Sheet

FEATURES

Input voltage range: 2.3 V to 5.5 V
One 0.8 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to V
Dual watchdog for secure systems

Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle

Buck key specifications

Current mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode

LDOs key specifications

Low V

from 1.7 V to 5.5 V

IN

Stable with1 µF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise

110 µV rms typical output noise at V

Low dropout voltage: 150 mV at 300 mA load

−40°C to +125°C junction temperature range

= 1 V

CC

= 2.8 V

OUT

Micro PMU with 0.8 A Buck, Two 300 mA LDOs

HIGH LEVEL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADP5042 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.

The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes the
board space.

The MODE pin selects the buck mode of operation. When set
to logic high, the buck regulators operate in forced PWM mode.
When the MODE pin is set to logic low, the buck regulators
operate in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringement s of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5042 LDOs extend the battery life of
portable devices. The two LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.

Each regulator is activated by a high level on the respective
enable pin. The ADP5042 is available with factory programmable
default output voltages and can be set to a wide range of options.

The ADP5042 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. They also provide power-on
reset signals. An on-chip dual watchdog timer can reset the
microprocessor or power cycle the system (Watchdog 2) if it
fails to strobe within a preset timeout period.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

ADP5042 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

High Level Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

General Specification ................................................................... 3

Supervisory Specification ............................................................ 3

Buck Specifications ....................................................................... 5

LDO1, LDO2 Specifications ....................................................... 5

Input and Output Capacitor, Recommended Specifications .. 6

Absolute Maximum Ratings ............................................................ 7

Thermal Data ................................................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Theory of Operation ...................................................................... 18

Power Management Unit ........................................................... 18

Buck Section ................................................................................ 19

LDO Section ............................................................................... 20

Supervisory Section ................................................................... 20

Applications Information .............................................................. 23

Buck External Component Selection ....................................... 23

LDO Capacitor Selection .......................................................... 24

Supervisory Section ................................................................... 25

PCB Layout Guidelines .............................................................. 26

Evaluation Board Schematics and Artwork ............................ 27

Suggested Layout ........................................................................ 27

Bill of Materials ........................................................................... 28

Application Diagram ................................................................. 28

Factory Programmable Options ................................................... 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

10/11—Rev. 0 to Rev. A

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

12/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

Data Sheet ADP5042

Input Voltage Falling

UVLO

1.95

V

Thermal Shutdown Threshold

TSSD

TJ rising

150 °C

mV

SUPPLY

RESET THRESHOLD ACCURACY

VTH − 0.8%

VTH

VTH + 0.8%

V

TA = 25°C, sensed on VOUTx

RESET TIMEOUT PERIOD WATCHDOG2 (t

)

SPECIFICATIONS

GENERAL SPECIFICATION

AVIN, VIN1 = (V
are enabled.

Table 1.

Parameter Symbol Description Min Typ Max Unit

AVIN UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

SHUTDOWN CURRENT I
ENx = GND, TJ = −40°C to +125°C 2 µA

+ 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, VIN3, TA = 25°C, unless otherwise noted. Regulators

OUT1

TJ = −40°C to +125°C

AVIN

2.25 V

AVINRISE

AVIN FALL

ENx = GND 0.1 µA

GND-SD

Thermal Shutdown Hysteresis TS

ENx, WDIx, MODE, WMOD,

MR

INPUTS

20 °C

SD-HYS

Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V
Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V

ENx = AVIN or GND 0.05 µA

Input Leakage Current (WMOD

V

I-LEAKAGE

Excluded)
ENx = AVIN or GND, TJ = −40°C to +125°C 1 µA
WMOD Input Leakage Current V

I-LKG-WMOD

VWMOD = 3.6 V, TJ = −40°C to +125°C 50 µA

OPEN-DRAIN OUTPUTS

nRSTO, WSTAT Output Voltage VOL AVIN = 2.3 V to 5.5 V, I
Open-Drain Reset Output Leakage

1 µA

nRSTO/WSTAT

= 3 mA 30

Current

SUPERVISORY SPECIFICATION

AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

Supply Current (Supervisory Circuit Only) 45 55 µA AVIN = 5.5 V, EN1 = EN2 = EN3 = VIN

43 52 µA AVIN = 3.6 V, EN1 = EN2 = EN3 = VIN

VTH − 1.5% VTH VTH + 1.5% V

RESET THRESHOLD TO OUTPUT DELAY

GLITCH IMMUNITY (t

UOD

)

RESET TIMEOUT PERIOD WATCHDOG1 (t

RP1

50 125 400 µs V

)
Option A 24 30 36 ms
Option B 160 200 240 ms

RP2

3.5 5 7 ms
VCC TO RESET DELAY (tRD) 150 µs VIN1 falling at 1 mV/µs
REGULATORS SEQUENCING DELAY (tD1, tD2) 2 ms
WATCHDOG INPUTS

Watchdog 1 Timeout Period (t

)

WD1

Option A 81.6 102 122.4 ms
Option B 1.28 1.6 1.92 sec

= −40°C to +125°C, sensed on

T

J

V

OUTx

= V

TH

− 50 mV

UOT

Rev. A | Page 3 of 32

ADP5042 Data Sheet

Option D

6.4 8 9.6

min

Option A

210 ms

MANUAL RESET INPUT

Parameter Min Typ Max Unit Test Conditions/Comments

Watchdog 2 Timeout Period (t

Option A 6 7.5 9 sec
Option B Watchdog 2 disabled
Option C 3.2 4 4.8 min

Option E 11.2 16 19.2 min
Option F 25.6 32 38.4 min
Option G 51.2 64 76.8 min
Option H 102.4 128 153.8 min

Watchdog 2 Power Off Period (t

Option B 400 ms
WDI1 Pulse Width 80 ns VIL = 0.4 V, VIH = 1.2 V
WDI2 Pulse Width 8 µs VIL = 0.4 V, VIH = 1.2 V
Watchdog Status Timeout Period (t
WDI1 Input Current (Source) 8 15 20 µA V
WDI1 Input Current (Sink) −30 −25 −14 µA V
WDI2 Internal Pull-Down 45 kΩ

)

WD2

)

POFF

) 11.2 sec

WDCLEAR

= VCC, time average

WDI1

= 0, time average

WDI1

MR Input Pulse Width
MR Glitch Rejection
MR Pull-Up Resistance
MR to Reset Delay

1 µs
220 ns
25 52 80 kΩ
280 ns V

= 5 V

CC

Rev. A | Page 4 of 32

Data Sheet ADP5042

NFET, AVIN = VIN1 = 5 V

150

210

mΩ

I

= 1 mA

BUCK SPECIFICATIONS

AVIN, VIN1 = 3.6 V, V

for typical specifications, unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Input Voltage Range (VIN1) 2.3 5.5 V

OUTPUT CHARACTERISTICS

Output Voltage Accuracy PWM mode, TA= 25 °C , I

PWM mode −2 +2 %

PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA
INPUT CURRENT CHARACTERISTICS

DC Operating Current I
Shutdown Current ENx = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA

SW CHARACTERISTICS

SW On Resistance PFET 180 240 mΩ
PFET, AVIN = VIN1 = 5 V 140 190 mΩ

NFET 170 235 mΩ

= 1.8 V, TJ= −40°C to +125°C for minimum/maximum specifications, L = 1 µH, C

OUT1

1

VIN1 = 2.3 V to 5.5 V, PWM mode,

= 1 to 800 mA

I

LOAD

= 0 mA, device not switching 21 35 μA

LOAD

= 100 mA −1 +1 %

LOAD

−3 +3 %

= 10 µF, and TA = 25°C

OUT

Current Limit PFET switch peak current limit 1100 1360 1600 mA
ACTIVE PULL-DOWN EN1 = 0 V 75 Ω
OSCILLATOR FREQUENCY 2.5 3.0 3.5 MHz
STA RT-UP TIME 250 μs

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

LDO1, LDO2 SPECIFICATIONS

AVIN = 3.6 V, V
T

= 25°C, unless otherwise noted.

A

Table 4.

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE V
OPERATING SUPPLY CURRENT (per

LDO)
I
I
I
I
I
FIXED OUTPUT VOLTAGE ACCURACY V
100 µA < I
V
100 µA < I
V
TJ = −40°C to +125°C
REGULATION

Line Regulation ∆V

TJ = −40°C to +125°C

IN2, VIN3

= (V

+ 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 ≥ VIN2, VIN3; I

OUT3

, V

TJ = −40°C to +125°C 1.7

IN2

IN3

I

I

GND

OUT2, VOUT3

/∆V

OUT2

∆V

/∆V

OUT3

I

IN2

IN3

= 0 µA, V

OUT

= 0 µA, V

OUT

= 10 mA 67 µA

OUT

= 10 mA, TJ = −40°C to +125°C 105 µA

OUT

= 200 mA 100 µA

OUT

= 200 mA, TJ = −40°C to +125°C 245 µA

OUT

= 10 mA −1 +1 %

OUT

IN2, VIN3

IN2, VIN3

V

IN2, VIN3

OUT3

= 3.3 V 15 µA

OUT

= 3.3 V, TJ = −40°C to +125°C 50 µA

OUT

< 300 mA −2 +2 %

OUT

= (V

OUT2, VOUT3

< 300 mA −3 +3 %

OUT

= (V

OUT2, VOUT3

= (V

OUT2, VOUT3

+ 0.5 V) to 5.5 V

+ 0.5 V) to 5.5 V

+ 0.5 V) to 5.5 V −0.03 +0.03 %/V

= 10 mA; CIN = C

OUT

= 1 µF;

OUT

5.5 V

Rev. A | Page 5 of 32

ADP5042 Data Sheet

I

= 200 mA

60 mV

µV rms

Parameter Symbol Conditions Min Typ Max Unit

Load Regulation1 ∆V

∆V

OUT2

OUT3

/∆I
/∆I

OUT2

OUT3

I
TJ = −40°C to +125°C

DROPOUT VOLTAGE2 V

DROPOUT

V
I
I

I

ACTIVE PULL-DOWN R
STA RT-UP TIME T
CURRENT-LIMIT THRESHOLD3 I
OUTPUT NOISE OUT

EN2/EN3 = 0 V 600 Ω

PDLDO

V

STA RT-UP

TJ = −40°C to +125°C 335 470 mA

LIMIT

LDO2NOISE

10 Hz to 100 kHz, V
10 Hz to 100 kHz, V
OUT

LDO1NOISE

10 Hz to 100 kHz, V
10 Hz to 100 kHz, V
POWER SUPPLY REJECTION RATIO PSRR

1

Based on an end-point calculation using 1 mA and 100 mA loads.

2

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.3 V.

3

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

I

OUT2, VOUT3

= 1 mA to 200 mA 0.002 %/mA

OUT2, VOUT3

OUT2, VOUT3

OUT2, IOUT3

OUT2, IOUT3

OUT2, IOUT3

OUT2, IOUT3

OUT2, VOUT3

= 1 mA to 200 mA 0.0075 %/mA

= 3.3 V
= 10 mA 4 mV
= 10 mA, TJ = −40°C to +125°C 5 mV

= 200 mA, TJ = −40°C to +125°C 100 mV

= 3.3 V 85 µs

10 Hz to 100 kHz, V

10 Hz to 100 kHz, V

IN2, VIN3

IN2, VIN3

, V

IN2

= 3.3 V, V

= 3.3 V, V

= 3.3 V, V

IN3

1 kHz, V

= 100 mA

I

OUT

100 kHz, V

= 100 mA

I

OUT

1 MHz, V

= 100 mA

I

OUT

= 5 V, V

IN3

= 5 V, V

IN3

= 5 V, V

IN3

= 5 V, V

IN2

= 5 V, V

IN2

= 5 V, V

IN2

OUT3

OUT3

OUT3

OUT2

OUT2

OUT2

OUT2, OUT3

OUT2, VOUT3

OUT2, VOUT3

= 3.3 V 123 µV rms
= 2.8 V 110 µV rms
= 1.5 V 59 µV rms
= 3.3 V 140 µV rms
= 2.8 V 129 µV rms
= 1.5 V 66

= 2.8 V,

= 2.8 V,

= 2.8 V,

66 dB

57 dB

60 dB

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 5.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM OUTPUT CAPACITANCE (BUCK)1 C
MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO1, LDO2) C
CAPACITOR ESR R

1

The minimum output capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met.

2

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.

TJ = −40°C to +125°C 7 40 µF

MIN1

TJ = −40°C to +125°C 0.70 µF

MIN23

TJ = −40°C to +125°C 0.001 1 Ω

ESR

Rev. A | Page 6 of 32

Data Sheet ADP5042

ESD Machine Model

100 V

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx,
WMOD, WSTAT, nRSTO to GND
Storage Temperature Range −65°C to +150°C

Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
ESD Human Body Model 3000 V
ESD Charged Device Model 1500 V

−0.3 V to +6 V

Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The specified
value of θ

is based on a four-layer, 4” × 3”, 2.5 oz copper board,

JA

as per JEDEC standard. For additional information, see the

AN-772 Application Note, A Design and Manufacturing Guide

for the Lead Frame Chip Scale (LFCSP).

) of the package is

JA

may vary, depending on

JA

Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination.

The ADP5042 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit as long as the junction temperature is within specification
limits. The junction temperature of the device is dependent on
the ambient temperature, the power dissipation of the device
(P

), and the junction-to-ambient thermal resistance of the

D

package. Maximum junction temperature is calculated from the
ambient temperature and power dissipation using the formula

T

= TA + (PD × θJA)

J

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W

ESD CAUTION

Rev. A | Page 7 of 32

ADP5042 Data Sheet

D

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DI1

MO

W

MODE

W

MR
20

EN2

19

16

17

18

1

NC

2

VOUT3

VIN3

EN3

nRSTO

NOTES

1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.

2. NC = NO CONNE CT. DO NOT CONNECT TO THIS PIN.

3
4
5

ADP5042

TOP VIEW

(Not to S cale)

8

6

7

SW

VIN1

AVIN

15 WSTAT

VOUT2

14
13

VIN2

12

WDI2

11

VOUT1

9

10
EN1

PGND

08811-002

Figure 2. Pin Configuration—View from Top of the Die

Table 8. Preliminary Pin Function Descriptions

Pin No. Mnemonic Description

1 NC Do not connect to this pin.
2 VOUT3 LDO2 Output Voltage and Sensing Input.
3 VIN3 LDO2 Input Supply (1.7 V to 5.5 V).
4 EN3 Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2.
5 nRSTO Open-Drain Reset Output, Active Low.
6 AVIN Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V).
7 VIN1 Buck Input Supply (2.3 V to 5.5 V).
8 SW Buck Switching Node.
9 PGND Dedicated Power Ground for Buck Regulator.
10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.
11 VOUT1 Buck Sensing Node.
12 WDI2 Watchdog 2 (Long Timeout) Refresh Input from Processor. Can be disabled only by factory option.
13 VIN2 LDO1 Input Supply (1.7 V to 5.5 V).
14 VOUT2 LDO1 Output Voltage and Sensing Input.
15 WSTAT

Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:

Watchdog 2 timeout. Auto cleared after one second.
16 EN2 Enable LDO1. EN2 = high: turn on LDO1. EN2 = low: turn off LDO1.
17 MODE

Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: buck regulator operates

in pulse skipping mode (PSM) at light load and in constant PWM at higher load.
18 WMOD

Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by

a three-state condition applied on WDI1.
19 WDI1 Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled.
20

MR

Manual Reset Input, Active Low.
TP AGND Analog Ground (TP = Thermal Pad). Exposed pad should be connected to AGND.

Rev. A | Page 8 of 32

Data Sheet ADP5042

08811-003

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 2.0V/DIV 1MΩ

B

W

500M

CH3 2.0V/DIV 1MΩ

B

W

20.0M

A CH1 1.76V 200µs/DIV

50.0MS/s

20.0ns/pt

1

2

3

VOUT1

VOUT2

VOUT3

0

0.1

0.2

0.3

0.4

0.5

0.6

1.0

0.9

0.8

0.7

2.3 2.8 3.3 3.8 4.3 4.8 5.3

SYSTEM QUIESCENT CURRE NT (mA)

INPUT VOLTAGE (V)

08811-004

VOUT1 = 1.8V ,

VOUT2 = VO UT = 3.3V

08811-005

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 2.0V/DIV 1MΩ

B

W

500M

CH3 100mA/DIV 1MΩ

B

W

20.0M

CH4 5.0V/DIV 1MΩ

B

W

500M

A CH1 2.92V 50µs/DIV

50.0MS/s

20.0ns/pt

2

4

1

3

SW

VOUT1

EN

IIN

08811-006

CH1 4.0V/DIV 1MΩ

B

W

20.0M

CH2 3.0V/DIV 1MΩ

B

W

500M

CH3 200mA/DIV 1MΩ

B

W

20.0M

CH4 5.0V/DIV 1MΩ

B

W

500M

A CH1 2.24V 50µs/DIV

20.0MS/s

50.0ns/pt

4

2

1

3

SW

VOUT1

LOAD

EN

3.22

3.24

3.26

3.28

3.30

3.32

3.34

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

0 0.1 0.2 0.3 0.4 0.5 0.6

0.7 0.8 0.9 1.0

08811-007

+25°C

–40°C
+85°C

1.775

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

1.825

1.830

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

+25°C

–40°C
+85°C

08811-008

TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.

Figure 3. 3-Channel Start-Up Waveforms

Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage,

VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V

Figure 6. Buck Startup, VOUT1 = 1.8 V, I

OUT2

= 20 mA

Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode

Figure 5. Buck Startup, VOUT1 = 1.8 V, I

= 20 mA

OUT1

Rev. A | Page 9 of 32

Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode

ADP5042 Data Sheet

1.784

1.785

1.786

1.787

1.788

1.789

1.790

1.791

1.792

1.793

1.794

1.795

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

–40°C

+25°C

+85°C

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

08811-009

1.790

1.791

1.792

1.793

1.794

1.795

1.796

1.797

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

VIN = 5.5V

VIN = 4.5V

VIN = 3.6V

08811-010

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.5V

08811-011

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.5V

08811-012

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001

0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

2.4V

3.6V

4.5V

5.5V

08811-013

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

I

OUT

(A)

2.4V

3.6V

4.5V

5.5V

08811-014

Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode

Figure 10. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode

Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V,

PWM Mode

Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V,

Auto Mode

Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V,

Auto Mode

Figure 14. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V,

PWM Mode

Rev. A | Page 10 of 32

Data Sheet ADP5042

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

+25ºC

–40ºC
+85ºC

08811-015

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

+25°C

–40°C
+85°C

08811-016

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

+25°C

–40°C
+85°C

08811-017

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

2.6 3.6 4.6 5.6
INPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

08811-018

2.85

2.90

2.95

3.00

3.05

3.10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

FREQUENCY (MHz)

+25°C

–40°C

+85°C

08811-019

OUTPUT CURRE NT (A)

08811-020

CH1 20.0mV/ DIV

B

W

20.0M

CH2 200mA/DIV 1MΩ

B

W

20.0M

CH3 2.0V/ DIV 1MΩ

B

W

20.0M

A CH1 2.4mV 5.0µs/DIV

20.0MS/s

50.0ns/pt

1

2

3

VOUT

I

SW

SW

Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,

PWM Mode

Figure 16. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V,

Auto Mode

Figure 18. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V

Figure 19. Buck Switching Frequency vs. Output Current, Across Temperature,

VOUT1 = 1.8 V, PWM Mode

Figure 17. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,

Auto Mode

Figure 20. Typical Waveforms, VOUT1 = 3.3 V, I

= 30 mA, Auto Mode

OUT1

Rev. A | Page 11 of 32

ADP5042 Data Sheet

08811-021

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 50.0mV/ DIV

B

W

20.0M

CH3 500mA/DIV

B

W

20.0M

A CH1 1.56mV 5.0µs/DIV

200MS/s

5.0ns/pt

2

3

1

VOUT

I

SW

SW

08811-022

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 50.0mV/ DIV

B

W

20.0M

CH3 500mA/DIV

B

W

20.0M

A CH1 1.56mV 500ns/DIV

200MS/s

5.0ns/pt

2

3

1

VOUT

I

SW

SW

08811-023

CH1 20.0mV/ DIV

B

W

20.0M

CH2 200mA/DIV 1MΩ

B

W

20.0M

CH3 2.0V/DIV 1MΩ

B

W

20.0M

A CH1 2.4mV 200ns/DIV

500MS/s

2.0ns/pt

1

2

3

VOUT

I

SW

SW

08811-024

CH1 3V/DI V

B

W

20.0M

CH2 50mV/DI V

B

W

20.0M

CH3 900mV/DIV 1MΩ

B

W

20.0M

A CH3 4.79V 100µs/DIV

10.0MS/s
100ns/pt

1

3

VIN

VOUT

SW

2

08811-025

CH2 50mV/DI V

B

W

20.0M

CH3 1V/DI V 1MΩ

B

W

20.0M

CH4 2V/DI V 1MΩ

B

W

20.0M

A CH3 4.96mV 100µs/DIV

20MS/s
100ns/pt

2

3
4

VIN

VOUT

SW

08811-026

CH1 4V/DI V

B

W

20.0M

CH2 50mV/DI V 1MΩ

B

W

20.0M

CH3 50mA/DIV 1M Ω

B

W

20.0M

A CH3 44mA 200µs/DIV

10MS/s
100ns/pt

2

3

1

SW

VOUT

IOUT

Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT2 = 30 mA, Auto Mode

Figure 22. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode

Figure 24. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V,

VOUT1 = 3.3 V, PWM Mode

Figure 25. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V,

PWM Mode

Figure 23. Typical Waveforms, VOUT1 = 3.3 V, IOUT2 = 30 mA, PWM Mode

Figure 26. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,

VOUT1 = 3.3 V, Auto Mode

Rev. A | Page 12 of 32

Data Sheet ADP5042

08811-027

CH1 4V/DI V

B

W

20.0M

CH2 50mV/DI V

B

W

20.0M

CH3 50mA/DIV 1M Ω

B

W

20.0M

A CH3 28mA 200µs/DIV

5MS/s
200ns/pt

2

3

1

VOUT

SW

V

OUT

LOAD

A CH3 86mA

2

3

1

VOUT

SW

LOAD

08811-028

CH1 4V/DI V

B

W

20.0M

CH2 50mV/DIV

B

W

20.0M

CH3 50mA/DIV 1MΩ

B

W

20.0M

200µs/DIV
10MS/s
100ns/pt

3

4

2

08811-029

VOUT1

LOAD

SW

CH2 4V/DI V 1MΩ

B

W

20.0M

CH3 50mV/DI V 1MΩ

B

W

20.0M

CH4 50mA/DIV 1MΩ

B

W

20.0M

200µs/DIV
50MS/s
20ns/pt

A CH3 145mA

1

2

3

08811-030

VOUT

EN

IIN

A CH2 1.14V

CH1 1V/DI V 1MΩ

B

W

500M

CH2 3V/DIV 1MΩ

B

W

500M

CH3 50mA/DIV 1MΩ

B

W

20.0M

50µs/DIV
2MS/s
500ns/pt

08811-031

1

2

3

VOUT

IIN

EN

A CH2 1.14V

CH1 1V/DI V 1MΩ

B

W

500M

CH2 3V/DIV 1MΩ

B

W

500M

CH3 50mA/DIV 1MΩ

B

W

20.0M

100µs/DIV
1MS/s

1.0µs/pt

1.500

1.502

1.504

1.506

1.508

1.510

0.0001 0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

3.3V

4.5V

5.0V

5.5V

08811-032

Figure 27. Buck Response to Load Transient, IOUT2 from 1 mA to 50 mA,

VOUT2 = 1.8 V, Auto Mode

Figure 28. Buck Response to Load Transient, IOUT1 from 20 mA to 140 mA,

VOUT1 = 3.3 V, Auto Mode

Figure 30. LDO1 Startup, VOUT3=1.5 V, IOUT3 = 5 mA

Figure 31. LDO2 Startup, VOUT3=3.3 V, IOUT3 = 5 mA

Figure 29. Buck Response to Load Transient, IOUT2 from 20 mA to 180 mA,

VOUT1 = 1.8 V, PWM Mode

Figure 32. LDO1 Load Regulation Across Input Voltage, VOUT2 = 1.5 V

Rev. A | Page 13 of 32

ADP5042 Data Sheet

0.0001 0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

1.47

1.48

1.49

1.5

1.51

1.52

1.53
+85°C
+25°C
–40°C

08811-033

1.480

1.485

1.490

1.495

1.500

1.505

1.510

1.515

1.520

3.6 4.5 5.0 5.5

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

100µA
1mA
10mA
100mA
150mA

08811-034

3.25

3.26

3.27

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

0.0001 0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.0V

5.5V

08811-035

3.25

3.26

3.27

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

0.0001 0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

+85°C
+25°C
–40°C

08811-036

3.280

3.285

3.290

3.295

3.300

3.305

3.310

3.315

3.320

3.325

3.6 4.5 5.0 5.5

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

100µA
1mA
10mA
100mA
150mA

08811-037

0 0.05 0.10 0.15

LOAD (A)

CURRENT (µA)

08811-038

0

50

100

150

200

250

Figure 33. LDO1 Load Regulation Across Temperature, VIN2 = 3.3 V, VOUT2 = 1.5 V

Figure 34. LDO1 Line Regulation Across Output Load, VOUT2 = 1.5 V

Figure 36. LDO2 Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 3.3 V

Figure 37. LDO2 Line Regulation Across Output Load, VOUT3 = 3.3 V

Figure 35. LDO2 Load Regulation Across Input Voltage, VOUT3 = 3.3 V

Figure 38. LDO2 Ground Current vs. Output Load, VOUT3 = 2.8 V

Rev. A | Page 14 of 32

Data Sheet ADP5042

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8

GROUND CURRENT ( mA)

INPUT VOLTAGE (V)

1µA
100µA
1mA
10mA
100mA
150mA

08811-039

3

1

08811-040

VOUT

IOUT

CH1 50mV/DI V 1MΩ

B

W

500M

CH3 50mA/DIV 1M Ω

B

W

20.0M

200µs/DIV
500kS/s

2.0µs/pt

A CH3 28mA

1

3

08811-041

IOUT

VOUT

CH1 50mV/DI V 1MΩ

B

W

500M

CH3 50mA/DIV 1M Ω

B

W

20.0M

200µs/DIV
500kS/s

2.0µs/pt

A CH3 50mA

08811-042

21

22

CH1 10.0mV/DIV

CH2 800mV/DIV

A CH2 5.33V

1MΩ

B

W

20.0M

VOUT

VIN

B

W

20.0M

08811-043

21

CH1 10.0mV/Div

CH2 800mV/Div

A CH2 5.33V

B

W

20.0M

1MΩ

B

W

20.0M

VOUT

VIN

2

LOAD CURRENT ( A)

OUTPUT VOLTAGE (V)

0 0.1 0.2 0.3

0.5

0

1.0

1.5

2.0

2.5

3.0

0.4 0.5 0.6 0.7

0.8

5.5V

4.5V

3.6V

08811-056

Figure 39. LDO2 Ground Current vs. Input Voltage, Across Output Load,

VOUT3 = 2.8 V

Figure 40. LDO2 Response to Load Transient, IOUT3 from 1 mA to 80 mA,

VOUT3 = 3.3 V

Figure 42. LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V,

VOUT3 = 3.3 V

Figure 43. LDO1 Line Transient VIN = 4.5 V to 5.5 V, VOUT2 = 1.5 V

Figure 41. LDO1 Response to Load Transient, IOUT3 from 1 mA to 80 mA,

VOUT2 = 1.5 V

Figure 44. LDO1, LDO2 Output Current Capability vs. Input Voltage

Rev. A | Page 15 of 32

ADP5042 Data Sheet

LOAD (mA)

RMS NOISE (µV)

08811-044

100

10

CH2; V

OUT

= 3.3V; VIN = 5V

CH2; V

OUT

= 3.3V; VIN = 3.6V

CH2; V

OUT

= 2.8V; VIN = 3.1V

CH2; V

OUT

= 1.5V; VIN = 5V

CH2; V

OUT

= 1.5V; VIN = 1.8V

0.0001 0.001 0.01 0.1 1 10 100 1k

LOAD (mA)

RMS NOISE (µV)

08811-045

100

10

CH3; VOUT = 3. 3V ; V IN = 5V
CH3; VOUT = 3. 3V ; V IN = 3.6V
CH3; VOUT = 2. 8V ; V IN = 3.1V
CH3; VOUT = 1. 5V ; V IN = 5V
CH3; VOUT = 1. 5V ; V IN = 1.8V

0.0001 0.001 0.01 0.1 1 10 100 1k

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

NOISE (µV/√Hz)

08811-046

VOUT2 = 3.3V, VIN2 = 3.6V, I

LOAD

= 300mA

VOUT2 = 1.5V, VIN2 = 1.8V, I

LOAD

= 300mA

VOUT2 = 2.8V, VIN2 = 3.1V, I

LOAD

= 300mA

100

10

1.0

0.1

0.01

VOUT3 = 3.3V , VIN3 = 3.6V , I

LOAD

= 300mA

VOUT3 = 1.5V , VIN3 = 1.8V , I

LOAD

= 300mA

VOUT3 = 2.8V , VIN3 = 3.1V , I

LOAD

= 300mA

NOISE (µV/√Hz)

100

10

1

0.1

0.01
1 10 100 1k

FREQUENCY ( Hz )

10k 100k 1M

08811-055

100

10

1.0

0.1

0.01
10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

08811-048

NOISE (µV/

√Hz

)

VOUT3 = 1.5V, VIN3 = 1.8V, I

LOAD

= 300mA

VOUT2 = 2.8V, VIN2 = 3.1V, I

LOAD

= 300mA

VOUT3 = 2.8V, VIN3 = 3.1V, I

LOAD

= 300mA

VOUT2 = 3.3V, VIN2 = 3.6V, I

LOAD

= 300mA

VOUT3 = 3.3V, VIN3 = 3.6V, I

LOAD

= 300mA

VOUT2 = 1.5V, VIN2 = 1.8V, I

LOAD

= 300mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10 100 1k

10k 100k 1M 10M

FREQUENCY ( Hz )

PSRR (dB)

08811-049

1mA
10mA
100mA
200mA
300mA

Figure 45. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage

Figure 46. LDO2 Output Noise vs. Load Current, Across Input and Output Voltage

Figure 48. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V

Figure 49. LDO1 vs. LDO2 Noise spectrum

Figure 47. LDO1 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V

Figure 50. LDO2 PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V

Rev. A | Page 16 of 32

Data Sheet ADP5042

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

PSRR (dB)

08811-050

1mA
10mA
100mA
200mA
300mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10 100 1k

10k 100k 1M 10M

FREQUENCY ( Hz )

PSRR (dB)

08811-051

1mA
10mA
100mA
200mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10 100 1k

10k 100k 1M 10M

FREQUENCY ( Hz )

PSRR (dB)

08811-052

1mA
10mA
100mA
200mA
300mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

PSRR (dB)

08811-053

1mA
10mA
100mA
200mA
300mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10 100 1k

10k 100k 1M 10M

FREQUENCY ( Hz )

PSRR (dB)

08811-054

1mA
10mA
100mA
200mA
300mA

Figure 51. LDO2 PSRR Across Output Load, VIN3 = 3.1 V, VOUT3 = 2.8 V

Figure 52. LDO2 PSRR Across Output Load, VIN3 = 5 V, VOUT3 = 3.3 V

Figure 54. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V

Figure 55. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V

Figure 53. LDO2 PSRR Across Output Load, VIN3 = 3.6 V, VOUT3 = 3.3 V

Rev. A | Page 17 of 32

ADP5042 Data Sheet

ENABLE

AND MODE

CONTROL

LD

O1

CONTROL

SOFT START

PWM/

PSM

CONTROL

BUCK1

DRIVER

AND

AN

TISHOOT

THROUGH

OSCILLATOR

V

REF

THERMAL

SHUTDOWN

SYSTEM

UNDERVOLTAGE

LOCK OUT

RESET

GENERATOR

DEBOUNCE

PWM
COMP

VDDA

VDDA

VDDA

GM ERROR

AMP

PSM

COMP

LOW
CURRENT

I

LIMIT

R1

R2

ADP5042

VOUT1 WMOD

ENWD1 ENWD2

VIN1

AVIN

SW

PGND

EN1

ENBK

ENLDO1

ENLDO2

MODE

MODE

EN2

EN3

SEL

OPMODE_FUSES

VIN2 AGND VOUT2 VIN3

LDO2

CONTROL

R3

R4

ENLDO1

500Ω

ENBK

60Ω

ENLDO2

500Ω

D

C

B Y

A

VDDA

R0 R1

MR

WDI1

200kΩ

VDDA

52kΩ

40kΩ

WATCHDOG

DETECTOR1

WATCHDOG

STATUS

MONITOR

WDI2

WATCHDOG
DETECTOR2

POFF

POFF

VOUT3

nRSTO

WSTAT

08811-057

THEORY OF OPERATION

POWER MANAGEMENT UNIT

The ADP5042 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc convertor, two low

Figure 56. Functional Block Diagram

dropout linear regulators (LDOs), and a supervisory circuit, with
dual watchdog, for processor control. The regulators are activated
by a logic level high applied to the respective EN pin. The EN1
controls the buck regulator, the EN2 controls LDO1, and the
EN3 controls LDO2. The ADP5042 has factory programmed
output voltages and reset voltage threshold. Other features
available in this device are the mode pin to control the buck
switching operation, a status pin informing the external processor
which watchdog caused a reset and push-button reset input.

When a regulator is turned on, the output voltage is controlled
through a soft start circuit to avoid a large inrush current due to
the discharged output capacitors.

The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition is a function of
the current load and the output capacitor value. This operating
mode reduces the switching and quiescent current losses.

Rev. A | Page 18 of 32

Data Sheet ADP5042

Thermal Protection

In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off the buck and the LDOs.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the buck and LDOs do not return to operation until the
on-chip temperature drops below 130°C. When coming out of
thermal shutdown, soft start is initiated.

Undervoltage Lockout

To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the system. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.

Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device hits the turn-off threshold when the input
supply drops to 3.65 V typical.

Enable/Shutdown

The ADP5042 has individual control pins for each regulator. A
logic level high applied to the ENx pin activates a regulator, a
logic level low turns off a regulator.

When regulators are turned off after a Watchdog 2 event (see
the Watchdog 2 Input section), the reactivation of the regulator
occurs with a factory programmed order (see Tabl e 9). The
delay between the regulator activation (

Table 9. ADP5042 Regulators Sequencing

REGSEQ[1:0] Regulators Sequence (First to Last)

0 0
0 1
1 0
1 1 No sequence, all regulators start at same time

LDO1  LDO2  Buck
Buck  LDO1  LDO2
LDO1  Buck  LDO2

t

, tD2) is 2 ms.

D1

BUCK SECTION

The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.

Control Scheme

The buck operates with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a power save mode (PSM) control scheme at light
loads to lower the regulation power losses. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted and regulates the output voltage. When
operating in PSM at light loads, the output voltage is controlled
in a hysteretic manner, with higher output voltage ripple. During
part of this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.

PWM Mode

In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.

Power Save Mode (PSM)

The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level that is approximately 1.5% above
the PWM regulation level, PWM operation is turned off. At this
point, both power switches are off, and the buck enters an idle
mode. The output capacitor discharges until the output voltage
falls to the PWM regulation voltage, at which point the device
drives the inductor to make the output voltage rise again to the
upper threshold. This process is repeated while the load current
is below the PSM current threshold.

PSM Current Threshold

The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con­trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from the PSM.
The PSM current threshold is optimized for excellent efficiency
over all load currents.

Short-Circuit Protection

The buck includes frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possi­bility of a hard short at the output, the switching frequency is
reduced to half the internal oscillator frequency. The reduction
in the switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.

Soft Start

The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.

Current Limit

The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits

Rev. A | Page 19 of 32

RSTO

nRSTO

t

RD

t

RD

VOUT2

t

RP1

t

RP1

VOUT2

VOUT2

V

TH

V

TH

0V

1V
0V

1V
0V

08811-058

ADP5042 Data Sheet

the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.

100% Duty Operation

With a dropping input voltage or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.

LDO SECTION

The ADP5042 contains two LDOs with low quiescent current,
low dropout linear regulator, and provides up to 300 mA of
output current. Drawing a low 15 μA quiescent current (typical)
at no load makes the LDO ideal for battery-operated portable
equipment.

The LDO operates with an input voltage range of 1.7 V to 5.5 V.
The wide operating range makes these LDOs suitable for
cascading configurations where the LDO supply voltage is
provided from the buck regulator.

The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with just a small 1 µF ceramic input and output capacitor.

LDO2 is optimized to supply analog circuits because it offers
better noise performance compared to LDO1. LDO1 should be
used in applications where noise performance is not critical.

Internally, one LDO consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is con­trolled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
reducing the current flowing to the output.

SUPERVISORY SECTION

The ADP5042 provides microprocessor supply voltage super­vision by controlling the reset input of the microprocessor.
Code execution errors are avoided during power-up, power­down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be monitored
and corrected with a dual-watchdog timer.

Rev. A | Page 20 of 32

Reset Output

The ADP5042 has an active-low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail that is no higher than 6 V. The
resistor should comply with the logic low and logic high voltage
level requirements of the microprocessor while supplying input
current and leakage paths on the nRSTO pin. A 10 kΩ resistor is
adequate in most situations.

The reset output is asserted when the monitored rail is below
the reset threshold (V
within the watchdog timeout period (t

), when WDI1 or WDI2 is not serviced

TH

WD1

and t

). Reset remains

WD12

asserted for the duration of the reset active timeout period (t
after V

rises above the reset threshold or after the watchdog

CC

timer times out. Figure 57 illustrates the behavior of the reset
output, nRSTO, and it assumes that VOUT2 is selected as the
rail to be monitored and supplies the external pull-up connected
to the nRSTO output.

Figure 57. Reset Timing Diagram

The reset threshold voltage and the sensed rail (VOUT1,
VOUT2, VOUT3, or AVIN) are factory programmed. Refer to
Table 16 for a complete list of the reset thresholds available for
the ADP5042.

When monitoring the input supply voltage, AVIN, if the
selected reset threshold is below the UVLO level (factory
programmable to 2.25 V or 3.6 V) the reset output, nRSTO, is
asserted low as soon as the input voltage falls below the UVLO
threshold. Below the UVLO threshold, the reset output is
maintained low down to ~1 V VIN. This it to ensure that the reset
output is not released when there is sufficient voltage on the rail
supplying a processor to restart the processor operations.

Manual Reset Input

The ADP5042 features a manual reset input (MR) which, when
driven low, asserts the reset output. When

MR

transitions from
low to high, reset remains asserted for the duration of the reset
active timeout period before deasserting. The

MR

input has a
52 kΩ, internal pull-up, connected to AVIN, so that the input is
always high when unconnected. An external push-button
switch can be connected between

MR

and ground so that the
user can generate a reset. Debounce circuitry for this purpose is
integrated on chip. Noise immunity is provided on the

MR

input,
and fast, negative-going transients of up to 100 ns (typical) are
ignored. A 0.1 µF capacitor between

MR

and ground provides

additional noise immunity.

)

RP

Data Sheet ADP5042

WDI1

n

RSTO

t

RP1

t

RP1

t

WD1

V

SENSED

V

TH

1V
0V

0V

0V

08811-059

AVIN/VINx/ENx

V

OUT1

V

OUT2

V

OUT3

n

RSTO

WDI2

WSTAT

0V

0V

0V

0V

0V

t

POFF

t

RP2

t

WD2

t

RP1

t

RP1

t

WDCLEAR

t

D1

t

D1

t

D2

V

TH

t

D2

08811-060

Watchdog 1 Input

The ADP5042 features a watchdog timer that monitors micro­processor activity. A timer circuit is cleared with every low-to­high or high-to-low logic transition on the watchdog input pin
(WDI1), which detects pulses as short as 80 ns. If the timer
counts through the preset watchdog timeout period (t
is asserted. The microprocessor is required to toggle the WDI1
pin to avoid being reset. Failure of the microprocessor to toggle
WDI1 within the timeout period, therefore, indicates a code
execution error, and the reset pulse generated restarts the
microprocessor in a known state.

As well as logic transitions on WDI1, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the monitored rail. When reset is asserted, the watchdog timer
is cleared and does not begin counting again until reset deasserts.
Watchdog 1 timer can be disabled by leaving WDI1 floating or
by three-stating the WDI1 driver. The pin WMOD controls the
Watchdog 1 operating mode. If WMOD is set to logic level low,
Watchdog 1 is enabled as long as WDI1 is not in three-state. If
WMOD is set to logic level high, Watchdog 1 is always active
and cannot be disabled by a three-state condition. WMOD
input has an internal 200 kΩ pull-down resistor.

Watchdog 1 timeout is factory set to two possible values as
indicated in Table 18.

WD1

), reset

Figure 58. Watchdog 1 Timing Diagram

Watchdog 2 Input

The ADP5042 features an additional watchdog timer that
monitors microprocessor activity in parallel to the first watchdog
with a much longer timeout. This provides additional security
and safety in case Watchdog 1 is incorrectly strobed. A timer
circuit is cleared with every low-to-high or high-to-low logic
transition on the watchdog input pin (WDI2), which detects pulses
as short as 8 µs. If the timer counts through the preset watchdog
timeout period (t

), reset is asserted, followed by a power

WD2

cycle of all regulators . The microprocessor is required to toggle
the WDI2 pin to avoid being reset and powered down. Failure
of the microprocessor to toggle WDI2 within the timeout period,
therefore, indicates a code execution error, and the reset output
nRSTO is forced low for
off for the t

time. After the t

POFF

t

. Then, all the regulators are turned

RP2

period, the regulators are re-

POFF

activated according to a predefined sequence (see Tab l e 9). Finally,
the reset line (nRSTO) is asserted for

t

. This guarantees a

RP1

clean power-up of the system and proper reset.

As well as logic transitions on WDI2, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the VTH monitored rail which can be factory programmable
between VOUT1, VOUT2, VOUT3, an d AV IN (see Tabl e 21).
When reset is asserted, the watchdog timer is cleared and does
not begin counting again until reset deasserts.

Watchdog 2 timeout is factory set to seven possible values as
indicated in Table 19. One additional option allows Watchdog 2
to be factory disabled.

Figure 59. Watchdog 2 Timing Diagram (Assuming That VOUT2 Is the Monitored Rail)

Rev. A | Page 21 of 32

ADP5042 Data Sheet

Low

Don't care

Watchdog 2

NO POWER APPLIED TO AVIN.

ALL REGULATORS AND SUPERVISORY

TURNED OFF

NO POWER

POR

STANDBY

WSTAT = HIGH

WSTAT = HIGH

RESET

NORMAL

WSTAT = LOW

AVIN < VUVLO

ALL ENx = LOW

AVIN > VUVLO

TRANSITION

STATE

TRANSITION

STATE

TRANSITION

STATE

END OF POR

WSTAT

TIMEOUT

(t

WDCLEAR

)

WSTAT = 1

TRANSITION

STATE

ALL REGULATORS AND

SUPERVISOR ACTIVATED

WDOG2

TIMEOUT

(t

WD2

)

WSTAT = 0

END OF (t

POFF

)

PULSE

WDOG1 TIMEOUT

(t

WD1

) AND

WSTAT TIMEOUT

WSTAT = 1

WDOG1 TIMEOUT

(t

WD1

)

ALL ENx = HIGH

ACTIVE

POWER OFF

RESET SHORT

AVIN < VUVLO

END OF RESET

PULSE (t

RP2

)

INTERNAL CIRCUIT BIASED
REGULATORS AND
SUPERVISORY NOT ACTIVATED

AVIN < VUVLO

AVIN < VUVLO

VMON < VTH

END OF RESET

PULSE (t

RP1

)

08811-061

Watchdog Status Indicator

In addition to the dual watchdog function, the ADP5042
features a watchdog status monitor available on the WSTAT pin.
This pin can be queried by the external processor to determine
the origin of a reset. WSTAT is an open-drain output.

WSTAT outputs a logic level depending on the condition that
has generated a reset. WSTAT is forced low if the reset was
generated because of a Watchdog 2 timeout. WSTAT is pulled
high, through external pull-up, for any other reset cause (Watchdog
1 timeout, power failure or monitored voltage below threshold).
The status monitor is automatically cleared (set to logic level
high) 10 seconds after the nRSTO low to high transition (t

WDCLEAR

),
processor firmware must be designed being able to read the
WSTAT flag before t

expiration after a Watchdog 2 reset.

WDCLEAR

The WSTAT flag is not updated in the event of a reset due to a
low voltage threshold detection or Watchdog 1 event occurring
within 10 seconds after nRSTO low to high transition. In this

situation, WSTAT maintains the previous state (see state flow in
Figure 60).

The external processor can further distinguish a reset caused by
a Watchdog 1 timeout from a power failure, status monitor
WSTAT indicating a high level, by implementing a RAM check
or signature verification after reset. A RAM check or signature
failure indicates that a power failure has occurred, whereas a
RAM check or signature validation indicates that a Watchdog 1
timeout has occurred.

Tabl e 10 shows the possible watchdog decoded statuses.

Table 10. Watchdog Status Decoding

WSTAT RAM CHECKSUM RESET ORIGIN

High Failed Power failure
High Ok Watchdog 1

Figure 60. ADP5042 State Flow

Rev. A | Page 22 of 32

Data Sheet ADP5042

−×

2

I

0

2

4

6

8

10

12

0 1 2 3 4 5 6

DC BIAS VOLTAGE (V)

CAPACITANCE (µ F)

08811-062

APPLICATIONS INFORMATION

BUCK EXTERNAL COMPONENT SELECTION

Trade -offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 66.

Inductor

The high switching frequency of the ADP5042 buck allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 μH and 3 μH. Suggested inductors
are shown in Ta bl e 11.

The peak-to-peak inductor current ripple is calculated using
the following equation:

VVV

OUT

××

LfV

RIPPLE

)(

Dimensions
(mm)

I

SAT

(mA)

DCR
(mΩ)

I

RIPPLE

OUT

=

IN

IN

SW

where:

f

is the switching frequency.

SW

L is the inductor value.

The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:

II +=

PEAK

)(

MAXLOAD

Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the buck is high switching frequency dc-to-dc converters,
shielded ferrite core material is recommended for its low core
losses and low EMI.

Table 11. Suggested 1.0 μH Inductors

Vendor Model

Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85
Murata LQM18FN1R0M00B 1.6 × 0.8 × 0.8 150 26
Taiyo Yuden CBMF1608T1R0M 1.6 × 0.8 × 0.8 290 90
Coilcraft EPL2014-102ML 2.0 × 2.0 × 1.4 900 59
TDK GLFR1608T1R0M-LR 1.6 × 0.8 × 0.8 230 80
Coilcraft 0603LS-102 1.8 × 1.69 × 1.1 400 81
Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85

Output Capacitor

Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.

Ceramic capacitors are manufactured with a variety of dielec­trics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recom­mended for best performance. Y5V and Z5U dielectrics are
not recommended for use with any dc-to-dc converter because
of their poor temperature and dc bias characteristics.

The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu­lated using the following equation:

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL)

OUT

where:

is the effective capacitance at the operating voltage.

C

EFF

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C

is 9.2481 μF at 1.8 V, as shown in Figure 61.

OUT

Substituting these values in the equation yields

= 9.2481 μF × (1 − 0.15) × (1 − 0.1) = 7.0747 μF

C

EFF

To guarantee the performance of the buck, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.

Figure 61. Typical Capacitor Performance

Rev. A | Page 23 of 32

ADP5042 Data Sheet

V

OUT

SW

RIPPLE

CfI××=8

RIPPLE

V

Taiyo Yuden

X5R

JMK107BJ475

0603

6.3

SW

VIN1

VIN2

VIN3

VOUT1

VOUT2

nRSTO

PGND

VOUT3

L1

1µH

C6

4.7µF

C4

1µF

R1
100kΩ

C5
1µF

C2

4.7µF

C1
1µF

C3
1µF

AVIN

R

FLT

30Ω

V

IN

2.3V TO 5.5V

MICRO PMU

ADP5042

PROCESSOR

ANALOG

SUB-SYSTEM

VCORE

VDDIO

RESET

GPIO1

MODE

WDI

GPIO2

ENx

GPIO[x:y]

VANA

3

08811-063

Murata

X5R

GRM188R60J475ME19D

0603

6.3

The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:

V

RIPPLE

=

( )

×

π

SW

IN

×××

CLf

22

OUT

Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:

RIPPLE

ESR ≤

COUT

I

The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.

Input Capacitor

Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:

VVV

)(

−

IN

CIN

II

≥

OUT

MAXLOAD

)(

OUT

V

IN

To m i ni mize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR capacitor is recommended.

The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Tabl e 13.

Table 12. Suggested 10 μF Capacitors

Vendor Typ e Model

Case
Size

Voltage
Rating (V)

Murata X5R GRM188R60J106 0603 6.3

TDK X5R C1608JB0J106K 0603 6.3
Panasonic X5R ECJ1VB0J106M 0603 6.3

The buck regulator requires 10 µF output capacitors to guaran­tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 62).

Table 13. Suggested 4.7 μF Capacitors

Vendor Type Model

Size

Taiyo Yuden X5R JMK107BJ475 0603 6.3
Panasonic X5R ECJ-0EB0J475M 0402 6.3

Case

Voltage
Rating
(V)

LDO CAPACITOR SELECTION

Output Capacitor

The ADP5042 LDOs are designed for operation with small,
space-saving ceramic capacitors, but they function with most
commonly used capacitors as long as care is taken with the ESR
value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 µF capacitance with an
ESR of 1 Ω or less is recommended to ensure stability of the
ADP5042. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP5042 to
large changes in load current.

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN2 and VIN3 to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance is encountered. If greater than 1 µF of output
capacitance is required, increase the input capacitor to match it.

Figure 62. Processor System Power Management with PSM/PWM Control

Table 14. Suggested 1.0 μF Capacitors

Voltage

Case

Rev. A | Page 24 of 32

Vendor Type Model

Murata

X5R GRM155R61A105ME15

TDK X5R C1005JB0J105KT 0402 6.3
Panasonic X5R ECJ0EB0J105K 0402 6.3
Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0

Rating

Size

(V)

0402 10.0

Data Sheet ADP5042

1.2

1.0

0.8

0.6

0.4

0.2

0

0 1 2 3 4 5 6

DC BIAS VOLTAGE (V)

CAPACITANCE (µ F)

08811-064

1000

900

800

700

600
500

400

300
200

100

0

0.1 1 10 100
C

OMPARATOR OVERDRIVE (% OF V

TH

)

TRANSIENT DURATION (µs)

08811-065

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP5042 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe­rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.

Figure 63

depicts the capacitance vs. voltage bias characteristic

of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera­ture range and is not a function of package or voltage rating.

To guarantee the performance of the ADP5042, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.

SUPERVISORY SECTION

Watchdog 1 Input Current

To minimize watchdog input current (and minimize overall
power consumption), leave WDI1 low for the majority of the
watchdog timeout period. When driven high, WDI1 can draw
as much as 25 µA. Pulsing WDI1 low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI1 is unconnected and WMOD is set to logic level low, a
window comparator disconnects the watchdog timer from the
reset output circuitry so that reset is not asserted when the
watchdog timer times out.

Negative-Going VCC Transients

To av o id unnecessary resets caused by fast power supply transients,
the ADP5042 is equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 64 plots the monitored rail
voltage, V
The curve shows combinations of transient magnitude and
duration for which a reset is not generated for a 2.93 V reset
threshold part. For example, with the 2.93 V threshold, a
transient that goes 100 mV below the threshold and lasts 8 µs
typically does not cause a reset, but if the transient is any larger
in magnitude or duration, a reset is generated.

, transient duration vs. the transient magnitude.

TH

Figure 63. Capacitance vs. Voltage Characteristic

Use the following equation to determine the worst-case capa­citance accounting for capacitor variation over temperature,
component tolerance, and voltage.

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL)

BIAS

where:
C

is the effective capacitance at the operating voltage.

BIAS

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C

is 0.94 μF at 1.8 V as shown in Figure 63.

BIAS

Substituting these values into the following equation yields:

= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

C

EFF

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.

Figure 64. Maximum V

Threshold Overdrive

Transient Duration vs. Reset

TH

Watchdog Software Considerations

In implementing the watchdog strobe code of the micro­processor, quickly switching WDI1 low to high and then high
to low (minimizing WDI1 high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.

A low-to-high-to-low WDI1 pulse within a given subroutine
prevents the watchdog from timing out. However, if the sub­routine becomes stuck in an infinite loop, the watchdog cannot
detect this because the subroutine continues to toggle WDI1. A
more effective coding scheme for detecting this error involves

Rev. A | Page 25 of 32

ADP5042 Data Sheet

START

SET WDI

HIGH

PROGRAM

CODE

SUBROUTINE

SET WDI

LOW

RETURN

INFINITE LOOP:

WATCHDOG

TIMES OUT

RESET

08811-066

ADP5042

MICROPROCESSOR

V

CC

VOUT1
VOUT2

nRSTO

WDI1

RESET

WDI2

VIN1

I/O
I/O

V

CORE

VDDIO

08811-067

using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI1 is set high. The subroutine sets
WDI1 low when it is called. If the program executes without error,
WDI1 is toggled high and low with every loop of the program.
If the subroutine enters an infinite loop, WDI1 is kept low, the
watchdog times out, and the microprocessor is reset (see
Figure 65).

Figure 65. Watchdog Flow Diagram

The second watchdog, refreshed through the WDI2 pin, is
useful in applications where safety is a very critical factor and
the system must recover from unwanted operations, for example, a
processor stuck in a continuous loop where Watchdog 1 is kept
refreshed or environmental conditions that may unset or damage
the processor port controlling the WDI1 pin. In the event of a
Watchdog 2 timeout, the ADP5042 power cycles all the supplied
rails to guarantee a clean processor start.

Figure 66. Typical Applications Circuit

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5042 performance, causing electro­magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:

• Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.

• Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

• Maximize the size of ground metal on the component side

to help with thermal dissipation.

• Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference
on sensitive circuit nodes.

Rev. A | Page 26 of 32

Data Sheet ADP5042

SW
VOUT1
PGND

MODE

C6
10µF

L1

1µH

VIN1

TP1

TP2

TP11

TP6

TP5

TP8

EN3

EN1

VIN2

VIN3

EN2

AGND

C2
1µF

VOUT2

VOUT3

WSTAT

WDI1
WDI2

nRSTO

TP12

C4
1µF

C5

4.7µF

VIN1 = 2.3V

TO 5.5V

AVIN

R

FILT

30Ω

AVIN

VIN2 = 1.7V

TO 5.5V

C1

1µF

VIN3 = 1.7V

TO 5.5V

C3

1µF

VOUT1 AT
800mA

VOUT2 AT
300mA

VOUT3 AT
300mA

TP4

TP9

TP10

TP7

TP3

EN_BK

BUCK

EN_LDO1

LDO1

EN_LDO2

LDO2

SUPERVISOR

AVIN

08811-068

0.5

0.5

1.0 1.5 2.0

2.5 3.0

3.5

4.0 4.5

5.0

5.5

1.0

1.5

2.0

2.5

3.0

3.5

VIAs LEGEND

mm

mm

6.0

6.5

NC

MODE

VIN1

SW

PGND

EN1

4.0

4.5

5.0

5.5

6.0

C6- 10

µ

F

6.3V/XR50603

GPL

GP

L

1.5V

3.3V

7.0

TOP LAYER
SECOND LAYER

PPL

L1 – 1µH

0603

C5 – 4.7µF

10V/XR5 0603

C4 – 1µF

6.3V/XR5
0402

C1 – 1µF

10V/XR5

0402

C2 – 1µF
10V/XR5

0402

PPL = POWER PLANE (+4V)
GPL = GROUND PLANE

1.8V

AGND

ADP5042

GPLGPL

GPL

GPL

VOUT3

PIN 1

VIN3

WDI2

VIN2

VOUT2

WSTAT

EN2

NC

WDI1

WMOD

VOUT1

MR

nRSTO

N

C3 – 1µF

6.3V/XR5
0402

EN3

R

FILT

30Ω

0402

GPL

GPL

GPL

GPL

GPL

PPL PPL PPL

EVALUATION BOARD SCHEMATICS AND ARTWORK

SUGGESTED LAYOUT

Figure 67. Evaluation Board Schematic

Figure 68. Layout

Rev. A | Page 27 of 32

ADP5042 Data Sheet

C1, C2, C3, C4

1 µF, X5R, 6.3 V

LMK105BJ105MV-F

Taiyo Yuden

0402

V

V

V

BILL OF MATERIALS

Table 15.

Reference Value Part Number Vendor Package

C5 4.7 µF, X5R, 10 V LMK107BJ475MA-T Taiyo Yuden 0603
C6 10 µF, X5R, 6.3 V JMK107BJ106MA-T Taiyo Yuden 0603
R

30 Ω 0201/0402

FI LT

L1 1 µH, 0.09 Ω, 290 mA BRC1608T1R0M Taiyo Yuden 0603
1 µH, 0.08 Ω, 230 mA GLFR1608T1R0M-LR TDK 0603
IC1 3-regulator micro PMU ADP5042 Analog Devices 20-Lead LFCSP

APPLICATION DIAGRAM

R

FILT

30Ω

AVIN

IN1 = 2.3V

TO 5.5V

IN2 = 1.7V

TO 5.5V

PUSH-BUTTON

IN3 = 1.7V

TO 5.5V

4.7µF

OFF

C1

1µF

OFF

RESET

OFF

C3

1µF

C5

ON

ON

ON

VIN3

AVIN

6

VIN1

7

EN1

10

VIN2

13

EN2

16

MR

20

EN3

4

3 2

EN_BK

(DIGITAL)

EN_LDO1

AVIN

POFF

EN_LDO2

(ANALOG)

BUCK

LDO1

SUPERVISOR

LDO2

RESET

WDOG2

WDOG1

AGND

8

11

9

17

14

15

5

12

19

17

16

1

SW
VOUT1
PGND

MODE

VO

UT2

WSTAT

nRST

WDI2

WDI1

WMOD

EN2
NC

VOUT3

L1

1µH

FPWM

R1

O

V

DD

PWM/PSM

V

DD

R2

ON

F

OF

C4
1µF

VOUT1 AT
800mA

C6
10µ

F

VOUT2 AT
300mA

C2
1µF

VOUT3 AT
300mA

MAIN

MICROCONTROLLER

08811-070

Figure 69. Application Diagram

Rev. A | Page 28 of 32

Data Sheet ADP5042

Min

Typ

Max

Min

Max

111 (For VIN = 5 V − 6%)

4.630

4.700

V

110 (For VOUT = 3.3 V)

3.034

3.080

3.126

3.003

3.157

V

101 (For VOUT = 3.3 V)

2.886

2.930

2.974

2.857

3.000

V

100 (For VOUT = 2.8 V)

2.591

2.630

2.669

2.564

2.696

V

011 (For VOUT = 2.8 V)

2.463

2.500

2.538

2.438

2.563

V

010 (For VOUT = 2.5 V − 6%)

2.350

2.385

V

001 (For VOUT = 2.2 V − 6%)

2.068

2.099

V

000 (For VOUT = 1.8 V − 6%)

1.692

1.717

V

111

102.4

128

153.6

min

11

AVIN1 pin

FACTORY PROGRAMMABLE OPTIONS

Table 16. Reset Voltage Threshold Options1

T

= +25°C T

A

Selection

Table 17. Reset Timeout Options

Selection Min Ty p Max Unit

0 24 30 36 ms
1 160 200 240 ms

Table 18. Watchdog 1 Timer Options

Selection Min Ty p Max Unit

0 81.6 102 122.4 ms
1 1.12 1.6 1.92 sec

= −40°C to +85°C

A

Unit

Table 19. Watchdog 2 Timer Options

Selection Min Ty p Max Unit

000 6 7.5 9 sec
001 Watchdog 2 disabled
010 3.2 4 4.8 min
011 6.4 8 9.6 min
100 12.8 16 19.2 min
101 25.6 32 38.4 min
110 51.2 64 76.8 min

Table 20. Power-Off Timing Options

Selection Min Ty p Max Unit

0 140 200 280 ms
1 280 400 560 ms

Table 21. Reset Sensing Options

Selection Monitored Rail

00 VOUT1 pin
01 VOUT2 pin
10 VOUT3 pin

1

When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V).

Rev. A | Page 29 of 32

ADP5042 Data Sheet

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

0.30

0.25

0.20

16

15

EXPOSED

11

10

BOTTOM VIEWTOP VIEW

20

1

PAD

5

6

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

P

N

I

I

N

I

D

0.25 MIN

1

O

C

A

T

2.65

2.50 SQ

2.35

R

COMPLIANTTOJEDEC STANDARDS MO-220-WGGD.

061609-B

Figure 70. 20-Lead, Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2

Model

ADP5042ACPZ-1-R7 VOUT1 = 1.8 V WD1 t

Regulator Settings Supervisory Settings Temperature Range Package Description

= 1.6 sec TJ = −40°C to +125°C

OUT

20-Lead, Lead Frame
Scale Package

[LFCSP_WQ]
VOUT2 = 1.5 V WD2 t
VOUT3 = 3.3 V Reset t

= 128 min

OUT

= 200 ms

OUT

UVLO = 2.2 V POFF = 200 ms

Sequencing: LDO1,
LDO2, buck

VTH Sensing =
VOUT3, 2.93 V

ADP5042ACPZ-2-R7 VOUT1 = 1.5 V WD1 t

= 1.6 sec TJ = −40°C to +125°C

OUT

20-Lead, Lead Frame

Scale Package

[LFCSP_WQ]
VOUT2 = 1.8 V WD2 t
VOUT3 = 3.3 V Reset t

= 128 min

OUT

= 200 ms

OUT

UVLO = 2.2 V POFF = 200 ms

Sequencing: LDO1,
LDO2, buck

VTH Sensing =

VOUT3, 2.93 V
ADP5042CP-1-EVALZ Evaluation Board
ADP5042CP-2-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

2

Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits.

Package
Option

CP-20-10

CP-20-10

Rev. A | Page 30 of 32

Data Sheet ADP5042

NOTES

Rev. A | Page 31 of 32

ADP5042 Data Sheet

NOTES

©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08811-0-11/11(A)

Rev. A | Page 32 of 32