Datasheet ADP5041 Datasheet (ANALOG DEVICES)

Micro PMU with 1.2 A Buck, Two 300 mA LDOs

Supervisory, Watchdog and Manual Reset

Preliminary Technical Data

FEATURES

Input voltage range: 2.3 V to 5.5 V
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open drain processor reset with externally adjustable

threshold monitoring
Guaranteed reset output valid to V
Manual reset input
Watchdog refresh input
Buck key specifications
Output voltage range 0.8 V to 3.8 V
Current mode topology for excellent transient response
3 MHz operating frequency
Peak Efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Output Voltage Range 0.8 V to 5.2 V
Low input supply voltage from 1.7 V to 5.5 V
Stable with 2.2 μF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise
Low dropout voltage

−40°C to +125°C junction temperature range

AVIN

= 1 V

ADP5041

HIGH LEVEL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADP5041 combines one high performance buck regulator and
two low dropout regulators (LDO) in a small 20-lead LFCSP to
meet demanding performance and board space requirements.

The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes board
space.

When the MODE pin is set to logic high, the buck regulator
operates in forced PWM mode. When the MODE pin is set to logic
low, the buck regulator operates in PWM mode when the load is
around the nominal value. When the load current falls below a
predefined threshold the regulator operates in power save mode
(PSM) improving the light-load efficiency.
The low quiescent current, low dropout voltage, and wide input

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

voltage range of the ADP5041 LDOs extend the battery life of
portable devices. The ADP5041 LDOs maintain a power supply
rejection greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.

Each regulator in ADP5041 is activated by a high level on the
respective enable pin. The regulators’ output voltages and the reset
threshold are programmed though external resistor dividers to
address a variety of applications. The ADP5041 contains
supervisory circuits that monitor power supply voltage levels and
code execution integrity in microprocessor-based systems. They
also provide power-on reset signals. An on-chip watchdog timer
can reset the microprocessor if it fails to strobe within a preset
timeout period.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADP5041 Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

High Level Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

General Specification ................................................................... 3

Supervisory Specification ............................................................ 3

Buck Specifications ....................................................................... 4

LDO1, LDO2 Specifications ....................................................... 5

Input and Output Capacitor, Recommended Specifications .. 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 18

Power Management Unit ........................................................... 18

Buck Section ................................................................................ 19

LDO Section ............................................................................... 20

Supervisory Section ................................................................... 20

Applications Information .............................................................. 23

Buck External Component Selection ....................................... 23

LDO EXTERNAL COMPONENT Selection ......................... 24

Supervisory Section ................................................................... 25

Power Dissipation/Thermal Considerations ............................. 26

PCB Layout Guidelines .............................................................. 28

Suggested Layout ........................................................................ 29

Bill of Materials ........................................................................... 29

Application Diagram ................................................................. 30

Factory Programmable Options ................................................... 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

Rev. PrE | Page 2 of 32

Preliminary Technical Data ADP5041

SPECIFICATIONS

GENERAL SPECIFICATION

AVIN, VIN1 = 2.3V to 5.5V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum
specifications, and T

Table 1.

Parameter Symbol Description Min Typ Max Unit

AVIN UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

Option 0 2.275 V
Option 1 3.9 V

Input Voltage Falling UVLO

Option 0 1.95 V
Option 1 3.1 V

SHUTDOWN CURRENT I

Thermal Shutdown Threshold TSSD T

Thermal Shutdown Hysteresis TS

START-UP TIME1

BUCK t

LDO1, LDO2 t

ENx, WDI, MODE, MR INPUTS

Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V

Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V

Input Leakage Current V

OPEN-DRAIN OUTPUT

nRSTO Output Voltage V

V

V

V

Open-Drain Reset Output Leakage

Current

= 25°C for typical specifications, unless otherwise noted.

A

AVIN

AVIN RI SE

AVIN FALL

ENx = GND 0.1 2 µA

GND-SD

rising 150 °C

J

20 °C

SD-HYS

250 µs

START1

START2

VOUT2, VOUT3 = 3.3 V

ENx = AVIN or GND 0.05 1 µA

I-LEAKAGE

OL1V

OL1V2

AVIN ≥ 2.7 V, I

OL2V7

AVIN ≥ 4.5 V, I

OL4V5

AVIN ≥ 1.0 V, I
AVIN ≥ 1.2 V, I

= 50 μA

SINK

= 100 μA

SINK

= 1.2 mA 0.3

SINK

= 3.2 mA 0.4

SINK

AVIN = 5.5 V 1 µA

85 µs

0.3

0.3

V
V
V
V

SUPERVISORY SPECIFICATION

AVIN, VIN1 = 2.3 V to 5.5 V; TJ = -40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications
unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY

Supply Current (Supervisory Circuit Only) 45 55 µA

43 52 µA

THRESHOLD VOLTAGE 0.495 0.500 0.505 V
RESET TIMEOUT PERIOD

ADP5041B 24 30 36 ms

ADP5041C 160 200 240 ms

VCC TO RESET DELAY 80 µs VIN falling at 1 mV/µs
WATCHDOG INPUT

Watchdog Timeout Period

ADP5041xX 81.6 102 122.4 ms
ADP5041xY 1.28 1.6 1.92 sec

Rev. PrE | Page 3 of 32

AVIN = VIN1 = EN1 = EN2 = EN3 =

5.5V
AVIN = VIN1 = EN1 = EN2 = EN3 =

3.6V

ADP5041 Preliminary Technical Data

Parameter Min Typ Max Unit Test Conditions/Comments

WDI Pulse Width 80 ns VIL = 0.4 V, VIH = 1.2 V

WDI Input Threshold 0.4 1.2 V

WDI Input Current (Source) 8 15 20 µA V
WDI Input Current (Sink) −30 −25 -15 µA V

MANUAL RESET INPUT

MR Input Pulse Width

MR Glitch Rejection

MR Pull-Up Resistance

MR to Reset Delay

1

Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to V

Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.

1 µs

220 ns

25 52 90 kΩ

280 ns VCC = 5 V

to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level.

AVIN

BUCK SPECIFICATIONS

AVIN, VIN1 = 2.3V to 5.5 V; V
specifications, and T

= 25°C for typical specifications, unless otherwise noted.1

A

Table 3.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Input Voltage Range VIN1 2.3 5.5 V

OUTPUT CHARACTERISTICS

Output Voltage Accuracy V
Line Regulation (∆V

Load Regulation (∆V
VOLTAGE FEEDBACK V
PWM TO POWER SAVE MODE CURRENT

THRESHOLD
INPUT CURRENT CHARACTERISTICS MODE = ground

DC Operating Current I

Shutdown Current I
SW CHARACTERISTICS

SW On Resistance R

PFET, AVIN = VIN1 = 5 V 140 190 mΩ

R

NFET, AVIN = VIN1 = 5 V 150 210 mΩ

Current Limit I
ACTIVE PULL-DOWN EN1 = 0 V 85 Ω
OSCILLATOR FREQUENCY F

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

= 1.8 V; L = 1 µH; CIN = 10 µF; C

OUT1

PWM mode, I

OUT1

OUT1/VOUT1

OUT1/VOUT1

0.485 0.5 0,515 V

FB1

I

PSM_L

NOLOAD

SHTD

PFET

NFET

LIMIT

OSC

)/∆V
)/∆I

100 mA

EN1 = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 A

NFET, AVIN = VIN1 = 3.6 V 170 235 mΩ

2.5 3.0 3.5 MHz

= 10 µF; TJ= −40°C to +125°C for minimum/maximum

OUT

= 0 mA to 1200 mA −3 +3 %

LOAD

PWM mode -0.05 %/V

IN1

I

OUT1

= mA to 1200 mA, PWM mode -0.1 %/A

LOAD

I

= 0 mA, device not switching, all other

LOAD

channels disabled

PFET, AVIN = VIN1 = 3.6 V 180 240 mΩ

PFET switch peak current limit 1600 1950 2300 mA

= VCC, time average

WDI

= 0, time average

WDI

21 35 A

Rev. PrE | Page 4 of 32

Preliminary Technical Data ADP5041

LDO1, LDO2 SPECIFICATIONS

V
to +125°C for minimum/maximum specifications and T

Table 4.

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

This is the input current into VIN2/VIN3, which is not delivered to the output load.

3

Based on an end-point calculation using 1 mA and 300 mA loads.

4

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

5

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

IN2, VIN3

= (V

OUT2,VOUT3

+ 0.5 V) or 1.7 V (whichever is greater) to 5.5V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 µF, C

= 25°C for typical specifications, unless otherwise noted. 1

A

= 2.2 µF; TJ= −40°C

OUT

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE V

, V

T

IN2

IN3

= −40°C to +125°C 1.7

J

5.5 V

OPERATING SUPPLY CURRENT

Bias Current per LDO2

I

Total System Input Current

I

VIN2BIAS

IIN

/ I

I

VIN3BIAS

= I

= 0 µA

OUT4

= I

= 10 mA 60 100 µA

OUT3

= I

= 300 mA 165 245 µA

OUT3

I

OUT3

OUT2

OUT2

Includes all current into AVIN, VIN1, VIN2 and

10 30 µA

VIN3

LDO1 or LDO2 Only

LDO1 and LDO2 Only

OUTPUT VOLTAGE ACCURACY V

OUT2, VOUT3

100 µA < I

I

I

OUT2

OUT2

= I

= 0 µA, all other channels disabled

OUT3

= I

= 0 µA, buck disabled

OUT3

< 300 mA, 100 µA < I

OUT2

< 300 mA

OUT3

53
74

µA

µA

−3 +3 %

VIN2 = (VOUT2 + 0.5 V) to 5.5 V,
VIN3 = (VOUT3 + 0.5 V) to 5.5 V

REFERENCE VOLTAGE V

0.485 0.500 0.515 V

FB2,3

REGULATION

Line Regulation (∆V

(∆V

OUT2/VOUT2

OUT3/VOUT3

)/∆V
)/∆V

IN2

IN3

I
Load Regulation3 (∆V

DROPOUT VOLTAGE4 V

(∆V

DROPOUT

OUT2/VOUT2

OUT3/VOUT3

)/∆I

OUT2

)/∆I

OUT3

ACTIVE PULL-DOWN R
CURRENT-LIMIT THRESHOLD5 I
OUTPUT NOISE OUT

EN2/EN3 = 0 V 600 Ω

PDLDO

T

LIMIT

10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 123 µV rms

LDO2NOISE

VIN2,

VIN3 = (VOUT2, VOUT3 + 0.5 V)

to 5.5 V

= 1 mA

OUT2, IOUT3

I

= 1 mA to 300 mA 0.002 0.0075 %/mA

OUT2, IOUT3

V

= V
= V
= V
= V

OUT3

OUT3

OUT3

OUT3

= 5.0 V, I
= 3.3 V, I
= 2.5 V, I
= 1.8 V, I

OUT2

V

OUT2

V

OUT2

V

OUT2

= −40°C to +125°C 335 470 mA

J

OUT2

OUT2

OUT2

OUT2

= I

= 300 mA

OUT3

= I

= 300 mA

OUT3

= I

= 300 mA

OUT3

= I

= 300 mA

OUT3

−0.03 +0.03 %/ V

72 mV

86 140 mV

107 mV

180 mV

10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 110 µV rms
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 59 µV rms
OUT

10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 140 µV rms

LDO1NOISE

10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 129 µV rms
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 66
POWER SUPPLY REJECTION RATIO PSRR 1 kHz, V IN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,

= 100 mA

I

OUT

100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,

= 100 mA

I

OUT

1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,

I

= 100 mA

OUT

66 dB

57 dB

60 dB

µV rms

voltages above 1.7 V.

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

Rev. PrE | Page 5 of 32

ADP5041 Preliminary Technical Data

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 5.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CAPACITANCE (BUCK)1 C
OUTPUT CAPACITANCE (BUCK)2 C
INPUT AND OUTPUT CAPACITANCE3 (LDO1, LDO2) C
CAPACITOR ESR R

1

The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and
Z5U capacitors are not recommended for use with the Buck.

2

The minimum output capacitance should be greater than 7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and
Z5U capacitors are not recommended for use with the Buck.

3

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs.

T

MIN1

T

MIN2

TJ = −40°C to +125°C 0.70 µF

MIN34

T

ESR

= −40°C to +125°C 4.7 40 µF

J

= −40°C to +125°C 7 40 µF

J

= −40°C to +125°C 0.001 1 Ω

J

Rev. PrE | Page 6 of 32

Preliminary Technical Data ADP5041

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVIN to AGND −0.3 V to +6 V
VIN1 to AVIN −0.3 V to +0.3 V
PGND to AGDN −0.3 V to +0.3 V

VIN2, VIN3, VOUTx, ENx, MODE, MR , WDI,
nRSTO, FBx, VTHR, SW to AGND

SW to PGND −0.3 V to (VIN1 + 0.3 V)
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
ESD Human Body Model 3000 V
ESD Charged Device Model 1500 V
ESD Machine Model 200 V

Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to (AVIN + 0.3 V)

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W

ESD CAUTION

Rev. PrE | Page 7 of 32

ADP5041 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration—View from Top of the Die

Table 8. Preliminary Pin Function Descriptions

Pin No. Mnemonic Description

1 FB3 LDO2 Feedback Input
2 VOUT3 LDO2 Output Voltage
3 VIN3 LDO2 Input Supply (1.7V to 5.5V)
4 EN3 EN3 = HIGH: Turn LDO2. EN3 = LOW: Turn off LDO2.
5 nRSTO Open-Drain reset output, active low
6 AVIN Housekeeping and Supervisory Input Supply (2.3V to 5.5V)
7 VIN1 BUCK Input Supply (2.3V to 5.5V)
8 SW BUCK switching Node

9 PGND Dedicated Power Ground for BUCK regulator
10 EN1 EN1 = HIGH: Turn BUCK. EN1 = LOW: Turn off BUCK.
11 VOUT1 BUCK Output Sensing Node
12 FB1 BUCK Feedback Input
13 VIN2 LDO1 Input Supply (1.7V to 5.5V)
14 VOUT2 LDO1 Output Voltage
15 FB2 LDO1 Feedback Input
16 EN2 EN2 = HIGH: Turn LDO1. EN2 = LOW: Turn off LDO1.
17 MODE

18 VTHR Reset Threshold Programming
19 WDI Watchdog Refresh input from processor. If WDI is in HiZ, Watchdog is disabled
20

TP AGND Analog Ground (TP = Exposed Pad). Exposed pad must be connected to system Ground Plane

MR

HIGH: The Buck regulator operates in fixed PWM mode. MODE = LOW: The Buck regulator operates in power
saving mode (PSM) at light load and in constant PWM at higher load.

Manual Reset Input, active low

Rev. PrE | Page 8 of 32

Preliminary Technical Data ADP5041

TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.

1

2

3

VOUT1

VOUT2

VOUT3

CH1 2.0V/DIV 1MΩ
CH2 2.0V/DIV 1MΩ
CH3 2.0V/DIV 1MΩ

B

20.0M

W

B

W

B

W

A CH1 1.76V 200µs/DIV

500M

20.0M

50.0MS/s

20.0ns/pt

08811-003

Figure 3. 3-Channel Start-Up Waveforms

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

SYSTEM QUI ESCENT CURRENT (mA)

0.1

0

2.3 2.8 3 .3 3.8 4.3 4.8 5. 3

VOUT1 = 1.8V,

VOUT2 = VO UT = 3.3V

INPUT VOLTAGE (V)

08811-004

Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage,

VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V

08811-006

Figure 6. Buck Startup, VOUT1 = 3.3 V, I

3.34

3.32

3.30

3.28

3.26

OUTPUT VOLTAGE (V)

3.24

3.22

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT CURRENT (A)

OUT2

= 20 mA

–40°C
+25°C
+85°C

08811-007

Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode

SW

4

VOUT1

2

EN

1

IIN

3

CH1 2.0V/DIV 1MΩ
CH2 2.0V/DIV 1MΩ
CH3 100mA/DIV 1MΩ
CH4 5.0V/DIV 1MΩ

B

20.0M

W

B

500M

W

B

20.0M

W

B

500M

W

Figure 5. Buck Startup, VOUT1 = 1.8 V, I

A CH1 2.92V 50µs/DIV

OUT1

50.0MS/s

20.0ns/pt

= 20 mA

08811-005

Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode

Rev. PrE | Page 9 of 32

1.830

1.825

1.820

1.815

1.810

1.805

1.800

1.795

OUTPUT VO LTAGE (V)

1.790

1.785

1.780

1.775

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRENT (A)

–40°C
+25°C
+85°C

08811-008

ADP5041 Preliminary Technical Data

1.795

1.794

1.793

1.792

1.791

1.790

1.789

1.788

OUTPUT VOLTAGE (V)

1.787

1.786

1.785

1.784
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

+85°C

+25°C

–40°C

08811-009

OUTPUT CURRENT (A)

Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode

1.797

1.796

1.795

1.794

1.793

OUTPUT VO LTAGE (V )

1.792

1.791

1.790

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

VIN = 5.5V

VIN = 4.5V

VIN = 3.6V

08811-010

OUTPUT CURRENT (A)

Figure 10. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.0001 0.001 0.01 0.1 1

OUTPUT CURRENT (A)

3.6V

4.5V

5.5V

08811-011

Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 3.3 V, Auto Mode

100

3.6V

4.5V

90

5.5V

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

OUTPUT CURRENT (A)

Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 3.3 V, PWM Mode

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

2.4V

3.6V

10

4.5V

5.5V

0

0.0001 0. 001 0. 01 0. 1 1

OUTPUT CURRENT (A)

Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 1.8 V, Auto Mode

100

2.4V

3.6V

90

4.5V

5.5V

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

I

(A)

OUT

Figure 14. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 1.8 V, PWM Mode

08811-012

08811-013

08811-014

Rev. PrE | Page 10 of 32

Preliminary Technical Data ADP5041

C

C

100

90

80

70

60

Y (%)

50

40

EFFICIEN

30

20

10

0

0.001 0.01 0.1 1

–40ºC
+25ºC
+85ºC

OUTPUT CURRENT (A)

Figure 15. Buck Efficiency vs. Load Current, Across Temperature,

VOUT1 = 1.8 V, PWM Mode

100

–40°C
+25°C

90

+85°C

80

70

60

50

40

EFFI CIENCY (%)

30

20

10

0

0.0001 0.001 0. 01 0.1 1

OUTPUT CURRENT (A)

Figure 16. Buck Efficiency vs. Load Current, Across Temperature,

VOUT1 = 3.3 V, Auto Mode

1.7

1.6

1.5

1.4

1.3

1.2

OUTPUT CURRENT (A)

1.1

08811-015

1.0

2.63.64.65.6

INPUT VOLTAGE (V)

08811-018

Figure 18. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V

3.10

3.05

3.00

2.95

FREQUENCY ( MHz)

2.90

08811-016

2.85

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

–40°C

+25°C

+85°C

08811-019

OUTPUT CURRENT (A)

Figure 19. Buck Switching Frequency vs. Output Current, Across Temperature,

VOUT1 = 1.8 V, PWM Mode

100

–40°C
+25°C

90

+85°C

80

70

60

Y (%)

50

40

EFFICIEN

30

20

10

0

0.0001 0. 001 0.01 0.1 1

OUTPUT CURRENT (A)

Figure 17. Buck Efficiency vs. Load Current, Across Temperature,

1

2

3

08811-017

Figure 20. Typical Waveforms, VOUT1 = 3.3 V, I

VOUT

I

SW

SW

CH1 20.0mV/ DIV
CH2 200mA/DIV 1M Ω
CH3 2.0V/DIV 1MΩ

B

W

B

W

B

W

A CH1 2.4mV 5.0µs/DIV

20.0M

20.0M

20.0M

20.0MS/s

50.0ns/pt

= 30 mA, Auto Mode

OUT1

08811-020

VOUT1 = 1.8 V, Auto Mode

Rev. PrE | Page 11 of 32

ADP5041 Preliminary Technical Data

VOUT

2

VIN

I

SW

3

SW

1

CH1 2.0V/DIV 1MΩ
CH2 50.0mV/DIV
CH3 500mA/DIV

B

B

B

A CH1 1.56mV 5.0µs/DIV

20.0M

W

20.0M

W

20.0M

W

200MS/s

5.0ns/p t

Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA,

Auto Mode

VOUT

2

08811-021

VOUT

2

SW

1

3

CH1 3V/DIV
CH2 50mV/DIV
CH3 900mV/DI V 1MΩ

B

W

B

W

B

W

A CH3 4.79V 100µs/DIV

20.0M

20.0M

20.0M

10.0MS/s
100ns/pt

08811-024

Figure 24. Buck Response to Line Transient, Input Voltage from 4.5 V

to 5.0 V, VOUT1 = 3.3 V, PWM Mode

I

SW

3

SW

1

CH1 2.0V/DIV 1MΩ
CH2 50.0mV/DIV
CH3 500mA/DIV

B

B

B

A CH1 1.56mV 500ns/DIV

20.0M

W

20.0M

W

20.0M

W

200MS/s

5.0ns/p t

Figure 22. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA,

PWM Mode

VOUT

1

I

SW

2

SW

3

CH1 20.0mV/DIV
CH2 200mA/DIV 1MΩ
CH3 2.0V/DIV 1MΩ

B

B

B

A CH1 2.4mV 200ns/DIV

20.0M

W

20.0M

W

20.0M

W

500MS/s

2.0ns/p t

Figure 23. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA,

PWM Mode

VIN

VOUT

2

SW

3

4

08811-022

CH2 50mV/DIV
CH3 1V/DIV 1MΩ
CH4 2V/DIV 1MΩ

Figure 25. Buck Response to Line Transient, V

B

B

B

A CH3 4.96mV 100 µs/DIV

20.0M

W

20.0M

W

20.0M

W

20MS/s
100ns/pt

= 4.5 V to 5.0 V,

IN

08811-025

VOUT1 = 1.8 V, PWM Mode

SW

1

VOUT

2

IOUT

3

08811-023

CH1 4V/DIV
CH2 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ

B

W

B

W

B

W

A CH3 44mA 200 µs/DIV

20.0M

20.0M

20.0M

10MS/s
100ns/pt

08811-026

Figure 26. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,

VOUT1 = 3.3 V, Auto Mode

Rev. PrE | Page 12 of 32

Preliminary Technical Data ADP5041

SW

1

IIN

3

VOUT

V

2

OUT

VOUT

1

LOAD

3

CH1 4V/DIV
CH2 50mV/DIV
CH3 50mA/DIV 1MΩ

B

W

B

W

B

W

A CH3 28mA 200µs/DIV

20.0M

20.0M

20.0M

5MS/s
200ns/pt

08811-027

Figure 27. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,

VOUT1 = 1.8 V, Auto Mode

SW

1

VOUT

2

LOAD

3

CH1 4V/DIV
CH2 50mV/DIV
CH3 50mA/DIV 1MΩ

B

B

B

W

W

W

20.0M

20.0M

20.0M

A CH3 86mA

200µs/DIV
10MS/s
100ns/pt

08811-028

Figure 28. Buck Response to Load Transient, IOUT1 from 20 mA

to 140 mA, VOUT1 = 3.3 V, Auto Mode

EN

2

CH1 1V/DIV 1MΩ
CH2 3V/DIV 1MΩ
CH3 50mA/DIV 1MΩ

B

B

B

W

W

W

500M
500M

20.0M

A CH2 1.14V

Figure 30. LDO1 Startup, VOUT2=1.5 V, IOUT2 = 5 mA

IIN

3

VOUT

1

EN

2

CH1 1V/DIV 1MΩ
CH2 3V/DIV 1MΩ
CH3 50mA/DI V 1MΩ

B

B

B

W

W

W

500M
500M

20.0M

A CH2 1.14V

Figure 31. LDO2 Startup, VOUT3=3.3 V, IOUT3 = 5 mA

50µs/DIV
2MS/s
500ns/pt

100µs/DIV
1MS/s

1.0µs/p t

08811-030

08811-031

SW

2

VOUT1

3

LOAD

4

CH2 4V/DIV 1MΩ
CH3 50mV/DI V 1MΩ
CH4 50mA/DIV 1MΩ

B

B

B

W

W

W

20.0M

20.0M

20.0M

A CH3 145mA

200µs/DI V
50MS/s
20ns/pt

Figure 29. Buck Response to Load Transient, IOUT1 from 20 mA

to 180 mA, VOUT1 = 1.8 V, PWM Mode

08811-029

Rev. PrE | Page 13 of 32

1.510

1.508

1.506

1.504

OUTPUT VOLTAGE (V)

1.502

1.500

3.3V

4.5V

5.0V

5.5V

0.0001 0. 001 0. 01 0.1

OUTPUT CURRENT (A)

Figure 32. LDO1 Load Regulation Across Input Voltage, VOUT2 = 1.5 V

08811-032

ADP5041 Preliminary Technical Data

1.53
+85°C
+25°C
–40°C

1.52

1.51

1.5

1.49

OUTPUT VOLTAGE (V)

1.48

1.47

0.0001 0.001 0.01 0 .1

OUTPUT CURRENT (A)

08811-033

Figure 33. LDO1 Load Regulation Across Temperature, VIN2 = 3.3 V, VOUT2 = 1.5 V

OUTPUT VOLTAGE (V)

1.520

1.515

1.510

1.505

1.500

1.495

1.490

1.485

1.480

100µA
1mA
10mA
100mA
150mA

3.6 4.5 5.0 5.5

INPUT VOLTAGE (V)

08811-034

Figure 34. LDO1 Line Regulation Across Output Load, VOUT2 = 1.5 V

3.35

3.6V

4.5V

3.34

5.0V

5.5V

3.33

3.32

3.31

3.30

3.29

3.28

OUTPUT VOLTAGE (V)

3.27

3.26

3.25

0.0001 0.001 0. 01 0.1

OUTPUT CURRENT (A)

08811-035

Figure 35. LDO2 Load Regulation Across Input Voltage, VOUT3 = 3.3 V

Figure 36. LDO2 Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 3.3 V

3.35
+85°C
+25°C

3.34
–40°C

3.33

3.32

3.31

3.30

3.29

3.28

OUTPUT VOLTAGE (V)

3.27

3.26

3.25

0.0001 0.001 0. 01 0.1

OUTPUT CURRENT (A)

OUTPUT VOLTAGE (V)

3.325

3.320

3.315

3.310

3.305

3.300

3.295

3.290

3.285

3.280

100µA
1mA
10mA
100mA
150mA

3.6 4.5 5.0 5.5

INPUT VOLTAGE (V)

Figure 37. LDO2 Line Regulation Across Output Load, VOUT3 = 3.3 V

250

200

150

100

CURRENT (µA)

50

0

0 0.050.100.15

LOAD (A)

Figure 38. LDO2 Ground Current vs. Output Load, VOUT3 = 2.8 V

08811-038

08811-036

08811-037

Rev. PrE | Page 14 of 32

Preliminary Technical Data ADP5041

0.50

1µA
100µA

0.45

1mA
10mA

0.40

100mA
150mA

0.35

0.30

0.25

0.20

0.15

GROUND CURRENT (mA)

0.10

0.05

0

2.32.83.33.84.34.85.35.8

INPUT VOLTAGE (V)

Figure 39. LDO2 Ground Current vs. Input Voltage, Across Output Load,

VOUT3 = 2.8 V

08811-039

Figure 42. LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V,

VIN

VOUT

21

22

CH1 10.0mV/DIV

CH2 800mV/ DIV

B

W

B

1MΩ

W

VOUT3 = 3.3 V

20.0M

20.0M

A CH2 5.33V

08811-042

IOUT

3

VOUT

1

CH1 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ

B

W

B

W

500M

20.0M

A CH3 28mA

200µs/DI V
500kS/s

2.0µs/p t

Figure 40. LDO2 Response to Load Transient, IOUT3 from 1 mA

to 80 mA, VOUT3 = 3.3 V

IOUT

3

VOUT

1

CH1 50mV/DI V 1MΩ
CH3 50mA/DIV 1MΩ

B

B

W

W

500M

20.0M

A CH3 50mA

200µs/DI V
500kS/s

2.0µs/pt

Figure 41. LDO1 Response to Load Transient, IOUT2 from 1 mA

to 80 mA, VOUT2 = 1.5 V

VIN

VOUT

21

2

B

CH1 10.0mV/Div

08811-040

CH2 800mV/ Div

1MΩ

20.0M

W

B

20.0M

W

A CH2 5.33V

08811-043

Figure 43. LDO1 Line Transient VIN2 = 4.5 V to 5.5 V,VOUT2 = 1.5 V

3.0

2.5

2.0

1.5

1.0

OUTPUT VOLTAGE (V)

0.5

0

00.10.20.3

08811-041

0.4 0.5 0.6 0. 7 0. 8

LOAD CURRENT (A)

5.5V

4.5V

3.6V

08811-056

Figure 44. LDO1, LDO2 Output Current Capability vs. Input Voltage

Rev. PrE | Page 15 of 32

ADP5041 Preliminary Technical Data

√

√

–

100

10

VOUT3 = 3. 3V, VIN3 = 3.6V, I
VOUT3 = 1. 5V, VIN3 = 1.8V, I
VOUT3 = 2. 8V, VIN3 = 3.1V, I

LOAD
LOAD
LOAD

= 300mA
= 300mA
= 300mA

100

RMS NOISE (µV)

CH2; V
CH2; V
CH2; V
CH2; V

10

0.0001 0.001 0.01 0.1 1 10 100 1k

CH2; V

LOAD (mA)

=3.3V;VIN=5V

OUT

= 3.3V; VIN = 3. 6V

OUT

= 2.8V; VIN = 3.1V

OUT

=1.5V;VIN=5V

OUT

= 1.5V; VIN = 1. 8V

OUT

08811-044

Figure 45. LDO1 Output Noise vs. Load Current, Across Input

and Output Voltage

100

RMS NOI SE (µV)

CH3; VOUT = 3.3V; VIN = 5V
CH3; VOUT = 3.3V; VIN = 3.6V
CH3; VOUT = 2.8V; VIN = 3.1V
CH3; VOUT = 1.5V; VIN = 5V

10

0.0001 0.001 0.01 0. 1 1 10 100 1k

CH3; VOUT = 1.5V; VIN = 1.8V

LOAD (mA)

08811-045

Figure 46. LDO2 Output Noise vs. Load Current, Across Input

Hz)

1

NOISE (µV/

0.1

0.01
1 10 100 1k

FREQUENCY (Hz)

10k 100k 1M

08811-055

Figure 48. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT+0.3V

100

10

Hz)

1.0

NOISE (µV/

0.1

VOUT3 = 1.5V, VIN3 = 1.8V, I
VOUT2 = 2.8V, VIN2 = 3.1V, I
VOUT3 = 2.8V, VIN3 = 3.1V, I

0.01
10 100 1k 10k 100k 1M 10M

VOUT2 = 3.3V, VIN2 = 3.6V, I
VOUT3 = 3.3V, VIN3 = 3.6V, I
VOUT2 = 1.5V, VIN2 = 1.8V, I

=300mA

LOAD

=300mA

LOAD

=300mA

LOAD

FREQUENCY (Hz)

LOAD

LOAD

LOAD

=300mA
=300mA
=300mA

08811-048

Figure 49. LDO1 vs. LDO2 Noise spectrum

and Output Voltage

100

10

1.0

NOISE (µV/√Hz)

0.1

0.01
10 100 1k 10k 10 0k 1M 10M

Figure 47. LDO1 Noise Spectrum Across Output Voltage,

VOUT2 = 3.3V, VIN2 = 3.6V, I
VOUT2 = 1.5V, VIN2 = 1.8V, I
VOUT2 = 2.8V, VIN2 = 3.1V, I

FREQUENCY (Hz)

VIN = VOUT + 0.3 V

LOAD

LOAD

LOAD

=300mA
=300mA
=300mA

10

1mA
10mA

–20

100mA
200mA

–30

300mA

–40

–50

–60

PSRR (dB)

–70

–80

–90

08811-046

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

08811-049

Figure 50. LDO2 PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V

Rev. PrE | Page 16 of 32

Preliminary Technical Data ADP5041

–

–

–

–

–

10

1mA
10mA

–20

100mA
200mA

–30

300mA

–40

–50

–60

PSRR (dB)

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 51. LDO2 PSRR Across Output Load, VIN3 = 3.1 V,

VOUT3 = 2.8 V

10

1mA
10mA

–20

100mA
200mA

–30

–40

–50

–60

PSRR (dB)

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 52. LDO2 PSRR Across Output Load, VIN3 = 5 V,

VOUT3 = 3.3 V

08811-050

08811-051

10

1mA
10mA

–20

100mA
200mA

–30

300mA

–40

–50

–60

PSRR (dB)

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 54. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V

10

1mA
10mA

–20

100mA
200mA

–30

300mA

–40

–50

–60

PSRR (dB)

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 55. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V

08811-053

08811-054

10

1mA
10mA

–20

100mA
200mA

–30

300mA

–40

–50

–60

PSRR (dB)

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

08811-052

Figure 53. LDO2 PSRR Across Output Load, VIN3 = 3.6 V,

VOUT3 = 3.3 V

Rev. PrE | Page 17 of 32

ADP5041 Preliminary Technical Data

THEORY OF OPERATION

Figure 56. Functional Block Diagram

POWER MANAGEMENT UNIT

The ADP5041 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc regulator, two low
dropout linear regulators (LDOs), and a supervisory circuit, with
watchdog, for processor control. The high switching frequency and
tiny 20-pin LFCSP package allow for a small power management
solution.

The regulators are activated by a logic level high applied to the
respective EN pin. The EN1 controls the buck regulator, the
EN2 controls LDO1, and the EN3 controls LDO2. Other
features available in this device are the mode pin to control the
buck switching operation and a push-button reset input.

Regulator output voltages and reset threshold are set through
external resistor dividers.

When a regulator is turned on, the output voltage ramp is
controlled through a soft start circuit to avoid a large inrush
current due to the discharged output capacitors.

Rev. PrE | Page 18 of 32

The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at a logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent
current losses.

Preliminary Technical Data ADP5041

Thermal Protection

In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off the buck and the LDOs.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included in the thermal shutdown circuit so
that when thermal shutdown occurs, the buck and the LDOs do
not return to normal operation until the on-chip temperature
drops below 130°C. When coming out of thermal shutdown, all
regulators start with soft start control.

Undervoltage Lockout

To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the ADP5041. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.

Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device hits the turn-off threshold when the input
supply drops to 3.65 V typical.

Enable/Shutdown

The ADP5041 has individual control pins for each regulator.
A logic level high applied to the ENx pin activates a regulator,
whereas a logic level low turns off a regulator.

Active Pull-Down

ADP5041 can be ordered with the active pull down option
enabled. The pull-down resistors are connected between each
regulator output and AGND. The pull-downs are enabled,
when the regulators are turned off. The typical value of the
pull-down resistor is 600  for the LDOs and 85  for the buck.

BUCK SECTION

The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.

The Buck output voltage is set though external resistors divider,
shown in Figure 57. VOUT1 must be connected to the output
capacitor. VFB1 is internally set to 0.5V. The output voltage can
be set from 0.8 V to 3.8V.

⎛
⎜

VV

FBOUT

11

⎜
⎝

Figure 57 Buck External Output Voltage Setting

Control Scheme

The buck operates with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency,
but operation shifts to a power save mode (PSM) control
scheme at light loads to lower the regulation power losses.
When operating in fixed frequency PWM mode, the duty cycle
of the integrated switches is adjusted and regulates the output
voltage. When operating in PSM at light loads, the output
voltage is controlled in a hysteretic manner, with higher output
voltage ripple. During part of this time, the converter is able to
stop switching and enters an idle mode, which improves
conversion efficiency.

PWM Mode

In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.

Power Save Mode (PSM)

The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level that is approximately 1.5% above
the PWM regulation level, PWM operation is turned off. At this
point, both power switches are off, and the buck enters an idle
mode. The output capacitor discharges until the output voltage
falls to the PWM regulation voltage, at which point the device
drives the inductor to make the output voltage rise again to the
upper threshold. This process is repeated while the load current
is below the PSM current threshold.

The ADP5041 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE

⎞

R

1

⎟

+= 1

⎟

R

2

⎠

Rev. PrE | Page 19 of 32

ADP5041 Preliminary Technical Data

pin forces the buck to operate in PWM mode. A Logic level low
sets the buck to operate in auto PSM/PWM.

PSM Current Threshold

The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con­trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to, and exit from, the PSM
mode. The PSM current threshold is optimized for excellent
efficiency over all load currents.

Short-Circuit Protection

The buck includes frequency foldback to prevent current
runaway on a hard short at the output. When the voltage at the
feedback pin falls below half the internal reference voltage,
indicating the possibility of a hard short at the output, the
switching frequency is reduced to half the internal oscillator
frequency. The reduction in the switching frequency allows
more time for the inductor to discharge, preventing a runaway
of output current.

Soft Start

The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.

Current Limit

The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.

100% Duty Operation

With a drop in input voltage, or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.

LDO SECTION

The ADP5041 contains two LDOs with low quiescent current
that provide output currents up to 300 mA. The low 15 A
typical quiescent current at no load makes the LDO ideal for
battery-operated portable equipment.

The LDOs operate with an input voltage range of 1.7 V to

5.5 V. The wide operating range makes these LDOs suitable for
cascade configurations where the LDO supply voltage is
provided from the buck regulator.

Rev. PrE | Page 20 of 32

Each LDO output voltage is set though external resistor dividers
as shown in Figure 58. VFB2 and VFB3 are internally set to

0.5V. The output voltage can be set from 0.8 V to 5.2 V.

Ra
Rb

+= 1

⎞
⎟

⎠

⎛

VV

⎜

3,23,2

FBOUT

⎝

Figure 58. LDOs External Output Voltage Setting

The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with small ceramic 1 µF input and 2.2 µF output capacitors.

LDO2 is optimized to supply analog circuits because it offers
better noise performance compared to LDO1. LDO1 should be
used in applications where noise performance is not critical.

SUPERVISORY SECTION

The ADP5041 provides microprocessor supply voltage super­vision by controlling the reset input of the microprocessor.
Code execution errors are avoided during power-up, power­down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be monitored
and corrected with a watchdog timer.

Reset Output

The ADP5041 has an active-low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail that is no higher than 6V. The
resistor should comply with the logic low and logic high voltage
level requirements of the microprocessor while supplying input
current and leakage paths on the nRSTO pin. A 10 kΩ resistor is
adequate in most situations.

The reset output is asserted when the monitored rail is below
the reset threshold (V
the watchdog timeout period (t
duration of the reset active timeout period (t
monitored rail rises above the reset threshold or after the
watchdog timer times out. Figure 59 illustrates the behavior of
the reset output, nRSTO, and it assumes that VOUT2 is selected
as the rail to be monitored and supplies the external pull-up
connected to the nRSTO output.

) or when WDI is not serviced within

TH

). Reset remains asserted for the

WD1

) after the

RP

Preliminary Technical Data ADP5041

MR input,

Figure 59. Reset Timing Diagram

The ADP5041 has dedicated sensing input pin VTHR to
monitor a supply rail.

The reset threshold voltage at VTHR input is typically 0.5 V.
To monitor a voltage greater than 0.5 V, connect a resistor
divider network to the device as depicted in Figure 60, where,





0.5 

1  2

2



integrated on chip. Noise immunity is provided on the
and fast, negative-going transients of up to 100 ns (typical) are

ignored. A 0.1 µF capacitor between

MR

and ground provides

additional noise immunity.

Watchdog Input

The ADP5041 features a watchdog timer that monitors
microprocessor activity. The watchdog timer circuit is cleared
with every low-to-high or high-to-low logic transition on the
watchdog input pin (WDI), which detects pulses as short as 80 ns.
If the timer counts through the preset watchdog timeout period
(t

), an output reset is asserted. The microprocessor is

WD1

required to toggle the WDI pin to avoid being reset. Failure of
the microprocessor to toggle WDI within the timeout period,
therefore, indicates a code execution error, and the reset pulse
generated restarts the microprocessor in a known state.

As well as logic transitions on WDI, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the monitored rail. When reset is asserted, the watchdog timer
is cleared and does not begin counting again until reset
deasserts. Watchdog timer can be disabled by leaving WDI
floating or by three-stating the WDI driver.

Figure 60. External Reset Threshold Programming.

Do not allow VTHR input to float or to be grounded. Connect
it to a supply voltage greater than its specified threshold voltage.
A small capacitor can be added on VTHR to improve the noise
rejection and to prevent false reset generation.

ADP5041 can be ordered with 2.25V or 3.6V UVLO thresholds.
When monitoring the input supply voltage, if the selected reset
threshold is below the UVLO level the reset output, nRSTO, is
asserted low as soon as the input voltage falls below the UVLO
threshold. Below the UVLO threshold, the reset output is
maintained low down to ~1V VIN. This is to ensure that the
reset output is not released when there is sufficient voltage on
the rail supplying a processor to restart the processor
operations.

Manual Reset Input

The ADP5041 features a manual reset input ( MR ) which, when

driven low, asserts the reset output. When

MR transitions from

low to high, reset remains asserted for the duration of the reset

active timeout period before deasserting. The

MR input has a

52 kΩ, internal pull-up, connected to AVIN, so that the input is
always high when unconnected. An external push-button

switch can be connected between

MR and ground so that the

user can generate a reset. Debounce circuitry for this purpose is

Rev. PrE | Page 21 of 32

ADP5041 can be ordered with two possible Watchdog timer
values as indicated in Table 18.

Figure 61. Watchdog Timing Diagram

ADP5041 Preliminary Technical Data

Figure 62. ADP5041 State Flow

Rev. PrE | Page 22 of 32

Preliminary Technical Data ADP5041

APPLICATIONS INFORMATION

BUCK EXTERNAL COMPONENT SELECTION

Trade-offs between performance parameters such as efficiency
and transient response are made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.

Feedback Resistors

Referring to Figure 57 the total combined resistance for R1 and
R2 is not to exceed 400 k.

Inductor

The high switching frequency of the ADP5041 buck allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 H and 3.0 H. Suggested
inductors are shown in Table 9.

The peak-to-peak inductor current ripple is calculated using
the following equation:

VVV

−×

I

RIPPLE

OUT

LfV

××

2

)(

Dimensions
(mm)

I

SAT

(mA)

DCR
(mΩ)

I

RIPPLE

OUT

=

IN

IN

SW

where:

f

is the switching frequency.

SW

L is the inductor value.

The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:

II +=

PEAK

)(

MAXLOAD

Table 9. Suggested 1.0 μH Inductors

Vendor Model

Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85
Murata LQM18FN1R0M00B 3.2 × 2.5 × 1.5 230 0 54
Tayo Yuden CBC322ST1R0MR 3.2 × 2.5 × 2.5 2000 71
Coilcraf t XFL4020-102ME 4.0 × 4.0 × 2.1 5400 11
Coilcraf t XPL2010-102ML 1.9 × 2.0 × 1.0 1800 89
Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85

Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the buck is a high switching frequency dc-to-dc converter,
shielded ferrite core material is recommended for its low core
losses and low EMI.

Output Capacitor

Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing the
capacitor value, it is also important to account for the loss of
capacitance due to output voltage dc bias.

Ceramic capacitors are manufactured with a variety of dielec­trics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are highly
recommended for best performance. Y5V and Z5U dielectrics
are not recommended for use with any dc-to-dc converter
because of their poor temperature and dc bias characteristics.

The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu­lated using the following equation:

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL)

OUT

where:

C

is the effective capacitance at the operating voltage.

EFF

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C

is 9.24 F at 1.8 V, as shown in Figure 63.

OUT

Substituting these values in the equation yields

C

= 9.24 F × (1 − 0.15) × (1 − 0.1) = 7.0747 F

EFF

To guarantee the performance of the buck, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.

12

10

8

6

4

CAPACITANCE (µF)

2

0

0123456

DC BIAS VO LTAGE (V)

Figure 63. Typical Capacitor Performance

08811-062

The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:

=V ≈

RIPPLE

I

RIPPLE

C×f×8

OUTSW

V

IN

2

()

SW

C×L×f×π2

OUT

Rev. PrE | Page 23 of 32

ADP5041 Preliminary Technical Data

Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:

V

RIPPLE

ESR ≤

COUT

I

RIPPLE

The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.

Table 10. Suggested 10 μF Capacitors

Case

Voltage

Vendor Type Model

Size

Rating (V)

Murata X5R GRM188R60J106 0603 6.3
Tai yo

X5R JMK107BJ106MA-T 0603 6.3

Yud en
TDK X5R C1608JB0J106K 0603 6.3
Panasonic X5R ECJ1VB0J106M 0603 6.3

The buck regulator requires 10 µF output capacitors to guaran­tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 64).

C3
1µF

C1

10µF

C2
1µF

AVIN

VIN1

VIN2

VIN3

ADP5041

MICRO PMU

SW

VOUT1

FB1

VOUT2

FB2

nRSTO

WDI

MODE

ENx

VOUT3

FB3

L1

1µH

R1

R2

PGND

R3

C6

2.2µF

R4

3

R5

R6

C5

4.7µF

R7

100 kΩ

C7

2.2µF

PROCESSOR

VCORE

VDDIO

RESET

GPIO1

GPIO2

GPIO[x:y]

VANALOG

ANALOG

SUB-SYSTEM

R

FLT

30Ω

V

IN

2.3V T O 5.5V

Figure 64. Processor System Power Management with PSM/PWM Control

Input Capacitor

Higher value input capacitor helps to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:

The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Table 11.

Table 11. Suggested 4.7 μF Capacitors

Case

Vendor Type Model

Size

Voltage
Rating (V)

Murata X5R GRM188R60J475ME19D 0603 6.3
Taiyo Yuden X5R JMK107BJ475 0603 6.3
Panasonic X5R ECJ-0EB0J475M 0402 6.3

LDO EXTERNAL COMPONENT SELECTION

Feedback Resistors

Referring to Figure 58 the maximum value of Rb is not to
exceed 200 k.

Output Capacitor

The ADP5041 LDOs are designed for operation with small,
space-saving ceramic capacitors, but they function with most
commonly used capacitors as long as care is taken with the ESR
value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 µF capacitance with an
ESR of 1 Ω or less is recommended to ensure stability of the
LDO. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the LDO to large
changes in load current.

When operating at output currents higher than 200 mA a
minimum of 2.2 µF capacitance with an ESR of 1 Ω or less is
recommended to ensure stability of the LDO.

Table 12 Suggested 2.2 μF Capacitors

Voltage

Case

Vendor Type Model

Size

Murata X5R GRM188B31A225K 0402 10.0
TDK X5R C1608JB0J225KT 0402 6.3
Panasonic X5R ECJ1VB0J225K 0402 6.3
Tai yo

X5R JMK107BJ225KK-T 0402 6.3

Yud en

Input Bypass Capacitor

Connecting 1 µF capacitors from VIN2 and VIN3 to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance is encountered. If greater than 1 µF of output
capacitance is required, increase the input capacitor to match it.

Rating
(V)

VVV

)(

−

IN

CIN

II

≥

MAXLOAD

OUT

)(

OUT

V

IN

To minimize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR capacitor is recommended.

Rev. PrE | Page 24 of 32

Preliminary Technical Data ADP5041

Table 13 Suggested 1.0 μF Capacitors

Voltage

Vendor Type Model

Case
Size

Rating
(V)

Murata X5R GRM155B30J105K 0402 6.3
TDK X5R C1005JB0J105KT 0402 6.3
Panasonic X5R ECJ0EB0J105K 0402 6.3
Tai yo

X5R LMK105BJ105MV-F 0402 10.0

Yud en

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP5041 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe­rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.

Figure 65

depicts the capacitance vs. voltage bias characteristic

of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera­ture range and is not a function of package or voltage rating.

1.2

1.0

0.8

0.6

0.4

CAPACITANCE (µF)

0.2

0

01 23456

Figure 65. Capacitance vs. Voltage Characteristic

DC BIAS VOLTAGE (V)

08811-064

Use the following equation to determine the worst-case capa­citance accounting for capacitor variation over temperature,
component tolerance, and voltage.

= C

C

EFF

× (1 − TEMPCO) × (1 − TOL)

BIAS

where:
C

is the effective capacitance at the operating voltage.

BIAS

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C

is 0.94 F at 1.8 V as shown in Figure 65.

BIAS

Substituting these values into the following equation yields:

C

= 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F

EFF

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP5041, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.

SUPERVISORY SECTION

Threshold Setting Resistors

Referring to Figure 60 the maximum value of R2 is not to
exceed 200 k.

Watchdog Input Current

To minimize watchdog input current (and minimize overall
power consumption), leave WDI low for the majority of the
watchdog timeout period. When driven high, WDI can draw
as much as 25 µA. Pulsing WDI low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI is unconnected, a window comparator disconnects the
watchdog timer from the reset output circuitry so that reset is
not asserted when the watchdog timer times out.

Negative-Going Transients at the Monitored Rail

To avoid unnecessary resets caused by fast power supply transients,
the ADP5041 is equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 66 plots the monitored rail
voltage, V
The curve shows combinations of transient magnitude and
duration for which a reset is not generated. In this example,
with the 3.00 V threshold, a transient that goes 100 mV below
the threshold and lasts 8 µs typically does not cause a reset, but
if the transient is any larger in magnitude or duration, a reset is
generated. In this example the reset threshold programming
resistor values were R2=200 kΩ, R1= 1 MΩ (see Figure 60).

, transient duration vs. the transient magnitude.

TH

Rev. PrE | Page 25 of 32

ADP5041 Preliminary Technical Data

N

P

1000

900

800

700

600

500

400

300

TRANSIENT DURAT ION (µs)

200

100

0

0.1 1 10 100

COMPARATOR OVERDRIVE (% OF V

Figure 66. Maximum V

Threshold Overdrive

Transient Duration vs. Reset

TH

)

TH

08811-065

Watchdog Software Considerations

In implementing the watchdog strobe code of the
microprocessor, quickly switching WDI low to high and then
high to low (minimizing WDI high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.

A low-to-high-to-low WDI pulse within a given subroutine
prevents the watchdog from timing out. However, if the sub­routine becomes stuck in an infinite loop, the watchdog cannot
detect this because the subroutine continues to toggle WDI.

A more effective coding scheme for detecting this error involves
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI is set high. The subroutine sets WDI
low when it is called. If the program executes without error, WDI
is toggled high and low with every loop of the program. If the
subroutine enters an infinite loop, WDI is kept low, the watchdog
times out, and the microprocessor is reset (see Figure 67).

START

SET WDI

HIGH

PROGRAM

CODE

SUBROUTINE

SET WDI

LOW

RETURN

Figure 67. Watchdog Flow Diagram

RESET

INFINITE LOOP:

WATCHDOG

TIMES OUT

08811-066

Rev. PrE | Page 26 of 32

POWER DISSIPATION/THERMAL CONSIDERATIONS

The ADP5041 is a highly efficient micropower management
unit (microPMU), and in most cases the power dissipated in the
device is not a concern. However, if the device operates at high
ambient temperatures and with maximum loading conditions,
the junction temperature can reach the maximum allowable
operating limit (125°C).

When the junction temperature exceeds 150°C, the ADP5041
turns off all the regulators, allowing the device to cool down.
Once the die temperature falls below 135°C, the ADP5041
resumes normal operation.

This section provides guidelines to calculate the power dissi­pated in the device and to make sure the ADP5041 operates
below the maximum allowable junction temperature.

The efficiency for each regulator on the ADP5041 is given by

OUT

P

I

where:
η is efficiency.

P

is the input power.

IN

is the output power.

P

OUT

Power loss is given by

P

= PIN − P

LOSS

or

P

= P

LOSS

OUT

The power dissipation of the supervisory function is small and
can be neglected.

Power dissipation can be calculated in several ways. The most
intuitive and practical is to measure the power dissipated at
the input and all the outputs. The measurements should be
performed at the worst-case conditions (voltages, currents,
and temperature). The difference between input and output
power is dissipated in the device and the inductor. Use
Equation 4 to derive the power lost in the inductor, and from
this use Equation 3 to calculate the power dissipation in the
ADP5041 buck regulator.

A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, while the
power lost on a LDO is calculated using Equation 12. Once the
buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor, use Equation 4
to derive the power lost in the inductor, and thus calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the LDOs to find the
total dissipated power.

Note that the buck efficiency curves are typical values and may
not be provided for all possible combinations of V
I

. To account for these variations, it is necessary to include a

OUT

safety margin when calculating the power dissipated in the
buck.

(1)

100%×=η

(2a)

OUT

(1-η)/η (2b)

, V

, and

IN

OUT

Preliminary Technical Data ADP5041

A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDOs provided
by Equation 12.

Buck Regulator Power Dissipation

The power loss of the buck regulator is approximated by

= P

P

LOSS

+ PL (3)

DBUCK

where:

P

is the power dissipation on the ADP5041 buck regulator.

DBUCK

P

is the inductor power losses.

L

The inductor losses are external to the device and they don’t
have any effect on the die temperature.

The inductor losses are estimated (without core losses) by

L

2

RMSOUT1

)(

(4)

DCRIP ×≅

L

Where:

DCR

is the inductor series resistance.

L

I

is the RMS load current of the buck regulator.

OUT1(RMS)

/12+1)(rII

×=

OUT1

RMSOUT1

(5)

where r is the normalized inductor ripple current.

r ≈ V

× (1-D)/(I

OUT1

× L × fSW) (6)

OUT1

where:

L is inductance.

f

is switching frequency.

SW

D is duty cycle.

D = V

OUT1/VIN1

The ADP5041 buck regulator power dissipation, P

(7)

,

DBUCK

includes the power switch conductive losses, the switch losses,
and the transition losses of each channel. There are other
sources of loss, but these are generally less significant at high
output load currents, where the thermal limit of the application
will be. Equation 8 shows the calculation made to estimate the
power dissipation in the buck regulator.

P

DBUCK

= P

COND

+ PSW + P

(8)

TRAN

The power switch conductive losses are due to the output current,
I

, flowing through the PMOSFET and the NMOSFET power

OUT1

switches that have internal resistance, R

DSON-P

and R

DSON-N

. The

amount of conductive power loss is found by:

P

COND

= [R

DSON-P

× D + R

× (1 − D)] × I

DSON-N

2

(9)

OUT1

For the ADP5041, at 125°C junction temperature and VIN1 =

3.6 V, R

is approximately 0.2 , and R

DSON-P

DSON-N

is

approximately 0.16 . At VIN1 = 2.3 V, these values change to

0.31  and 0.21  respectively, and at VIN1 = 5.5 V, the values
are 0.16  and 0.14 , respectively.

Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:

P

SW

= (C

GATE-P

+ C

GATE-N

) × V

2

× fSW (10)

IN1

where:

C

is the PMOSFET gate capacitance.

GATE-P

is the NMOSFET gate capacitance.

C

GATE-N

For the ADP5041, the total of (C

GATE-P

+ C

GATE-N

) is

approximately 150 pF.

The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near V

(and from V

OUT1

OUT1

to

ground). The amount of transition loss is calculated by:

P

= V

× I

× (t

+ t

) × fSW (11)

FALL

where t

TRAN

RISE

and t

IN1

OUT1

RISE

are the rise time and the fall time of the

FALL

switching node, SW. For the ADP5041, the rise and fall times of
SW are in the order of 5 ns.

If the preceding equations and parameters are used for
estimating the converter efficiency, it must be noted that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout, so a sufficient safety margin should be
included in the estimate.

LDO Regulator Power Dissipation

The power loss of a LDO regulator is given by:

P

DLDO

= [(VIN − V

OUT

) × I

] + (VIN × I

LOAD

) (12)

GND

where:

I

is the load current of the LDO regulator.

LOAD

V

and V

IN

are input and output voltages of the LDO,

OUT

respectively.

I

is the ground current of the LDO regulator.

GND

Power dissipation due to the ground current is small and it
can be ignored.

The total power dissipation in the ADP5041 simplifies to:

P

= {[P

D

DBUCK

+ P

DLDO1

+ P

]} (13)

DLDO2

Junction Temperature

In cases where the board temperature, TA, is known, the
thermal resistance parameter, θ
junction temperature rise. T

, can be used to estimate the

JA

is calculated from TA and PD using

J

the formula

T

= TA + (PD × θJA) (14)

J

The typical θ

value for the 20-lead, 4 mm × 4 mm LFCSP is

JA

38°C/W (see Table 7). A very important factor to consider is
that θ

is based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per

JA

JEDEC standard, and real applications may use different sizes

Rev. PrE | Page 27 of 32

ADP5041 Preliminary Technical Data

and layers. To remove heat from the device, it is important to
maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. The thermal
pad (TP) should be connected to the ground plane with several
vias as shown in Figure 68.

If the case temperature can be measured, the junction temperature
is calculated by

T

= TC + (PD × θJC) (15)

J

where:

T

is the case temperature.

C

is the junction-to-case thermal resistance provided in

θ

JC

Tabl e 7

When designing an application for a particular ambient
temperature range, calculate the expected ADP5041 power
dissipation (P

) due to the losses of all channels by using

D

Equation 8 to Equation 13. From this power calculation, the
junction temperature, T

, can be estimated using Equation 14.

J

The reliable operation of the buck regulator and the LDO
regulator can be achieved only if the estimated die junction
temperature of the ADP5041 (Equation 14) is less than 125°C.
Reliability and mean time between failures (MTBF) is highly
affected by increasing the junction temperature. Additional

information about product reliability can be found in the

Analog Devices, Inc., Reliability Handbook, which is available

at the following URL: www.analog.com/reliability_handbook.

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5041 performance, causing electro­magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:

• Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.

• Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

• Maximize the size of ground metal on the component side

to help with thermal dissipation.

• Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference
on sensitive circuit nodes.

Rev. PrE | Page 28 of 32

Preliminary Technical Data ADP5041

SUGGESTED LAYOUT

Figure 68. Suggested Board Layout

BILL OF MATERIALS

Table 14.

Reference Value Part Number Vendor Package

C1 4.7µF, X5R, 6.3V JMK107BJ475 Taiyo-Yuden 0603
C2, C3 1µF, X5R, 6.3V LMK105BJ105MV-F Taiyo-Yuden 0402
C4 10µF, X5R, 6.3V JMK107BJ106MA-T Taiyo-Yuden 0603
C5,C6 2.2µF, X5R, 6.3V JMK105BJ225MV-F Taiyo-Yuden 0402
L1 1 µH, 85 mΩ, 1400 mA

1 µH, 85 mΩ, 1350 mA
1 µH, 89 mΩ, 1800 mA

IC1 3-Regulators µPMU ADP5041 Analog Devices 20-Lead LFCSP

LQM2MPN1R0NG0B
MDT2520-CN
XPL2010-1102ML

Murata
Tok o
Coilcraft

2.0 × 1.6 × 0.9 (mm)

2.5 × 2.0 × 1.2 (mm)

1.9 × 2.0 × 1.0 (mm)

Rev. PrE | Page 29 of 32

ADP5041 Preliminary Technical Data

APPLICATION DIAGRAM

R

VIN1:

2.3V to 5.5V

VIN2:

1.7V to 5.5V

30 ohm

C1

4.7 µF

ON

OFF

C2

1µF

ON

OFF

Push-Button

Reset

FILT

AVIN

VIN1

EN1

VIN2

EN2

MR

6

BUCK

7

EN_BK

10

13

16

20

LDO1

EN_LDO1

Supervisor

RESET

WDOG

VOUT1

11

8

FB1

12

9

MODE

17

VOUT2

14

FB2

15

5

19

SW

R2

PGND

nRSTO

WDI

L1 - 1uH

R1

FPWM

R3

R4

V

DD

R9

VOUT1 @

1.2A

C4

10 µF

PWM/PSM

VOUT2 @

300mA

C5

2.2 µF

Main

µC

VIN3:

1.7V to 5.5V

OFF

C3

1µF

ON

EN3

VIN3

VTH

1

EN_LDO2

3

LDO2

TP

AGND

Figure 69. Application Diagram

VTHR

18

VOUT3

2

1

FB3

R6

R7

R8

R5

VOUT3 @

300mA

C6

2.2 µF

Rev. PrE | Page 30 of 32

Preliminary Technical Data ADP5041

FACTORY PROGRAMMABLE OPTIONS

Table 15. Regulator Output Discharge Resistor Options

Options

Option 0 All discharge resistors disabled
Option 1 All discharge resistors enabled

Table 16. Under Voltage Lockout Options

Options Min Typ Max Unit

Option 0 1.95 2.15 2.25 V
Option 1 3.10 3.65 3.90 V

Table 17. Reset Timeout Options

Options Min Typ Max Unit

Option B 24 30 36 Ms
Option C 160 200 240 Ms

Table 18. Watchdog Timer Options

Selection Min Typ Max Unit

Option X 81.6 102 122.4 Ms
Option Y 1.12 1.6 1.92 Sec

Table 19. Standard Models

Option Discharge Resistors UVLO Minimum Reset Timeout Typical Watchdog Timeout

ADP5041CYACPZ-1-R7 Enabled 2.15 V 160 ms 1.6 sec
ADP5041CYACPZ-2-R7 Disabled 2.15 V 160 ms 1.6 sec
ADP5041CYACPZ-3-R7 Enabled 3.65 V 160 ms 1.6 sec
ADP5041CYACPZ-4-R7 Disabled 3.65 V 160 ms 1.6 sec
ADP5041BYACPZ-1-R7 Enabled 2.15 V 24 ms 1.6 sec
ADP5041BYACPZ-2-R7 Disabled 2.15 V 24 ms 1.6 sec
ADP5041BYACPZ-3-R7 Enabled 3.65 V 24 ms 1.6 sec
ADP5041BYACPZ-4-R7 Disabled 3.65 V 24 ms 1.6 sec
ADP5041CXACPZ-1-R7 Enabled 2.15 V 160 ms 102 ms
ADP5041CXACPZ-2-R7 Disabled 2.15 V 160 ms 102 ms
ADP5041CXACPZ-3-R7 Enabled 3.65 V 160 ms 102 ms
ADP5041CXACPZ-4-R7 Disabled 3.65 V 160 ms 102 ms
ADP5041BXACPZ-1-R7 Enabled 2.15 V 24 ms 102 ms
ADP5041BXACPZ-2-R7 Disabled 2.15 V 24 ms 102 ms
ADP5041BXACPZ-3-R7 Enabled 3.65 V 24 ms 102 ms
ADP5041BXACPZ-4-R7 Disabled 3.65 V 24 ms 102 ms

Rev. PrE | Page 31 of 32

ADP5041 Preliminary Technical Data

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

11

0.08

0.30

0.25

0.20

16

15

EXPOSED

10

BOTTOM VIEWTOP VIEW

20

1

PAD

5

6

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

1

P

N

I

C

I

N

I

D

2.65

2.50 SQ

2.35

0.25 MIN

R

O

A

T

COMPLIANTTOJEDEC STANDARDS MO-220-WGGD.

061609-B

Figure 70. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

1,

Model

ADP5041CYACPZ-1-R7 WD t

Min Reset t
V

Supervisory Settings

= 1.6 sec

OUT

= 160 ms

OUT

= 2.15V

UVLO

Discharge resistors
enabled

ADP5041CP-1-EVALZ Evaluation Board for ADP5041CYACPZ-1-R7

1

Z = RoHS Compliant Part.

Temperature
Range Package Description Package Option

= −40°C to

T

J

20-Lead LFCSP_WQ CP-20-10

+125°C

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR09652-0-11/11(PrE)

Rev. PrE | Page 32 of 32