Page 1
Micro PMU with 1.2 A Buck Regulator
SW
C3
1µF
09665-001
FB2
R4
R2
R1
R3
FB3
R3
R7
C2
2.2µF
C4
2.2µF
VOUT2
VOUT1
FB1
V
IN1
= 2.3V TO
5.5V
VIN1
EN1
VIN2
EN2
EN3
VIN3
V
IN3
= 1.7V
TO 5.5V
EN_LDO2
LDO2
(ANALOG)
BUCK
PGND
MODE
VOUT3
LDO1
(DIGITAL)
EN_LDO1
AVIN
AVIN
R
FILT
= 30Ω
C5
4.7µF
V
IN2
= 1.7V
TO 5.5V
V
OUT1
AT
1.2A
V
OUT2
AT
300mA
V
OUT3
AT
300mA
C6
10µF
L1
1µH
C1
1µF
ON
OFF
ON
OFF
ON
OFF
AGND
EN_BK
PSM/PWM
FPWM
Data Sheet
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Buck key specifications
Output voltage range: 0.8 V to 3.8 V
Current mode topology for excellent transient response
3 MHz operating frequency
Peak efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Output voltage range: 0.8 V to 5.2 V
Low V
from 1.7 V to 5.5 V
IN
Stable with 2.2 µF ceramic output capacitors
High PSRR
Low output noise
Low dropout voltage
−40°C to +125°C junction temperature range
and Two 300 mA LDOs
ADP5040
GENERAL DESCRIPTION
The ADP5040 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables the use
of tiny multilayer external components and minimizes board space.
When the MODE pin is set to logic high, the buck regulator
operates in forced pulse width modulation (PWM) mode.
When the MODE pin is set to logic low, the buck regulator
operates in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency. The low quiescent current, low
dropout voltage, and wide input voltage range of the ADP5040
LDOs extend the battery life of portable devices. The ADP5040
LDOs maintain a power supply rejection greater than 60 dB for
frequencies as high as 10 kHz while operating with a low headroom
voltage.
Each regulator in the ADP5040 is activated by a high level on
the respective enable pin. The output voltages of the regulators
are programmed though external resistor dividers to address a
variety of applications.
FUNCTIONAL BLOCK DIAGRAM
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respec tive owners.
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
Page 2
ADP5040 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
General Specifications ................................................................. 3
Buck Specifications ....................................................................... 3
LDO1, LDO2 Specifications ....................................................... 4
Input and Output Capacitor, Recommended Specifications .. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Theory of Operation ...................................................................... 25
REVISION HISTORY
12/11—Revision 0: Initial Version
Power Management Unit ........................................................... 25
Buck Section ................................................................................ 26
LDO Section ............................................................................... 27
Applications Information .............................................................. 29
Buck External Component Selection ....................................... 29
LDO External Component Selection ...................................... 30
Power Dissipation/Thermal Considerations ............................. 31
Application Diagram ................................................................. 33
PCB Layout Guidelines .................................................................. 34
Suggested Layout ........................................................................ 34
Bill of Materials ........................................................................... 35
Factory Programmable Options ................................................... 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
Rev. 0 | Page 2 of 40
Page 3
Data Sheet ADP5040
SPECIFICATIONS
GENERAL SPECIFICATIONS
AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum
specifications, and T
Table 1.
Parameter Symbol Description Min Typ Max Unit
AVIN UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO
Option 0 2.275 V
Option 1 3.9 V
Input Voltage Falling UVLO
Option 0 1.95 V
Option 1 3.1 V
SHUTDOWN CURRENT I
Thermal Shutdown Threshold TSSD TJ rising 150 °C
Thermal Shutdown Hysteresis TS
STA RT-UP TIME1
BUCK t
LDO1, LDO2 t
Enx, MODE, INPUTS
Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V
Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V
Input Leakage Current V
1
Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to V
nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more
information.
= 25°C for typical specifications, unless otherwise noted.
A
AVIN
AVINRISE
AVI NFAL L
ENx = GND 0.1 2 µA
GND-SD
20 °C
SD-HYS
250 µs
STA RT1
V
STA RT2
ENx = AVIN or GND 0.05 1 µA
I-LEAKAGE
OUT2
, V
= 3.3 V 85 µs
OUT3
to the moment VOUT1, VOUT2, and VOUT3 reache 90% of their
AVIN
BUCK SPECIFICATIONS
AVIN, VIN1 = 2.3 V to 5.5 V; V
specifications, and T
= 25°C for typical specifications, unless otherwise noted.1
A
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Accuracy V
Line Regulation (ΔV
Load Regulation (ΔV
VOLTAGE FEEDBACK V
PWM TO POWER SAVE MODE
CURRENT THRESHOLD
INPUT CURRENT CHARACTERISTICS
DC Operating Current I
Shutdown Current I
= 1.8 V; L = 1 µH; CIN = 10 µF; C
OUT1
V
2.3 5.5 V
IN1
PWM mode,
OUT1
I
LOAD
)/ΔV
PWM mode −0.05 %/V
IN1
)/ΔI
I
OUT1
LOAD
MODE = ground
I
LOAD
FB1
I
PSM_L
NOLO AD
OUT1/VOUT1
OUT1/VOUT1
= 10 µF; TJ= −40°C to +125°C for minimum/maximum
OUT
−3 +3 %
= 0 mA to 1200 mA
= mA to 1200 mA, PWM mode −0.1 %/A
0.485 0.5 0.515 V
100 mA
= 0 mA, device not switching, all other
21 35 μA
channels disabled
EN1 = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA
SHTD
Rev. 0 | Page 3 of 40
Page 4
ADP5040 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SW CHARACTERISTICS
SW On Resistance R
PFET, AVIN = VIN1 = 5 V 140 190 mΩ
R
NFET, AVIN = VIN1 = 5 V 150 210 mΩ
Current Limit I
ACTIVE PULL-DOWN EN1 = 0 V 85 Ω
OSCILLATOR FREQUENCY F
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1, LDO2 SPECIFICATIONS
V
, V
= (V
IN2
IN3
OUT2,VOUT3
T
= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1
J
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE V
OPERATING SUPPLY CURRENT
Bias Current per LDO2 I
Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2 and VIN3
LDO1 or LDO2 Only I
LDO1 and LDO2 Only I
OUTPUT VOLTAGE ACCURACY V
100 μA < I
REFERENCE VOLTAGE V
REGULATION
Line Regulation (ΔV
I
Load Regulation3 (ΔV
DROPOUT VOLTAGE4 V
V
V
V
V
ACTIVE PULL-DOWN R
CURRENT-LIMIT THRESHOLD5 I
OUTPUT NOISE OUT
10 Hz to 100 kHz, V
10 Hz to 100 kHz, V
OUT
10 Hz to 100 kHz, V
10 Hz to 100 kHz, V
+ 0.5 V) or 1.7 V (whichever is greater) to 5.5V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 μF , C
I
I
(ΔV
(ΔV
PFET
NFET, AVIN = VIN1 = 3.6 V 170 235 mΩ
NFET
LIMIT
2.5 3.0 3.5 MHz
OSC
, V
T
IN2
IN3
VIN2BIAS /IVIN3BIAS
OUT2, VOUT3
I
OUT3
OUT2
OUT2
OUT2
OUT2
V
V
, V
0.485 0.500 0.515 V
FB2
FB3
OUT2/VOUT2
OUT3/VOUT3
OUT2/VOUT2
OUT3/VOUT3
DROPOUT
PDLDO
T
LIMIT
)/ΔV
)/ΔV
)/ΔI
)/ΔI
EN2/EN3 = 0 V 600 Ω
10 Hz to 100 kHz, V
LDO2NOISE
10 Hz to 100 kHz, V
LDO1NOISE
IN2
IN3
OUT2
OUT3
V
V
OUT2
I
OUT2 = IOUT3
PFET, AVIN = VIN1 = 3.6 V 180 240 mΩ
PFET switch peak current limit 1600 1950 2300 mA
= 2.2 μF;
OUT
= −40°C to +125°C 1.7
J
= I
= 0 μA 10 30 μA
OUT4
60 100 μA
−3 +3 %
−0.03 +0.03 %/ V
IN2
IN3
IN2
IN3
= I
= 10 mA
OUT3
= I
= 300 mA
OUT3
= I
= 0 μA, all other channels disabled 53 μA
OUT3
= I
= 0 μA, buck disabled 74 μA
OUT3
< 300 mA, 100 μA < I
OUT2
= (V
+ 0.5 V) to 5.5 V,
OUT2
= (V
+ 0.5 V) to 5.5 V
OUT3
= (V
+ 0.5 V) to 5.5 V
OUT2
= (V
+ 0.5 V) to 5.5 V
OUT3
= I
= 1 mA
OUT3
< 300 mA
OUT3
165 245 μA
5.5 V
= 1 mA to 300 mA 0.002 0.0075 %/mA
= V
= V
= V
= V
= 5.0 V, I
OUT3
= 3.3 V, I
OUT3
= 2.5 V, I
OUT3
= 1.8 V, I
OUT3
OUT2
OUT2
OUT2
OUT2
= −40°C to +125°C 335 470 mA
J
OUT2
OUT2
OUT2
OUT2
= 5 V, V
IN3
= 5 V, V
IN3
= 5 V, V
IN3
= 5 V, V
IN2
= 5 V, V
IN2
= 5 V, V
IN2
= I
= 300 mA 72 mV
OUT3
= I
= 300 mA 86 140 mV
OUT3
= I
= 300 mA 107 mV
OUT3
= I
= 300 mA 180 mV
OUT3
= 3.3 V 123 μV rms
OUT3
= 2.8 V 110 μV rms
OUT3
= 1.5 V 59 μV rms
OUT3
= 3.3 V 140 μV rms
OUT2
= 2.8 V 129 μV rms
OUT2
= 1.5 V 66
OUT2
μV rms
Rev. 0 | Page 4 of 40
Page 5
Data Sheet ADP5040
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY REJECTION
RATIO
100 kHz, V
1 MHz, V
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2
This is the input current into V
3
Based on an end-point calculation using 1 mA and 300 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 1.7 V.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
PSRR 1 kHz, V
and V
IN2
, which is not delivered to the output load.
IN3
= 100 mA
I
OUT
= 100 mA
I
OUT
= 100 mA
I
OUT
IN2, VIN3
IN2, VIN3
, V
IN2
= 3.3 V, V
= 3.3 V, V
= 3.3 V, V
IN3
, V
OUT2
OUT2, VOUT3
OUT2, VOUT3
= 2.8 V,
OUT3
= 2.8 V,
= 2.8 V,
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CAPACITANCE (BUCK)1 C
OUTPUT CAPACITANCE (BUCK)2 C
INPUT AND OUTPUT CAPACITANCE3 (LDO1, LDO2) C
CAPACITOR ESR R
1
The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas
Y5V and Z5U capacitors are not recommended for use with the buck.
2
The minimum output capacitance should be greater than 7 µF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas
Y5V and Z5U capacitors are not recommended for use with the buck.
3
The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
whereas Y5V and Z5U capacitors are not recommended for use with LDOs.
TJ = −40°C to +125°C 4.7 40 µF
MIN1
TJ = −40°C to +125°C 7 40 µF
MIN2
TJ = −40°C to +125°C 0.70 µF
MIN34
TJ = −40°C to +125°C 0.001 1 Ω
ESR
66 dB
57 dB
60 dB
Rev. 0 | Page 5 of 40
Page 6
ADP5040 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVIN to AGND −0.3 V to +6 V
VIN1 to AVIN −0.3 V to +0.3 V
PGND to AGDN −0.3 V to +0.3 V
VIN2, VIN3, VOUTx, ENx, MODE, FBx, SW to
AGND
SW to PGND −0.3 V to (VIN1 + 0.3 V)
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
ESD Human Body Model 3000 V
ESD Charged Device Model 1500 V
ESD Machine Model 200 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−0.3 V to (AVIN + 0.3 V)
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W
ESD CAUTION
Rev. 0 | Page 6 of 40
Page 7
Data Sheet ADP5040
14
13
12
1
3
4
VOUT2
15 FB2
VIN2
FB1
11
VOUT1
FB3
VIN3
2
VOUT3
EN3
5
NC
7
VIN1
6
AVIN
8
SW
9
PGND
10
EN1
19
NC
20
NC
18
NC
17
MODE
16
EN2
ADP5040
TOP VIEW
(Not to S cale)
NOTES
1. EXPO S E D P AD M US T BE CONNECT E D TO
SYSTEM GROUND PLANE.
09665-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration—View from Top of the Die
Table 7. Preliminary Pin Function Descriptions
Pin No. Mnemonic Description
1 FB3 LDO2 Feedback Input.
2 VOUT3 LDO2 Output Voltage.
3 VIN3 LDO2 Input Supply (1.7 V to 5.5 V).
4 EN3 Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2.
6 AVIN Housekeeping Input Supply (2.3 V to 5.5 V).
7 VIN1 Buck Input Supply (2.3 V to 5.5 V).
8 SW Buck Switching Node.
9 PGND Dedicated Power Ground for Buck Regulator.
10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.
11 VOUT1 Buck Output Sensing Node.
12 FB1 Buck Feedback Input.
13 VIN2 LDO1 Input Supply (1.7 V to 5.5 V).
14 VOUT2 LDO1 Output Voltage.
15 FB2 LDO1 Feedback Input.
16 EN2 Enable LDO1. EN2 = high: turn on LDO1; EN2 = low: turn off LDO1.
17 MODE
5, 18, 19, 20 NC Not Connected.
0 EPAD Exposed Pad. ( AGND = Analog Ground). The exposed pad must be connected to the system ground plane.
Buck Mode. Mode = high: buck regulator operates in fixed PWM mode; mode = low: buck regulator operates in
power save mode (PSM) at light load and in constant PWM at higher load.
Rev. 0 | Page 7 of 40
Page 8
ADP5040 Data Sheet
CH4 2.0V/DIV 1MΩ
B
W
500M
CH2 2.0V/DIV 1MΩ
B
W
20.0M
CH3 2.0V/DIV 1MΩ
B
W
500M
A CH2 1.88V 200µs/DIV
1.0MS/s
1.0µs/pt
4
2
3
V
OUT1
V
OUT2
V
OUT3
09665-003
CH1
CH2
CH3
CH4
A CH1 1.08V 200µs/DIV
5.0MS/s
200ns/pt
1
2
3
4
V
OUT3
V
OUT2
V
OUT1
I
IN
2.0V/DIV 1MΩ
B
W
20.0M
2.0V/DIV 1MΩ
B
W
20.0M
300mA/DIV 1MΩ
B
W
20.0M
2.0V/DIV 1MΩ
B
W
20.0M
09665-004
1.0
0
2.4 2.9 3.4 3.9 4.4 4.9 5.4
I
IN
(mA)
V
IN
(V)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
09665-005
CH1
CH2
CH3
CH4
A CH1 2.32V 50µs/DIV
2.0MS/s
500ns/pt
1
2
3
4
SW
V
OUT1
EN
I
IN
4.0V/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
500M
200mA/DIV 1MΩ
B
W
20.0M
5.0V/DIV 1MΩ
B
W
500M
09665-006
CH1
CH2
CH3
CH4
A CH1 1.12V 50µs/DIV
2.0MS/s
500ns/pt
1
2
3
4
SW
V
OUT1
EN
I
IN
8.0V/DIV 1MΩ
B
W
20.0M
2.0V/DIV 1MΩ
B
W
500.0M
200mA/DIV 1MΩ
B
W
20.0M
5.0V/DIV 1MΩ
B
W
500.0M
09665-007
CH1
CH2
CH3
CH4
A CH1 640mV 50µs/DIV
2.0MS/s
500ns/pt
SW
V
OUT1
EN
I
IN
8.0V/DIV 1MΩ
B
W
20.0M
2.0V/DIV 1MΩ
B
W
500.0M
200mA/DIV 1MΩ
B
W
20.0M
5.0V/DIV 1MΩ
B
W
500.0M
1
2
3
4
09665-008
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.
Figure 3. 3-Channel Start-Up Waveforms
Figure 4. Total Inrush Current, All Channels Started Simultaneously
Figure 6. Buck Startup, V
Figure 7. Buck Startup, V
OUT1
OUT1
= 3.3 V, I
= 1.8 V, I
= 20 mA
OUT2
= 20 mA
OUT
Figure 5. System Quiescent Current (Sum of All the Input Currents) vs.
V
OUT1
= 1.8 V, V
Input Voltage
= V
OUT2
= 3.3 V, (UVLO = 3.3 V)
OUT3
Figure 8. Buck Startup, V
OUT1
= 1.2 V, I
= 20 mA
OUT
Rev. 0 | Page 8 of 40
Page 9
Data Sheet ADP5040
3.90
3.70
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
3.72
3.74
3.76
3.78
3.80
3.82
3.84
3.86
3.88
–40°C
+25°C
+85°C
09665-009
3.39
OUTPUT VOLTAGE (V)
1.820
1.815
1.810
1.800
1.805
1.795
1.790
1.780
1.785
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-011
1.24
1.23
1.22
1.21
1.20
1.19
1.18
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-012
3.90
3.88
3.86
3.70
3.72
3.74
3.76
3.78
3.80
3.82
3.84
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-013
3.32
3.31
3.30
3.25
3.26
3.27
3.28
3.29
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-014
Figure 9. Buck Load Regulation Across Temperature, V
Auto Mode
3.37
3.35
3.33
3.31
3.29
3.27
3.25
0.01 0.1 1
OUTPUT CURRE NT (A)
Figure 10. Buck Load Regulation Across Temperature, V
Auto Mode
OUT1
OUT1
–40°C
+25°C
+85°C
= 3.8 V,
= 3.3 V,
Figure 12. Buck Load Regulation Across Temperature, V
OUT1
= 1.2 V,
Auto Mode
09665-010
Figure 13. Buck Load Regulation Across Temperature, V
OUT1
= 3.8 V,
PWM Mode
Figure 11. Buck Load Regulation Across Temperature, V
Auto Mode
OUT1
= 1.8 V,
Figure 14. Buck Load Regulation Across Temperature, V
OUT1
= 3.3 V,
PWM Mode
Rev. 0 | Page 9 of 40
Page 10
ADP5040 Data Sheet
1.820
1.815
1.810
1.800
1.805
1.795
1.790
1.780
1.785
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-015
1.205
1.200
1.195
1.185
1.190
1.180
0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-016
100
0
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRE NT (A)
10
20
30
40
50
60
70
80
90
V
IN
= 5.5V
V
IN
= 4.5V
09665-017
EFFICIENCY (%)
100
EFFICIENCY (%)
100
0
0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRE NT (A)
10
20
30
40
50
60
70
80
90
V
IN
= 5.5
VIN= 3.6
V
IN
= 4.5
09665-020
100
Figure 15. Buck Load Regulation Across Temperature,
= 1.8 V, PWM Mode
V
OUT1
Figure 16. Buck Load Regulation Across Temperature,
V
= 1.2 V, PWM Mode
OUT1
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage,
VIN= 3.6V
90
80
70
60
50
40
30
20
10
0
0.0001 0.001 0.01 0.1 1
Figure 19. Buck Efficiency vs. Load Current, Across Input Voltage,
V
VIN= 4.5V
V
VIN= 4.5V
VIN= 5.5V
OUTPUT CURRE NT (A)
= 3.8 V, PWM Mode
OUT1
VIN= 5.5V
OUTPUT CURRE NT (A)
= 3.3 V, Auto Mode
OUT1
09665-018
09665-019
Figure 17. Buck Efficiency vs. Load Current, Across Input Voltage,
V
= 3.8 V, Auto Mode
OUT1
Figure 20. Buck Efficiency vs. Load Current, Across Input Voltage,
= 3.3 V, PWM Mode
V
OUT1
Rev. 0 | Page 10 of 40
Page 11
Data Sheet ADP5040
EFFICIENCY (%)
100
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
100
EFFICIENCY (%)
100
0
0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRE NT (A)
10
20
30
40
50
60
70
80
90
–40°C
+25°C
+85°C
09665-026
100
90
80
70
60
50
40
30
20
10
0
0.0001 0.001 0.01 0.1 1
VIN = 2.4V
V
= 3.6V
IN
= 4.5V
V
IN
V
= 5.5V
IN
OUTPUT CURRE NT (A)
Figure 21. Buck Efficiency vs. Load Current, Across Input Voltage,
V
= 1.8 V, Auto Mode
OUT1
09665-021
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
VIN = 2.4V
V
= 3.6V
IN
= 4.5V
V
IN
V
= 5.5V
IN
OUTPUT CURRE NT (A)
Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage,
V
= 1.2 V, PWM Mode
OUT1
09665-024
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
OUTPUT CURRE NT (A)
Figure 22. Buck Efficiency vs. Load Current, Across Input Voltage,
= 1.8 V, PWM Mode
V
OUT1
90
80
70
60
50
40
30
20
10
0
0.0001 0.001 0.01 0.1 1
OUTPUT CURRE NT (A)
Figure 23. Buck Efficiency vs. Load Current, Across Input Voltage,
= 1.2 V, Auto Mode
V
OUT1
VIN = 2.4V
V
= 3.6V
IN
= 4.5V
V
IN
V
= 5.5V
IN
VIN = 2.4V
V
= 3.6V
IN
= 4.5V
V
IN
V
= 5.5V
IN
09665-022
09665-023
Rev. 0 | Page 11 of 40
90
80
70
60
50
40
30
20
10
0
0.0001 0.001 0.01 0.1 1
–40°C
+25°C
+85°C
OUTPUT CURRE NT (A)
Figure 25. Buck Efficiency vs. Load Current, Across Temperature,
= 5.0 V, V
V
IN
= 3.3 V, Auto Mode
OUT1
Figure 26. Buck Efficiency vs. Load Current, Across Temperature,
= 5.0 V, V
V
IN
= 3.3 V, PWM Mode
OUT1
09665-025
Page 12
ADP5040 Data Sheet
EFFICIENCY (%)
100
EFFICIENCY (%)
100
0
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRE NT (A)
10
20
30
40
50
60
70
80
90
–40°C
+25°C
+85°C
09665-029
EFFICIENCY (%)
2.5
2.0
0.5
1.0
1.5
0
3.4 3.9 4.4 4.9 5.4
OUTPUT CURRE NT (A)
VIN (V)
V
OUT
= 3.3V
09665-031
2.0
1.8
0.2
0.4
0.6
0.8
1.6
1.4
1.2
1.0
0
2.4 3.93.42.9 4.4 4.9 5.4
OUTPUT CURRE NT (A)
VIN (V)
V
OUT
= 1.8V
09665-032
100
90
80
70
60
50
40
30
20
10
0
0.0001 0.001 0.01 0.1 1
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
Figure 27. Buck Efficiency vs. Load Current, Across Temperature,
V
= 5.0 V, V
IN
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
= 1.8 V, Auto Mode
OUT1
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
Figure 28. Buck Efficiency vs. Load Current, Across Temperature,
= 5.0 V, V
V
IN
= 1.8 V, PWM Mode
OUT1
09665-027
09665-028
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
Figure 30. Buck Efficiency vs. Load Current, Across Temperature,
V
= 5.0 V, V
IN
= 1.2 V, PWM Mode
OUT1
Figure 31. Buck DC Current Capability vs. Input Voltage
09665-030
Figure 29. Buck Efficiency vs. Load Current, Across Temperature,
V
= 5.0 V, V
IN
= 1.2 V, Auto Mode
OUT1
Figure 32. Buck DC Current Capability vs. Input Voltage
Rev. 0 | Page 12 of 40
Page 13
Data Sheet ADP5040
2.0
1.8
0.2
0.4
0.6
0.8
1.6
1.4
1.2
1.0
0
2.4 3.93.42.9 4.4 4.9 5.4
OUTPUT CURRE NT (A)
V
IN
(V)
V
OUT
= 1.2V
09665-033
2.80
2.82
2.84
2.86
2.88
2.90
2.92
2.94
0 1.21.00.2 0.4 0.6 0.8
FREQUENCY (MHz)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
09665-034
CH2
CH3
CH4
A CH1 640mV 5µs/DIV
500MS/s
2.0ns/pt
SW
V
OUT
I
SW
200mA/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
20.0M
40.0mV/DIV 20.0M
2
3
4
09665-035
CH2
CH3
CH4
A CH1 640mV 5µs/DIV
500MS/s
2.0ns/pt
SW
V
OUT
I
SW
200mA/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
20.0M
40.0mV/DIV 20.0M
2
3
4
09665-036
CH2
CH3
CH4
A CH3 1.14V 5µs/DIV
500MS/s
2.0ns/pt
SW
V
OUT
I
SW
200mA/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
20.0M
40.0mV/DIV 20.0M
2
3
4
09665-037
CH2
CH3
CH4
A CH1 640mV 200ns/DIV
500MS/s
2.0ns/pt
SW
V
OUT
I
SW
200mA/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
20.0M
10.0mV/DIV 20.0M
2
3
4
09665-038
Figure 33. Buck DC Current Capability vs. Input Voltage
Figure 34. Buck Switching Frequency vs. Output Current,
Across Temperature, V
= 1.8 V, PWM Mode
OUT1
Figure 36. Typical Waveforms, V
Figure 37. Typical Waveforms, V
OUT1
OUT1
= 1.8 V, I
= 1.2 V, I
= 30 mA, Auto Mode
OUT1
= 30 mA, Auto Mode
OUT1
Figure 35. Typical Waveforms, V
= 3.3 V, I
OUT1
= 30 mA, Auto Mode
OUT1
Figure 38. Typical Waveforms, V
OUT1
= 3.3 V, I
= 30 mA, PWM Mode
OUT1
Rev. 0 | Page 13 of 40
Page 14
ADP5040 Data Sheet
CH2
CH3
CH4
A CH1 640mV 200ns/DIV
500MS/s
2.0ns/pt
SW
V
OUT
I
SW
200mA/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
20.0M
20.0mV/DIV 20.0M
2
3
4
09665-039
CH2
CH3
CH4
A CH3 1.14V 200ns/DIV
500MS/s
2.0ns/pt
SW
V
OUT
I
SW
200mA/DIV 1MΩ
B
W
20.0M
3.0V/DIV 1MΩ
B
W
20.0M
40.0mV/DIV 20.0M
2
3
4
09665-040
CH1
CH2
CH3
A CH3 4.48V
SW
V
OUT
V
IN
3.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1.0V/DIV
2
1
3
B
W
400M
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
09665-041
CH1
CH2
CH3
A CH3 4.48V
SW
V
OUT
V
IN
3.0V/DIV
30.0mV/DIV
1MΩ
B
W
20.0M
1.0V/DIV
2
1
3
B
W
400M
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
09665-042
CH1
CH2
CH3
A CH3 4.48V
SW
V
OUT
V
IN
3.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1.0V/DIV
2
1
3
B
W
400M
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
09665-043
CH1
CH2
CH3
A CH3 4.48V
SW
V
OUT
V
IN
3.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1.0V/DIV
2
1
3
B
W
400M
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
09665-044
Figure 39. Typical Waveforms, V
Figure 40. Typical Waveforms, V
OUT1
OUT1
= 1.8 V, I
= 1.2 V, I
= 30 mA, PWM Mode
OUT1
= 30 mA, PWM Mode
OUT1
Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to
OUT1
= 1.8 V, I
5.0 V, V
= 5 mA, Auto Mode
OUT1
Figure 43. Buck Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, V
OUT1
= 1.2 V, I
= 5 mA, Auto Mode
OUT1
Figure 41. Buck Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, V
= 3.3 V, I
OUT1
= 5 mA, Auto Mode
OUT1
Figure 44. Buck Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, V
= 3.3 V, PWM Mode
OUT1
Rev. 0 | Page 14 of 40
Page 15
Data Sheet ADP5040
CH1
CH2
CH3
A CH3 4.48V
SW
V
OUT
V
IN
3.0V/DIV
20.0mV/DIV
1MΩ
B
W
20.0M
1.0V/DIV
2
1
3
B
W
400M
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
09665-045
CH1
CH2
CH3
A CH3 4.48V
SW
V
OUT
V
IN
3.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1.0V/DIV
2
1
3
B
W
20.0M
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
09665-046
CH1
CH2
CH3
A CH3 150mA
V
OUT
SW
4.0V/DIV
100mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
2
1
3
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-047
CH1
CH2
CH3
A CH3 150mA
V
OUT
SW
4.0V/DIV
100mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
2
1
3
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-048
CH1
CH2
CH3
A CH3 150mA
V
OUT
SW
4.0V/DIV
100mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
2
1
3
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-049
CH1
CH2
CH3
A CH3 150mA
2
3
V
OUT
SW
4.0V/DIV
100mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
1
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-050
Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, V
= 1.8 V, PWM Mode
OUT1
Figure 46. Buck Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, V
= 1.2 V, PWM Mode
OUT1
Figure 48. Buck Response to Load Transient, I
= 3.3 V, Auto Mode
V
OUT1
Figure 49. Buck Response to Load Transient, I
V
= 1.8 V, Auto Mode
OUT1
= 50 mA to 500 mA,
OUT1
= 20 mA to 200 mA,
OUT1
Figure 47. Buck Response to Load Transient, I
= 3.3 V, Auto Mode
V
OUT1
= 20 mA to 200 mA,
OUT1
Rev. 0 | Page 15 of 40
Figure 50. Buck Response to Load Transient, I
= 1.8 V, Auto Mode
V
OUT1
= 50 mA to 500 mA,
OUT1
Page 16
ADP5040 Data Sheet
CH1
CH2
CH3
A CH3 94.0mA
2
3
V
OUT
SW
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
120M
1MΩ
B
W
20.0M
100mA/DIV
1
B
W
20.0M
200µs/DIV
500kS/s
2.0µs/pt
I
OUT
09665-051
CH1
CH2
CH3
A CH3 92.0mA
2
3
V
OUT
SW
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
120M
B
W
20.0M
200mA/DIV
1
B
W
20.0M
200µs/DIV
500kS/s
2.0µs/pt
I
OUT
09665-052
CH1
CH2
CH3
A CH3 150mA
2
3
V
OUT
SW
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
1
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-053
CH1
CH2
CH3
A CH3 150mA
2
3
V
OUT
SW
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
1
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-054
CH1
CH2
CH3
A CH3 150mA
2
3
V
OUT
SW
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
1
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-055
CH1
CH2
CH3
A CH3 150mA
2
3
V
OUT
SW
4.0V/DIV
100mV/DIV
1MΩ
B
W
20.0M
1MΩ
B
W
20.0M
300mA/DIV
1
B
W
20.0M
500µs/DIV
20.0MS/s
50.0ns/pt
I
OUT
09665-056
Figure 51. Buck Response to Load Transient, I
= 1.2 V, Auto Mode
V
OUT1
Figure 52. Buck Response to Load Transient, I
V
= 1.2 V, Auto Mode
OUT1
= 20 mA to 200 mA,
OUT1
= 50 mA to 500 mA,
OUT1
Figure 54. Buck Response to Load Transient, I
= 3.3 V, PWM Mode
V
OUT1
Figure 55. Buck Response to Load Transient, I
V
= 1.8 V, PWM Mode
OUT1
= 50 mA to 500 mA,
OUT1
= 20 mA to 200 mA,
OUT1
Figure 53. Buck Response to Load Transient, I
= 3.3 V, PWM Mode
V
OUT1
= 20 mA to 200 mA,
OUT1
Rev. 0 | Page 16 of 40
Figure 56. Buck Response to Load Transient, I
= 1.8 V, PWM Mode
V
OUT1
= 50 mA to 500 mA,
OUT1
Page 17
Data Sheet ADP5040
SW
CH1
CH2
CH3
A CH3 94.0mA
2
3
V
OUT
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
120.0M
B
W
20.0M
100mA/DIV
1
B
W
20.0M
200µs/DIV
500kS/s
2.0ns/pt
I
OUT
09665-057
CH1
CH2
CH3
A CH3 92.0mA
2
3
V
OUT
4.0V/DIV
50.0mV/DIV
1MΩ
B
W
20.0M
20.0M
200mA/DIV
1
20.0M
200µs/DIV
500kS/s
2.0ns/pt
SW
I
OUT
09665-058
CH1
CH2
CH3
A CH1 1.72V
2
3
V
OUT
2.0V/DIV
2.0V/DIV
B
W
20.0M
1MΩ
B
W
20.0M
200mA/DIV
1
1MΩ
B
W
20.0M
50.0µs/DIV
200MS/s
5.0ns/pt
I
IN
EN
09665-059
CH1
CH2
CH3
A CH1 1.72V
V
OUT
2.0V/DIV
2.0V/DIV
B
W
20.0M
1MΩ
B
W
20.0M
200mA/DIV
1MΩ
B
W
20.0M
50.0µs/DIV
200MS/s
5.0ns/pt
I
IN
EN
09665-060
CH1
CH2
CH3
A CH1 760mV
2
3
V
OUT
2.0V/DIV
1.0V/DIV
B
W
20.0M
1MΩ
B
W
20.0M
200mA/DIV
1
1MΩ
B
W
20.0M
50.0µs/DIV
200MS/s
5.0ns/pt
I
IN
EN
09665-061
CH1
CH2
CH3
A CH1 1.72V
2
3
V
OUT
2.0V/DIV
1.0V/DIV
B
W
20.0M
1MΩ
B
W
20.0M
200mA/DIV
1
1MΩ
B
W
20.0M
50.0µs/DIV
200MS/s
5.0ns/pt
I
IN
EN
09665-062
Figure 57. Buck Response to Load Transient, I
= 1.2 V, PWM Mode
V
OUT1
Figure 58. Buck Response to Load Transient, I
V
= 1.2 V, PWM Mode
OUT1
= 20 mA to 200 mA,
OUT1
= 50 mA to 500 mA,
OUT1
Figure 60. LDO1, LDO2 Startup, V
Figure 61. LDO1, LDO2 Startup, V
= 3.3 V, I
OUT
= 1.8 V, I
OUT
= 5 mA
OUT
= 5 mA
OUT
Figure 59. LDO1, LDO2 Startup, V
= 4.7 V, I
OUT
OUT
= 5 mA
Figure 62. LDO1, LDO2 Startup, V
= 1.2 V, I
OUT
= 5 mA
OUT
Rev. 0 | Page 17 of 40
Page 18
ADP5040 Data Sheet
4.758
4.708
4.658
4.608
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
5.5V
5.0V
09665-063
3.40
3.20
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
5.5V
3.6V
4.5V
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
09665-064
1.800
1.770
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
1.775
1.780
1.785
1.790
1.795
3.6V
4.5V
5.5V
2.8V
09665-065
1.220
1.180
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
3.6V
4.5V
5.5V
2.8V
1.185
1.190
1.195
1.200
1.205
1.210
1.215
09665-066
3.40
3.20
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
–40°C
+25°C
+85°C
09665-067
1.800
1.770
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
–40°C
+25°C
+85°C
1.775
1.780
1.785
1.790
1.795
09665-068
Figure 63. LDO1, LDO2 Load Regulation Across Input Voltage, V
= 4.7 V
OUT
Figure 66. LDO1, LDO2 Load Regulation Across Input Voltage, V
OUT
= 1.2 V
Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, V
Figure 65. LDO1, LDO2 Load Regulation Across Input Voltage, V
= 3.3 V
OUT
= 1.8 V
OUT
Figure 67. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V,
V
= 3.3 V
OUT
Figure 68. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V,
V
= 1.8 V
OUT
Rev. 0 | Page 18 of 40
Page 19
Data Sheet ADP5040
1.220
1.180
0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
1.185
1.190
1.195
1.200
1.205
1.210
1.215
–40°C
+25°C
+85°C
09665-069
4.75
4.73
4.65
4.67
4.69
4.71
5.0 5.1 5.55.45.35.2
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
100µA
1mA
10mA
100mA
200mA
09665-070
3.310
3.280
3.6 3.9 4.2 4.5 5.14.8 5.4
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3.285
3.290
3.295
3.300
3.305
100µA
1mA
10mA
100mA
200mA
09665-071
1.820
1.790
2.5 3.0 3.5 4.0 5.04.5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
100µA
1mA
10mA
100mA
200mA
1.795
1.800
1.805
1.810
1.815
09665-072
1.201
1.192
2.5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1.193
1.194
1.195
1.196
1.197
1.198
1.199
1.200
3.0 3.5 4.0 4.5 5.0
100µA
1mA
10mA
100mA
200mA
09665-073
200
0
0 0.05 0.10 0.15 0.20 0.25 0.30
GROUND CURRENT ( µ A)
OUTPUT CURRE NT (A)
20
40
60
80
100
120
140
160
180
09665-074
Figure 69. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V,
= 1.2 V
V
OUT
Figure 70. LDO1, LDO2 Line Regulation Across Input Voltage, V
OUT
= 4.7 V
Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, V
Figure 73. LDO1, LDO2 Line Regulation Across Input Voltage, V
OUT
OUT
= 1.8 V
= 1.2 V
Figure 71. LDO1, LDO2 Line Regulation Across Input Voltage, V
OUT
= 3.3 V
Figure 74. LDO1, LDO2 Ground Current vs. Output Current, V
OUT
= 3.3 V
Rev. 0 | Page 19 of 40
Page 20
ADP5040 Data Sheet
200
0
3.8 4.3 4.8 5.3
GROUND CURRENT ( µ A)
INPUT VOLTAGE (V)
20
40
60
80
100
120
140
160
180
0.000001A
0.0001A
0.001A
0.01A
0.1A
0.15A
0.3A
09665-075
CH2
CH3
A CH3 27.2mA
2
V
OUT
30.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
5.0MS/s
200ns/pt
I
OUT
09665-076
CH2
CH3
A CH3 27.2mA
2
V
OUT
30.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
5.0MS/s
200ns/pt
I
OUT
09665-077
CH2
CH3
A CH3 42.0mA
2
V
OUT
30.0mV/DIV
50.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
120M
200µs/DIV
500kS/s
2.0µs/pt
I
OUT
09665-078
CH2
CH3
A CH3 89.6mA
2
V
OUT
50.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
120M
200µs/DIV
500kS/s
2.0µs/pt
I
OUT
09665-079
CH2
CH3
A CH3 89.6mA
2
V
OUT
30.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
120M
200µs/DIV
500kS/s
2.0µs/pt
I
OUT
09665-080
Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output
Load (A), V
Figure 76. LDO1, LDO2 Response to Load Transient, I
80 mA, V
OUT
= 4.7 V
OUT
= 3.3 V
from 1 mA to
OUT
Figure 78. LDO1, LDO2 Response to Load Transient, I
80 mA, V
OUT
= 3.3 V
Figure 79. LDO1, LDO2 Response to Load Transient, I
200 mA, V
OUT
= 3.3 V
from 1 mA to
OUT
from 10 mA to
OUT
Figure 77. LDO1, LDO2 Response to Load Transient, I
200 mA, V
OUT
= 4.7 V
from 10 mA to
OUT
Figure 80. LDO1, LDO2 Response to Load Transient, I
OUT
= 1.8 V
80 mA, V
from 1 mA to
OUT
Rev. 0 | Page 20 of 40
Page 21
Data Sheet ADP5040
CH2
CH3
A CH3 89.6mA
2
V
OUT
50.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
120M
200µs/DIV
500kS/s
2.0µs/pt
I
OUT
09665-081
CH2
CH3
A CH3 27.2mA
2
V
OUT
30.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
5.0MS/s
200ns/pt
I
OUT
09665-082
CH2
CH3
A CH3 27.2mA
2
V
OUT
30.0mV/DIV
80.0mA/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
5.0MS/s
200ns/pt
I
OUT
09665-083
CH2
CH3
A CH3 4.84V
2
V
OUT
20.0mV/DIV
1.0V/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
V
IN
09665-084
CH2
CH3
A CH3 4.86V
2
V
OUT
20.0mV/DIV
1.0V/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
500µs/DIV
1.0MS/s
1.0µs/pt
V
IN
09665-085
CH2
CH3
A CH3 4.48V
2
V
OUT
20.0mV/DIV
1.0V/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
V
IN
09665-086
Figure 81. LDO1, LDO2 Response to Load Transient, I
200 mA, V
OUT
= 1.8 V
Figure 82. LDO1, LDO2 Response to Load Transient, I
80 mA, V
= 1.2 V
OUT
from 10 mA to
OUT
from 1 mA to
OUT
Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from
4.5 V to 5.5 V, V
OUT
= 3.3 V
Figure 85. LDO1, LDO2 Response to Line Transient, Input Voltage from
4.5 V to 5.5 V, V
OUT
= 1.8 V
Figure 83. LDO1, LDO2 Response to Load Transient, I
= 1.2 V
OUT
200 mA, V
from 10 mA to
OUT
Rev. 0 | Page 21 of 40
Figure 86. LDO1, LDO2 Response to Line Transient, Input Voltage from
4.5 V to 5.5 V, V
OUT
= 1.2 V
Page 22
ADP5040 Data Sheet
CH2
CH3
A CH3 4.02V
2
V
OUT
20.0mV/DIV
1.0V/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
V
IN
09665-087
CH2
CH3
A CH3 4.84V
2
V
OUT
20.0mV/DIV
1.0V/DIV
B
W
20.0M
3
1MΩ
B
W
20.0M
200µs/DIV
1.0MS/s
1.0µs/pt
V
IN
09665-088
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.6 4.1 4.6 5.1 5.6
OUTPUT CURRE NT (A)
VIN (V)
V
OUT
= 3.3V
09665-089
LOAD (mA)
RMS NOISE (µV)
100
10
0.0001 0.001 0.01 0.1 1 10 100 1k
CH2; V
OUT
= 3.3V; VIN = 5V
CH2; V
OUT
= 3.3V; V
IN
= 3.6V
CH2; V
OUT
= 2.8V; V
IN
= 3.1V
CH2; V
OUT
= 1.5V; VIN = 5V
CH2; V
OUT
= 1.5V; V
IN
= 1.8V
09665-104
LOAD (mA)
RMS NOISE (µV)
100
10
CH3; V
OUT
= 3.3V; V
IN
= 5V
CH3; V
OUT
= 3.3V; VIN = 3.6V
CH3; V
OUT
= 2.8V; V
IN
= 3.1V
CH3; V
OUT
= 1.5V; VIN = 5V
CH3; V
OUT
= 1.5V; VIN = 1.8V
0.0001 0.001 0.01 0.1 1 10 100 1k
09665-105
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
NOISE (µV/√Hz)
100
10
1.0
0.1
0.01
V
OUT2
= 3.3V, V
IN2
= 3.6V, I
LOAD
= 300mA
V
OUT2
= 1.5V, V
IN2
= 1.8V, I
LOAD
= 300mA
V
OUT2
= 2.8V, V
IN2
= 3.1V, I
LOAD
= 300mA
09665-106
Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from
3.3 V to 3.8 V, V
OUT
= 1.8 V
Figure 88. LDO1, LDO2 Response to Line Transient, Input Voltage from
3.3 V to 3.8 V, V
OUT
= 1.2 V
Figure 90. LDO1 Output Noise vs. Load Current, Across Input and
Output Voltage
Figure 91. LDO2 Output Noise vs. Load Current, Across Input and Output
Voltage
Figure 89. LDO1, LDO2 Output Current Capability vs. Input Voltage
Figure 92. LDO1 Noise Spectrum Across Output Voltage,
= V
V
+ 0.3 V
IN
OUT
Rev. 0 | Page 22 of 40
Page 23
Data Sheet ADP5040
NOISE (µV/√Hz)
100
10
1
0.1
0.01
1 10 100 1k
FREQUENCY (Hz)
10k 100k 1M
V
OUT3
= 3.3V, V
IN3
= 3.6V, I
LOAD
= 300mA
V
OUT3
= 1.5V, V
IN3
= 1.8V, I
LOAD
= 300mA
V
OUT3
= 2.8V, V
IN3
= 3.1V, I
LOAD
= 300mA
09665-115
100
10
1.0
0.1
0.01
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
NOISE (µV/
√Hz
)
V
OUT2
= 3.3V, V
IN2
= 3.6V, I
LOAD
= 300mA
V
OUT3
= 3.3V, V
IN3
= 3.6V, I
LOAD
= 300mA
V
OUT2
= 1.5V, V
IN2
= 1.8V, I
LOAD
= 300mA
V
OUT3
= 1.5V, V
IN3
= 1.8V, I
LOAD
= 300mA
V
OUT2
= 2.8V, V
IN2
= 3.1V, I
LOAD
= 300mA
V
OUT3
= 2.8V, V
IN3
= 3.1V, I
LOAD
= 300mA
09665-108
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
1mA
10mA
100mA
200mA
300mA
09665-109
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
1mA
10mA
100mA
200mA
300mA
09665-110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
1mA
10mA
100mA
200mA
09665-111
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
1mA
10mA
100mA
200mA
300mA
09665-112
Figure 93. LDO2 Noise Spectrum Across Output Voltage,
= V
+ 0.3 V
V
IN
OUT
Figure 94. LDO1 vs. LDO2 Noise Spectrum
Figure 96. LDO2 PSRR Across Output Load,
V
= 3.1 V, V
IN3
OUT3
= 2.8 V
Figure 97. LDO2 PSRR Across Output Load,
= 5.0 V, V
V
IN3
OUT3
= 3.3 V
Figure 95. LDO2 PSRR Across Output Load,
V
= 3.3 V, V
IN3
= 2.8 V
OUT3
Figure 98. LDO2 PSRR Across Output Load,
= 3.6 V, V
V
IN3
OUT3
= 3.3 V
Rev. 0 | Page 23 of 40
Page 24
ADP5040 Data Sheet
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
1mA
10mA
100mA
200mA
300mA
09665-113
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
1mA
10mA
100mA
200mA
300mA
09665-114
Figure 99. LDO1 PSRR Across Output Load,
= 5.0 V, V
V
IN2
OUT2
= 1.5 V
Figure 100. LDO1 PSRR Across Output Load,
= 1.8 V, V
V
IN2
OUT2
= 1.5 V
Rev. 0 | Page 24 of 40
Page 25
Data Sheet ADP5040
PWM/
PSM
CONTROL
BUCK1
DRIVER
AND
ANTISHOOT
THROUGH
PSM
COMP
ADP5040
VOUT1 FB1
VIN1
AVIN
SW
PGND
AGND
VIN2 FB2 VOUT2 VIN3
ENLDO1
600Ω
ENBK
ENLDO2
600Ω
VOUT3FB3
09665-090
OSCILLATOR
THERMAL
SHUTDOWN
VDDA
PWM
COMP
GM ERROR
AMP
85Ω
SOFT START
SYSTEM
UNDERVOLTAGE
LOCK OUT
LDO1
CONTROL
LDO2
CONTROL
VDDA
ENABLE
& MODE
CONTROL
ENLDO1
ENBK
ENLDO2
MODE
SEL
MODE
EN1
EN2
EN3
OPMODE_FUSES
VDDA
I
LIMIT
LOW
CURRENT
THEORY OF OPERATION
POWER MANAGEMENT UNIT
The ADP5040 is a micro power management unit (micro PMU)
Figure 101. Functional Block Diagram
combing one step-down (buck) dc-to-dc regulator and two low
dropout linear regulators (LDOs). The high switching frequency
and tiny 20-pin LFCSP package allow for a small power
management solution.
The regulators are activated by a logic level high applied to the
respective EN pin. The EN1 pin controls the buck regulator, the
EN2 pin controls LDO1, and the EN3 pin controls LDO2. The
MODE pin controls the buck switching operation.
The regulator output voltages are set through external resistor
dividers.
When a regulator is turned on, the output voltage ramp is
controlled through a soft start circuit to avoid a large inrush
current due to the discharged output capacitors.
The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at a logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power save current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent
current losses.
Rev. 0 | Page 25 of 40
Page 26
BUCK
VOUT1
VOUT1
SW
VIN1
FB1
AGND
C5
10µF
R1
R2
L1 – 1µH
09665-091
ADP5040 Data Sheet
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off the buck and the LDOs.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included in the thermal shutdown circuit so
that when thermal shutdown occurs, the buck and the LDOs do
not return to normal operation until the on-chip temperature
drops below 130°C. When coming out of thermal shutdown, all
regulators start with soft start control.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the ADP5040. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device reaches the turn-off threshold when the
input supply drops to 3.65 V typical.
Enable/Shutdown
The ADP5040 has individual control pins for each regulator.
A logic level high applied to the ENx pin activates a regulator,
whereas a logic level low turns off a regulator.
Active Pull-Down
The ADP5040 can be purchased with the active pull-down
option enabled. The pull-down resistors are connected between
each regulator output and AGND. The pull-downs are enabled,
when the regulators are turned off. The typical value of the pulldown resistor is 600 Ω for the LDOs and 85 Ω for the buck.
BUCK SECTION
The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
The buck output voltage is set though external resistor dividers,
as shown in Figure 102. VOUT1 must be connected to the
output capacitor. VFB1 is internally set to 0.5 V. The output
voltage can be set from 0.8 V to 3.8 V.
Figure 102. Buck External Output Voltage Setting
Control Scheme
The buck operates with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency,
but operation shifts to a power save mode (PSM) control
scheme at light loads to lower the regulation power losses.
When operating in fixed frequency PWM mode, the duty cycle
of the integrated switches is adjusted and regulates the output
voltage. When operating in PSM at light loads, the output
voltage is controlled in a hysteretic manner, with higher output
voltage ripple. During part of this time, the converter is able to
stop switching and enters an idle mode, which improves
conversion efficiency.
PWM Mode
In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Power Save Mode (PSM)
The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power save mode, an offset is introduced in the
PWM regulation level, which makes the output voltage rise.
When the output voltage reaches a level that is approximately
1.5% above the PWM regulation level, PWM operation is
turned off. At this point, both power switches are off, and the
buck enters an idle mode. The output capacitor discharges until
the output voltage falls to the PWM regulation voltage, at which
point the device drives the inductor to make the output voltage
rise again to the upper threshold. This process is repeated while
the load current is below the PSM current threshold.
Rev. 0 | Page 26 of 40
Page 27
Data Sheet ADP5040
LD01, LD02
R
A
R
B
VIN2, VI N3
VOUT2, VOUT3
VOUT2,
VOUT3
FB2, FB3
C7
2.2µF
09665-092
The ADP5040 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE
pin forces the buck to operate in PWM mode. A logic level low
sets the buck to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to, and exit from, the PSM
mode. The PSM current threshold is optimized for excellent
efficiency over all load currents.
Short-Circuit Protection
The buck includes frequency foldback to prevent current
runaway on a hard short at the output. When the voltage at the
feedback pin falls below half the internal reference voltage,
indicating the possibility of a hard short at the output, the
switching frequency is reduced to half the internal oscillator
frequency. The reduction in the switching frequency allows
more time for the inductor to discharge, preventing a runaway
of output current.
Soft Start
The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a dropping input voltage or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
LDO SECTION
The ADP5040 contains two LDOs with low quiescent current
that provide output currents up to 300 mA. The low 10 μA
typical quiescent current at no load makes the LDO ideal for
battery-operated portable equipment.
The LDOs operate with an input voltage range of 1.7 V to 5.5 V.
The wide operating range makes these LDOs suitable for
cascade configurations where the LDO supply voltage is
provided from the buck regulator.
Each LDO output voltage is set though external resistor dividers
as shown in Figure 103. V
output voltage can be set from 0.8 V to 5.2 V.
Figure 103. LDOs External Output Voltage Setting
The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with small 1 µF ceramic input and output capacitors.
LDO2 is optimized to supply analog circuits because it offers
better noise performance compared to LDO1. LDO1 should be
used in applications where noise performance is not critical.
FB2
and V
are internally set to 0.5 V. The
FB3
Rev. 0 | Page 27 of 40
Page 28
ADP5040 Data Sheet
POR
STANDBY
AVIN < VUVLO
ALL ENx = LOW
ALL REGULATORS ACTIVATED
AVIN < VUVLO
INTERNAL CIRCUIT BIASED
REGULATORS NOT ACTIVATED
NO POWER APPLIED TO AVIN.
ALL REGULATORS TURNE D OFF
TRANSITION
STATE
09665-096
END OF POR
AVIN > VUVLO
ENx = HIGH
NO POWER
ACTIVE
Figure 104. ADP5040 State Flow
Rev. 0 | Page 28 of 40
Page 29
Data Sheet ADP5040
LfV
VVV
I
SW
IN
OUT
IN
OUT
RIPPLE
××
−×
=
)(
2
)(
RIPPLE
MAXLOAD
PEAK
I
II +=
0
2
4
6
8
10
12
0 1 2 3 4 5 6
DC BIAS VOLTAGE (V)
CAPACITANCE (µ F)
09665-097
( )
OUTSW
IN
OUTSW
RIPPLE
RIPPLE
CLf
V
Cf
I
V
×××
××
=
2
2
≈
8
π
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response are made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Feedback Resistors
Referring to Figure 102, the total combined resistance for R1
and R2 is not to exceed 400 kΩ.
Inductor
The high switching frequency of the ADP5040 buck allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 μH and 3.0 μH. Suggested inductors
are shown in Ta bl e 8.
The peak-to-peak inductor current ripple is calculated using
the following equation:
where:
f
is the switching frequency.
SW
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are highly
recommended for best performance. Y5V and Z5U dielectrics
are not recommended for use with any dc-to-dc converter
because of their poor temperature and dc bias characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated using the following equation:
C
= C
EFF
× (1 − TEMPCO) × (1 − TOL)
OUT
where:
C
is the effective capacitance at the operating voltage.
EFF
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C
is 9.2481 μF at 1.8 V, as shown in Figure 105.
OUT
Substituting these values in the equation yields
C
= 9.24 μF × (1 − 0.15) × (1 − 0.1) = 7.07 μF
EFF
To guarantee the performance of the buck, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Table 8. Suggested 1.0 μH Inductors
Vendor Model
Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85
Murata LQM18FN1R0M00B 3.2 × 2.5 × 1.5 2300 54
Tayo Yuden CBC322ST1R0MR 3.2 × 2.5 × 2.5 2000 71
Coilcraft XFL4020-102ME 4.0 × 4.0 × 2.1 5400 11
Coilcraft XPL2010-102ML 1.9 × 2.0 × 1.0 1800 89
Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85
(mm)
Dimensions
I
SAT
(mA)
DCR
(mΩ)
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the buck is high switching frequency dc-to-dc converter,
shielded ferrite core material is recommended for its low core
losses and low EMI.
Output Capacitor
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing the
Figure 105. Typical Capacitor Performance
capacitor value, it is also important to account for the loss of
capacitance due to output voltage dc bias.
Rev. 0 | Page 29 of 40
Page 30
ADP5040 Data Sheet
SW
VIN1
VIN2
VIN3
VOUT1
VOUT2
PGND
VOUT3
C1
10µF
C2
1µF
C3
1µF
PROCESSOR
VCORE
VDDIO
MODE
GPIO1
ENx
GPIO[x:y]
3
R5
FB3
R6
R1
R2
R3
R4
VANALOG
FB1
FB2
C5
2.2µF
C4
4.7µF
C6
2.2µF
09665-098
ADP5040
MICRO PMU
V
IN
2.3V TO 5. 5V
R
FLT
30Ω
L1
1µH
AVIN
ANALOG
SUBSYSTEM
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
V
RIPPLE
ESR ≤
COUT
I
RIPPLE
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.
Table 9. Suggested 10 μF Capacitors
Voltage
Vendor Type Model
Case
Size
Rating
(V)
Murata X5R GRM188R60J106 0603 6.3
Taiyo Yuden X5R JMK107BJ106MA-T 0603 6.3
TDK X5R C1608JB0J106K 0603 6.3
Panasonic X5R ECJ1VB0J106M 0603 6.3
The buck regulator requires 10 µF output capacitors to guaran-
tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 106).
To minimize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Tabl e 10.
Table 10. Suggested 4.7 μF Capacitors
Voltage
Case
Vendor Type Model
Size
Rating
(V)
Murata X5R GRM188R60J475ME19D 0603 6.3
Taiyo Yuden X5R JMK107BJ475 0603 6.3
Panasonic X5R ECJ-0EB0J475M 0402 6.3
LDO EXTERNAL COMPONENT SELECTION
Feedback Resistors
Referring to Figure 103 the maximum value of Rb is not to
exceed 200 kΩ.
Output Capacitor
The ADP5040 LDOs are designed for operation with small,
space-saving ceramic capacitors, but they function with most
commonly used capacitors as long as care is taken with the ESR
value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 µF capacitance with an
ESR of 1 Ω or less is recommended to ensure stability of the
LDO. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the LDO to large
changes in load current.
When operating at output currents higher than 200 mA a
minimum of 2.2 µF capacitance with an ESR of 1 Ω or less is
recommended to ensure stability of the LDO.
CIN
II
≥
MAXLOAD
OUT
IN
V
IN
VVV
)()(−
OUT
Rev. 0 | Page 30 of 40
Figure 106. Processor System Power Management with PSM/PWM Control
Input Capacitor
A higher value input capacitor helps to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
Table 11. Suggested 2.2 μF Capacitors
Voltage
Vendor Type Model
Murata
TDK X5R
Panasonic X5R
X5R GRM188B31A225K
C1608JB0J225KT
ECJ1VB0J225K
Case
Size
0402 10.0
0402 6.3
0402 6.3
Rating
(V)
Taiyo Yuden X5R JMK107BJ225KK-T 0402 6.3
Input Bypass Capacitor
Connecting 1 µF capacitors from VIN2 and VIN3 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source impedance
is encountered. If greater than 1 µF of output capacitance is
required, increase the input capacitor to match it.
Page 31
Data Sheet ADP5040
1.2
1.0
0.8
0.6
0.4
0.2
0
0 1 2 3 4 5 6
DC BIAS VOLTAGE (V)
CAPACITANCE (µ F)
09665-099
Table 12. Suggested 1.0 μF Capacitors
Vendor Type Model
Murata X5R GRM155R61A105ME15 0402 10.0
TDK X5R C1005JB0J105KT 0402 6.3
Panasonic X5R ECJ0EB0J105K 0402 6.3
Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0
Case
Size
Voltage
Rating
(V)
Input and Output Capacitor Properties
Use any good quality ceramic capacitor with the ADP5040 as
long as it meets the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
Figure 107
depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.
Figure 107. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature,
component tolerance, and voltage.
C
= C
EFF
× (1 − TEMPCO) × (1 − TOL)
BIAS
where:
is the effective capacitance at the operating voltage.
C
BIAS
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
Rev. 0 | Page 31 of 40
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
is 0.94 μF at 1.8 V as shown in Figure 107.
BIAS
Substituting these values into the following equation yields:
= 0.94 μF × (1 – 0.15) × (1 – 0.1) = 0.72 μF
C
EFF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5040, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
POWER DISSIPATION/THERMAL CONSIDERATIONS
The ADP5040 is a highly efficient micropower management
unit (micro PMU), and in most cases the power dissipated in
the device is not a concern. However, if the device operates at
high ambient temperatures and with maximum loading
conditions, the junction temperature can reach the maximum
allowable operating limit (125°C).
When the junction temperature exceeds 150°C, the ADP5040
turns off all the regulators, allowing the device to cool down.
Once the die temperature falls below 135°C, the ADP5040
resumes normal operation.
This section provides guidelines to calculate the power dissipated in the device and to make sure the ADP5040 operates
below the maximum allowable junction temperature.
The efficiency for each regulator on the ADP5040 is given by
P
OUT
P
IN
where:
η is efficiency.
is the input power.
P
IN
P
is the output power.
OUT
Power loss is given by
P
= PIN − P
LOSS
or
P
= P
LOSS
OUT
Power dissipation can be calculated in several ways. The most
intuitive and practical way is to measure the power dissipated at
the input and all the outputs. The measurements should be
performed at the worst-case conditions (voltages, currents,
and temperature). The difference between input and output
power is dissipated in the device and the inductor. Use
Equation 4 to derive the power lost in the inductor, and from
this use Equation 3 to calculate the power dissipation in the
ADP5040 buck regulator.
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, whereas the
power lost on a LDO is calculated using Equation 12. When the
buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor. Use Equation 4
(1)
100%×=η
(2a)
OUT
× (1 − η)/η (2b)
Page 32
ADP5040 Data Sheet
/12+1
)(
rII
OUT1
RMSOUT1
×=
to derive the power lost in the inductor, and then calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the LDOs to find the
total dissipated power.
Note that the buck efficiency curves are typical values and may
not be provided for all possible combinations of V
. To account for these variations, it is necessary to include a
I
OUT
, V
, and
IN
OUT
safety margin when calculating the power dissipated in the buck.
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDOs provided
by Equation 12.
Buck Regulator Power Dissipation
The power loss of the buck regulator is approximated by
= P
P
LOSS
+ PL (3)
DBUCK
where:
P
is the power dissipation on the ADP5040 buck regulator.
DBUCK
P
is the inductor power losses.
L
The inductor losses are external to the device and they do not
have any effect on the die temperature.
The inductor losses are estimated (without core losses) by
L
2
)(
RMSOUT1
(4)
DCRIP ×≅
L
where:
is the inductor series resistance.
DCR
L
I
is the rms load current of the buck regulator.
OUT1(RMS)
(5)
where r is the normalized inductor ripple current.
R ≈ V
× (1 − D)/(I
OUT1
× L × fSW) (6)
OUT1
where:
L is inductance.
is switching frequency.
F
SW
D is duty cycle.
D = V
OUT1/VIN1
The ADP5040 buck regulator power dissipation, P
(7)
,
DBUCK
includes the power switch conductive losses, the switch losses,
and the transition losses of each channel. There are other
sources of loss, but these are generally less significant at high
output load currents, where the thermal limit of the application
is. Equation 8 shows the calculation made to estimate the power
dissipation in the buck regulator.
P
DBUCK
= P
COND
+ PSW + P
(8)
TRAN
The power switch conductive losses are due to the output current,
I
, flowing through the PMOSFET and the NMOSFET power
OUT1
switches that have internal resistance, R
DSON-P
and R
DSON-N
. The
amount of conductive power loss is found by:
P
COND
= [R
DSON-P
× D + R
× (1 – D)] × I
DSON-N
For the ADP5040, at 125°C junction temperature and V
3.6 V, R
0.16 Ω. At V
respectively, and at V
is approximately 0.2 Ω, and R
DSON-P
= 2.3 V, these values change to 0.31 Ω and 0.21 Ω,
IN1
= 5.5 V, the values are 0.16 Ω and
IN1
DSON-N
2
(9)
OUT1
=
IN1
is approximately
0.14 Ω, respectively.
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
P
SW
= (C
GATE-P
+ C
GATE-N
) × V
2
× fSW (10)
IN1
where:
is the PMOSFET gate capacitance.
C
GAT E-P
C
is the NMOSFET gate capacitance.
GAT E-N
For the ADP5040, the total of (C
GAT E-P
+ C
) is approximately
GAT E-N
150 pF.
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near V
(and from V
OUT1
OUT1
to
ground). The amount of transition loss is calculated by:
P
= V
× I
× (t
+ t
) × fSW (11)
FALL
where t
TRAN
RISE
and t
IN1
OUT1
RISE
are the rise time and the fall time of the
FALL
switching node, SW. For the ADP5040, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for
estimating the converter efficiency, note that the equations do
not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by:
P
DLDO
= [(VIN – V
OUT
) × I
] + (VIN × I
LOAD
) (12)
GND
where:
is the load current of the LDO regulator.
I
LOAD
V
and V
IN
are input and output voltages of the LDO,
OUT
respectively.
I
is the ground current of the LDO regulator.
GND
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the ADP5040 simplifies to:
P
= {[P
D
DBUCK
+ P
DLDO1
+ P
]} (13)
DLDO2
Rev. 0 | Page 32 of 40
Page 33
Data Sheet ADP5040
ON
OFF
FPWM
PWM/PSM
R
FILT
30Ω
SW
PGND
MODE
C4
10µF
L1
1µH
VIN1
EN3
EN1
VIN2
VIN3
EN2
AGND
VOUT2
VOUT1
FB3
VOUT3
C1
4.7µF
C2
1µF
C3
1µF
EN_BK
BUCK
EN_LDO1
LDO1
(DIGITAL)
EN_LDO2
LDO2
(ANALOG)
ON
OFF
ON
OFF
4
16
13
10
7
6
3
EP
1
14
FB2
FB1
15
17
9
11
8
12
R2
R1
2
R7
R8
C6
2.2µF
R4
R3
V
OUT1
AT
1.2A
C5
2.2µF
V
IN1
= 2.3V
TO 5.5V
V
IN2
= 1.7V
TO 5.5V
V
IN3
= 1.7V
TO 5.5V
V
OUT2
AT
300mA
V
OUT3
AT
300mA
09665-103
AVIN
Junction Temperature
In cases where the board temperature, TA, is known, the
thermal resistance parameter, θ
junction temperature rise. T
, can be used to estimate the
JA
is calculated from TA and PD using
J
the formula
T
= TA + (PD × θJA) (14)
J
The typical θ
value for the 20-lead, 4 mm × 4 mm LFCSP is
JA
38°C/W (see Table 6). A very important factor to consider is
that θ
is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as
JA
per JEDEC standard, and real applications may use different
sizes and layers. To remove heat from the device, it is important
to maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. The exposed
pad (EP) should be connected to the ground plane with several
vias as shown in Figure 109.
APPLICATION DIAGRAM
If the case temperature can be measured, the junction temperature
is calculated by
T
= TC + (PD × θJC) (15)
J
where:
T
is the case temperature.
C
θ
is the junction-to-case thermal resistance provided in Tabl e 6.
JC
When designing an application for a particular ambient
temperature range, calculate the expected ADP5040 power
dissipation (P
) due to the losses of all channels by using
D
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
, can be estimated using Equation 14.
J
The reliable operation of the buck regulator and the LDO
regulator can be achieved only if the estimated die junction
temperature of the ADP5040 (Equation 14) is less than 125°C.
Reliability and mean time between failures (MTBF) is highly
affected by increasing the junction temperature. Additional
information about product reliability can be found in the
Analog Devices, Inc., Reliability Handbook, which is available
at http://www.analog.com/reliability_handbook.
Figure 108. Application Diagram
Rev. 0 | Page 33 of 40
Page 34
ADP5040 Data Sheet
GPL
NC
NC
NC
AGND
NC
2
GPL
GPL
GPL
GPL
VOUT3
VOUT1
VOUT2
PPL
PPL
PPL
Pin1
GP L G PL
GP L G PL
GP L
GP L
PPL
PPL
TOP LAYER
09665-102
VIAS LEGEND:
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
2ND LAYER
MODE
EN
L1 – 1µH
0603
C5 – 4.7µF
10V/XR5 0603
C6 – 10µF
6.3V/XR5
0603
1.0
1.0
2.0
2.0
3.0
3.0
mm
mm
4.0
4.0
5.0
5.0
6.0
6.0
6.5
6.5 7.0
0.5
0.5
1.5
1.5
2.5
2.5
3.5
3.5
4.5
4.5
5.5
5.5
R
FILT
30Ω
0402
C3 – 1µF
10V/XR5
0402
C4– 2.2µF
6.3V/XR5
0402
EN3
VIN3
VOUT3
FB3
VOUT1
FB1
VIN2
VOUT2
FB2
C2 – 1µF
10V/XR5
0402
C5 – 2.2µF
6.3V/XR5
0402
AVIN
VIN
SW
PGND
EN1
ADP5040
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5040 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
SUGGESTED LAYOUT
See Figure 109 for an example layout.
Figure 109. Evaluation Board Layout
Rev. 0 | Page 34 of 40
Page 35
Data Sheet ADP5040
BILL OF MATERIALS
Table 13.
Reference Value Part Number Vendor Package
C1 4.7 µF, X5R, 6.3 V JMK107BJ475 Taiyo -Yude n 0603
C2, C3 1 µF, X5R, 6.3 V LMK105BJ105MV-F Taiyo -Yud en 0402
C4 10 µF, X5R, 6.3 V JMK107BJ106MA-T Taiyo-Yuden 0603
C5, C6 2.2 µF, X5R, 6.3 V JMK105BJ225MV-F Taiyo -Yuden 0402
L1 1 µH, 85 mΩ, 1400 mA LQM2MPN1R0NG0B Murata 2.0 × 1.6 × 0.9 (mm)
1 µH, 85 mΩ, 1350 mA MDT2520-CN Toko 2.5 × 2.0 × 1.2 (mm)
1 µH, 89 mΩ, 1800 mA XPL2010-1102ML Coilcraft 1.9 × 2.0 × 1.0 (mm)
IC1 3-regulator micro PMU ADP5040 Analog Devices 20-Lead LFCSP
Rev. 0 | Page 35 of 40
Page 36
ADP5040 Data Sheet
FACTORY PROGRAMMABLE OPTIONS
Table 14. Regulator Output Discharge Resistor Options
Selection
0 All discharge resistors disabled
1 All discharge resistors enabled
Table 15. Under Voltage Lockout options
Selection Min Typ Max Unit
0 1.95 2.15 2.275 V
1 3.10 3.65 3.90 V
Rev. 0 | Page 36 of 40
Page 37
Data Sheet ADP5040
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD.
061609-B
BOTTOMVIEWTOPVIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
15
16
5
OUTLINE DIMENSIONS
Figure 110. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
1
Model
UVLO Active Pull-Down Temperature Range Package Description
ADP5040ACPZ-1-R7 2.15 V Enabled on all channels TJ = −40°C to +125°C 20-Lead LFCSP_WQ CP-20-10
ADP5040CP-1-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.
Rev. 0 | Page 37 of 40
Package
Option
Page 38
ADP5040 Data Sheet
NOTES
Rev. 0 | Page 38 of 40
Page 39
Data Sheet ADP5040
NOTES
Rev. 0 | Page 39 of 40
Page 40
ADP5040 Data Sheet
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D096665-0-12/11(0)
Rev. 0 | Page 40 of 40
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