Main input voltage range: 2.3 V to 5.5 V
Two 1200 mA buck regulators and two 300 mA LDOs
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±3%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The ADP5034 combines two high performance buck regulators
and two low dropout (LDO) regulators in a small, 24-lead 4 mm ×
Regulators with Two 300 mA LDOs
ADP5034
4 mm LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced PWM mode. When the MODE pin is set to low, the buck
regulators operate in PWM mode when the load is above a predefined threshold. When the load current falls below a predefined
threshold, the regulator operates in power save mode (PSM),
improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the ADP5034 LDOs extend the
battery life of portable devices. The ADP5034 LDOs maintain
power supply rejection greater than 60 dB for frequencies as
high as 10 kHz while operating with a low headroom voltage.
Regulators in the ADP5034 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
AVIN
0.1µF
C1
C2
ON
1µF
ON
1µF
AVIN
VIN1
EN1
VIN2
EN2
EN3
VIN3
C3
EN4
VIN4
C4
C
2.3V TO
5.5V
1.7V TO
5.5V
4.7µF
OFF
4.7µF
OFF
HOUSEKEEPING
EN1
EN2
EN3
(ANALOG)
EN4
(DIGITAL)
ADP5034
BUCK1
MODE
MODE
BUCK2
LDO1
LDO2
AGND
Figure 1.
VOUT1
SW1
FB1
PGND1
MODE
VOUT2
SW2
FB2
PGND2
VOUT3
FB3
VOUT4
FB4
L1 1µH
R1
R2
PWM
L2 1µH
R3
R4
R5
R6
R7
R8
C5
10µF
PSM/PWM
C6
10µF
C7
1µF
C8
1µF
V
OUT1
1200mA
V
OUT2
1200mA
V
OUT3
300mA
V
OUT4
300mA
AT
AT
AT
AT
09703-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Change to Equation 5 Where Statement ..................................... 22
Change to Equation 6..................................................................... 22
Change to Undervoltage Lockout Section .................................. 16
Changes to Figure 46 ...................................................................... 16
Change to Figure 47 ....................................................................... 17
Changes to LDO1/LDO2 Section ................................................ 18
Changes to Output Capacitor Section and Table 8 .................... 19
Change to V
Changes to Input and Output Capacitor Properties Section .... 21
Changes to Equation 3 ................................................................... 22
Changes to Junction Temperature Section .................................. 23
Changes to LDO Regulator Power Dissipation Section ............ 23
Changes to Figure 52 and Figure 53............................................. 25
Moved Bill of Materials Section .................................................... 25
Changes to Ordering Guide .......................................................... 26
6/11—Revision 0: Initial Version
Equation, Table 9, and Figure 50 ................... 20
RIPPLE
Rev. A | Page 2 of 28
Page 3
Data Sheet ADP5034
SPECIFICATIONS
GENERAL SPECIFICATIONS
V
= V
= V
AVI N
IN1
= 2.3 V to 5.5 V; V
IN2
25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V
THERMAL SHUTDOWN
Threshold TSSD T
Hysteresis TS
START-UP TIME1
BUCK1, LDO1, LDO2 t
BUCK2 t
EN1, EN2, EN3, EN4, MODE INPUTS
Input Logic High VIH 1.1 V
Input Logic Low VIL 0.4 V
Input Leakage Current V
INPUT CURRENT
All Channels Enabled I
All Channels Disabled I
VIN1 UNDERVOLTAGE LOCKOUT
High UVLO Input Voltage Rising UVLO
High UVLO Input Voltage Falling UVLO
Low UVLO Input Voltage Rising UVLO
Low UVLO Input Voltage Falling UVLO
1
Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 from 0 V to V
times are shorter for individual channels if another channel is already enabled. See the Typi section for more information. cal Performance Characteristics
IN3
= V
= 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA =
IN4
, V
, V
AVIN
SD-HYS
START1
START2
I-LEAKAGE
STBY-NOSW
SHUTDOWN
2.3 5.5 V
IN1
IN2
rising 150 °C
J
20 °C
250 µs
300 µs
0.05 1 µA
No load, no buck switching 108 175 µA
T
3.9 V
VIN1RISE
VIN1FALL
2.275 V
VIN1RISE
VIN1FALL
= −40°C to +85°C 0.3 1 µA
J
3.1 V
1.95 V
to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up
AVIN
Rev. A | Page 3 of 28
Page 4
ADP5034 Data Sheet
BUCK1 AND BUCK2 SPECIFICATIONS
V
= V
= V
AVI N
IN1
specifications, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Accuracy V
Line Regulation
Load Regulation
VOLTAGE FEEDBACK V
OPERATING SUPPLY CURRENT MODE = ground
BUCK1 Only IIN
BUCK2 Only IIN
BUCK1 and BUCK2 IIN
PSM CURRENT THRESHOLD I
SW CHARACTERISTICS
SW On Resistance R
R
R
R
Current Limit I
ACTIVE PULL-DOWN R
OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
= 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
IN2
OUT1
, V
1
OUT2
PWM mode; I
LOAD1
= I
= 0 mA to
LOAD2
−3 +3 %
1200 mA
(∆V
(∆V
(∆V
(∆V
FB1
OUT1/VOUT1
OUT2/VOUT2
OUT1/VOUT1
OUT2/VOUT2
, V
)/∆V
)/∆V
)/∆I
)/∆I
Models with adjustable outputs 0.485 0.5 0.515 V
FB2
PWM mode −0.05 %/V
,
IN1
IN2
= 0 mA to 1200 mA, PWM mode −0.1 %/A
I
,
LOAD
OUT1
OUT2
= 0 mA, device not switching, all
I
LOAD 1
44 A
other channels disabled
= 0 mA, device not switching, all
I
LOAD 2
55 A
other channels disabled
I
LOAD 1
= I
= 0 mA, device not switching,
LOAD 2
67 A
LDO channels disabled
PSM to PWM operation 100 mA
PSM
V
NFET
V
PFET
V
NFET
V
PFET
, I
LIMIT1
LIMIT2
Channel disabled 75 Ω
PDWN-B
= V
= 3.6 V 155 240 mΩ
IN1
IN2
= V
= 3.6 V 205 310 mΩ
IN1
IN2
= V
= 5.5 V 137 204 mΩ
IN1
IN2
= V
= 5.5 V 162 243 mΩ
IN1
IN2
pFET switch peak current limit 1600 1950 2300 mA
LDO1 AND LDO2 SPECIFICATIONS
V
= (V
IN3
1 µF; T
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V
OPERATING SUPPLY CURRENT
Bias Current per LDO2 I
I
I
Total System Input Current
LDO1 or LDO2 Only I
LDO1 and LDO2 Only I
OUTPUT CHARACTERISTICS
Output Voltage Accuracy V
Line Regulation
Load Regulation3
+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, V
OUT3
= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1
J
, V
1.7 5.5 V
IN3
IN4
VIN3BIAS/IVIN4BIAS
IIN
I
OUT3
OUT3
OUT3
Includes all current into AVIN, VIN1, VIN2, VIN3,
= (V
IN4
= I
= 0 µA 10 30 µA
OUT4
= I
= 10 mA 60 100 µA
OUT4
= I
= 300 mA 165 245 µA
OUT4
+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = C
OUT4
and VIN4
= I
= 0 µA, all other channels disabled 53 µA
OUT4
= I
= 0 µA, buck channels disabled 74 µA
OUT4
< 300 mA, 100 µA < I
OUT3
OUT4
<
−3 +3 %
OUT3
, V
OUT4
OUT3
OUT3
100 µA < I
300 mA
= I
(∆V
(∆V
(∆V
(∆V
OUT3/VOUT3
OUT4/VOUT4
OUT3/VOUT3
OUT4/VOUT4
)/∆V
)/∆V
)/∆I
)/∆I
IN3
IN4
OUT3
OUT4
I
,
OUT3
I
,
OUT3
= 1 mA −0.03 +0.03 %/V
OUT4
= I
= 1 mA to 300 mA 0.001 0.003 %/mA
OUT4
Rev. A | Page 4 of 28
OUT
=
Page 5
Data Sheet ADP5034
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
V
, V
VOLTAGE FEEDBACK
DROPOUT VOLTAGE4 V
V
V
V
CURRENT-LIMIT THRESHOLD5 I
ACTIVE PULL-DOWN R
OUTPUT NOISE
Regulator LDO1 NOISE
Regulator LDO2 NOISE
POWER SUPPLY REJECTION
RATIO
Regulator LDO1 10 kHz, V
100 kHz, V
1 MHz, V
Regulator LDO2 10 kHz, V
100 kHz, V
1 MHz, V
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2
This is the input current into VIN3/VIN4, which is not delivered to the output load.
3
Based on an endpoint calculation using 1 mA and 300 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.7 V.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
FB3
FB4
V
DROPOUT
, I
LIMIT3
PDWN-L
335 600 mA
LIMIT4
Channel disabled 600 Ω
10 Hz to 100 kHz, V
LDO1
10 Hz to 100 kHz, V
LDO2
0.485 0.5 0.515 V
= V
OUT3
OUT3
OUT3
OUT3
= V
= V
= V
OUT4
OUT4
OUT4
OUT4
= 5.2 V, I
= 3.3 V, I
= 2.5 V, I
= 1.8 V, I
OUT3
OUT3
OUT3
OUT3
= 5 V, V
IN3
= 5 V, V
IN4
= I
= 300 mA 50 mV
OUT4
= I
= 300 mA 75 140 mV
OUT4
= I
= 300 mA 100 mV
OUT4
= I
= 300 mA 180 mV
OUT4
= 2.8 V 100 µV rms
OUT3
= 1.2 V 60 µV rms
OUT4
PSRR
= 3.3 V, V
IN3
= 3.3 V, V
IN3
= 3.3 V, V
IN3
= 1.8 V, V
IN4
= 1.8 V, V
IN4
= 1.8 V, V
IN4
OUT3
OUT3
OUT3
OUT4
OUT4
OUT4
= 2.8 V, I
= 2.8 V, I
= 2.8 V, I
= 1.2 V, I
= 1.2 V, I
= 1.2 V, I
= 1 mA 60 dB
OUT3
= 1 mA 62 dB
OUT3
= 1 mA 63 dB
OUT3
= 1 mA 54 dB
OUT4
= 1 mA 57 dB
OUT4
= 1 mA 64 dB
OUT4
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified.
Table 4.
Parameter Symbol Min Typ Max Unit
SUGGESTED INPUT AND OUTPUT CAPACITANCE
BUCK1, BUCK2 Input Capacitor C
BUCK1, BUCK2 Output Capacitor C
LDO1, LDO21 Input and Output Capacitor C
CAPACITOR ESR R
1
The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.
, C
MIN1
MIN1
MIN3
ESR
4.7 40 µF
MIN2
, C
7 40 µF
MIN2
, C
0.70 µF
MIN4
0.001 1 Ω
Rev. A | Page 5 of 28
Page 6
ADP5034 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVIN to AGND −0.3 V to +6 V
VIN1, VIN2 to AVIN −0.3 V to +0.3 V
PGND1, PGND2 to AGND −0.3 V to +0.3 V
VIN3, VIN4, VOUT1, VOUT2, FB1, FB2,
FB3, FB4, EN1, EN2, EN3, EN4, MODE
to AGND
VOUT3 to AGND −0.3 V to (VIN3 + 0.3 V)
VOUT4 to AGND −0.3 V to (VIN4 + 0.3 V)
SW1 to PGND1 −0.3 V to (VIN1 + 0.3 V)
SW2 to PGND2 −0.3 V to (VIN2 + 0.3 V)
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature
Range
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
−0.3 V to (AVIN + 0.3 V)
−40°C to +125°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
24-Lead, 0.5 mm pitch LFCSP 35 3 °C/W
ESD CAUTION
Rev. A | Page 6 of 28
Page 7
Data Sheet ADP5034
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT4
24
PIN 1
INDICATOR
1
FB4
EN4
2
3
4
5
6
ADP5034
TOP VIEW
(Not to Scale)
7
EN2
VIN2
SW2
PGND2
NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE SOLDERED TO THE GROUND PLANE.
FB3
VOUT3
VIN3
EN3
VIN4
20
19
23
22
21
AGND
18
AVIN
17
VIN1
16
SW1
15
14
PGND1
MODE
13
9
8
11
12
10
FB1
FB2
EN1
VOUT1
VOUT2
09703-003
Figure 2. Pin Configuration—View from the Top of the Die
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 FB4
LDO2 Feedback Input. For device models with a adjustable output voltage, connect this pin to the middle of the
LDO2 resistor divider. For device models with a factory programmed output voltage, connect FB4 to the top of the
capacitor on VOUT4.
2 EN4 LDO2 Enable Pin. High level turns on this regulator, and low level turns it off.
3 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN.
4 SW2 BUCK2 Switching Node.
5 PGND2 Dedicated Power Ground for BUCK2.
6 NC No Connect. Leave this pin unconnected.
7 EN2 BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off.
8 FB2
BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2.
10 VOUT1 BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1.
11 FB1
BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
12 EN1 BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off.
13 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation.
14 PGND1 Dedicated Power Ground for BUCK1.
15 SW1 BUCK1 Switching Node.
16 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN.
17 AVIN Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2.
18 AGND Analog Ground.
19 FB3
LDO1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
LDO1 resistor divider. For device models with a factory programmed output voltage, connect FB3 to the top of the
capacitor on VOUT3.
20 VOUT3 LDO1 Output Voltage.
21 VIN3 LDO1 Input Supply (1.7 V to 5.5 V).
22 EN3 LDO1 Enable Pin. High level turns on this regulator, and low level turns it off.
23 VIN4 LDO2 Input Supply (1.7 V to 5.5 V).
24 VOUT4 LDO2 Output Voltage.
EPAD EP Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane.
Rev. A | Page 7 of 28
Page 8
ADP5034 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
V
= V
= V
= V
IN1
140
IN2
IN3
= 3.6 V, TA = 25°C, unless otherwise noted.
IN4
3.35
120
100
80
60
40
QUIESCENT CURRENT (µA)
20
0
2.32.83.33.84.34.85.3
INPUT VOLTAGE (V)
Figure 3. System Quiescent Current vs. Input Voltage, V
V
OUT2
4
2
1
3
= 1.8 V, V
= 1.2 V, V
OUT3
T
SW
IOUT
VOUT
EN
= 3.3 V, All Channels Unloaded
OUT4
OUT1
= 3.3 V,
3.33
VIN = 4.2V, +25°C
3.31
(V)
OUT
V
3.29
3.27
3.25
00.20.40.60.81.01.2
09703-039
Figure 6. BUCK1 Load Regulation Across Temperature, V
VIN = 4.2V, +85°C
= 4.2V, –40°C
V
IN
I
OUT
(A)
OUT1
= 3.3 V,
09703-025
Auto Mode
1.864
(V)
OUT
V
1.844
1.824
1.804
1.784
VIN = 3.6V, +2 5°C
VIN = 3.6V, +8 5°C
V
= 3.6V, –40° C
IN
CH1 2.00V
CH3 5.00V
B
CH2 50.0mA
W
B
CH4 5.00V
W
Figure 4. BUCK1 Startup, V
T
4
2
1
3
CH1 2.00V
CH3 5.00V
SW
IOUT
VOUT
EN
B
B
W
W
CH2 50.0mA
CH4 5.00V
Figure 5. BUCK2 Startup, V
B
M 40.0µsA CH32.2V
W
B
W
T 11.20%
OUT1
= 1.8 V, I
OUT1
= 5 mA
B
M 40.0µsA CH3 2.2V
W
B
W
T 11.2 0%
= 3.3 V, I
OUT2
OUT2
= 10 mA
09703-049
09703-048
Rev. A | Page 8 of 28
1.764
00.20.40.60.81.01.2
I
(A)
OUT
Figure 7. BUCK2 Load Regulation Across Temperature, V
Auto Mode
0.799
0.798
0.797
0.796
0.795
(V)
0.794
OUT
V
0.793
0.792
0.791
0.790
0.789
00.20.40.60.81.01.2
VIN = 3.6V, +85° C
VIN = 3.6V, +25 °C
= 3.6V, –40° C
V
IN
I
OUT
(A)
Figure 8. BUCK1 Load Regulation Across Input Voltage, V
PWM Mode
OUT2
OUT1
= 1.8 V,
= 0.8 V,
09703-024
09703-026
Page 9
Data Sheet ADP5034
C
C
C
100
VIN = 3.9V
V
= 4.2V
IN
90
= 5.5V
V
IN
80
70
60
Y (%)
50
40
EFFICIEN
30
20
10
0
0.00010.0010.010.11
I
(A)
OUT
Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
= 3.3 V, Auto Mode
V
OUT1
100
90
80
70
VIN = 3.9V
60
50
40
EFFICIENCY (%)
30
20
10
0
0.0010.010.11
VIN = 4.2V
I
OUT
(A)
VIN = 5.5V
Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
= 3.3 V, PWM Mode
V
OUT1
100
90
80
70
VIN = 3.6V
60
Y (%)
50
40
EFFICIEN
30
20
10
0
0.0010.010.11
VIN = 4.2V
I
OUT
VIN = 5.5V
(A)
VIN = 2.3V
Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
V
= 1.8 V, Auto Mode
OUT2
09703-027
09703-018
09703-020
100
VIN = 2.3V
VIN = 3.6V
I
OUT
VIN = 5.5V
VIN = 4.2V
(A)
90
80
70
60
Y (%)
50
40
EFFICIEN
30
20
10
0
0.0010.010.11
Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
= 1.8 V, PWM Mode
V
OUT2
100
90
80
70
60
50
VIN = 3.6V
40
EFFICIENCY(%)
30
20
10
0
0.0010.010.11
VIN = 4.2V
I
OUT
VIN = 5.5V
(A)
VIN = 2.3V
Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
= 0.8 V, Auto Mode
V
OUT1
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.0010.010.11
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
I
(A)
OUT
VIN = 5.5V
Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
= 0.8 V, PWM Mode
V
OUT1
09703-016
09703-015
09703-017
Rev. A | Page 9 of 28
Page 10
ADP5034 Data Sheet
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
+25°C
10
+85°C
–40°C
0
0.0010.010.11
I
(A)
OUT
Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature,
= 3.9 V, V
V
IN
100
90
+25°C
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.0010.010.11
+85°C
–40°C
= 3.3 V, Auto Mode
OUT1
I
(A)
OUT
Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature,
V
= 1.8 V, Auto Mode
OUT2
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.0010.010.11
I
(A)
OUT
+25°C
+85°C
–40°C
Figure 17. BUCK2 Efficiency vs. Load Current, Across Temperature,
= 0.8 V, Auto Mode
V
OUT1
09703-028
09703-030
09703-029
3.3
3.2
3.1
3.0
2.9
2.8
2.7
SCOPE FREQUENCY (MHz)
2.6
2.5
+25°C
+85°C
00.20.40.60.81.01.2
I
(A)
OUT
–40°C
Figure 18. BUCK2 Switching Frequency vs. Output Current, Across
Temperature, V
T
VOUT
1
I
SW
2
SW
4
CH1 50.0mVM 4.00µs A CH2 240mA
CH2 500mA
CH4 2.00V
Figure 19. Typical Waveforms, V
T
VOUT
1
I
2
4
CH1 50.0mVM 4.00µs A CH2 220mA
SW
SW
B
CH2 500mA
W
CH4 2.00V
Figure 20. Typical Waveforms, V
= 1.8 V, PWM Mode
OUT2
T 28.40%
= 3.3 V, I
OUT1
B
OUT2
W
T 28.40%
= 1.8 V, I
OUT1
OUT2
= 30 mA, Auto Mode
= 30 mA, Auto Mode
9703-031
09703-051
09703-050
Rev. A | Page 10 of 28
Page 11
Data Sheet ADP5034
T
T
1
I
SW
2
SW
VOUT
4
CH1 50mVM 400ns A CH2 220mA
Figure 21. Typical Waveforms, V
B
CH2 500mA
W
CH4 2.00V
B
OUT1
W
T 28.40%
= 3.3 V, I
= 30 mA, PWM Mode
OUT1
T
1
2
VOUT
I
SW
SW
VIN
1
VOUT
SW
4
3
CH1 50.0mV
09703-053
CH3 1.00VCH4 2.00V
Figure 24. BUCK2 Response to Line Transient, V
B
W
B
W
= 1.8 V, PWM Mode
V
OUT2
M 1.00msA CH3 4. 80V
B
W
T 30.40%
= 4.5 V to 5.0 V,
IN2
09703-041
T
SW
4
VOUT
1
4
CH1 50mVM 400ns A CH2 220mA
Figure 22. Typical Waveforms, V
B
CH2 500mA
W
CH4 2.00V
B
OUT2
W
T 28.40%
= 1.8 V, I
= 30 mA, PWM Mode
OUT2
09703-052
T
VIN
1
VOUT
SW
3
CH1 50.0mV
CH3 1.00VCH4 2.00V
B
W
B
W
M 1.00msA CH3 4.80V
B
W
T 30.40%
09703-040
Figure 23. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, V
= 3.3 V, PWM Mode
OUT1
I
OUT
2
CH1 50.0mV
B
CH2 50.0mA
W
CH4 5.00V
B
M 20.0µs A CH2 356mA
W
B
T 60.000µs
W
Figure 25. BUCK1 Response to Load Transient, I
= 3.3 V, Auto Mode
V
OUT1
T
SW
4
VOUT
1
I
OUT
2
CH1 50.0mV
B
CH2 50.0mA
W
CH4 5.00V
B
M 20.0µs A CH2 379mA
W
B
W
T 22.20%
Figure 26. BUCK2 Response to Load Transient, I
= 1.8 V, Auto Mode
V
OUT2
from 1 mA to 50 mA,
OUT1
from 1 mA to 50 mA,
OUT2
09703-044
9703-043
Rev. A | Page 11 of 28
Page 12
ADP5034 Data Sheet
T
SW
4
VOUT
1
I
OUT
T
I
2
1
IN
VOUT
EN
2
CH1 50.0mV
B
CH2 200mA
W
CH4 5.00V
B
M 20.0µs A CH2 408mA
W
B
W
T 20.40%
Figure 27. BUCK1 Response to Load Transient, I
= 3.3 V, Auto Mode
V
OUT1
T
SW
4
B
CH2 200mA
W
CH4 5.00V
VOUT
I
OUT
B
M 20.0µs A CH2 88.0mA
W
B
W
T 19.20%
1
2
CH1 100mV
Figure 28. BUCK2 Response to Load Transient, I
V
= 1.8 V, Auto Mode
OUT2
T
VOUT2
2
3
1
SW1
VOUT1
SW2
from 20 mA to 180 mA,
OUT1
from 20 mA to 180 mA,
OUT2
3
CH1 2.00VM 40.0µsA CH32.2V
9703-045
CH3 5.00V
B
CH2 50.0mA
W
B
W
Figure 30. LDO Startup, V
B
B
OUT3
W
W
T 11.20%
= 3.0 V, I
OUT3
= 5 mA
09703-064
2.820
2.815
2.810
2.805
(V)
2.800
OUT3
V
2.795
VIN = 4.5V
VIN = 3.3V
2.790
2.785
2.780
00.050.100.150.200.250.30
09703-046
Figure 31. LDO Load Regulation Across Input Voltage, V
VIN = 5.5V
I
(A)
OUT
VIN = 5.0V
OUT3
= 2.8 V
09703-032
400
350
300
250
(m)
200
ON
RDS
150
100
+25°C
–40°C
+125°C
4
CH1 5.00V
CH3 5.00V
B
W
B
W
CH2 5.00V
CH4 5.00V
B
M 400ns A CH4 1.90V
W
B
W
T 50.00%
09703-060
Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
Rev. A | Page 12 of 28
50
0
2.32.83.33.84.34.85.3
INPUT VOLTAGE (V)
Figure 32. NMOS RDS
vs. Input Voltage Across Temperature
ON
09703-037
Page 13
Data Sheet ADP5034
250
200
150
(m)
ON
100
RDS
50
0
2.32.83.33.84.34.85.3
INPUT VOLTAGE (V)
Figure 33. PMOS RDS
vs. Input Voltage Across Temperature
ON
+25°C
–40°C
+125°C
09703-038
50
45
40
35
30
25
20
15
GROUND CURRENT (µA)
10
5
0
00.050.100.150.200.25
LOAD CURREN T (A)
Figure 36. LDO Ground Current vs. Output Load, V
= 3.3 V, V
IN3
OUT3
09703-036
= 2.8 V
3.45
3.40
3.35
(V)
3.30
OUT
V
3.25
3.20
3.15
VIN = 4.2V, +85°C
= 4.2V, +25°C
V
IN
VIN = 4.2V, –40°C
00.050.100.150.200.250.30
I
(A)
OUT
Figure 34. LDO Load Regulation Across Temperature, V
Figure 35. LDO Line Regulation Across Output Load, V
OUT3
09703-034
= 2.8 V
Rev. A | Page 13 of 28
3
CH1 20.0mV
CH3 1.00V
M 100µsA CH3 4.80V
T 28.40%
09703-042
Figure 38. LDO Response to Line Transient, Input Voltage from 4.5 V to 5.5 V,
= 2.8 V
V
OUT3
Page 14
ADP5034 Data Sheet
60
55
50
45
40
RMS NOISE (µV)
35
30
25
0.0010.010.1110100
VIN = 5V
V
= 3.3V
IN
I
LOAD
(mA)
Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage,
= 2.8 V
V
OUT3
65
60
55
50
VIN = 5V
V
= 3.3V
IN
09703-055
0
–20
–40
–60
PSRR (dB)
–80
100µA
1mA
10mA
–100
50mA
100mA
150mA
–120
101001k10k100k1M10M
Figure 42. LDO PSRR Across Output Load, V
0
100µA
1mA
10mA
–20
50mA
100mA
150mA
–40
FREQUENCY (Hz )
= 3.3 V, V
IN3
OUT3
= 3.0 V
09703-058
45
40
RMS NOISE (µ V)
35
30
25
0.0010.010.1110100
I
LOAD
(mA)
Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage,
= 3.0 V
V
OUT3
0
100µA
1mA
–10
10mA
50mA
–20
100mA
150mA
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
–100
101001k10k100k1M10M
Figure 41. LDO PSRR Across Output Load, V
FREQUENCY (Hz )
= 3.3 V, V
IN3
OUT3
= 2.8 V
–60
PSRR (dB)
–80
–100
–120
101001k10k100k1M10M
09703-056
Figure 43. LDO PSRR Across Output Load, V
0
100µA
1mA
–10
10mA
50mA
–20
100mA
150mA
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
–100
101001k10k100k1M10M
09703-057
Figure 44. LDO PSRR Across Output Load, V
FREQUENCY (Hz )
FREQUENCY (Hz )
= 5.0 V, V
IN3
= 5.0 V, V
IN3
OUT3
OUT3
= 2.8 V
= 3.0 V
09703-059
09703-061
Rev. A | Page 14 of 28
Page 15
Data Sheet ADP5034
V
V
THEORY OF OPERATION
AVI N
PWM
VIN1
SW1
PGND1
EN1ENBK1
EN2
EN3
EN4
ENABLE
AND
MODE
CONTROL
COMP
I
LIMIT
LOW
CURRENT
DRIVER
AND
ANTISHOOT
THROUGH
ENBK2
ENLDO1
ENLDO2
CONTRO L
AV IN
GM ERROR
PWM/
PSM
BUCK1
AMP
SOFT START
ENBK1
PSM
COMP
LDO
UNDERVOLTAGE
LOCKOUT
LDO
CONTROL
FB1 FB2
OUT1
75
OSCILLATOR
SYSTEM
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
OUT2
75
R1
ENBK2
SOFT START
PSM
COMP
GM ERROR
AMP
PWM/
PSM
CONTROL
BUCK2
AVI N
PWM
COMP
I
LIMIT
LOW
CURRENT
DRIVER
OP
ANTISHOOT
MODE
THROUGH
SEL
MODE2
B
Y
A
LDO
UNDERVOLTAGE
LOCKOUT
LDO
CONTROL
AND
ENL DO 2
VIN2
SW2
PGND2
600
MODE
R3
ADP5034
VIN3AGNDVO UT3
Figure 45. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5034 is a micropower management units (micro
PMU) combining two step-down (buck) dc-to-dc convertors
and two low dropout linear regulators (LDOs). The high
switching frequency and tiny 24-lead LFCSP package allow for
a small power management solution.
To combine these high performance regulators into the micro
PMU, there is a system controller allowing them to operate
together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulators operate in auto PWM/PSM
mode. In this mode, the regulators operate at fixed PWM
frequency when the load current is above the PSM current
threshold. When the load current falls below the PSM current
threshold, the regulator in question enters PSM, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
Rev. A | Page 15 of 28
R2
FB3
600
VIN4
ENL DO 1
FB4
R4
VOUT4
This operating mode reduces the switching and quiescent
current losses. The auto PWM/PSM mode transition is
controlled independently for each buck regulator. The two
bucks operate synchronized to each other.
The ADP5034 has individual enable pins (EN1 to EN4) controlling the activation of each regulator. The regulators are activated
by a logic level high applied to the respective EN pin. EN1 controls
BUCK1, EN2 controls BUCK2, EN3 controls LDO1, and EN4
controls LDO2.
Regulator output voltages are set through external resistor
dividers or can be optionally factory programmed to default
values (see the
Ordering Guide section).
When a regulator is turned on, the output voltage ramp rate is
controlled though a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
09703-005
Page 16
ADP5034 Data Sheet
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators. Extreme
junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the regulators do not return to operation until the on-chip
temperature drops below 130°C. When coming out of thermal
shutdown, all regulators restart with soft start control.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated into the system. If the input
voltage on VIN1 drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channels, both the power
switch and the synchronous rectifier turn off. When the voltage
on VIN1 rises above the UVLO threshold, the part is enabled
once more.
AVIN
VOUT1
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for USB applications. For these
models, the device reaches the turn-off threshold when the
input supply drops to 3.65 V typical.
In case of a thermal or UVLO event, the active pull-downs (if
factory enabled) are enabled to discharge the output capacitors
quickly. The pull-down resistors remain engaged until the
thermal fault event is no longer present or the input supply
voltage falls below the V
V
is approximately 1 V.
POR
voltage level. The typical value of
POR
Enable/Shutdown
The ADP5034 has an individual control pin for each regulator.
A logic level high applied to the ENx pin activates a regulator,
whereas a logic level low turns off a regulator.
Figure 46 shows the regulator activation timings for the
ADP5034 when all enable pins are connected to AVIN. Also
shown is the active pull-down activation.
V
UVLO
V
POR
VOUT3
VOUT4
30µs
(MIN)
AVIN
50µs (MIN)
)
09703-006
VOUT2
BUCK1,
LDO1,
LDO2
PULL-DOWNS
BUCK2
PULL-DOWN
30µs
(MIN)
50µs (MIN)
Figure 46. Regulator Sequencing on the ADP5034 (
EN1 = EN2 = EN3 = EN4 = V
Rev. A | Page 16 of 28
Page 17
Data Sheet ADP5034
BUCK1 AND BUCK2
The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
The buck output voltage is set through external resistor
dividers, shown in Figure 47 for BUCK1. The output voltage
can optionally be factory programmed to default values as
indicated in the Ordering Guide section. In this event, R1 and
R2 are not needed, and FB1 can be left unconnected. In all
cases, VOUT1 must be connected to the output capacitor. FB1
is 0.5 V.
VIN1
BUCK
V
= V
OUT1
FB1
Figure 47. BUCK1 External Output Voltage Setting
Control Scheme
The bucks operate with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a power save mode (PSM) control scheme at light
loads to lower the regulation power losses. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted and regulates the output voltage. When
operating in PSM at light loads, the output voltage is controlled
in a hysteretic manner, with higher output voltage ripple. During
part of this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz
set by an internal oscillator. At the start of each oscillator cycle,
the pFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the pFET switch and turns on the nFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Power Save Mode (PSM)
The bucks smoothly transition to PSM operation when the load
current decreases below the PSM current threshold. When
either of the bucks enters PSM, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level approximately 1.5% above the
PWM regulation level, PWM operation is turned off. At this
point, both power switches are off, and the buck enters an idle
mode. The output capacitor discharges until the output voltage
falls to the PWM regulation voltage, at which point the device
VOUT1
L1
1µH
SW1
FB1
AGND
R1
+ 1
R2
R1
R2
C5
10µF
VOUT1
09703-008
Rev. A | Page 17 of 28
drives the inductor to make the output voltage rise again to the
upper threshold. This process is repeated while the load current
is below the PSM current threshold.
The ADP5034 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE
pin forces both bucks to operate in PWM mode. A logic level
low sets the bucks to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to100 mA. The bucks employ
a scheme that enables this current to remain accurately
controlled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from the PSM.
The PSM current threshold is optimized for excellent efficiency
over all load currents.
Oscillator/Phasing of Inductor Switching
The ADP5034 ensures that both bucks operate at the same
switching frequency when both bucks are in PWM mode.
Additionally, the ADP5034 ensures that when both bucks are in
PWM mode, they operate out of phase, whereby the Buck2
pFET starts conducting exactly half a clock period after the
BUCK1 pFET starts conducting.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is
reduced to half the internal oscillator frequency. The reduction
in the switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
Current Limit
Each buck has protection circuitry to limit the amount of
positive current flowing through the pFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a drop in input voltage, or with an increase in load
current, the buck may reach a limit where, even with the pFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the pFET switch stays on 100% of the time. When
Page 18
ADP5034 Data Sheet
V
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
Active Pull-Downs
All regulators have optional, factory programmable, active pulldown resistors discharging the respective output capacitors
when the regulators are disabled. The pull-down resistors are
connected between VOUTx and AGND. Active pull-downs are
disabled when the regulators are turned on. The typical value of
the pull-down resistor is 600 for the LDOs and 75 for the
bucks. Figure 46 shows the activation timings for the active
pull-downs during regulator activation and deactivation.
LDO1 AND LDO2
The ADP5034 contains two LDOs with low quiescent current
and low dropout linear regulators, and provides up to 300 mA
of output current. Drawing a low 10 A quiescent current
(typical) at no load makes the LDO ideal for battery-operated
portable equipment.
Each LDO operates with an input voltage of 1.7 V to 5.5 V. The
wide operating range makes these LDOs suitable for cascading
configurations where the LDO supply voltage is provided from
one of the buck regulators.
Each LDO output voltage is set through external resistor dividers
as shown in Figure 48 for LDO1. The output voltage can optionally be factory programmed to default values as indicated in the
Ordering Guide section. In this event, Ra and Rb are not needed,
and FB3 must be connected to the top of the capacitor on VOUT3.
IN3
LDO1
V
= V
OUT3
FB3
Figure 48. LDO1 External Output Voltage Setting
VOUT3
Ra
FB3
Rb
Ra
+ 1
Rb
C7
1µF
VOUT3
09703-009
The LDOs also provide high power supply rejection ratio
(PSRR), low output noise, and excellent line and load transient
response with only a small 1 µF ceramic input and output
capacitor.
LDO1 is optimized to supply analog circuits because it offers
better noise performance compared to LDO2. LDO1 should be
used in applications where noise performance is critical.
Rev. A | Page 18 of 28
Page 19
Data Sheet ADP5034
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Feedback Resistors
For the adjustable model, referring to Figure 49 the total
combined resistance for R1 and R2 is not to exceed 400 kΩ.
Inductor
The high switching frequency of the ADP5034 bucks allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 H and 3 H. Suggested inductors
are shown in Ta bl e 8 .
The peak-to-peak inductor current ripple is calculated using
the following equation:
VVV
−×
I
RIPPLE
)(
OUT
LfV
××
2
IN
I
RIPPLE
OUT
=
IN
SW
where:
f
is the switching frequency.
SW
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
II+=
PEAK
)(
MAXLOAD
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the bucks are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for
its low core losses and low EMI.
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are
not recommended for use with any dc-to-dc converter because
of their poor temperature and dc bias characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated using the following equation:
= C
C
EFF
× (1 − TEMPCO) × (1 − TOL)
OUT
where:
is the effective capacitance at the operating voltage.
C
EFF
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
is 9.2 F at 1.8 V, as shown in Figure 49.
OUT
Substituting these values in the equation yields
C
= 9.2 F × (1 − 0.15) × (1 − 0.1) ≈ 7.0 F
EFF
To guarantee the performance of the bucks, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
V
RIPPLE
I
RIPPLE
=
SW
≈
××
Cf
()
OUT
V
IN
SW
2
28
×××π
CLf
OUT
Capacitors with lower effective series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
V
ESR≤
COUT
RIPPLE
I
RIPPL
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.
The buck regulators require 10 µF output capacitors to guarantee stability and response to rapid load variations and to transition
into and out of the PWM/PSM modes. A list of suggested capacitors is shown in Tabl e 9. In certain applications where one or
both buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 50).
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
VVV
)(
−
IN
CIN
II
≥
MAXLOAD
OUT
)(
OUT
V
IN
AVI N
C
AVIN
0.1µF
OFF
OFF
4.7µF
4.7µF
ON
VIN1
C1
ON
VIN2
C2
ON
VIN3
C3
1µF
VIN4
C4
1µF
2.3V TO
1.7
5.5V
5.5V
TO
OFF
Figure 50. Processor System Power Management with PSM/PWM Control
EN1
EN2
EN3
EN4
HOUSEKEEPING
EN1
EN2
EN3
EN4
ADP5034
BUCK1
MODE
MODE
BUCK2
LDO1
(ANALOG)
LDO2
(DIGITAL)
To minimize supply noise, place the input capacitor as close as
possible to the VINx pin of the buck. As with the output
capacitor, a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Tabl e 9 and Tab l e 10 .
For the adjustable model, the maximum value of Rb is not to
exceed 200 kΩ (see Figure 48).
Output Capacitor
The ADP5034 LDOs are designed for operation with small, spacesaving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken with the ESR value. The
ESR of the output capacitor affects stability of the LDO control
loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω
or less is recommended to ensure that stability of the ADP5034.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP5034 to large
changes in load current.
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN3 and VIN4 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source impedance is encountered. If greater than 1 µF of output capacitance
is required, increase the input capacitor to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5034 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use
with any LDO because of their poor temperature and dc bias
characteristics.
Figure 51 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating.
In general, a capacitor in a larger package or with higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
CAPACITANCE ( µF)
0.2
0
01 2345 6
Figure 51. Capacitance vs. Voltage Characteristic
DC BIAS VOLTAGE ( V)
09703-012
Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature,
component tolerance, and voltage:
C
= C
EFF
× (1 − TEMPCO) × (1 − TOL)
BIAS
where:
C
is the effective capacitance at the operating voltage.
BIAS
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
is 0.85 F at 1.8 V as shown in Figure 51.
BIAS
Substituting these values into the following equation,
= 0.85 F × (1 − 0.15) × (1 − 0.1) = 0.65 F
C
EFF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5034, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Rev. A | Page 21 of 28
Page 22
ADP5034 Data Sheet
P
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The ADP5034 is a highly efficient µPMU, and, in most cases,
the power dissipated in the device is not a concern. However,
if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach
the maximum allowable operating limit (125°C).
When the temperature exceeds 150°C, the ADP5034 turns off
all the regulators, allowing the device to cool down. When the
die temperature falls below 130°C, the ADP5034 resumes
normal operation.
This section provides guidelines to calculate the power dissipated in the device and ensure that the ADP5034 operates
below the maximum allowable junction temperature.
The efficiency for each regulator on the ADP5034 is given by
OUT
η
100%×=
P
IN
(1)
where:
η is the efficiency.
P
is the input power.
IN
P
is the output power.
OUT
Power loss is given by
P
= PIN − P
LOSS
(2a)
OUT
or
P
= P
LOSS
(1− η)/η (2b)
OUT
Power dissipation can be calculated in several ways. The most
intuitive and practical is to measure the power dissipated at the
input and all the outputs. Perform the measurements at the
worst-case conditions (voltages, currents, and temperature).
The difference between input and output power is dissipated in
the device and the inductor. Use Equation 4 to derive the power
lost in the inductor and, from this, use Equation 3 to calculate
the power dissipation in the ADP5034 buck converter.
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, and the power
lost on each LDO can be calculated using Equation 12. When
the buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor, use Equation 4 to
derive the power lost in the inductor, and then calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the two LDOs to find
the total dissipated power.
Note that the buck efficiency curves are typical values and may
, V
not be provided for all possible combinations of V
To account for these variations, it is necessary to include a
I
OUT.
, and
IN
OUT
safety margin when calculating the power dissipated in the buck.
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDO provided
by Equation 12.
BUCK REGULATOR POWER DISSIPATION
The power loss of the buck regulator is approximated by
P
= P
LOSS
where:
P
is the power dissipation on one of the ADP5034 buck
DBUCK
regulators.
P
is the inductor power losses.
L
The inductor losses are external to the device, and they do not
have any effect on the die temperature.
The inductor losses are estimated (without core losses) by
P
≈ I
L
OUT1(RMS)
where:
DCRL is the inductor series resistance.
I
where
is the rms load current of the buck regulator.
OUT1(RMS)
r is the normalized inductor ripple current.
r = V
OUT1
where:
L is the inductance.
f
is the switching frequency.
SW
is the duty cycle.
D
= V
D
ADP5034 buck regulator power dissipation, P
power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but
these are generally less significant at high output load currents,
where the thermal limit of the application is. Equation 8
captures the calculation that must be made to estimate the
power dissipation in the buck regulator.
P
DBUCK
The power switch conductive losses are due to the output current,
, flowing through the P-MOSFET and the N-MOSFET
I
OUT1
power switches that have internal resistance, RDS
RDS
where
. The amount of conductive power loss is found by
ON-N
P
= [RDS
COND
RDS
mately 0.16 Ω at 125°C junction temperature and VIN1 = VIN2 =
3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 Ω and
0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are
0.16 Ω and 0.14 Ω, respectively.
+ PL (3)
DBUCK
2
× DCRL (4)
II
OUT1
)(1
RMSOUT
× (1 − D)/(I
OUT1/VIN1
= P
ON-P
(7)
+ PSW + P
COND
× D + RDS
ON-P
is approximately 0.2 Ω, and RDS
r
×=(5)
+1
12
× L × fSW) (6)
OUT1
, includes the
DBUCK
(8)
TRAN
and
ON-P
× (1 − D)] × I
ON-N
OUT1
is approxi-
ON-N
2
(9)
Rev. A | Page 22 of 28
Page 23
Data Sheet ADP5034
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
P
SW
= (C
GATE-P
+ C
GATE-N
) × V
IN1
2
× f
SW
(10)
where:
C
is the P-MOSFET gate capacitance.
GATE-P
C
is the N-MOSFET gate capacitance.
GATE-N
C
For the ADP5034, the total of (
GATE-P
+ C
GATE-N
) is
approximately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
V
OUT1
(and from V
to ground). The amount of transition
OUT1
loss is calculated by
P
= V
× I
× (t
+ t
where
TRAN
t
RISE
and t
IN1
OUT1
are the rise time and the fall time of the
FALL
RISE
FALL
) × f
SW
(11)
switching node, SW. For the ADP5034, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations
do not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by
P
= [(VIN − V
DLDO
OUT
) × I
] + (VIN × I
LOAD
) (12)
GND
where:
I
is the load current of the LDO regulator.
LOAD
V
and V
IN
are input and output voltages of the LDO,
OUT
respectively.
I
is the ground current of the LDO regulator.
GND
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the ADP5034 simplifies to
P
D
= P
DBUCK1
+ P
DBUCK2
+ P
DLDO1
+ P
(13)
DLDO2
JUNCTION TEMPERATURE
In cases where the board temperature, TA, is known, the
thermal resistance parameter, θ
junction temperature rise. T
the formula
T
= TA + (PD × θJA) (14)
J
The typical θ
value for the 24-lead, 4 mm × 4 mm LFCSP is
JA
35°C/W (see Tab l e 6 ). A very important factor to consider is
is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per
that θ
JA
JEDEC standard, and real applications may use different sizes
and layers. It is important to maximize the copper used to remove
the heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers. The exposed pad
should be connected to the ground plane with several vias.
If the case temperature can be measured, the junction
temperature is calculated by
T
= TC + (PD × θJC) (15)
J
T
where
is the case temperature and θJC is the junction-to-case
C
thermal resistance provided in Tabl e 6.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5034 power
dissipation (P
) due to the losses of all channels by using the
D
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
, can be estimated using Equation 14.
J
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the ADP5034 (Equation 14) is less than 125°C. Reliability and
mean time between failures (MTBF) are highly affected by increasing the junction temperature. Additional information about
product reliability can be found from the
which can be found at www.analog.com/reliability_handbook
, can be used to estimate the
JA
is calculated from TA and PD using
J
ADI Reliability Handbook,
.
Rev. A | Page 23 of 28
Page 24
ADP5034 Data Sheet
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5034 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines. Also, refer to the
UG-271 user guide.
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
• Connect VIN1, VIN2, and AVIN together close to the IC
using short tracks.
Rev. A | Page 24 of 28
Page 25
Data Sheet ADP5034
TYPICAL APPLICATION SCHEMATICS
AVI N
C
AVIN
OFF
OFF
OFF
0.1µF
4.7µF
4.7µF
C1
ON
C2
ON
C3
1µF
ON
C4
1µF
2.3V TO
1.7V TO
5.5V
5.5V
Figure 52. ADP5034 Fixed Output Voltages with Enable Pins
AVI N
C
AVIN
0.1µF
OFF
OFF
4.7µF
4.7µF
ON
VIN1
C1
ON
VIN2
C2
ON
VIN3
C3
1µF
VIN4
C4
1µF
2.3V TO
1.7V TO
5.5V
5.5V
OFF
Figure 53. ADP5034 Adjustable Output Voltages with Enable Pins
VIN1
EN1
VIN2
EN2
EN3
VIN3
EN4
VIN4
EN1
EN2
EN3
EN4
HOUSEKEEPING
BUCK1
EN1
BUCK2
EN2
EN3
(ANALOG)
EN4
(DIGITAL)
ADP5034
HOUSEKEEPING
BUCK1
EN1
MODE
MODE
BUCK2
EN2
EN3
(ANALOG)
EN4
(DIGITAL)
ADP5034
MODE
MODE
LDO1
LDO2
LDO1
LDO2
AGND
AGND
VOUT1
SW1
FB1
PGND1
MODE
VOUT2
SW2
FB2
PGND2
VOUT3
FB3
VOUT4
FB4
VOUT1
SW1
FB1
PGND1
MODE
VOUT2
SW2
FB2
PGND2
VOUT3
FB3
VOUT4
FB4
L1 1µH
PWM
L2 1µH
R3
L1 1µH
R1
R2
PWM
L2 1µH
R3
R4
R5
R6
R7
R8
C5
10µF
PSM/PWM
C6
10µF
C7
1µF
C8
1µF
C5
10µF
PSM/PWM
C6
10µF
C7
1µF
C8
1µF
V
OUT1
1200mA
V
OUT2
1200mA
V
OUT3
300mA
V
OUT4
300mA
V
OUT1
1200mA
V
OUT2
1200mA
V
OUT3
300mA
V
OUT4
300mA
@
@
@
@
9703-022
@
@
@
@
09703-023
BILL OF MATERIALS
Table 12.
Reference Value Part Number Vendor Package or Dimension (mm)
C
0.1 µF, X5R, 6.3 V JMK105BJ104MV-F Taiyo-Yuden 0402