Datasheet ADP3806JRU-12.5, ADP3806JRU, ADP3806JRU-12.6 Datasheet (Analog Devices)

High-Frequency Switch Mode

a

FEATURES
Li-Ion Battery Charger
Three Battery Voltage Options

Selectable 12.525 V/16.700 V
Selectable 12.600 V/16.800 V
Adjustable

High End-of-Charge Voltage Accuracy

0.4% @ 25C
0.6% @ 5C to 55⬚ C
0.7% @ 0C to 85C

Programmable Charge Current with Rail-to-Rail

Sensing
System Current Sense with Reverse Input Protection
Softstart Charge Current
Undervoltage Lockout
Bootstrapped Synchronous Drive for External NMOS
Programmable Oscillator Frequency
Oscillator SYNC Pin
Low Current Flag
Trickle Charge

Li-Ion Battery Charger

ADP3806

GENERAL DESCRIPTION

The ADP3806 is a complete Li-Ion battery-charging IC. The
device combines high output voltage accuracy with constant
current control to simplify the implementation of Constant­Current, Constant-Voltage (CCCV) chargers. The ADP3806 is
available in three options. The ADP3806-12.6 guarantees the
final battery voltage be selected to 12.6 V or 16.8 V ± 0.6%, the
ADP3806-12.5 guarantees 12.525 V/16.7 V ± 0.6% and the
ADP3806 is adjustable using two external resistors to set the
battery voltage. The current sense amplifier has rail-to-rail
inputs to accurately operate under low drop out and short circuit
conditions. The charge current is programmable with a dc
voltage on ISET. A second differential amplifier senses the system
current across an external sense resistor and outputs a linear
voltage on the ISYS pin. The bootstrapped synchronous driver
allows the use of two NMOS transistors for lower system cost.

APPLICATIONS
Portable Computers
Fast Chargers

BSTREG

SD

LC

VCC BST

VREF + VREG

UVLO

BIAS

LOGIC

CONTROL

ADP3806

FUNCTIONAL BLOCK DIAGRAM

DRVH DRVL

SW

BOOTSTRAPPED

SYNCHRONOUS

DRIVER

SD IN DRVLSD

VREF

PGND

DRVLSD

+

+

–

–

OSCILLATOR

CS+

CS–

+–

AMP1

–

+

+

V

–

TH

–

gm1

+

–

gm2

+

VREF

SYS+ SYS– ISYS

+–

AMP2

2.5V

SELECT

12.6/16.8

–

+

LIMIT

ISET

BAT

AGND

REG

SYNC

CT

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

COMPREF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

BATSEL

ADP3806–SPECIFICATIONS

(@ 0C ≤ TA ≤ 100C, VCC = 16 V, unless otherwise noted.)

Parameter Conditions Symbol Min Typ Max Unit

BATTERY SENSE INPUT

ADP3806-12.6 V and 16.8 V
ADP3806-12.525 V and 16.7 V

= 25°C, 13 V ⱕ VCC ⱕ 20 V V

T

A

5°C ⱕ T
0°C ⱕ T

ⱕ 55°CV

A

ⱕ 85°CV

A

Input Resistance Part in Operation R
Input Current Part in Shutdown I

BAT

BAT

BAT

BAT

BAT(SD)

–0.4 +0.4 %
–0.6 +0.6 %
–0.7 +0.7 %
250 350 kΩ

0.2 1.0 µA

BATTERY SENSE INPUT

ADP3806

= 2.5 V TA = 25°C, 13 V ⱕ VCC ⱕ 20 V V

V

BAT

0°C ⱕ T

ⱕ 85°CV

A

BAT

BAT

–0.5 +0.5 %
–0.7 +0.7 %

Input Current Operating BATSEL = Open, Part in Operation 0.2 1.0 µA
Input Current Shutdown BATSEL = 100 k to GND, Part in Shutdown 0.2 1.0 µA

OSCILLATOR

Maximum Frequency
Frequency Variation
CT Charge Current I

2

3

CT = 180 pF f

f

CT

CT

CT

1000 kHz
210 250 290 kHz
125 150 175 µA

0% Duty Cycle Threshold @ COMP Pin 1.0 V
Maximum Duty Cycle Threshold @ COMP Pin 2.5 V
SYNC Input High SYNC
SYNC Input Low SYNC
SYNC Input Current I

SYNC

2.2 V

H

L

0.8 V

0.2 1.0 µA

GATE DRIVE

On Resistance IL = 10 mA R
Rise, Fall Time C

= 1 nF, DRVL and DRVH tr , t

L

Overlap Protection Delay DRVL Falling to DRVH Rising, t

ON

f

OP

610 Ω
35 ns
50 ns

DRVH Falling to DRVL Rising
SW Bias Current Part in Shutdown, V
BST Cap Refresh Threshold V

BST

– V

SW

= 12.6 V 0.2 1.0 µA

SW

3.7 V

CURRENT SENSE AMPLIFIER

Input Common-Mode Range V
Input Differential Mode Range V
Input Offset Voltage

5

Gain

5

Input Bias Current 0 V ⱕ V
Input Offset Current 0 V ⱕ V

and V

CS+

4

CS

0 V ⱕ V

CS–

ⱕ VCC V

CS(CM)

ⱕ VCC, Part in Operation V

CS(CM)

ⱕ VCC V

CS(CM)

V

CS(CM)

V

CS(DM)

CS(VOS)

CS(IB)

CS(IOS)

0.0 VCC + 0.3 V

0.0 160 mV

1.0 mV
25 V/V
50 100 µA

1.0 2.0 µA

Input Bias Current Part in Shutdown 0.2 1.0 µA
DRVL Shutdown Threshold Measured between V

SYSTEM CURRENT SENSE

6

Input Common-Mode Range SYS+ and SYS–, IL = 0 mA, V
Input Differential Range (V

SYS+

) – (V

)V

SYS–

CS+

and V

CS-

= 3 V V

ISYS

V

CS(SD)

SYS(CM)

SYS(DM)

48 mV

4.0 VCC + 0.3 V

0 100 mV
Input Offset Voltage 0.5 mV
Input Bias Current, SYS+ V
Input Bias Current, SYS- V
Voltage Gain 10 V ⱕ V
Output Range I

L

Limit Output Threshold V
Limit Output Voltage V

= 0 V, V

SYS(DM)

= 0 V, V

SYS(DM)

= 1 mA7, V

ⱕ 0.2 V, 50 kΩ Pull-up to 5 V V

LIMIT

> 2.65 V, I

ISYS

ⱕ VCC + 0.3 V, IL = 100 µA 48.5 50 51.5 V/V

SYS(CM)

SYS(CM)

SINK

= 16 V I

SYS(CM)

= 16 V I

SYS(CM)

> 6 V V

= 700 µAV

B(SYS+)

B(SYS–)

ISYS

TH(LIMIT)

O(LIMIT)

200 300 µA
70 125 µA

0 5.0 V

2.3 2.5 2.7 V

0.1 0.2 V

–2–

REV. 0

ADP3806

Parameter Conditions Symbol Min Typ Max Unit

ISET INPUT

Charge Current Programming

Function 0.0 V ⬍ V

Programming Function Accuracy V

= 4.0 V, 1 V ≤ V

ISET

V

= 0.50 V, 1 V ⱕ V

ISET

ISET Bias Current 0.0 V ⱕ V

ⱕ 4.0 V V

ISET

ⱕ 4.0 V I

ISET

ⱕ 16 V–5±1.0 +5 %

CS(CM)

ⱕ 10 V –30 ± 10 +30 %

CS(CM)

ISET/VCS

B

BATSEL INPUT

V

= 12.6 V 2.0 V

BAT

V

= 16.8 V 0.8 V

BAT

BATSEL Input Current 0.2 5.0 µΑ

BOOST REGULATOR

OUTPUT
Output Voltage C
Output Current

10

= 0.1 µFV

L

BSTREG

I

BSTREG

6.8 7.0 7.2 V

3.0 5.0 mA

ANALOG REGULATOR

OUTPUT
Output Voltage C
Output Current

10

= 10 nF V

L

I

REG

REG

5.8 6.0 6.2 V

3.0 5.0 mA

PRECISION REFERENCE

OUTPUT
Output Voltage V
Output Current

10

I

REF

REF

2.47 2.5 2.53 V

0.5 1.1 mA

SHUTDOWN (SD)

ON SD
OFF SD

H

L

2.0 V

SD Input Current 0.2 1.0 µA

POWER SUPPLY

ON Supply Current No External Loads, UVLO ⱕ VCC ⱕ 20 V I
OFF Supply Current No External Loads, VCC ⱕ 20 V I
UVLO

Threshold Voltage Turn On V

SYON

SYOFF

UVLO

5.65 6.0 6.25 V

UVLO Hysteresis Turn Off 0.1 0.3 0.5 V

LC OUTPUT

Output Voltage Low High Current Mode8, I
Output Voltage High Low Current Mode

9

= 100 µA 0.1 0.4 V

SINK

OUTPUT REVERSE

LEAKAGE PROTECTION
Leakage Current VCC = Floating, V

= 12.6 V I

BAT

DISCH

OVERCURRENT

COMPARATOR
Overcurrent Threshold V
Response Time VCS > 180 mV to COMP < 1 V t

CS(OC)

OC

OVERVOLTAGE COMPARATOR

Overvoltage Threshold V
Response Time V

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Guaranteed by design, not tested in production.

3

If SYNC function is used, then f

4

VCS = (V

5

Accuracy guaranteed by ISET INPUT, Programming Function Accuracy specification.

6

System current sense is active during shutdown.

7

Load current is supplied through SYS+ pin.

8

V

BAT

9

V

BAT

10

Guaranteed Output Current from 0 to Min specified value to maintain regulation.

Specifications subject to change without notice.

) – (V

CS–

).

CS+

⬍ 93% of final or VCS ⬎ 25 mV.
ⱖ 93% of final and VCS ⱕ 25 mV.

must be greater than fCT, but less than 120% of fCT.

SYNC

> 120% to COMP < 1 V t

BAT

BAT(OV)

OV

25 V/V

0.2 1.0 µA

0.8 V

6.0 8.0 mA

1.0 5.0 µA

External V

15 µA

180 mV
2 µs

120 %
2 µs

REV. 0

–3–

ADP3806

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Input Voltage (VCC) . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

BAT, CS+, CS– . . . . . . . . . . . . . . . . . .

–0.3 V to VCC +0.3 V

SYS+, SYS– . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V to +25 V

BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to +25 V

DRVL to PGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

ISET, BATSEL, SD, SYNC, CT,

LIMIT, ISYS, LC . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V

COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3 V

GND to PGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Operating Ambient Temperature Range . . . . . . 0°C to 100°C

θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W

Operating Junction Temperature Range . . . . . . 0°C to 125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

*This is a stress rating only, operation these limits can cause the device to be

permanently damaged. Unless otherwise specified, all voltages are referenced to
GND. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

ORDERING GUIDE

Battery Package Package

Model Voltage Description Option

ADP3806JRU Adjustable TSSOP-24 RU-24
ADP3806JRU-12.5 12.525 V/ TSSOP-24 RU-24

16.7 V

ADP3806JRU-12.6 12.600 V/ TSSOP-24 RU-24

16.8 V

PIN CONFIGURATION

24-Lead TSSOP

VCC

SYS–

SYS+

ISYS

LIMIT

SYNC

REG

REF

COMP

CT

SD

LC

1

2

3

4

5

ADP3806

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

SW

DRVH

BST

BSTREG

DRVL

PGND

CS+

CS–

ISET

BATSEL

BAT

AGND

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1 VCC Supply Voltage
2 SYS– Negative System Current Sense Input
3 SYS+ Positive System Current Sense Input
4 ISYS System Current Sense Output
5 LIMIT System Current Sense Limit Output
6 CT Oscillator Timing Capacitor
7 SYNC Oscillator Synchronization Pin
8 REG 6.0 V Analog Regulator Output
9 REF 2.5 V Precision Reference Output
10 SD Shutdown Control Input
11 COMP External Compensation Node
12 LC Low Current Output
13 AGND Analog Ground
14 BAT Battery Sense Input.

2.5 V for ADP3806,

12.525 V/16.7 V for ADP3806-12.5,
or 12.6 V/16.8 V for ADP3806-12.6

15 BATSEL Battery Voltage Sense Input

High = 3 Cells, Low = 4 Cells
16 ISET Charge Current Program Input
17 CS– Negative Current Sense Input
18 CS+ Positive Current Sense Input
19 PGND Power Ground
20 DRVL Low Drive Output switches between

REG and PGND
21 BSTREG 7.0 V Regulator Output for Boost
22 BST Floating Bootstrap Supply for DRVH
23 DRVH High Drive Output switches between

SW and BST
24 SW Buck Switching Node Reference

for DRVH

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3806 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

Typical Performance Characteristics–ADP3806

–0.10

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

0.10

5 101520

VCC – V

T

A

= 25C

V

REF

ACCURACY – %

4.0

4.4

4.8

5.2

5.6

6.0

10 12 14 16 18 20

VCC – V

NO LOADS

TA = 25C

TA = 100C

TA = 0C

ON SUPPLY CURRENT – mA

30

25

20

15

10

NUMBER OF PARTS

5

0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5

ACCURACY – %

V

BAT

ACCURACY – %

BAT

V

TPC 1. V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

Accuracy Distribution

BAT

VCC = 16V

TA = 25C

VCC = 16V

0.5

0.4

0.3

0.2

0.1

0

–0.1

ACCURACY – %

REF

–0.2

V

–0.3

–0.4

–0.5

0 20 40 60 80 100

TPC 4. V

TEMPERATURE –

Accuracy vs. Temperature

REF

VCC = 16V



C

–0.4

0 20 40 60 80 100

TPC 2. V

0.10

0.05

0

ACCURACY – %

BAT

V

–0.05

REV. 0

–0.10

10

TPC 3. V

BAT

TEMPERATURE –

Accuracy vs. Temperature

BAT

12

14 16 18 20

VCC – V

Accuracy vs. Supply Voltage



C

T

= 25C

A

TPC 5. V

Accuracy vs. VCC

REF

TPC 6. ON Supply Current vs. VCC

–5–

ADP3806

18

VCC = 16V
T

= 25C

16

A

f

= 250kHz

OSC

14

12

10

8

6

SUPPLY CURRENT – mA

4

2

0

500 1000 1500 2000 2500 3000 3500

0

DRIVER LOAD CAPACITANCE – pF

TPC 7. Supply Current vs. Driver Load Capacitance

1.0

0.8

TA = 100C

0.6

0.4
TA = 25C

6

ISYS

VCC = 16V
T

= 25C

A

50k TO 5V

5

4

– Volts

3

50k TO 2.5V

LIMIT

V

2

1

0

2.0 2.2 2.4 2.6 2.8 3.0 3.2

TPC 10. V

10

VCC = 16V

8

6

4

V

– V

ISYS

vs. V

LIMIT

DRIVER SOURCING

DRIVER SINKING

OFF SUPPLY CURRENT – A

0.2

0

10.0 12.5 15.0 17.5 20.0

VCC – V

TA = 0C

TPC 8. OFF Supply Current vs. VCC

600

500

400

300

200

FREQUENCY – kHz

100

0

0 200 400 600 800

CT – pF

VCC = 16V
T

= 25C

A

TPC 9. Oscillator Frequency vs. CT

DRIVER ON RESISTANCE – 

2

0

0 20406080100

TEMPERATURE –



C

TPC 11. Driver On-Resistance vs. Temperature

= 16V

V

DRVH
5V/DIV

DRVL 5V/DIV

CC

= 25C

T

A

FIGURE 1

200ns/DIV

TPC 12. Driver Waveforms

–6–

REV. 0

100

1.00

2

V

O

EFFICIENCY

4 6 8 10 12 14

0.95

0.90

0.85

0.80

0.75

0.70

19VIN 85C

19VIN 0C

98

96

94

92

90

88

86

CONVERSION EFFICIENCY – %

84

82

80

0.1 1 10
CHARGE CURRENT – Amps

VCC = 19V
V

= 12.4V

BAT

= 25C

T

A

FIGURE 1

TPC 13. Conversion Efficiency vs. Charge Current

96

I

94

92

CHARGE

= 2A

I

CHARGE

= 3A

ADP3806

TPC 15. Conversion Efficiency vs. Battery Voltage at
Temperatures

90

88

86

CONVERSION EFFICIENCY – %

84

82

3

5678910111213

4

– V

V

BAT

VCC = 19V
T

= 25C

A

FIGURE 1

TPC 14. Conversion Efficiency vs. Battery Voltage

REV. 0

–7–

ADP3806

THEORY OF OPERATION

The ADP3806 combines a bootstrapped synchronous switching
driver with programmable current control and accurate final
battery voltage control in a Constant Current, Constant Voltage
(CCCV) Li-Ion battery charger. High accuracy voltage control
is needed to safely charge Li-Ion batteries, which are typically
specified at 4.2 V ± 1% per cell. For a typical notebook computer
battery pack, three or four cells are in series giving a total voltage
of 12.6 V or 16.8 V. The ADP3806 is available in three versions,
a selectable 12.525 V/16.7 V output, a selectable 12.6 V/16.8 V
output, and an adjustable output. The adjustable output can be
programmed for a wide range of battery voltages using two
external precision resistors.

Another requirement for safely charging Li-Ion batteries is
accurate control of the charge current. The actual charge
current depends on the number of cells in parallel within the
battery pack. Typically this is in the range of 2 A to 3 A. The
ADP3806 provides flexibility in programming the charge
current over a wide range. An external resistor is used to
sense the charge current and this voltage is compared to a
DC input voltage. This programmability allows the current
to be changed during charging. For example, the charge
current can be reduced for trickle charging.

VIN

C14

2.2F

R13

10

VCC

1/2 Q1

FD56990A

+

C15

22F

–

C9

100nF

DRVH DRVL

BST

SW

PGND

1/2 Q1
FD56990A

L1

22H

22F

C16

+

–

CS+

The synchronous driver provides high efficiency when charg­ing at high currents. Efficiency is important mainly to reduce
the amount of heat generated in the charger, but also to stay
within the power limits of the AC adapter. With the addition
of a bootstrapped high side driver, the ADP3806 drives two
external power NMOS transistors for a simple, lower cost
power stage.

The ADP3806 also provides an uncommitted current sense
amplifier. This amplifier provides an analog output pin for
monitoring the current through an external sense resistor. The
amplifier can be used anywhere in the system that high side
current sensing is needed.

Charge Current Control

AMP1 in Figure 1 has a differential input to amplify the voltage
drop across an external sense resistor R

. The input common

CS

mode range is from ground to VCC allowing current control in
short circuit and low drop-out conditions. The gain of AMP1 is
internally set to 25 V/V for low voltage drop across the sense
resistor. During CC mode, g

1 forces the voltage at the output

m

of AMP1 to be equal to the external voltage at the ISET pin.
By choosing R

and V

CS

appropriately, a wide range of charge

ISET

currents can be programmed:

V

R

40m

R3
249

C13

22nF

I

CS

CS–

CHARGE

R4
249

470nF

C1

SYS+

ISET

=

R

×25

CS

R

SS

10m

R1

2.2

SYS–

R2

2.2

C2
470nF

ISYS

SYSTEM

DC/DC

BATTERY

12.6V/16.8V

(1)

BOOTSTRAPPED

SYNCHRONOUS

DRIVER

SD IN DRVLSD

C17

100nF

REG

6.0V

VREF

REF

2.5V

VREF + VREG

CONTROL

ADP3806

AGND

UVLO

BIAS

LOGIC

BSTREG

7.0V
C10

0.1F

SD

LC

**R7

100k

*ADP3806-12.6, ADP3806-12.5: R11 = SHORT, R12 = OPEN;
ADP3806, R11 = 412k, R12 = 102k, R14 = OPEN.
**R7, OPEN IF LC FUNCTION IS NOT USED.

SYNC

C7
200pF

AMP1

DRVLSD

–

+

VTH

–

+

–

OSCILLATOR

CT

C6

180pF

COMP

0.22F

gm1

+

–

gm2

+

VREF

C8

R8
56

Figure 1. Typical Application

– +

–+

AMP2

*R12

102k

0.1%

2.5V

SELECT

12.6/16.8

–

+

BATSEL

*R14
0

R5

6.81k

LIMIT

ISET

BAT

7.5k

*R11
412k

0.1%

R6

–8–

REV. 0

ADP3806

Typical values of RCS are in the range from 25 mΩ to 50 mΩ,
and the input range of ISET is from 0 V to 4 V. If, for example,
a 3 A charger is required, R
The power dissipation in R
this example, the power is a maximum of 360 mW. Once R

could be set to 40 mΩ and V

CS

should be kept below 500 mW. In

CS

ISET

= 3 V.

CS

has been chosen, the charge current can be adjusted during
operation with V

. Lowering V

ISET

to 125 mV gives a charge

ISET

current of 125 mA for trickle charging. Components R3, R4,
and C13 provide high-frequency filtering for the current sense signal.

Final Battery Voltage Control

As the battery approaches its final voltage, the ADP3806
switches from CC mode to CV mode. The change is achieved
by the common output node of g

1 and gm2. Only one of the

m

two outputs controls the voltage at the COMP pin. Both ampli­fiers can only pull down on COMP, such that when either
amplifier has a positive differential input voltage, its output is
not active. For example, when the battery voltage, V
g

2 does not control V

m

the desired final voltage, g

. When the battery voltage reaches

COMP

2 takes control of the loop, and the

m

BAT

, is low,

charge current is reduced.

Amplifier g

2 compares the battery voltage to the internal refer-

m

ence voltage of 2.5 V. In the case of the ADP3806-12.5 and
ADP3806-12.6, an internal resistor divider sets the selectable
final battery voltage.

When BATSEL is high, the final battery voltage is set to three
cells (12.6 V or 12.525 V). BATSEL can be tied to REG for this
state. When BATSEL is tied to ground, VBAT equals four cells
(16.8 V or 16.7 V). BATSEL has a 2

µΑ

pull-up current as a

fail-safe to select three cells when it is left open.

The reference and internal resistor divider are referenced to the
AGND pin, which should be connected close to the negative
terminal of the battery to minimize sensing errors.

In contrast, the ADP3806 requires external, precision resistors.
The divider ratio should be set to divide the desired final voltage
down to 2.5 V at the BAT pin:

R

V

11

R

12 2 51=.

BATTERY

–

V

(2)

These resistors should have a parallel impedance of approxi­mately 80 kΩ to minimize bias current errors. When the
ADP3806 is in shutdown, an internal switch disconnects the
BAT pin as shown in Figure 2. This disconnects the resistor,
R11 from the battery and minimizes leakage. The resistance of
the internal switch is less than 200 Ω.

ADP3806

g

m

2

SD

VREF

BATSEL

R12
102k

0.1%

BAT

R11
412k

0.1%
BATTERY

Figure 2. Battery Sense Disconnect Circuit

Oscillator and PWM

The oscillator generates a triangle waveform between 1 V and

2.5 V, which is compared to the voltage at the COMP pin,
setting the duty cycle of the driver stage. When V

COMP

is below
1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches
its maximum.

SD

DRVLSD

ADP3806

BOOTSTRAPPED SYNCHRONOUS DRIVER

MIN

IN

OFF

TIME

–

CMP1
+

1V

Figure 3. Bootstrapped Synchronous Driver

DELAY

DELAY

BSTREG

CMP3

CMP2

BST

CBST

DRVH

+

–

SW

–

+

1V

DRVL

PGND

Q1

Q2

REV. 0

–9–

ADP3806

The oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 µA according to
the following formula:

A

150

f

OSC

=

22 15

µ

CV

××

..

T

(3)

A 180 pF capacitor sets the frequency to 250 kHz. The fre­quency can also be synchronized to an external oscillator by
applying a square wave input on SYNC. The SYNC function is
designed to allow only increases in the oscillator frequency. The
f

should be no more than 20% higher than f

SYNC

. The duty

OSC

cycle of the SYNC input is not important and can be anywhere
between 5% and 95%.

7 V Bootstrap Regulator

The driver stage is powered by the internal 7 V bootstrap
regulator, which is available at the BSTREG pin. Because the
switching currents are supplied by this regulator, decoupling
must be added. A 0.1 µF capacitor should be placed close
to the ADP3806, with the ground side connected close to the
power ground pin, PGND. This supply is not recommended for
use externally due to high switching noise.

Bootstrapped Synchronous Driver

The PWM comparator controls the state of the synchronous
driver shown in Figure 3. A high output from the PWM com­parator forces DRVH on and DRVL off. The drivers have an
ON resistance of approximately 6 Ω for fast rise and fall times
when driving external MOSFETs. Furthermore, the bootstrapped
drive allows an external NMOS transistor for the main switch
instead of a PMOS. An external boost diode should be con­nected between BSTREG and BST, and a boost capacitor of

0.1 µF must be added externally between BST and SW. The
voltage between BST and SW is typically 6.5 V.

The DRVL pin switches between BSTREG and PGND. The
7 V output of BSTREG drives the external NMOS with high
VGS to lower the ON resistance. PGND should be connected
close to the source pin of the external synchronous NMOS.
When DRVL is high, this turns on the lower NMOS and pulls
the SW node to ground. At this point, the boost capacitor is
charged up through the boost diode. When the PWM switches
high, DRVL is turned off and DRVH turns on. DRVH switches
between BST and SW. When DRVH is on, the SW pin is
pulled up to the input supply (typically 16 V), and BST rises
above this voltage by approximately 6.5 V.

Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to the
inductor current. The ADP3806 monitors the SW voltage, and
DRVL goes high to turn on the lower MOSFET when SW goes
below 1 V. When DRVL turns off, an internal timer adds a delay
of 50 ns before turning DRVH on.

When the charge current is low, the DRVLSD comparator
signals the driver to turn off the low side MOSFET and DRVL
is held low. As shown in Figure 1, the DRVLSD comparator
looks at the output of AMP1. The DRVLSD threshold is set to 1.2 V,
corresponding to 48 mV differential voltage between the CS pins.

The driver stage monitors the voltage across the BST cap with
CMP3. When this voltage is less than 4 V, CMP3 forces a mini­mum offtime of 200 ns. This ensures that the BST cap is charged
even during DRVLSD. However, because a minimum off time is only
forced when needed, the maximum duty cycle is greater than 99%.

2.5 V Precision Reference

The voltage at the BAT pin is compared to an internal preci­sion, low temperature drift reference of 2.5 V. The reference is
available externally at the REF pin. This pin should be bypassed
with a 100 pF capacitor to the analog ground pin, AGND. The
reference can be used as a precision voltage externally. However,
the current draw should not be greater than 100 µA, and noisy,
switching type loads should not be connected.

6 V Regulator

The 6 V regulator supplies power to most of the analog circuitry
on the ADP3806. This regulator should be bypassed to AGND
with a 0.1 µF capacitor. This reference has a 3 mA source capa-
bility to power external loads if needed.

LC

The ADP3806 provides a low current (LC) logic output to signal
when the current sense voltage (V

) is below a fixed threshold

CS

and the battery voltage is greater than 95%. LC is an open drain
output that is pulled low when V

is above the threshold. When

CS

the low current threshold condition is reached, LC is pulled
high by an external resistor to REF or another appropriate
pull-up voltage. To determine when LC goes low, an internal
comparator senses when the current falls below 12.5% of full
scale (20 mV across the CS pins). The comparator has hysteresis
to prevent oscillation around the trip point.

To prevent false triggering (such as during soft-start), the com­parator is only enabled when the battery voltage is within 5% of
its final voltage. As the battery is charging up, the comparator
will not go low even if the current falls below 12.5% as long as
the battery voltage is below 95% of full scale. Once the battery
has risen above 95%, the comparator is enabled. This pin can be
used to indicate the end of the charge process.

System Current Sense

An uncommitted differential amplifier is provided for additional
high side current sensing. This amplifier, AMP2, has a fixed gain
of 50 V/V from the SYS+ and SYS– pins to the analog output at
ISYS. ISYS has a 1 mA source capability to drive an external
load. The common-mode range of the input pins is from 4 V to
VCC. This amplifier is the only part of the ADP3806 that
remains active during shutdown. The power to this block is
derived from the bias current on the SYS+ and SYS– pins.

A separate comparator at the LIMIT pin signals when the voltage
on the ISYS pin exceeds 2.5 V typically. The internal comparator
has an open drain output, which produces the function shown in
the TPC 10 graph of V

LIMIT

versus V

. The LIMIT pin

ISYS

should be externally pulled up to 5 V, 2.5 V, or other voltage as
needed through a resistor. This graph was taken with a 50 kΩ
pull-up resistor to 5 V and to 2.5 V. When ISYS is below 2.4 V,
the LIMIT pin has high output impedance. The open drain
output is capable of sinking 700 µA when the threshold is
exceeded. This comparator is turned off during shutdown to
conserve power.

–10–

REV. 0

ADP3806

Shutdown

A high impedance CMOS logic input is provided to turn off
the ADP3806. When the voltage on SD is less than 0.8 V, the
ADP3806 is placed in low power shutdown. With the exception
of the system current sense amplifier, AMP2, all other circuitry
is turned off. The reference and regulators are pulled to ground
during shutdown and all switching is stopped. During this state,
the supply current is less than 5 µA. Also, the BAT, CS+, CS–,
and SW pins go to high impedance to minimize current drain
from the battery.

UVLO

Under-Voltage Lock-Out, UVLO, is included in the ADP3806
to ensure proper start-up. As VCC rises above 1 V, the refer­ence and regulators will track VCC until they reach their final
voltages. However, the rest of the circuitry is held off by the
UVLO comparator. The UVLO comparator monitors both
regulators to ensure that they are above 5 V before turning on
the main charger circuitry. This occurs when VCC reaches 6 V.
Monitoring the regulator outputs makes sure that the charger
circuitry and driver stage have sufficient voltage to operate nor­mally. The UVLO comparator includes 300 mV of hysteresis to
prevent oscillations near the threshold.

Startup Sequence

During a startup from either SD going high or VCC exceed­ing the UVLO threshold, the ADP3806 initiates a soft-start
sequence. The soft-start timing is set by the compensation
capacitor at the COMP pin and an internal 40 µA source. Ini-
tially, both DRVH and DRVL are held low until V

COMP

reaches

1 V. This delay time is set by:

CV

×1

t

DELAY

For a 0.22 µF COMP capacitor, t

COMP

=

40 µ

A

is 5 ms. After this initial

DELAY

(4)

delay, the duty cycle is very low and then ramps up to its final value
with the same ramp rate given for t

. For example, if VIN is

DELAY

16 V and the battery is 10 V when charging is started, the duty cycle
will be approximately 65%, corresponding to a V
time for the duty cycle to ramp from 0% at V
at V

= 2 V is approximately 5 ms. Because the charge current

COMP

of ~2 V.

COMP

= 1 V to 65%

COMP

The

is equal to zero at first, DRVLSD is active and DRVL will not turn
on. However, if the BST cap is discharged, DRVL will be forced
on for a minimum ON time of 200 ns each clock period until the
BST cap is charged to greater than 4 V.

Typically the BST cap is

charged in 5 to 10 clock cycles.

Loop Feed Forward

As the startup sequence discussion shows, the response time at
COMP is slowed by the large compensation capacitor. To speed
up the response, two comparators can quickly feed forward
around the normal control loop and pull the COMP node down
to limit any over shoot in either short circuit or overvoltage
conditions. The overvoltage comparator has a trip point set to
20% higher than the final battery voltage. The overcurrent com­parator threshold is set to 180 mV across the CS pins, which
is 15% above the maximum programmable threshold. When
these comparators are tripped, a normal soft-start sequence is
initiated. The overvoltage comparator is valuable when the
battery is removed during charging. In this case, the current in
the inductor causes the output voltage to spike up, and the
comparator limits the maximum voltage. Neither of these com­parators affect the loop under normal charging conditions.

APPLICATION INFORMATION
Design Procedure

Please refer to Figure 1, the typical application circuit, for the
following description. The design follows that of a buck con­verter. With Li-Ion cells it is important to have a regulator with
accurate output voltage control.

Battery Voltage Settings: The ADP3806 has three options for
voltage selection:

1. 12.525 V/16.7 V as selectable fixed voltages.

2. 12.6 V/16.8 V as selectable fixed voltages.

3. Adjustable.

When using the fixed versions, R11 should be a short or 0 Ω
wire jumper and R12 should be an open circuit. When using
the adjustable version, the following equation gives the ratio
of the two resistors:



R

11

R

12 2 5



V

BAT

1=




–




.

(5)

Often 0.1% resistors are required to maintain the overall accu­racy budget in the design.

Inductor Selection: Usually the inductor is chosen based on the
assumption that the inductor ripple current is ±15% of the
maximum output dc current at maximum input voltage. As long
as the inductor used has a value close to this, the system should
work fine. The final choice affects the trade-offs between cost,
size, and efficiency. For example, the lower the inductance, the
size is smaller but ripple current is higher. This situation, if taken
too far, will lead to higher ac losses in the core and the windings.
Conversely, a higher inductance results in lower ripple current
and smaller output filter capacitors, but the transient response
will be slower. With these considerations the required induc­tance can be found from:

VV

IN MAX BAT

L

=××

where the maximum input voltage V
minimum duty ratio D
of the output voltage to the input voltage, V

–

,

I

∆

DT

MIN S1

is used with the

. The duty ratio is defined as the ratio

MIN

IN, MAX

BAT/VIN

. The ripple

(6)

current is found from:

∆II

=×03.

BAT MAX

,

(7)

the maximum peak-to-peak ripple is 30%, that is 0.3, and maxi­mum battery current, I

For example, with V
3A, and T

= 4 µs, the value of L1 is calculated as 18.9 µH.

S

BAT, MAX

IN, MAX

Choosing the closest standard value gives L

is used.

= 19 V, V

= 12.6 V, I

BAT

1

= 22 µH.

BAT, MAX

=

Output Capacitor Selection: An output capacitor is needed
in the charger circuit to absorb the switching frequency ripple
current and smooth the output voltage. The RMS value of the
output ripple current is given by:

V

IN MAX

,

DD

1

–

()

12

(8)

I

RMS

=

fL

1

The maximum value occurs when the duty cycle is 0.5. Thus:

V

I

RMS MAX

.= 0 072

IN MAX_,

fL

1

(9)

REV. 0

–11–

ADP3806

For an input voltage of 19 V and a 22 µH inductance, the
maximum RMS current is 0.26A. A typical 10 µF or 22 µF
ceramic capacitor is a good choice to absorb this current.

Input Capacitor Ripple: As is the case with a normal buck
converter, the pulse current at the input has a high rms compo­nent. Therefore, since the input capacitor has to absorb this
current ripple, it must have an appropriate rms current rating.
The maximum input rms current is given by:

DD

P

=

BAT

DV

××

×

IN

I

RMS

−η()1

D

(10)

where η is the estimated converter efficiency (approximately
90%, 0.9) and P

is the maximum battery power consumed.

BAT

This is a worst-case calculation and, depending on total charge
time, the calculated number could be relaxed. Consult the
capacitor manufacturer for further technical information.

Decoupling the VCC Pin: It is a good idea to use an RC filter
(R13 and C14) from the input voltage to the IC both to filter
out switching noise and to supply bypass to the chip. During
layout, this capacitor should be placed as close to the IC as
possible. Values between 0.1 µF and 2.2 µF are recommended.

Current-Sense Filtering: During normal circuit operation the
current-sense signals can have high-frequency transients that
need filtering to ensure proper operation. In the case of the CS+
and CS– inputs, the resistors (R3 and R4) are set to 249 Ω while
the filter capacitor (C13) value is 22 nF. For the system current
sense circuits, common mode filtering from SYS+ and SYS– to
ground is needed. 470 nF ceramic capacitors (C1, C2) with

2.2 Ω resistors (R1, R2) will often due. These time constants can
be adjusted in the laboratory if required, but represent a good
starting point.

MOSFET Selection: One of the features of the ADP3806 is
that it allows use of a high-side NMOS switch instead of a more
costly PMOS device. The converter also uses synchronous recti­fication for optimal efficiency. In order to use a high-side NMOS,
an internal bootstrap regulator automatically generates a 7 V
supply across C9.

Maximum output current determines the R

DS(ON)

requirement
for the two power MOSFETs. When the ADP3806 is operating
in continuous mode, the simplifying assumption can be made
that one of the two MOSFETs is always conducting the load
current. The power dissipation for each MOSFET is given by:

Upper MOS

P

DISS

= R

DS(ON)

× (I

BAT

× √D )2 +VIN × I

× √D × TSW × f

BAT

(11)

Lower MOS

P

= R

DISS

Where f is the switching frequency and T

DS(ON)

× (I

× √1–D )2 +VIN × I

BAT

× √1–D × TSW × f

BAT

is the switch transi-

SW

(12)

tion time, usually 10 ns. The first term accounts for conduction
losses while the second term estimates switching losses. Using
these equations and the manufacturer’s data sheets, the proper
device can be selected.

A Schottky diode D1 in parallel with Q2 conducts only during
dead time between the two power MOSFETs. D1’s purpose is to
prevent the body-diode of the lower N-channel MOSFET from
turning on which could cost as much as 1% in efficiency. One
option is to use a combined MOSFET with the Schottky diode
in a single package–these integrated packages often work better
in practice. Examples are the IRF7807D2 and the Si4832.

C02611–1–10/01(0)

24

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Thin Shrink SO Package (TSSOP)

(RU-24)

0.311 (7.90)

0.303 (7.70)

13

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

MAX

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8
0

0.028 (0.70)

0.020 (0.50)

0.0256 (0.65)
BSC

121

0.0433 (1.10)

0.0118 (0.30)

0.0075 (0.19)

PRINTED IN U.S.A.

–12–

REV. 0