Datasheet ADP3654 Datasheet (ANALOG DEVICES)

High Speed, Dual,

FEATURES

Industry-standard-compatible pinout
High current drive capability
Precise UVLO comparator with hysteresis

3.3 V-compatible inputs
10 ns typical rise time and fall time at 2.2 nF load
Matched propagation delays between channels
Fast propagation delay

4.5 V to 18 V supply voltage
Parallelable dual outputs
Rated from −40°C to +125°C junction temperature
Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead

MINI_SO_EP

APPLICATIONS

AC-to-dc switch mode power supplies
DC-to-dc power supplies
Synchronous rectification
Motor drives

4 A MOSFET Driver

ADP3654

GENERAL DESCRIPTION

The ADP3654 high current and dual high speed driver is capable
of driving two independent N-channel power MOSFETs. The
driver uses the industry-standard footprint but adds high speed
switching performance.

The wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.

Digital power controllers are powered from a low voltage
supply, and the driver is powered from a higher voltage supply.
The ADP3654 driver adds UVLO and hysteresis functions,
allowing safe startup and shutdown of the higher voltage supply
when used with low voltage digital controllers.

The driver is available in thermally enhanced SOIC_N_EP and
MINI_SO_EP packaging to maximize high frequency and
current switching in a small printed circuit board (PCB) area.

FUNCTIONAL BLOCK DIAGRAM

1

NC

INA

PGND

INB

2

3

4

ADP3654

UVLO

Figure 1.

8

7

6

5

NC

OUTA

VDD

OUTB

09054-001

V

DD

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADP3654

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagrams.......................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

8/10—Revision 0: Initial Version

Test Circuit .........................................................................................8

Theory of Operation .........................................................................9

Input Drive Requirements (INA and INB)................................9

Low-Side Drivers (OUTA, OUTB).............................................9

Supply Capacitor Selection ..........................................................9

PCB Layout Considerations.........................................................9

Parallel Operation ...................................................................... 10

Thermal Considerations............................................................ 10

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. 0 | Page 2 of 12

ADP3654

SPECIFICATIONS

VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SUPPLY

Supply Voltage Range V

DD

Supply Current IDD No switching 1.2 3 mA

UVLO

Turn-On Threshold Voltage V
Turn-Off Threshold Voltage V

UVLO_ON

UVLO_OFF

Hysteresis 0.3 V

DIGITAL INPUTS (INA, INB)

Input Voltage High VIH See Figure 2 2.0 V
Input Voltage Low VIL See Figure 2 0.8 V
Input Current IIN 0 V < VIN < VDD −20 +20 μA
Internal Pull-Up/Pull-Down Current 6 μA

OUTPUTS (OUTA, OUTB)

Output Resistance, Unbiased VDD = PGND 80 kΩ
Peak Source Current See Figure 14 4 A
Peak Sink Current See Figure 14 −4 A

SWITCHING TIME

OUTA and OUTB Rise Time t
OUTA and OUTB Fall Time t
OUTA and OUTB Rising Propagation Delay t
OUTA and OUTB Falling Propagation Delay t

RISE

FALL

D1

D2

Delay Matching Between Channels 2 ns

1

All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.

4.5 18 V

VDD rising, TJ = 25°C, see Figure 3 3.8 4.2 4.5 V

VDD falling, TJ = 25°C, see Figure 3 3.5 3.9 4.3 V

C

= 2.2 nF, see Figure 2 10 25 ns

LOAD

C

= 2.2 nF, see Figure 2 10 25 ns

LOAD

C

= 2.2 nF, see Figure 2 14 30 ns

LOAD

C

= 2.2 nF, see Figure 2 22 35 ns

LOAD

TIMING DIAGRAMS

INA,
INB

OUTA,
OUTB

V

IH

t

10%

V

UVLO_ON

V

UVLO_OFF

V

DD

OUTPUTS DISABLED

D1tRISE

90%

Figure 2. Output Timing Diagram

NORMAL OP E RATIONUVLO MO DE

Figure 3. UVLO Function

V

IL

tD2t

FALL

90%

UVLO MO DE

OUTPUTS DISABLED

10%

09054-002

9054-003

Rev. 0 | Page 3 of 12

ADP3654

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD −0.3 V to +20 V
OUTA, OUTB

DC −0.3 V to VDD + 0.3 V

<200 ns −2 V to VDD + 0.3 V
INA, INB −0.3 V to VDD + 0.3 V
ESD

Human Body Model (HBM) 3.5 kV

Field Induced Charged Device Model

(FICDM)

SOIC_N_EP 1.5 kV
MINI_SO_EP 1.0 kV

θJA, JEDEC 4-Layer Board

SOIC_N_EP1 59°C/W

MINI_SO_EP1 43°C/W
Junction Temperature Range −40°C to +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature

Soldering (10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 260°C

1

θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as

appropriate with the exposed pad soldered to the PCB.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 4 of 12

ADP3654

2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

NC

ADP3654

INA

2

TOP VIEW

3

PGND

NOTES

1. NC = NO CO N NE C T.
. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECT LY

CONNECTED TO ANY PIN OF T HE PACKAGE, BUT I T I S
ELECTRI CALLY AND THERMALLY CONNECTED T O THE DIE
SUBSTRATE, WHICH IS T HE G ROUND OF THE DE VICE. IT I S
RECOMMENDED TO HAVE THE EXPOSED PAD AND THE
PGND PIN CONNECTED ON THE PCB.

INB

(Not to Scale)

4

8
7
6
5

NC
OUTA
VDD
OUTB

09054-004

Figure 4. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 NC No Connect.
2 INA Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 μF to 5 μF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8 NC No Connect.
9 EPAD

Exposed Pad. The exposed pad of the package is not directly connected to any pin of the package, but it is
electrically and thermally connected to the die substrate, which is the ground of the device. It is recommended
to have the exposed pad and the PGND pin connected on the PCB.

Rev. 0 | Page 5 of 12

ADP3654

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 12 V, TJ = 25°C, unless otherwise noted.

9

V

8

7

6

UVLO (V)

5

UVLO_ON

V

UVLO_OFF

25

20

15

t

FALL

TIME (ns)

10

t

RISE

4

3

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

Figure 5. UVLO vs. Temperature

14

12

10

8

6

TIME (ns)

4

2

0

–50 –30 –10 10 30 50 70 90 110 130

t

FALL

t

RISE

TEMPERATURE (°C)

Figure 6. Rise and Fall Times vs. Temperature

60

VDD = 12V

50

40

5

0

0 5 10 15 20

09054-005

Figure 8. Rise and Fall Times vs. V

70

60

50

40

30

TIME (ns)

20

10

0

9054-006

0 5 10 15 20

Figure 9. Propagation Delay vs. V

V

(V)

DD

VDD (V)

t

D2

t

D1

OUTA/OUTB

09054-008

DD

9054-009

DD

30

TIME (ns)

20

10

0

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (° C)

t

D2

t

D1

Figure 7. Propagation Delay vs. Temperature

9054-007

Rev. 0 | Page 6 of 12

2

INA/INB

1

VDD = 12V
TIME = 20ns/DIV

09054-010

Figure 10. Typical Rise Propagation Delay

ADP3654

2

VDD = 12V

1

TIME = 20ns/DIV

2

1

OUTA/OUTB

INA/INB

Figure 11. Typical Fall Propagation Delay

OUTA/OUTB

INA/INB

VDD = 12V
TIME = 20ns/DIV

2

VDD = 12V

1

09054-011

TIME = 20ns/DIV

Figure 13. Typical Fall Time

09054-012

OUTA/OUTB

INA/INB

09054-013

Figure 12. Typical Rise Time

Rev. 0 | Page 7 of 12

ADP3654

TEST CIRCUIT

1

2

3

4

NC

INA

PGND

ADP3654

A

B

NC

OUTA

VDD

OUTBINB

8

7

6

5

V

DD

4.7µF
CERAMIC

SCOPE
PROBE

100nF
CERAMIC

C

LOAD

9054-014

Figure 14. Test Circuit

Rev. 0 | Page 8 of 12

ADP3654

THEORY OF OPERATION

The ADP3654 dual driver is optimized for driving two
independent enhancement N-channel MOSFETs or insulated
gate bipolar transistors (IGBTs) in high switching frequency
applications.

These applications require high speed, fast rise and fall times, as
well as short propagation delays. The capacitive nature of the
aforementioned gated devices requires high peak current
capability as well.

8

1

NC

ADP3654

2

3

4

INA

PGND

A

B

Figure 15. Typical Application Circuit

NC

OUTA

VDD

OUTBINB

V

DS

7

V

DD

6

V

DS

5

09054-015

INPUT DRIVE REQUIREMENTS (INA AND INB)

The ADP3654 is designed to meet the requirements of modern
digital power controllers; the signals are compatible with 3.3 V
logic levels. At the same time, the input structure allows for
input voltages as high as V

An internal pull-down resistor is present at the input, which
guarantees that the power device is off in the event that the
input is left floating.

DD

.

LOW-SIDE DRIVERS (OUTA, OUTB)

The ADP3654 dual drivers are designed to drive ground
referenced N-channel MOSFETs. The bias is internally
connected to the V

supply and PGND.

DD

When ADP3654 is disabled, both low-side gates are held low.
Internal impedance is present between the OUTA pin and GND
and between the OUTB pin and GND; this feature ensures that
the power MOSFET is normally off when bias voltage is not
present.

When interfacing ADP3654 to external MOSFETs, the designer
should consider ways to make a robust design that minimizes
stresses on both the driver and the MOSFETs. These stresses
include exceeding the short time duration voltage ratings on the
OUTA and OUTB pins, as well as the external MOSFET.

Power MOSFETs are usually selected to have a low on resistance
to minimize conduction losses, which usually implies a large
input gate capacitance and gate charge.

SUPPLY CAPACITOR SELECTION

For the supply input (VDD) of the ADP3654, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents that are drawn.

An improper decoupling can dramatically increase the rise
times because excessive resonance on the OUTA and OUTB
pins can, in some extreme cases, damage the device, due to
inductive overvoltage on the VDD, OUTA, or OUTB pin.

The minimum capacitance required is determined by the size
of the gate capacitances being driven, but as a general rule, a

4.7 μF, low ESR capacitor should be used. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size. Use a smaller ceramic capacitor (100 nF)
with a better high frequency characteristic in parallel to the
main capacitor to further reduce noise.

Keep the ceramic capacitor as close as possible to the ADP3654
device and minimize the length of the traces going from the
capacitor to the power pins of the device.

PCB LAYOUT CONSIDERATIONS

Use the following general guidelines when designing PCBs:

• Trace out the high current paths and use short, wide

• Minimize trace inductance between the OUTA and OUTB

• Connect the PGND pin of the ADP3654 device as closely

• Place the V

• Use vias to other layers, when possible, to maximize

Rev. 0 | Page 9 of 12

(>40 mil) traces to make these connections.

outputs and MOSFET gates.

as possible to the source of the MOSFETs.

bypass capacitor as close as possible to the

DD

VDD and PGND pins.

thermal conduction away from the IC.

ADP3654

Figure 16 shows an example of the typical layout based on the
preceding guidelines.

09054-016

Figure 16. External Component Placement Example

Note that the exposed pad of the package is not directly con­nected to any pin of the package, but it is electrically and
thermally connected to the die substrate, which is the ground
of the device.

PARALLEL OPERATION

The two driver channels present in the ADP3654 device can be
combined to operate in parallel to increase drive capability and
minimize power dissipation in the driver.

The connection scheme is shown in Figure 17. In this configura­tion, INA and INB are connected together, and OUTA and
OUTB are connected together.

Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.

1

NC

ADP3654

INA

2

PGND

3

4

A

B

Figure 17. Parallel Operation

NC

OUTA

VDD

OUTBINB

8

7

V

DD

6

V

DS

5

9054-017

THERMAL CONSIDERATIONS

When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding maximum junction temperature.

Data on package thermal resistance is provided in Tabl e 2 to
help the designer with this task.

There are several equally important aspects that must be
considered, such as the following:

• Gate charge of the power MOSFET being driven

• Bias voltage value used to power the driver

• Maximum switching frequency of operation

• Value of external gate resistance

• Maximum ambient (and PCB) temperature

• Type of package

All of these factors influence and limit the maximum allowable
power dissipated in the driver.

The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as C
useful to calculate power losses.

The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under Q
This parameter varies from a few nanocoulombs (nC) to several
hundred nC, and is specified at a specific V

GS

or 4.5 V).

The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as:

P

= VGS × QG × fSW

GATE

where:

V

is the bias voltage powering the driver (VDD).

GS

Q

is the total gate charge.

G

is the maximum switching frequency.

f

SW

The power dissipated for each gate (P

) still needs to be

GATE

multiplied by the number of drivers (in this case, 1 or 2) being
used in each package, and it represents the total power dissi­pated in charging and discharging the gates of the power
MOSFETs.

Not all of this power is dissipated in the gate driver because part
of it is actually dissipated in the external gate resistor, R
larger the external gate resistor is, the smaller the amount of
power that is dissipated in the gate driver.

In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
minimize switching losses.

In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be neglected, and the extra loss is assumed in the driver,
providing a good guard band to the power loss calculations.

, it is not

ISS

value (10 V

G

G

. The

.

Rev. 0 | Page 10 of 12

ADP3654

In addition to the gate charge losses, there are also dc bias
losses, due to the bias current of the driver. This current is
present regardless of the switching.

P

= VDD × IDD

DC

The total estimated loss is the sum of P

= PDC + (n × P

P

LOSS

GATE

)

DC

and P

GATE

.

where n is the number of gates driven.

When the total power loss is calculated, the temperature
increase can be calculated as

ΔT

= P

× θJA

J

LOSS

Design Example

For example, consider driving two IRFS4310Z MOSFETs with a

of 12 V at a switching frequency of 300 kHz, using an

V

DD

ADP3654 in the SOIC_N_EP package.

The maximum PCB temperature considered for this design is 85°C.

From the MOSFET data sheet, the total gate charge is Q

= 12 V × 120 nC × 300 kHz = 432 mW

P

GATE

P

= 12 V × 1.2 mA = 14.4 mW

DC

P

= 14.4 mW + (2 × 432 mW) = 878.4 mW

LOSS

= 120 nC.

G

The SOIC_N_EP thermal resistance is 59°C/W.

ΔT

= 878.4 mW × 59°C/W = 51.8°C

J

T

= TA + ΔTJ = 136.8°C ≤ T

J

JMAX

This estimated junction temperature does not factor in the
power dissipated in the external gate resistor and, therefore,
provides a certain guard band.

If a lower junction temperature is required by the design,
the MINI_SO_EP package can be used, which provides a
thermal resistance of 43°C/W, so that the maximum junction
temperature is

ΔT

= 878.4 mW × 43°C/W = 37.7°C

J

T

= TA + ΔTJ = 122.7°C ≤ T

J

JMAX

Other options to reduce power dissipation in the driver include
reducing the value of the V

bias voltage, reducing switching fre-

DD

quency, and choosing a power MOSFET with smaller gate charge.

Rev. 0 | Page 11 of 12

ADP3654

OUTLINE DIMENSIONS

FOR PROPE R CO NNE CTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DATA SHEET.

2.29 (0.090)

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

5.00 (0.197)

4.90 (0.193)

4.80 (0.189)

85

TOP VIEW

6.20 (0.244)

6.00 (0.236)

41

5.80 (0.228)

2.29 (0.090)

BOTTOM VIEW

0.25 (0.0098)

0.17 (0.0067)

(PINS UP)

8°
0°

0.50 (0.020)

0.25 (0.010)

45°

1.27 (0.050)

0.40 (0.016)

072808-A

1.75 (0.069)

1.35 (0.053)

0.10 (0.004)
MAX

COPLANARITY

0.10

1.27 (0.05)
BSC

1.65 (0.065)

1.25 (0.049)

SEATING

0.51 (0.020)

0.31 (0.012)

CONTROLL I NG DI M ENSIONS ARE IN MILL I M ET E R; I NCH DIM ENS I O NS
(IN PARENTHESES) ARE ROUNDED-O FF MIL L IMETER EQ UIVALENTS FOR
REFERENCE ON LY AND ARE NO T APPROPRI ATE FOR USE IN DESIGN.

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 18. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body (RD-8-1)

Dimensions shown in millimeters and (inches)

3.10

3.00

2.90

5

3.10

3.00

2.90

PIN 1

INDICATOR

0.94

0.86

0.78

0.15

0.10

0.05

COPLANARITY

0.10

8

TOP

VIEW

1

0.65 BSC

0.40

0.33

0.25

COMPLIANT TO JEDEC STANDARDS MO-187-AA- T

4

5.05

4.90

4.75

0.525 BSC

1.10 MAX

SEATING
PLANE

BOTTOM VIEW

0.23

0.18

0.13

Figure 19. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]

(RH-8-1)

Dimensions shown in millimeters

EXPOSED

PAD

8°
0°

2.26

2.16

2.06

1.83

1.73

1.63
FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIO NS
SECTION OF THIS DATA SHEET.

0.70

0.55

0.40

071008-A

ORDERING GUIDE

UVLO

Model1

Option

ADP3654ARDZ-RL 4.5 V −40°C to +125°C

ADP3654ARHZ-RL 4.5 V −40°C to +125°C

1

Z = RoHS Compliant Part.

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09054-0-8/10(0)

Temperature
Range Package Description

8-Lead Standard Small Outline Package
(SOIC_N_EP), 13“ Tape and Reel

8-Lead Mini Small Outline Package (MINI_SO_EP),
13” Tape and Reel

Rev. 0 | Page 12 of 12

Package
Option

Ordering
Quantity Branding

RD-8-1 2,500

RH-8-1 3,000 78