Datasheet ADP3650 Datasheet (ANALOG DEVICES)

Dual, Bootstrapped, 12 V MOSFET

V

FEATURES

All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anti-crossconduction protection circuitry

for disabling the driver outputs

OD

APPLICATIONS

Telecom and datacom networking
Industrial and medical systems
Point of load conversion: memory, DSP, FPGA, ASIC

Driver with Output Disable

ADP3650

GENERAL DESCRIPTION

The ADP3650 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated synchronous buck power converter. Each driver is
capable of driving a 3000 pF load with a 45 ns propagation delay
and a 25 ns transition time. One of the drivers can be boot­strapped and is designed to handle the high voltage slew rate
associated with floating high-side gate drivers. The ADP3650
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs.

The

MOSFETs to prevent rapid output capacitor discharge during
system shutdown.

The ADP3650 is specified over the temperature range of −40°C
to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP_VD
packages.

pin shuts off both the high-side and the low-side

OD

OD

IN

2

3

ADP3650

FUNCTIONAL BLOCK DIAGRAM

12

C

BST1

D1

C

BST2

R

G

R

BST

Q1

TO

INDUCTOR

Q2

7826-001

VCC

4

BST

1

LATCH

R1
R2

Q

S

DELAY

CMP

VCC

6

CMP

1V

DELAY

CONTROL

LOGIC

8

7

5

6

DRVH

SW

DRVL

PGND

Figure 1.

Rev. A

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ADP3650

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

REVISION HISTORY

7/10—Rev. 0 to Rev. A

Changes to General Description Section ...................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Operating Ambient Temperature Range Parameter,

Table 2 ................................................................................................ 5

Changes to Figure 8 and Figure 9 ................................................... 7

Changes to Ordering Guide .......................................................... 12

10/08—Revision 0: Initial Version

Low-Side Driver ............................................................................9

High-Side Driver ...........................................................................9

Overlap Protection Circuit ...........................................................9

Applications Information .............................................................. 10

Supply Capacitor Selection ....................................................... 10

Bootstrap Circuit ........................................................................ 10

MOSFET Selection ..................................................................... 10

High-Side (Control) MOSFETs ................................................ 10

Low-Side (Synchronous) MOSFETs ........................................ 11

PCB Layout Considerations ...................................................... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. A | Page 2 of 12

ADP3650

SPECIFICATIONS

VCC = 12 V, BST = 4 V to 26 V, TA = −40°C to +85°C, unless otherwise noted.1

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

DIGITAL INPUTS (IN, OD)

Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 μA
Hysteresis 40 250 350 mV

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current BST − SW = 12 V; TA = 25°C 3.3 Ω
BST − SW = 12 V; TA = −40°C to +85°C 2.5 3.9 Ω
Output Resistance, Sinking Current BST − SW = 12 V; TA = 25°C 1.8 Ω
BST − SW = 12 V; TA = −40°C to +85°C 1.4 2.6 Ω
Output Resistance, Unbiased BST − SW = 0 V 10 kΩ
Transition Times t
t
Propagation Delay Times t
25°C ≤ TA ≤ 85°C, see Figure 3
t

SW Pull-Down Resistance SW to PGND 10 kΩ

LOW-SIDE DRIVER

Output Resistance, Sourcing Current TA = 25°C 3.3 Ω
T
Output Resistance, Sinking Current TA = 25°C 1.8 Ω
T
Output Resistance, Unbiased VCC = PGND 10 kΩ
Transition Times t
t
Propagation Delay Times t
t

Timeout Delay SW = 5 V 110 190 ns
SW = PGND 95 150 ns

SUPPLY

Supply Voltage Range V
Supply Current I
UVLO Voltage VCC rising 1.5 3.0 V
Hysteresis 350 mV

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

rDRVH

fDRVH

pdhDRVH

pdlDRVH

t

pdl

OD

t

pdh

OD

rDRVL

fDRVL

pdhDRVL

pdlDRVL

t

pdl

OD

t

pdh

OD

CC

BST = 12 V, IN = 0 V 2 5 mA

SYS

BST − SW = 12 V, C
BST − SW = 12 V, C
BST − SW = 12 V, C

BST − SW = 12 V, C
See Figure 2 20 35 ns

See Figure 2 40 55 ns

= −40°C to +85°C 2.4 3.9 Ω

A

= −40°C to +85°C 1.4 2.6 Ω

A

C

= 3 nF, see Figure 3 20 35 ns

LOAD

C

= 3 nF, see Figure 3 16 30 ns

LOAD

C

= 3 nF, see Figure 3 12 35 ns

LOAD

C

= 3 nF, see Figure 3 30 45 ns

LOAD

See Figure 2 20 35 ns

See Figure 2 110 190 ns

4.15 13.2 V

= 3 nF, see Figure 3 25 40 ns

LOAD

= 3 nF, see Figure 3 20 30 ns

LOAD

= 3 nF, 32 45 70 ns

LOAD

= 3 nF, see Figure 3 25 35 ns

LOAD

Rev. A | Page 3 of 12

ADP3650

TIMING CHARACTERISTICS

Timing is referenced to the 90% and 10% points, unless otherwise noted.

OD

t

pdlOD

t

pdhOD

DRVH
OR
DRVL

90%

10%

7826-004

Figure 2. Output Disable Timing Diagram

IN

t

DRVL

DRVH

TO

SW

SW

pdlDRVLtfDRVL

t

pdhDRVHtrDRVH

V

TH

t

pdlDRVH

t

rDRVL

t

fDRVH

V

TH

t

pdhDRVL

1V

07826-005

Figure 3. Timing Diagram

Rev. A | Page 4 of 12

ADP3650

ABSOLUTE MAXIMUM RATINGS

All voltages are referenced to PGND, unless otherwise noted.

Table 2.

Parameter Rating

VCC −0.3 V to +15 V
BST

DC −0.3 V to VCC + 15 V

<200 ns −0.3 V to +35 V
BST to SW −0.3 V to +15 V
SW

DC −5 V to +15 V

<200 ns −10 V to +25 V
DRVH

DC SW − 0.3 V to BST + 0.3 V

<200 ns SW − 2 V to BST + 0.3 V
DRVL

DC −0.3 V to VCC + 0.3 V

<200 ns −2 V to VCC + 0.3 V
IN, OD
Operating Ambient Temperature Range −40°C to +85°C
Junction Temperature Range 0°C to 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature

Soldering (10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 260°C

−0.3 V to +6.5 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

8-Lead SOIC_N (R-8)

2-Layer Board 123 °C/W
4-Layer Board 90 °C/W

8-Lead LFCSP_VD1 (CP-8-2)

4-Layer Board 50 °C/W

1

For LFCSP_VD, θJA is measured per JEDEC STD with exposed pad soldered to PCB.

ESD CAUTION

Rev. A | Page 5 of 12

ADP3650

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

BST

OD
CC

IN

1
2

ADP3650

3

TOP VIEW

(Not to S cale)

4

8
7
6
5

Figure 4. 8-Lead SOIC_N Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET while it is switching.

2 IN

Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD
4 VCC
5 DRVL
6 PGND

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET. This pin is not internally

connected to the exposed pad on the LFCSP. It is recommended that this pin and the exposed pad be
connected on the PCB.

7 SW

Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET source.
It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to

prevent the lower MOSFET from turning on until the voltage is below ~1 V.
8 DRVH
EP Exposed pad

Buck Drive. Output drive for the upper (buck) MOSFET.

For the LFCSP, the exposed pad and the PGND pin should be connected on the PCB. For more information

about exposed pad packages, see the AN-772 Application Note at www.analog.com.

DRVH
SW
PGND
DRVL

1
2
3
4

PIN 1
INDICATOR

ADP3650

TOP VIEW

(Not to Scale)

8
7
6
5

DRVH
SW
PGND
DRVL

07826-003

BST

IN

OD

VCC

07826-002

NOTES

1. IT IS RE COMMENDED THAT THE
EXPOSED PAD AND THE PGND PIN
BE CONNE C TED ON THE PCB.

Figure 5. 8-Lead LFCSP_VD Pin Configuration

Rev. A | Page 6 of 12

ADP3650

TYPICAL PERFORMANCE CHARACTERISTICS

19.0

18.5

18.0

17.5

17.0

16.5

16.0

FALL TIME (ns)

15.5

15.0

14.5

14.0
–40–30–20–100 1020304050607080

JUNCTION TEMPERATURE (°C)

DRVH

DRVL

Figure 9. DRVH and DRVL Fall Times vs. Temperature

40

TA = 25°C
VCC = 12V

35

30

DRVH

07826-009

1

2

3

CH1 5V
CH3 10V

1

IN

DRVL

DRVH

CH2 5V M40ns A CH1 2.4V

T 20.2%

Figure 6. DRVH Rise and DRVL Fall Times,

C

= 6 nF for DRVL, C

LOAD

= 2 nF for DRVH

LOAD

IN

07826-006

RISE TIME (ns)

2

3

CH1 5V
CH3 10V

28

26

24

22

20

18

16

DRVL

DRVH

CH2 5V M40ns A CH1 2.4V

T 20.2%

Figure 7. DRVH Fall and DRVL Rise Times,

= 6 nF for DRVL, C

C

LOAD

= 2 nF for DRVH

LOAD

DRVL

DRVH

25

20

RISE TIM E (ns)

15

10

5

07826-007

2.0

2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE (nF)

DRVL

5.0

07826-010

Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance

35

VCC = 12V
T

= 25°C

A

30

25

20

FALL TIME (ns)

15

10

DRVH

DRVL

14

–40–30–20–100 10203040506070

JUNCTION TEMPERATURE (°C)

Figure 8. DRVH and DRVL Rise Times vs. Temperature

80

07826-008

Rev. A | Page 7 of 12

5

2.0

2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE (nF)

Figure 11. DRVH and DRVL Fall Times vs. Load Capacitance

5.0

07826-011

ADP3650

60

TA= 25°C
VCC = 12V

= 3nF

C

LOAD

45

30

SUPPLY CURRENT (mA)

15

0

0

200 400 600 800 1000 1200 1400

FREQUENCY ( kHz )

07826-012

Figure 12. Supply Current vs. Frequency

12

TA = 25°C

11

C

= 3nF

LOAD

10

9
8
7
6
5
4
3

DRVL OUTPUT VOLTAGE (V)

2
1
0

01

1234567891011

V

(V)

CC

2

07826-014

Figure 14. DRVL Output Voltage vs. Supply Voltage

13

VCC = 12V
C

= 3nF

LOAD

= 250kHz

f

IN

12

11

SUPPLY CURRENT (mA)

10

9

0

25 50 75 100

JUNCTION TEMPERATURE (°C)

125

07826-013

Figure 13. Supply Current vs. Temperature

Rev. A | Page 8 of 12

ADP3650

THEORY OF OPERATION

The ADP3650 is optimized for driving two N-channel
MOSFETs in a synchronous buck converter topology. A single
PWM input (IN) signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each driver is capable
of driving a 3 nF load at speeds up to 500 kHz. A functional
block diagram of the ADP3650 is shown in Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground referenced
N-channel MOSFET. The bias supply to the low-side driver is
internally connected to the VCC supply and PGND.

When the driver is enabled, the driver output is 180° out of
phase with the PWM input. When the ADP3650 is disabled,
the low-side gate is held low.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit that is connected
between the BST and SW pins.

The bootstrap circuit comprises Diode D1 and Bootstrap
Capacitor C
side gate drive voltage and to limit the switch node slew rate.
When the ADP3650 starts up, the SW pin is at ground, so the
bootstrap capacitor charges up to V
PWM input goes high, the high-side driver begins to turn on
the high-side MOSFET, Q1, by pulling charge out of C
C

. As Q1 turns on, the SW pin rises up to VIN and forces the

BST2

BST pin to V
to-source voltage is provided. To complete the cycle, Q1 is
switched off by pulling the gate down to the voltage at the SW
pin. When the low-side MOSFET, Q2, turns on, the SW pin is
pulled to ground. This allows the bootstrap capacitor to charge
up to VCC again.

The output of the high-side driver is in phase with the PWM
input. When the driver is disabled, the high-side gate is held low.

BST1

IN

. C

+ V

BST2

C (BST)

and R

are included to reduce the high-

BST

through D1. When the

CC

. This holds Q1 on because enough gate-

BST1

and

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn-off to the Q2 turn-on and by internally setting the
delay from the Q2 turn-off to the Q1 turn-on.

To prevent the overlap of the gate drives during the Q1 turn-off
and the Q2 turn-on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from
V

to 1 V. When the voltage on the SW pin falls to 1 V, Q2

IN

begins to turn on. If the SW pin has not gone high first, the Q2
turn-on is delayed by a fixed 150 ns. By waiting for the voltage
on the SW pin to reach 1 V or for the fixed delay time, the
overlap protection circuit ensures that Q1 is off before Q2 turns
on, regardless of variations in temperature, supply voltage, input
pulse width, gate charge, and drive current. If SW does not go
below 1 V after 190 ns, DRVL turns on. This can occur if the
current flowing in the output inductor is negative and flows
through the high-side MOSFET body diode.

Rev. A | Page 9 of 12

ADP3650

C

APPLICATIONS INFORMATION

SUPPLY CAPACITOR SELECTION

For the supply input (VCC) of the ADP3650, a local bypass
capacitor is recommended to reduce noise and to supply some
of the peak currents that are drawn. Use a 4.7 μF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3650.

BOOTSTRAP CIRCUIT

The bootstrap circuit uses a charge storage capacitor (C
and a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that can handle twice the
maximum supply voltage. A minimum 50 V rating is recom­mended. The capacitor values are determined by

Q

V

CC

GATE

V

GATE

GATE

(2)

VV

−

D

CC ×=+ 10 (1)

BST2BST1

BST1

+

=

CC

BST2BST1

where:

Q

is the total gate charge of the high-side MOSFET at V

GATE

V

is the desired gate drive voltage (usually in the range of

GATE

5 V to 10 V, 7 V being typical).

V

is the voltage drop across D1.

D

Rearranging Equation 1 and Equation 2 to solve for C

Q

GATE

×= 10

C

1

BST

C

can then be found by rearranging Equation 1.

BST2

C −×=

BST2

Q

V

CC

GATE

GATE

VV

−

D

C

110BST

For example, an NTD60N02 has a total gate charge of about
12 nC at V
C

= 12 nF and C

BST1

= 7 V. Using VCC = 12 V and VD = 1 V, then

GATE

= 6.8 nF. Good quality ceramic capacitors

BST2

should be used.

R

is used to limit slew rate and minimize ringing at the switch

BST

node. It also provides peak current limiting through D1. An
R

value of 1.5 Ω to 2.2 Ω is a good choice. The resistor needs

BST

to handle at least 250 mW due to the peak currents that flow
through it.

BST1

)

BST

GATE

yields

.

A small signal diode can be used for the bootstrap diode due
to the ample gate drive voltage supplied by V

. The bootstrap

CC

diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can
be estimated by

fQI ×=

(3)

MAX

GATE

)(

is the maximum switching frequency of the

where

f

AVGF

MAX

controller.

The peak surge current rating should be calculated by

VVI−

D

CC

=

PEAKF

)(

(4)

R

BST

MOSFET SELECTION

When interfacing the ADP3650 to external MOSFETs, the
designer should consider ways to make a robust design that
minimizes stresses on both the driver and the MOSFETs. These
stresses include exceeding the short time duration voltage
ratings on the driver pins as well as on the external MOSFET.

It is also highly recommended that the bootstrap circuit be used
to improve the interaction of the driver with the characteristics
of the MOSFETs (see the Bootstrap Circuit section). If a simple
bootstrap arrangement is used, make sure to include a proper
snubber network on the SW node.

HIGH-SIDE (CONTROL) MOSFETS

A high-side, high speed MOSFET is usually selected to
minimize switching losses. This typically implies a low gate
resistance and low input capacitance/charge device. Yet, a
significant source lead inductance can also exist that depends
mainly on the MOSFET package; it is best to contact the
MOSFET vendor for this information.

The ADP3650 DRVH output impedance and the input resistance
of the MOSFETs determine the rate of charge delivery to the
internal capacitance of the gate. This determines the speed at
which the MOSFETs turn on and off. However, because of
potentially large currents flowing in the MOSFETs at the on and
off times (this current is usually larger at turn-off due to ramping
up of the output current in the output inductor), the source lead
inductance generates a significant voltage when the high-side
MOSFETs switch off. This creates a significant drain-source
voltage spike across the internal die of the MOSFETs and can
lead to a catastrophic avalanche. The mechanisms involved in
this avalanche condition are referenced in literature from the
MOSFET suppliers.

Rev. A | Page 10 of 12

ADP3650

The MOSFET vendor should provide a safe operating rating for
maximum voltage slew rate at a given drain current. This allows
the designer to derate for the FET turn-off condition described
in this section. When this specification is obtained, determine
the maximum current expected in the MOSFET by

D

MAX

MAX

×

Lf

OUT

()

VVphaseperII

)((5)

CCDCMAX

OUT

×−+=

where:

D

is determined by the voltage controller being used with

MAX

the driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).

L

is the output inductor value.

OUT

When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as in the PCB. However, it can be measured to
determine whether it is safe. If it appears that the dV/dt is too
fast, an optional gate resistor can be added between DRVH and
the high-side MOSFETs. This resistor slows down the dV/dt,
but it increases the switching losses in the high-side MOSFETs.
The ADP3650 is optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently, yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending on
the currents being switched in the MOSFET.

LOW-SIDE (SYNCHRONOUS) MOSFETS

The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure that the power delivery from the ADP3650 DRVL
does not exceed the thermal rating of the driver.

The next concern for the low-side MOSFETs is to prevent
them from being inadvertently switched on when the high-side
MOSFET turns on. This occurs due to the drain-gate capacitance
(Miller capacitance, also specified as C
the drain of the low-side MOSFET is switched to VCC by the
high-side MOSFET turning on (at a dV/dt rate), the internal
gate of the low-side MOSFET is pulled up by an amount roughly
equal to V

CC

× (C

). It is important to make sure that this

rss/Ciss

does not put the MOSFET into conduction.

Another consideration is the nonoverlap circuitry of the
ADP3650 that attempts to minimize the nonoverlap period.
During the state of the high-side MOSFET turning off to the
low-side MOSFET turning on, the SW pin is monitored (as well
as the conditions of SW prior to switching) to adequately
prevent overlap.

) of the MOSFET. When

rss

However, during the low-side turn-off to high-side turn-on,
the SW pin does not contain information for determining
the proper switching time, so the state of the DRVL pin is
monitored to go below one-sixth of V

; then, a delay is added.

CC

Due to the Miller capacitance and internal delays of the low­side MOSFET gate, ensure that the Miller-to-input capacitance
ratio is low enough, and that the low-side MOSFET internal
delays are not so large as to allow accidental turn-on of the
low-side MOSFET when the high-side MOSFET turns on.

PCB LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed
circuit boards. Figure 15 shows an example of the typical land
patterns based on these guidelines.

• Trace out the high current paths and use short, wide

(>20 mil) traces to make these connections.

• Minimize trace inductance between the DRVH and DRVL

outputs and the MOSFET gates.

• Connect the PGND pin of the ADP3650 as close as

possible to the source of the lower MOSFET.

• Locate the VCC bypass capacitor as close as possible to

the VCC and PGND pins.

• When possible, use vias to other layers to maximize

thermal conduction away from the IC.

C

BST1

R

C

D1

C

VCC

Figure 15. External Component Placement Example

BST2

BST

07826-015

Rev. A | Page 11 of 12

ADP3650

OUTLINE DIMENSIONS

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

PIN 1

12° MAX

3.25

3.00 SQ

2.75

TOP

VIEW

0.70 MAX

0.65TYP

0.30

0.23

0.18

2.95

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

0.60 MAX

0.50

0.40

0.30

0.60 MAX

5

EXPOSED

(BOTT OM VIEW)

4

FOR PROPE R CONNECTION O F
THE EXPOSED PAD, REFER T O
THE PIN CONFIGURATION AND
FUNCTION DE SCRIPTIO NS
SECTION OF THIS DATA SHEET.

PAD

0.50
BSC

8

1

1.89

1.74

1.59

1.60

1.45

1.30

PIN 1
INDICATOR

90308-B

Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm x 3 mm Body, Very Thin, Dual Lead

(CP-8-2)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Model1 Temperature Range Package Description

Option

ADP3650JRZ −40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 98
ADP3650JRZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 2,500
ADP3650JCPZ-RL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 5,000 L91

1

Z = RoHS Compliant Part.

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D07826-0-7/10(A)

Rev. A | Page 12 of 12

Ordering
Quantity

Branding