Datasheet ADP3629 Datasheet (ANALOG DEVICES)

Page 1

High Speed, Dual, 2 A MOSFET Driver

FEATURES

Industry-standard-compatible pinout High current drive capability Precise threshold shutdown comparator UVLO with hysteresis Overtemperature warning signal Overtemperature shutdown

3.3 V-compatible inputs Rise time and fall time: 10 ns typical at 2.2 nF load Fast propagation delay Matched propagation delays between channels Supply voltage: 9.5 V to 18 V Dual outputs can be operated in parallel

(ADP3629/ADP3630) Rated from −40°C to +85°C ambient temperature 8-lead SOIC_N and 8-lead MSOP

APPLICATIONS

AC-to-DC switch mode power supplies DC-to-DC power supplies Synchronous rectification Motor drives

ADP3629/ADP3630/ADP3631

GENERAL DESCRIPTION

The ADP3629/ADP3630/ADP3631 are dual, high current, high speed drivers, capable of driving two independent N-channel power MOSFETs. The ADP3629/ADP3630/ADP3631 use the industry-standard footprint but add high speed switching performance and improved system reliability.

The ADP3629/ADP3630/ADP3631 have an internal temperature sensor and provide two levels of overtemperature protection: an overtemperature warning and an overtemperature shutdown at extreme junction temperatures.

The SD function, generated from a precise internal comparator, provides fast system enable or shutdown. This feature allows redundant overvoltage protection, complementing the protection inside the main controller device, or provides safe system shutdown in the event of an overtemperature warning.

The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers.

Digital power controllers are supplied from a low voltage supply, and the driver is supplied from a higher voltage supply. The ADP3629/ADP3630/ADP3631 add UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers.

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

INA, INA

PGND

INB, INB

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INVERTING

NONINVERTING

INVERTING

ADP3629/ADP3630/ADP3631

OTW

OVERTEMPERATURE

PROTECTION

UVLO

Figure 1.

OUTA

VDD

OUTB

08401-101

Page 2

ADP3629/ADP3630/ADP3631

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Diagrams .......................................................................... 4

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

9/09—Revision 0: Initial Version

Test Circuit ...................................................................................... 10

Theory of Operation ...................................................................... 11

Input Drive Requirements (INA,

Low-Side Drivers (OUTA, OUTB) .......................................... 11

Shutdown (SD) Function .......................................................... 11

Overtemperature Protections ................................................... 12

Supply Capacitor Selection ....................................................... 12

PCB Layout Considerations ...................................................... 12

Parallel Operation ...................................................................... 12

Thermal Considerations ............................................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

INA

, INB,

INB

, and SD) .. 11

Rev. 0 | Page 2 of 16

Page 3

ADP3629/ADP3630/ADP3631

SPECIFICATIONS

VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SUPPLY

Supply Voltage Range V

Supply Current IDD

Standby Current I

SD = 5 V 1.2 3 mA

SBY

UVLO

Turn-On Threshold Voltage V

Turn-Off Threshold Voltage V

UVLO_ON

UVLO_OFF

Hysteresis 1.0 V

DIGITAL INPUTS (INA, INA, INB, INB, SD)

Input Voltage High VIH 2.0 V

Input Voltage Low VIL 0.8 V

Input Current IIN 0 V < VIN < VDD −20 +20 μA

SD Threshold High V

SD_H

SD Threshold Low V

SD Hysteresis V

SD_L

SD_HYST

Internal Pull-Up/Pull-Down Current 6 μA

OUTPUTS (OUTA, OUTB)

Output Resistance, Unbiased VDD = PGND 80 kΩ

Peak Source Current See Figure 20 2 A

Peak Sink Current See Figure 20 −2 A

SWITCHING TIME

OUTA, OUTB Rise Time t

OUTA, OUTB Fall Time t

OUTA, OUTB Rising Propagation Delay t

OUTA, OUTB Falling Propagation Delay t

SD Propagation Delay Low t

SD Propagation Delay High t

RISE

FALL

dL_SD

dH_SD

Delay Matching Between Channels 2 ns

OVERTEMPERATURE PROTECTION

Overtemperature Warning Threshold TW See Figure 6 120 135 150 °C

Overtemperature Shutdown Threshold TSD See Figure 6 150 165 180 °C

Temperature Hysteresis for Shutdown T

Temperature Hysteresis for Warning T

Overtemperature Warning Low V

All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.

HYS_SD

HYS_W

OTW_O L

9.5 18 V No switching, INA, INA

, INB, and INB

1.2 3 mA

disabled

VDD rising, TA = 25°C 8.0 8.7 9.5 V

VDD falling, TA = 25°C 7.0 7.7 8.5 V

1.19 1.28 1.38 V = 25°C 1.21 1.28 1.35 V

= 25°C 0.95 1.0 1.05 V

TA = 25°C 240 280 320 mV

= 2.2 nF, see Figure 3 and Figure 4 10 25 ns

LOAD

= 2.2 nF, see Figure 3 and Figure 4 10 25 ns

LOAD

= 2.2 nF, see Figure 3 and Figure 4 14 30 ns

LOAD

= 2.2 nF, see Figure 3 and Figure 4 22 35 ns

LOAD

See Figure 2 32 45 ns

See Figure 2 48 75 ns

See Figure 6 30 °C

See Figure 6 10 °C

Open drain, −500 μA 0.4 V

Rev. 0 | Page 3 of 16

Page 4

ADP3629/ADP3630/ADP3631

TIMING DIAGRAMS

dL_SD

dH_SD

OUTA,

OUTB

90%

Figure 2. Shutdown Timing Diagram

10%

08401-002

INA, INB

OUTA, OUTB

D1tRISE

90%

10%

tD2t

FALL

90%

10%

08401-003

Figure 3. Output Timing Diagram (Noninverting)

INA, INB

OUTA, OUTB

D1tRISE

90%

10%

Figure 4. Output Timing Diagram (Inverting)

tD2t

FALL

90%

10%

08401-103

UVLO_ON

UVLO_OFF

NORMAL OPERATIONUVLO MODE

OUTPUTS DI SABL E D

UVLO MODE

OUTPUTS DI S ABLED

8401-005

Figure 5. UVLO Function

Rev. 0 | Page 4 of 16

Page 5

ADP3629/ADP3630/ADP3631

–

HYS_SD

NORMAL OPERATION NORMAL OPERATION

OTW

OT WARNING

OUTPUTS ENABLED

OT SHUTDO WN

OUTPUTS

DISABLED

OT WARNING

OUTPUTS ENABLED

–

HYS_W

08401-006

Figure 6. Overtemperature Warning and Shutdown

Rev. 0 | Page 5 of 16

Page 6

ADP3629/ADP3630/ADP3631

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD −0.3 V to +20 V OUTA, OUTB

DC −0.3 V to VDD + 0.3 V

<200 ns −2 V to VDD + 0.3 V INA, INA, INB, INB, SD ESD

Human Body Model (HBM) 3.5 kV

Field Induced Charged Device

Model (FICDM) SOIC_N 1.5 kV

MSOP 1.0 kV Junction Temperature Range −40°C to +150°C Storage Temperature Range −65°C to +150°C Lead Temperature

Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 260°C

−0.3 V to V

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for a device soldered in a 4-layer circuit board and is measured per JEDEC standards JESD51-2, JESD51-5, and JESD51-7.

Table 3. Thermal Resistance

Package Type θJA Unit

8-Lead SOIC_N 110.6 °C/W 8-Lead MSOP 162.2 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 16

Page 7

ADP3629/ADP3630/ADP3631

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADP3629

INA

PGND

TOP VIEW

(Not to Scale)

INB

Figure 7. ADP3629 Pin Configuration

Table 4. ADP3629 Pin Function Descriptions

Pin No. Mnemonic Description

1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2

INA

Inverting Input Pin for Channel A Gate Driver. 3 PGND Ground. This pin should be closely connected to the source of the power MOSFET. 4

INB

Inverting Input Pin for Channel B Gate Driver. 5 OUTB Output Pin for Channel B Gate Driver. 6 VDD Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor. 7 OUTA Output Pin for Channel A Gate Driver. 8

OTW

Overtemperature Warning Flag. Open drain, active low.

ADP3630

INA

2 3

PGND

Figure 8. ADP3630 Pin Configuration

INB

TOP VIEW

(Not to Scale)

8 7 6 5

OTW OUTA VDD OUTB

08401-008

08401-001

Table 5. ADP3630 Pin Function Descriptions

Pin No. Mnemonic Description

1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2 INA Input Pin for Channel A Gate Driver. 3 PGND Ground. This pin should be closely connected to the source of the power MOSFET. 4 INB Input Pin for Channel B Gate Driver. 5 OUTB Output Pin for Channel B Gate Driver. 6 VDD Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor. 7 OUTA Output Pin for Channel A Gate Driver. 8

OTW

Overtemperature Warning Flag. Open drain, active low.

INA

PGND

INB

ADP3631

2 3

TOP VIEW

(Not to Scale)

8 7 6 5

OTW OUTA VDD OUTB

08401-009

Figure 9. ADP3631 Pin Configuration

Table 6. ADP3631 Pin Function Descriptions

Pin No. Mnemonic Description

1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2

INA

Inverting Input Pin for Channel A Gate Driver. 3 PGND Ground. This pin should be closely connected to the source of the power MOSFET. 4 INB Input Pin for Channel B Gate Driver. 5 OUTB Output Pin for Channel B Gate Driver. 6 VDD Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor. 7 OUTA Output Pin for Channel A Gate Driver. 8

OTW

Overtemperature Warning Flag. Open drain, active low.

Rev. 0 | Page 7 of 16

Page 8

ADP3629/ADP3630/ADP3631

TYPICAL PERFORMANCE CHARACTERISTICS

UVLO ( V)

UVLO_ON

UVLO_OFF

FALL

TIME (ns)

RISE

3 –50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE ( °C)

Figure 10. UVLO vs. Temperature

TIME (ns)

–50 –30 –10 10 30 50 70 90 110 130

FALL

RISE

TEMPERATURE (°C)

Figure 11. Rise and Fall Times vs. Temperature

0 5 10 15 20

08401-022

(V)

08401-012

Figure 13. Rise and Fall Times vs. VDD

VDD (V)

dH_SD

dL_SD

t t

08401-013

TIME (ns)

0 5 10 15 20

08401-010

Figure 14. Propagation Delay vs. VDD

VDD = 12V

TIME (ns)

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

dH_SD

dL_SD

Figure 12. Propagation Delay vs. Temperature

08401-011

Rev. 0 | Page 8 of 16

1400

1200

1000

800

600

400

SHUTDOWN THRESHOLD (mV)

200

0 –50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

SD_H

SD_L

SD_HYST

Figure 15. Shutdown Threshold vs. Temperature

8401-014

Page 9

ADP3629/ADP3630/ADP3631

OUTA/OUTB

INA/INB

VDD = 12V TIME = 20ns/DIV

Figure 16. Typical Rising Propagation Delay (Noninverting)

OUTA/OUTB

INA/INB

08401-023

VDD = 12V TIME = 20ns/DIV

08401-025

Figure 18. Typical Rise Time (Noninverting)

OUTA/OUTB

VDD = 12V

TIME = 20ns/DIV

INA/INB

Figure 17. Typical Falling Propagation Delay (Noninverting)

VDD = 12V

08401-024

TIME = 20ns/DIV

INA/INB

08401-026

Figure 19. Typical Fall Time (Noninverting)

Rev. 0 | Page 9 of 16

Page 10

ADP3629/ADP3630/ADP3631

TEST CIRCUIT

ADP3629/ADP3630/ADP3631

NONINVERTING

INA, INA

INVERTING

NONINVERTING

INB, INB

INVERTING

Figure 20. Test Circuit

OTW

OUTA

VDDPGND

4.7µF

OUTB

CERAMIC

SCOPE PROBE

100nF CERAMIC

LOAD

08401-007

Rev. 0 | Page 10 of 16

Page 11

ADP3629/ADP3630/ADP3631

THEORY OF OPERATION

The ADP3629/ADP3630/ADP3631 family of dual drivers is optimized for driving two independent enhancement N-channel MOSFETs or insulated gate bipolar transistors (IGBTs) in high switching frequency applications.

These applications require high speed, fast rise and fall times, and short propagation delays. The capacitive nature of MOSFETs and IGBTs requires high peak current capability, as well.

ADP3629/ADP3630/ADP3631

INA,

INA

PGND

INB, INB

NONINVERTING

INVERTING

NONINVERTING

INVERTING

OTW

OUTA

VDD

OUTB

LOW-SIDE DRIVERS (OUTA, OUTB)

The ADP3629/ADP3630/ADP3631 family of dual drivers is designed to drive ground referenced N-channel MOSFETs. The bias is internally connected to the V

When the ADP3629/ADP3630/ADP3631 are disabled, both low-side gates are held low. An internal impedance is present between the OUTA/OUTB pins and GND, even when V not present; this feature ensures that the power MOSFET is normally off when bias voltage is not present.

When interfacing the ADP3629/ADP3630/ADP3631 to external MOSFETs, the designer should consider ways to create a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the OUTA and OUTB pins, as well as on the external MOSFET.

Power MOSFETs are usually selected to have low on resistance to minimize conduction losses, which usually implies a large input gate capacitance and gate charge.

supply and to PGND.

08401-017

Figure 21. Typical Application Circuit

INPUT DRIVE REQUIREMENTS (INA, INA, INB, INB, AND SD)

The inputs of the ADP3629/ADP3630/ADP3631 are designed to meet the requirements of modern digital power controllers; the signals are compatible with 3.3 V logic levels. At the same time, the input structure allows for input voltages as high as V

INA

The signals applied to the inputs (INA,

, INB, and should have steep and clean fronts. It is not recommended that slow changing signals be applied to drive these inputs because such signals can result in multiple switching output signals when the thresholds are crossed, causing damage to the power MOSFET or IGBT.

An internal pull-down resistor is present at the input, which guarantees that the power device is off in the event that the input is left floating.

The SD input has a precision comparator with hysteresis and is therefore suitable for slow changing signals (such as a scaleddown output voltage); see the Shutdown (SD) Function section for more information about this comparator.

INB

)

SHUTDOWN (SD) FUNCTION

The ADP3629/ADP3630/ADP3631 feature an advanced shutdown function with accurate thresholds and hysteresis.

The SD signal is an active high signal. An internal pull-up is present on this pin and, therefore, it is necessary to pull down the pin externally for the drivers to operate normally.

In some power systems, it is sometimes necessary to provide an

additional overvoltage protection (OVP) or overcurrent protection (OCP) shutdown signal to turn off the power devices (MOSFETs or IGBTs) in case of failure of the main controller.

An accurate internal reference is used for the SD comparator so that it can be used to detect OVP or OCP fault conditions.

DC OUTPUT

AC INPUT

OUTA PGND

–

Rev. 0 | Page 11 of 16

ADP3629/ADP3630/ADP3631

Figure 22. Shutdown Function Used for Redundant OVP

8401-018

Page 12

ADP3629/ADP3630/ADP3631

OVERTEMPERATURE PROTECTIONS

The ADP3629/ADP3630/ADP3631 provide two levels of overtemperature protection:

VDD

OTW

)

3.3

• Overtemperature warning (

• Overtemperature shutdown

The overtemperature warning is an open-drain logic signal and is active low. In normal operation, when no thermal warning is present, the signal is high, whereas when the warning threshold is crossed, the signal is pulled low.

PCB LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed circuit boards (PCBs) for the ADP3629/ADP3630/ADP3631:

• Trace out the high current paths and use short, wide

(>40 mil) traces to make these connections.

• Minimize trace inductance between the OUTA and OUTB

outputs and the MOSFET gates.

• Connect the PGND pin as close as possible to the source of

the MOSFETs.

• Place the VDD bypass capacitor as close as possible to the

VDD and PGND pins.

• When possible, use vias to other layers to maximize thermal

conduction away from the IC.

FLAGIN

ADP3629/ADP3630/ADP3631

ADP1043

08401-019

ADP3629/ADP3630/ADP3631

Figure 23.

OTW

The

open-drain configuration allows the connection

PGND

VDD

OTW

PGND

OTW

Signaling Scheme Example

of multiple devices to the same warning bus in a wire-OR’ed configuration, as shown in . Figure 23

The overtemperature shutdown turns off the device to protect it in the event that the die temperature exceeds the absolute maximum limit of 150°C (see Table 2 ).

SUPPLY CAPACITOR SELECTION

A local bypass capacitor for the supply input (VDD) of the ADP3629/ADP3630/ADP3631 is recommended to reduce the noise and to supply some of the peak currents that are drawn.

An improper decoupling can dramatically increase the rise times, cause excessive resonance on the OUTA and OUTB pins, and, in some extreme cases, even damage the device due to inductive overvoltage on the VDD or OUTA/OUTB pins.

The minimum capacitance required is determined by the size of the gate capacitances being driven, but as a general rule, a 4.7 μF, low ESR capacitor should be used. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. To further reduce noise, use a smaller ceramic capacitor (100 nF) with a better high frequency characteristic in parallel with the main capacitor.

Place the ceramic capacitor as close as possible to the ADP3629/ ADP3630/ADP3631 device and minimize the length of the traces going from the capacitor to the power pins of the device.

Figure 24 shows an example of the typical layout based on the preceding guidelines.

08401-027

Figure 24. External Component Placement Example

PARALLEL OPERATION

The two driver channels in the ADP3629 and ADP3630 devices can be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver.

The connection scheme for the ADP3630 is shown in Figure 25. In this configuration, INA and INB are connected together, and OUTA and OUTB are connected together.

Particular attention must be paid to the layout in this case to optimize load sharing between the two drivers.

ADP3630

INA

PGND

Figure 25. Parallel Operation

OTW

OUTA

VDD

OUTBINB

08401-021

Rev. 0 | Page 12 of 16

Page 13

ADP3629/ADP3630/ADP3631

THERMAL CONSIDERATIONS

When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding the maximum junction temperature.

Data on package thermal resistance is provided in Ta ble 3 to help the designer in this task.

Several equally important aspects must also be considered.

• Gate charge of the power MOSFET being driven

• Bias voltage value used to power the driver

• Maximum switching frequency of operation

• Value of external gate resistance

• Maximum ambient (and PCB) temperature

• Type of package

All of these factors influence and limit the maximum allowable power dissipated in the driver.

The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as C useful to calculate power losses.

The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under Q This parameter varies from a few nanocoulombs (nC) to several hundreds of nC and is specified at a specific V or 4.5 V).

The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as follows:

= VGS × QG × fSW

GATE

where:

is the bias voltage powering the driver (VDD).

is the total gate charge.

is the maximum switching frequency.

The power dissipated for each gate (P

) must be multiplied

GATE

by the number of drivers (in this case, 1 or 2) being used in each package; this P

value represents the total power dissipated in

GATE

charging and discharging the gates of the power MOSFETs.

Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, R The larger the external gate resistor, the smaller the amount of power that is dissipated in the gate driver.

In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and to minimize switching losses.

, it is not

ISS

value (10 V

In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be ignored, and the extra loss is assumed to be in the driver, providing a good guard band for the power loss calculations.

In addition to the gate charge losses, there are also dc bias losses (P

) due to the bias current of the driver. This current is present

regardless of the switching frequency.

= VDD × IDD

The total estimated loss is the sum of P

= PDC + (n × P

LOSS

GATE

)

and P

GATE

where n is the number of gates driven.

When the total power loss is calculated, the temperature increase can be calculated as follows:

ΔT

= P

× θJA

LOSS

Design Example

For example, consider driving two IRFS4310Z MOSFETs with a

of 12 V at a switching frequency of 100 kHz, using an

ADP3630 in the MSOP package.

The maximum PCB temperature considered for this design is 85°C.

From the MOSFET data sheet, the total gate charge is Q

= 12 V × 120 nC × 100 kHz = 144 mW

GATE

= 12 V × 1.2 mA = 14.4 mW

= 14.4 mW + (2 × 144 mW) = 302.4 mW

LOSS

= 120 nC.

The MSOP thermal resistance is 162.2°C/W (see Table 3 ).

ΔT

= 302.4 mW × 162.2°C/W = 49.0°C

= TA + ΔTJ = 134.0°C ≤ T

J_MAX

This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band.

If a lower junction temperature is required by the design, the SOIC_N package, which provides a thermal resistance of 110.6°C/W, can be used. Using the SOIC_N package, the maximum junction temperature is

ΔT

= 302.4 mW × 110.6°C/W = 33.4°C

= TA + ΔTJ = 118.4°C ≤ T

J_MAX

Other options to reduce power dissipation in the driver include reducing the value of the V

bias voltage, reducing the switching

frequency, and choosing a power MOSFET with a smaller gate charge.

Rev. 0 | Page 13 of 16

Page 14

ADP3629/ADP3630/ADP3631

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLI M E TERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 26. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

0.40

0.25

5.15

4.90

4.65

1.10 MAX

15° MAX

6° 0°

0.23

0.13

0.70

0.55

0.40

091709-A

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 27. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADP3629ARZ-R7 ADP3629ARMZ-R7 ADP3630ARZ-R7 ADP3630ARMZ-R7 ADP3631ARZ-R7 ADP3631ARMZ-R7

Z = RoHS Compliant Part.

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2,500

Temperature Range Package Description

Package Option

Ordering Quantity Branding

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2,500

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 3,000 L8Q

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2,500

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 3,000 L8R

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 3,000 L8S

Rev. 0 | Page 14 of 16

Page 15

ADP3629/ADP3630/ADP3631

NOTES

Rev. 0 | Page 15 of 16

Page 16

ADP3629/ADP3630/ADP3631

NOTES

Rev. 0 | Page 16 of 16

Datasheet ADP3629 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUIT

THEORY OF OPERATION

LOW-SIDE DRIVERS (OUTA, OUTB)

SHUTDOWN (SD) FUNCTION

OVERTEMPERATURE PROTECTIONS

PCB LAYOUT CONSIDERATIONS

SUPPLY CAPACITOR SELECTION

PARALLEL OPERATION

THERMAL CONSIDERATIONS

Design Example

OUTLINE DIMENSIONS

ORDERING GUIDE