Page 1
50 mA Switched Capacitor
a
Voltage Boost with Regulated Output
FEATURES
Fully Regulated Output Voltage (5 V and Adjustable)
Input Voltage Range From 3 V to 5 V
50 mA Output Current
Output Accuracy: ⴞ5%
High Switching Frequency: 250 kHz
SO-8 and TSSOP-8 Packages
–40ⴗC to +85ⴗC Ambient Temperature Range
APPLICATIONS
Computer Peripherals and Add-On Cards
Portable Instruments
Battery Powered Devices
Pagers and Radio Control Receivers
Disk Drives
Mobile Phones
GENERAL DESCRIPTION
The ADP3607 is a 50 mA regulated output switched capacitor
voltage doubler. It provides a regulated output voltage with
minimum voltage loss and requires a minimum number of external components. In addition, the ADP3607 does not require
the use of an inductor.
The internal oscillator of the ADP3607 runs at 500 kHz nominal frequency, which produces an output switching frequency of
250 kHz. This allows for the use of smaller charge pump and
filter capacitors.
The ADP3607 provides an accuracy of ±5% with a typical shutdown current of 150 µA. It can also operate from a single posi-
tive input voltage as low as 3 V. The ADP3607 is offered with
the regulation fixed at 5 V, or adjustable via external resistors
over a 3 V to 9 V range.
ADP3607
FUNCTIONAL BLOCK DIAGRAM
C
D1
GND
–
P
S3
S4
V
OUT
FB
GND
V
OUT
V
SENSE
+
*C
4.7mF
V
SENSE
V
OUT
5.0V
O
C
+
P
V
IN
SD
3.3V
S1
S2
OSC
CLOCK
GEN
1.5 V
V
REF
SD103
V
IN
+
*C
IN
4.7mF
*C
4.7mF
OFF
*FOR BEST PERFORMANCE, 10mF IS RECOMMENDED
C
P
C
IN
SD
ON
0
: SPRAGUE, 293D475X0010B2W
, CO: TOKIN, 1E475ZY5UC205F
P
+
V
IN
CP+
ADP3607-5
C
–
P
Figure 1. Typical Application Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Page 2
1, 2, 3
WARNING!
ESD SENSITIVE DEVICE
ADP3607–SPECIFICATIONS
Parameter Symbol Condition Min Typ Max Units
OPERATING SUPPLY RANGE V
SUPPLY CURRENT I
Shutdown Mode VSD = V
OUTPUT VOLTAGE
4
LOAD REGULATION ∆V
OUTPUT RESISTANCE (Open Loop) R
OUTPUT RIPPLE VOLTAGE V
SWITCHING FREQUENCY f
SHUTDOWN
Logic Input High V
Input Current I
Logic Input Low V
Input Current I
NOTES
1
Capacitors CIN, CO and C
2
See Figure 1 conditions.
3
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
4
For the adjustable version, a 1% resistor should be used to maintain output voltage tolerance. For both device types, tolerances can be improved by >1% using larger
value and lower ESR capacitors for CO and CP.
Specifications subject to change without notice.
in the test circuit are 4.7 µF with 0.1 Ω ESR. Capacitors with higher ESR may reduce output voltage and efficiency.
P
S
S
V
O
V
O
O
RIPPLE
S
IH
IH
IL
IL
O/IO
(VIN = 3.3 V @ TA = +25ⴗC, CP = CO = 4.7 F unless otherwise noted.)
3.0 3.3 5 V
–40°C < TA < +85°C 3.5 6 mA
, –40°C < TA < +85°C 150 200 µA
IN
IO = 25 mA 4.85 5 5.15 V
IO = 10 mA to 50 mA 4.75 5 5.25 V
–40°C ≤ T
≤ +85°C
A
3.0 V ≤ VS ≤ 3.6 V
IO = 10 mA–25 mA 0.3 mV/mA
IO = 10 mA–50 mA 0.25 mV/mA
11 Ω
C
= C
= 4.7 µF
IN
O
= 25 mA 16 mV
I
LOAD
I
= 50 mA 31 mV
LOAD
VIN = 3.3 V
–40°C < TA < +85°C 212 250 288 kHz
2.4 V
1 µA
0.4 V
1 µA
ABSOLUTE MAXIMUM RATINGS
(T
= +25°C unless otherwise noted)
A
Input Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . +7.5 V
Output Voltage (V
Output Short Circuit Protection . . . . . . . . . . . . . . . . . . . 1 sec
θ
, SO-8 Package
JA
, TSSOP-8 Package
θ
JA
to GND) . . . . . . . . . . . . . . . . . . +12 V
OUT
2
. . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
2
. . . . . . . . . . . . . . . . . . . . . . 208°C/W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
1
ORDERING GUIDE
Model Output Voltage Package Option*
ADP3607AR-5 5 V, 50 mA SO-8
ADP3607AR Adjustable, 50 mA SO-8
ADP3607ARU-5 5 V, 50 mA RU-8
ADP3607ARU Adjustable, 50 mA RU-8
*SO = Small Outline Package; RU = Thin Small Outline Package.
Contact the factory for the availability of other output voltage options.
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTES
1
This is a stress rating only, operation beyond these limits can cause the device to be
permanently damaged.
2
θ
is specified for worst case conditions with device soldered on a circuit board.
JA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3607 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–2–
REV. 0
Page 3
ADP3607
Table I. Other Members of ADP360x Family
1
Output Package
Model Current Option2Comments
ADP3603AR 50 mA SO-8 Nom. –3 V ± 3% Inverter
ADP3604AR 120 mA SO-8 Nom. –3 V ± 3% Inverter
ADP3605AR-3 120 mA SO-8 Nom. –3 V ± 5% Inverter
ADP3605AR 120 mA SO-8 Adj. Output Inverter
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline package.
Table II. Alternative Capacitor Technologies
High
T
ype Life Freq Temp Size Cost
Aluminum
Electrolytic
Capacitor Fair Fair Fair Small Low
Multilayer
Ceramic
Capacitor Long Good Poor Fair High
Solid
Tantalum
Capacitor Above Avg Avg Avg Avg Avg
OS-CON
Capacitor Above Avg Good Good Good Avg
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
1C
2V
+ Positive Terminal for the Pump Capacitor.
P
IN
Input Voltage. Connect a low ESR bypass
capacitor between this pin and device
ground to minimize supply transients.
3C
– Negative Terminal for the Pump Capacitor.
P
4 SD Logic Level Shutdown. Apply a logic Hi or
connect to V
to shut down the device. In
IN
Shutdown mode, the charge pump is turned
off and quiescent current is reduced. Apply
a logic low or connect to ground for normal
operation.
5V
SENSE
Output Voltage Sense Line. This is used to
improve load regulation by eliminating IR
drops on the high current carrying output
traces. For normal operation, connect
V
SENSE
to V
. See Application Informa-
OUT
tion section for more detail.
6 NC No Connection.
7 GND Ground.
8V
OUT
Regulated Output Voltage. Connect a low
ESR, 4.7 µF or larger capacitor between
this pin and device GND.
PIN CONFIGURATION
Table III. Recommended Capacitor Manufacturers
Manufacturer Capacitor Capacitor Type
Sprague 672D, 673D,
674D, 678D Aluminum Electrolytic
Sprague 675D, 173D,
199D Tantalum
Nichicon PF and PL Aluminum Electrolytic
Mallory TDC and TDL Tantalum
TOKIN MLCC Multilayer Ceramic
MuRata GRM Multilayer Ceramic
1
+
C
P
2
ADP3607
V
IN
TOP VIEW
3
CP–
(Not to Scale)
4
SD
NC = NO CONNECT
8
V
OUT
7
GND
6
NC
5
V
SENSE
REV. 0
–3–
Page 4
ADP3607
–Typical Performance Characteristics
270
265
260
255
OSCILLATOR FREQUENCY – kHz
250
3.0 3.5
SUPPLY VOLTAGE – Volts
4.0
4.5
Figure 2. Oscillator Frequency vs. Supply Voltage
5.05
5.03
IL = 10mA
5.01
IL = 25mA
5.0
4.00
3.75
VIN = +5.0V
3.50
SUPPLY CURRENT – mA
3.25
3.00
–40 –15 10 35 60 85
= +4.0V
V
IN
VIN = +3.0V
TEMPERATURE – 8C
VIN = +3.3V
Figure 5. Supply Current vs. Temperature in Normal Mode
300
280
260
4.99
OUTPUT VOLTAGE – Volts
4.97
4.95
–40 –15 8510 35 60
IL = 50mA
TEMPERATURE – 8C
Figure 3. Output Voltage vs. Temperature
125
100
75
50
25
AVERAGE INPUT CURRENT – mA
0
10 15
20 25 30 35 40 45 50
OUTPUT CURRENT – mA
Figure 4. Average Input Current vs. Output Current
240
220
OSCILLATOR FREQUENCY – kHz
200
–40 –15 8510 35 60
TEMPERATURE – 8C
Figure 6. Oscillator Frequency vs. Temperature
5.05
5.00
4.95
VIN = +5.0V
4.90
VIN = +4.0V
4.85
VIN = +3.3V
4.80
OUTPUT VOLTAGE – Volts
VIN = +3.0V
4.75
4.70
0
LOAD CURRENT – mA
125755025
100 150 175
Figure 7. Output Voltage vs. Load Current
200
–4–
REV. 0
Page 5
ADP3607
3.7
3.6
FIXED VERSION
3.5
ADJUSTABLE VERSION
R = 38kV
SUPPLY CURRENT – mA
3.4
3.3
3.0 3.5
SUPPLY VOLTAGE – Volts
4.0
4.5
Figure 8. Supply Current vs. Supply Voltage in
Normal Mode
240
VIN = +5.0V
220
200
180
VIN = +4.0V
5.0
300
250
200
FIXED VERSION
150
100
SUPPLY CURRENT – mA
50
0
3.0 3.5
SUPPLY VOLTAGE – Volts
ADJUSTABLE VERSION
R = 38kV
4.0
4.5
Figure 11. Supply Current vs. Supply Voltage in
Shutdown Mode
80
70
60
50
40
5.0
160
SUPPLY CURRENT – mA
140
120
–40 –15 10 35 60 85
VIN = +3.3V
V
= +3.0V
IN
TEMPERATURE – 8C
Figure 9. Supply Current vs. Temperature in
Shutdown Mode
V
= +5.0V
O
V
OUT
= 0V
V
O
V
= +3.3V
1.12V
IN
= 0V
V
IN
V
IN
CH1 2.00V
T
CH2
2.00V M2.00ms
CH2
Figure 10. Start-up Under Full Load Based on Circuit of
Figure 1
30
EFFICIENCY – %
20
10
0
04050
LOAD CURRENT – mA
302010
Figure 12. Efficiency vs. Load Current Based on Circuit of
Figure 1
VO = +5.0V
V
OUT
V
= +4.96V
O
I
= 50mA
O
I
L
B
20.0mV CH4
CH2
CH4 10.0mV
M4.00ms
W
V
B
W
IO = 1mA
9.0mV
Figure 13. Load Transient Response Based on Circuit of
Figure 1
REV. 0
–5–
Page 6
ADP3607
THEORY OF OPERATION
The ADP3607 uses a switched capacitor principle to generate
a regulated boost voltage from a positive input voltage. An
on-board oscillator generates a two-phase clock to control a
switching network that transfers charge between the storage
capacitors. The switches turn on and off at a 250 kHz rate that
is generated from an internal 500 kHz oscillator. The basic
principle behind the voltage conversion scheme is illustrated in
Figures 14 and 15.
V
IN
C
S2S1
+
P
–
S3S4
V
OUT
Figure 14. ADP3607 Switch Configuration Charging the
Pump Capacitor
During phase one, S1 and S3 are ON, charging the pump capacitor to the input voltage. Before the next phase begins, S1
are turned OFF, as are S2 and S4 to prevent any over-
and S3
lap. S2 and S4
are turned ON during the second phase (see
Figure 15) and charge stored in the pump capacitor is transferred to the output capacitor.
V
IN
S1
C
S4
S2
+
P
–
S3
V
OUT
Figure 15. ADP3607 Switch Configuration Charging the
Output Capacitor
During the second phase, the negative terminal of the pump
capacitor is connected to V
through variable resistance switch
IN
S4, and the positive terminal is connected to the output, resulting in a voltage shift at the output terminal. The ADP3607
block diagram is shown on the front page.
10
ALUMINUM
1.0
CERAMIC
TANTALUM
ESR – V
0.1
ORGANIC SEMIC
0.01
–50 100
0
TEMPERATURE – 8C
50
Figure 16. ESR vs. Temperature
APPLICATION INFORMATION
Capacitor Selection
The ADP3607’s high internal oscillator frequency permits the
use of small capacitors for both the pump and the output capacitors. For a given load current, factors affecting the output
voltage performance are:
• Pump (C
• ESR of the C
) and output (CO) capacitance.
P
and CO.
P
–6–
When selecting the capacitors, keep in mind that not all manufacturers guarantee capacitor ESR in the range required by the
circuit. In general, the capacitor’s ESR is inversely proportional
to its physical size, so larger capacitance values and higher voltage ratings tend to reduce ESR. Since the ESR is also a function
of the operating frequency, when selecting a capacitor make sure
its value is rated at the circuit’s operating frequency. Another
factor affecting capacitor performance is temperature.
Figure 16 illustrates the temperature effect on various capacitors. If the circuit has to operate at temperatures significantly
different from +25°C, the capacitance and ESR values must be
carefully selected to adequately compensate for the change.
Various capacitor technologies offer improved performance over
temperature; for example, certain tantalum capacitors provide
good low temperature ESR but at a higher cost. Table II provides the ratings for different types of capacitor technologies to
help the designer select the right capacitors for the application.
The exact values of C
and CO are not critical. However, low
IN
ESR capacitors such as solid tantalum and multilayer ceramic
capacitors are recommended to minimize voltage loss at high
currents. Table III shows a partial list of the recommended low
ESR capacitor manufacturers.
40
I
LOAD
ADP3607-5
= 50mA
150mV
100mV
50mV
35
30
25
20
OUTPUT RIPPLE – mV
15
10
5
0
20
40 60 80 100 120 140
CAPACITANCE – mF
Figure 17. Output Ripple Voltage (mV) vs. Capacitance
and ESR
Input Capacitor
A small 1 µF input bypass capacitor (preferably with low ESR)
such as tantalum or multilayer ceramic, is recommended to
reduce noise and supply transients, and supply part of the peak
input current drawn by the ADP3607. A large capacitor is recommended if the input supply is connected to the ADP3607
through long leads, or if the pulse current drawn by the device
might affect other circuitry through supply coupling.
Output Capacitor
The output capacitor (CO) is alternately charged to the CP voltage when C
introduces steps in the V
pump charges C
ceramic or tantalum capacitors are recommended for C
is switched in parallel with CO. The ESR of C
P
, which contributes to V
O
waveform whenever the charge
OUT
ripple. Thus,
OUT
O
O
to
minimize ripple on the output. Figure 17 illustrates the output
ripple voltage effect for various capacitance and ESR values.
Note that as the capacitor value increases beyond the point
where the dominant contribution to the output ripple is due to
the ESR, no significant reduction in V
ripple is achieved by
OUT
added capacitance. Since output current is supplied solely by
REV. 0
Page 7
ADP3607
the output capacitor, CO, during one-half of the charge-pump
cycle, peak-to-peak output ripple voltage is calculated by using
the following formula.
I
V
RIPPLE
=
L
FC
××
2
PUMP O
I ESR
+× ×
2
LCO
where
I
= Load Current
L
F
= 250 kHz nominal switching frequency
PUMP
C
= 10 µF with an ESR of 0.15 Ω
O
mA
V
RIPPLE
=
50
kHz F
××
2 250 10
+× ×
250 015
µ
mA
.
= 25 mV
Multiple smaller capacitors can be connected in parallel to yield
lower ESR and potential cost savings. For lighter loads, proportionally smaller capacitors are required. To reduce high frequency
noise, bypass the output with a 0.1 µF ceramic capacitor in parallel
with the output capacitor.
Pump Capacitor
The ADP3607 alternately charges CP to the input voltage when
C
is switched in parallel with the input supply, and then trans-
P
fers charge to C
ing the time C
two times the output current. During the time C
charge to C
when CP is switched in parallel with CO. Dur-
O
is charging, the peak current is approximately
P
, the supply current drops down to about 3 mA.
O
is delivering
P
A low ESR capacitor has much greater impact on performance
for C
than CO since current through CP is twice the CO cur-
P
rent. Therefore, the voltage drop due to C
the ESR of C
times the load current. While the ESR of C
P
is about four times
P
O
affects the output ripple voltage, the voltage drop generated by
the ESR of C
put source resistance, determines the maximum available V
combined with the voltage drop due to the out-
P,
OUT
.
Improved Load Regulation
In most applications, IR drops due to printed circuit board
traces are not critical. V
should be connected to the output
SENSE
at a convenient pcb location close to the load. However, if a
reduction in IR drops, or improvement in load regulation is
desired, the sense line can be used to monitor the output voltage
at the load. To avoid excessive noise pickup, keep the V
SENSE
line as short as possible and away from any noisy line.
Shutdown Mode
The ADP3607’s output can be disabled by pulling the SD Pin
to a TTL/CMOS logic high level which will stop the internal
oscillator. Applying a logic low will turn ON the oscillator. If
the shutdown feature is not used, the SD pin should be tied to
ground. The shutdown mode current is dominated by the resistor divider connected to the V
pin. This current can be
SENSE
calculated using one of the following formulas.
5 V fixed output version:
VV
( –. )
I
SENSE SDIN()
=
03
k
.
23 75 Ω
Adjustable output version:
VV
( –. )
03
IN
=
kR
(. )
95 Ω
+
EXT
where R
is in kΩ.
EXT
I
SENSE SD
()
Because of the external Schottky diode between V
and V
IN
the output voltage will be held to a diode drop below V
when
IN
OUT
,
the ADP3607 is in shutdown mode.
Power Dissipation
The power dissipation of the ADP3607 circuit must be limited
such that the junction temperature of the device does not exceed
the maximum junction temperature rating. Total power dissipation is calculated as follows:
P = (2 VIN – V
Where I
and V
and IS are output current and supply current, V
OUT
are input and output voltages respectively.
OUT
For example: assuming worst case conditions, V
V
OUT
= 5 V, I
= 50 mA and IS = 6 mA. Calculated device
OUT
OUT
) I
+ (VIN) I
OUT
S
= 5 V,
IN
IN
power dissipation is:
P ≈ (2 × 5 V – 5 V)(0.05 A) + (5 V)(0.006 A) = 280 mW
This is far below the 660 mW power dissipation capability of the
ADP3607.
General Board Layout Guidelines
Since the ADP3607’s internal switches turn on and off very
quickly, good PC board layout practices are critical to ensure
optimal operation of the device. Improper layouts will result in
poor load regulation, especially with heavy loads. Following
these simple layout guidelines will improve output performance.
1. Use adequate ground and power traces or planes.
2. Use single point ground for device ground and input and
output capacitor grounds.
3. Keep external components as close to the device as possible.
4. Use short traces from the input and output capacitors
to the input and output pins respectively.
Maximum Output Voltage
Maximum unregulated output voltage can be obtained by connecting the V
pin to ground instead of to the V
SENSE
OUT
pin (see
Figure 18). Under this condition, the magnitude of the unregulated output voltage depends on the load current. V
OUT
is
inversely proportional to the load current.
7.3
7.1
6.9
6.7
6.5
6.3
6.1
OUTPUT VOLTAGE – Volts
5.9
5.7
5.5
0
V
4.7mF
VIN = 3.3V
IN
+
C
IN
4.7mF
C
+
P
10 50540453530252015
V
CP+
C
IN5819
D1
V
IN
V
SENSE
–
P
SD
OUTPUT CURRENT – mA
OUT
GND
VIN = 3.6V
V
O
+
C
O
4.7mF
Figure 18. Maximum Unregulated Output Voltage
REV. 0
–7–
Page 8
ADP3607
Regulated Adjustable Output Voltage
For the adjustable version of the ADP3607, the regulated output voltage is programmed by a resistor that is inserted between
the V
SENSE
and V
pins, as illustrated in Figure 19. The in-
OUT
herent limit of the output voltage of a single doubling charge
pump stage is two times the input voltage. The scaling factor of
2.00 is reduced somewhat due to losses that increase with output current. To increase the scaling factor to attain a more
positive output voltage, an external pump stage can be added
with just passive components as shown in Figure 20. That single
stage increases the scaling factor to a limit of 3, although the
diode drops will limit the ability to noticeably attain that exact
3.00 scaling factor. Even further increases can be achieved
with more external pump stages. High accuracy on the adjustable output is achieved through the use of precision trimmed
internal resistors, which eliminates the need to trim the external
resistor or add a second resistor to form a divider. The adjustable output voltage is set using the following formula:
OUT
V
CP+
C
SD
IN5819
IN
P
V
–
D1
V
SENSE
GND
R
=+
951.
OUT
+
R
C
4.7mF
V
O
O
R = 47.5kV
R = 24.9kV
where V
OUT
6.5
6.0
5.5
5.0
4.5
OUTPUT VOLTAGE – Volts
4.0
3.5
V
is in volts and R is in kΩs.
VIN = 3.3V
+
C
IN
+
C
P
4.7mF
4.7mF
10 50
540453530252015
0
OUTPUT CURRENT – mA
Figure 19. Regulated Adjustable Output Voltage
D3
IN5819
C1
4.7mF
+
ADP3607
CP+
V
+
C
P
4.7mF
V
IN
+
C
IN
4.7mF
OUT
–
C
P
V
SENSE
V
IN
GND
SD
D2
SD103
D1
1N5819
+
C
4.7mF
12V
+
C
O2
4.7mF
R1
104.5kV
O
Figure 20. Regulated 12 V from a 5 V Input
Regulated Dual Supply System
The circuit in Figure 21 provides regulated positive and negative
voltages for systems that require dual supplies from a single
battery or power supply.
SD103
ADP3607-5
VIN = +3.3V
10mF
V
V
IN
CP+
C
OUT
V
SENSE
–
P
GND
SD
+
C
+
P1
10mF
+
C
O1
10mF
+5V
ADP3605
C
+
10mF
–2.6V
O2
C
10mF
V
V
IN
OUT
CP+
+
P2
V
SENSE
C
–
P
GND
SD
R1
16.5kV
1%
Figure 21. Regulated Dual Supply System
C3500–8–8/99
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.1968 (5.00)
0.1890 (4.80)
8
PIN 1
0.0500
(1.27)
BSC
8-Lead SOIC
(SO-8)
5
0.2440 (6.20)
41
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.0196 (0.50)
0.0099 (0.25)
8°
0°
x 45°
0.0500 (1.27)
0.0160 (0.41)
–8–
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.122 (3.10)
0.114 (2.90)
85
41
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
8-Lead TSSOP
(RU-8)
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
PRINTED IN U.S.A.
88
08
0.028 (0.70)
0.020 (0.50)
REV. 0
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