Datasheet ADP3417 Datasheet (Analog Devices)

Dual Bootstrapped

a

FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry

APPLICATIONS
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations

GENERAL DESCRIPTION

The ADP3417 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa­gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers.
The ADP3417 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.

The ADP3417 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.

MOSFET Driver

ADP3417

FUNCTIONAL BLOCK DIAGRAM

VCC

IN

OVERLAP

PROTECTION

CIRCUIT

ADP3417

VCC

ADP3417

IN

DELAY

BST

PGND

BST

C

BST

DRVH

SW

D1

DRVH

SW

DRVL

12V

Q1

TO
INDUCTOR

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

1V

1V

DRVL

PGND

Q2

Figure 1. General Application Circuit

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

1

ADP3417–SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY

Supply Voltage Range VCC 4.15 13.2 V
Quiescent Current ISYS VCC = BST = 12 V, IN = 0 V 5 7 mA

PWM INPUT

Input Voltage High
Input Voltage Low

HIGH SIDE DRIVER

Output Resistance, Sourcing Current V
Output Resistance, Sinking Current V
Transition Times

Transition Times

Propagation Delay

LOW SIDE DRIVER

Output Resistance, Sourcing Current VCC = 12 V 1.75 3.0 Ω
Output Resistance, Sinking Current VCC = 12 V 1.0 2.5 Ω
Transition Times

Propagation Delay

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).

3

AC specifications are guaranteed by characterization but not production tested.

4

For propagation delays, “TPDH” refers to the specified signal going high; “TPDL” refers to it going low.

Specifications subject to change without notice.

2

2

3

3

3, 4

3

3, 4

(See Figure 2) tpdh

tr

DRVH

tf

DRVH

tpdh
tpdl

tr

DRVL

tf

DRVL

tpdl

DRVH

DRVH

DRVL

DRVL

(VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 70C, unless otherwise noted.)

2.5 V

0.8 V

– VSW = 12 V 1.75 3.0 Ω

BST

– VSW = 12 V 1.0 2.5 Ω

BST

See Figure 2, V

= 3 nF

C

LOAD

See Figure 2, V

= 3 nF

C

LOAD

See Figure 2, V
V

– V

BST

SW

– VSW = 12 V, 45 55 ns

BST

– VSW = 12 V, 20 30 ns

BST

– V

BST

= 12 V, 45 65 ns

SW

= 12 V 15 35 ns

See Figure 2, VCC = 12 V, 25 35 ns
C

= 3 nF

LOAD

See Figure 2, VCC = 12 V, 21 30 ns

= 3 nF

C

LOAD

See Figure 2, VCC = 12 V 30 60 ns
See Figure 2, VCC = 12 V 10 20 ns

–2–

REV. A

ADP3417

ABSOLUTE MAXIMUM RATINGS

*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V

IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

Model Range Description Option

ADP3417JR 0°C to 70°C8-Lead Standard SOIC-8

ORDERING GUIDE

Temperature Package Package

Small Outline (SOIC)

Operating Ambient Temperature Range . . . . . . . 0°C to 70°C

Operating Junction Temperature Range . . . . . . 0°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W

θ

JC

PIN CONFIGURATION

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.

BST

NC

VCC

1

2

IN

3

4

ADP3417

TOP VIEW

(Not To Scale)

NC = NO CONNECT

8

DRVH

7

SW

6

PGND

5

DRVL

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 BST Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins

holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be

chosen between 100 nF and 1 ␮F.
2INLogic-level input signal that has primary control of the drive outputs.
3NC No Connection
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating

return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-

on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the

high low transition delay is determined at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3417 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

WARNING!

ESD SENSITIVE DEVICE

ADP3417

DRVL

IN

tpdl

DRVL

tf

DRVL

tpdh

DRVH

tr

DRVH

tpdl

DRVH

tf

DRVH

tr

DRVL

DRVH-SW

SW

V

TH

V

TH

tpdh

DRVL

1V

Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)

–4–

REV. A

T

3

1

2

TPC 1. DRVH Fall and DRVL
Rise Times

IN

DRVH

DRVL

Typical Performance Characteristics–

60

VCC = 12V
C

= 3nF

T

IN

3

DRVH

1

DRVL

2

TPC 2. DRVL Fall and DRVH
Rise Times

LOAD

50

40

RISE TIME – ns

30

20

025 12550 75 100

JUNCTION TEMPERATURE – C

TPC 3. DRVH and DRVL Rise Times
vs. Temperature

ADP3417

DRVH

DRVL

28

VCC = 12V

= 3nF

C

LOAD

26

DRVL

24

FALL TIME – ns

22

20

0

JUNCTION TEMPERATURE – C

25

50 75 100

DRVH

125

TPC 4. DRVH and DRVL Fall Times
vs. Temperature

60

TA = 25C
VCC = 12V

= 3nF

C

50

LOAD

40

30

20

SUPPLY CURRENT – mA

10

70

TA = 25C
VCC = 12V

60

50

40

RISE TIME – ns

30

20

10

1

2345

LOAD CAPACITANCE – nF

DRVH

DRVL

TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance

16

VCC = 12V

= 3nF

C

LOAD

f

= 250kHz

IN

15

14

13

SUPPLY CURRENT – mA

28

TA = 25C
VCC = 12V

26

24

22

20

FALL TIME – ns

18

16

14

1

2345

LOAD CAPACITANCE – nF

DRVL

DRVH

TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance

0

0 200 400 600

IN FREQUENCY – kHz

TPC 7. Supply Current vs.
Frequency

REV. A

800 1000 1200

12

0255075100

JUNCTION TEMPERATURE – C

TPC 8. Supply Current vs.
Temperature

–5–

125

ADP3417

THEORY OF OPERATION

The ADP3417 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high side and the low side FETs. Each driver
is capable of driving a 3 nF load.

A more detailed description of the ADP3417 and its features
follows. Refer to the Functional Block Diagram.

Low Side Driver

The low side driver is designed to drive low R

DS(ON)

N-channel
MOSFETs. The maximum output resistance for the driver is
3 Ω for sourcing and 2.5 Ω for sinking gate current. The low
output resistance allows the driver to have 25 ns rise times
and 20 ns fall times into a 3 nF load. The bias to the low side
driver is internally connected to the VCC supply and PGND.

When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the ADP3417 is dis­abled, the low side gate is held low.

High Side Driver

The high side driver is designed to drive a floating low R

DS(ON)

N-channel MOSFET. The maximum output resistance for the
driver is 3 Ω for sourcing and 2.5 Ω for sinking gate current.
The low output resistance allows the driver to have 45 ns rise times
and 20 ns fall times into a 3 nF load. The bias voltage for the
high side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW Pins.

The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C

. When the ADP3417 is starting up, the SW Pin

BST

is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high side
driver will begin to turn the high side MOSFET, Q1, ON by
pulling charge out of C
rise up to V

, forcing the BST Pin to VIN + V

IN

. As Q1 turns ON, the SW Pin will

BST

C(BST)

, which is
enough gate to source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt­age at the SW Pin. When the low side MOSFET, Q2, turns
ON, the SW Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again. The high side driver’s
output is in phase with the PWM input.

Overlap Protection Circuit

The overlap protection circuit (OPC) prevents both of the main
power switches, Q1 and Q2, from being ON at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that can
occur during their ON-OFF transitions. The overlap protection
circuit accomplishes this by adaptively controlling the delay from
Q1’s turn OFF to Q2’s turn ON and by internally setting the
delay from Q2’s turn OFF to Q1’s turn ON.

To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at the
SW Pin. When the PWM input signal goes low, Q1 will begin to
turn OFF (after a propagation delay), but before Q2 can turn ON,
the overlap protection circuit waits for the voltage at the SW Pin
to fall from V

to 1 V. Once the voltage on the SW Pin has fallen

IN

to 1 V, Q2 will begin turn ON. By waiting for the voltage on the
SW Pin to reach 1 V, the overlap protection circuit ensures that
Q1 is OFF before Q2 turns on, regardless of variations in tem­perature, supply voltage, gate charge, and drive current.

To prevent the overlap of the gate drives during Q2’s turn OFF
and Q1’s turn ON, the overlap circuit provides a internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn OFF (after a propagation delay), but before
Q1 can turn ON, the overlap protection circuit waits for the
voltage at DRVL to drop to around 10% of VCC. Once the
voltage at DRVL has reached the 10% point, the overlap protec­tion circuit will wait for a 50 ns typical propagation delay. Once
the delay period has expired, Q1 will begin turn ON.

APPLICATION INFORMATION
Supply Capacitor Selection

For the supply input (VCC) of the ADP3417, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size. Keep the ceramic capacitor
as close as possible to the ADP3417.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C

BST

) and a
diode, as shown in Figure 1. Selection of these components can
be done after the high side MOSFET has been chosen.

The bootstrap capacitor must have a voltage rating that is able
to handle the maximum supply voltage. A minimum 25 V rating
is recommended. The capacitance is determined using the
following equation:

Q

C

BST

where, Q
and ∆V

GATE

=

∆

V

BST

is the total gate charge of the high side MOSFET,

GATE

is the voltage droop allowed on the high side MOSFET

BST

(1)

drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot­strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.

A small-signal diode can be used for the bootstrap diode due to
the ample gate drive available for the high side MOSFET. The
bootstrap diode must have a minimum 15 V rating to withstand
the maximum boosted supply voltage. The average forward
current can be estimated by:

IQf

≈×

F(AVG) GATE MAX

where f

is the maximum switching frequency of the control-

MAX

(2)

ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 12 V
supply and the ESR of C

Printed Circuit Board Layout Considerations

BST

.

Use the following general guidelines when designing printed
circuit boards:

1. Trace out the high current paths and use short, wide traces

to make these connections.

2. Connect the PGND Pin of the ADP3417 as close as possible

to the source of the lower MOSFET.

3. The VCC bypass capacitor should be located as close as

possible to VCC and PGND Pins.

–6–

REV. A

ADP3417

Typical Application Circuits

The circuit in Figure 3 shows how three ADP3417 drivers can be combined with the ADP3163 to form a total power conversion
solution for V

CC(CORE)

generation for an Intel Pentium®4 CPU.

CC(CORE)

V

1.1V – 1.85V

2200F/6.3V  9

13m ESR (EACH)

RUBYCON MBZ SERIES

L2

600nH

Q3

FDB7030L

7

6

8

C11

100nF

U2

R7

5m

MLCC

10F  2

D2

D1

1N4148

DRVH

ADP3417

BST
1

1N4148

SW

IN
2

PGND

NC
3

CC(CORE)RTN

V

65A

C29

MLCC

++

C13

15nF

R8

5

DRVL

VCC
4

1F

C12

C20

2

Q7

FDB8030L

10F  27

C14

100nF

U3

D3

Q4

FDB7030L

8

DRVH

DRVH

ADP3417

BST

BST

1

1N4148

L3

600nH

7

SW

SW

IN

IN

234

C16

6

PGND

PGND

NC

NC

15nF

5

DRVL

DRVL

VCC

VCC

R9

C15

2

Q8

FDB8030L

1F

C17

100nF

U4

D4

Q5

FDB7030L

8

DRVH

DRVH

ADP3417

BST

BST
1

1N4148

L4

600nH

7

SW

SW

IN

IN
234

C19

6

PGND

PGND

NC

NC

15nF

5

DRVL

DRVL

VCC

VCC

R10

C18

NC = NO CONNECT

2

Q9

FDB8030L

1F

+

C3

C2

+

270F/16V x 3

OS-CON SP SERIES

L1

1H

18m ESR(EACH)

12V

IN

V

C1

+

Figure 3. 65 A Intel Pentium 4 CPU Supply Circuit, VR Down Guideline Design

C6

R5

20

15nF

R4

10

C4

4.7F

U1

C7

20

20

VCC

1nF

19

19

REF

18

18

PWM1

17

17

PWM2

16

16

PWM3

15

15

PC

14

14

PGND

13

13

CS–

12

12

CS+

11

11

PWRGD

ADP3163

VID4

VID3

VID2

VID1

VID0

SHARE

COMP

2

1

3

5

314

CPU

5

4

A

R

32.4k
Q1

2N7000

2

FROM

RTN

IN

V

6

6107

7

R2

10k

GNDFBCT
8

9

8

9

B

R

10.0k

OC

C

1.2nF

C9

150pF

R3

1k

C10

100pF

10

U5

1/6 7404

OUTEN

REV. A

–7–

ADP3417

OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

C02713–0–8/02(A)

PIN 1

1.27 (0.0500)

PLANE

BSC

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098)

0.10 (0.0040)

SEATING

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0196)

0.25 (0.0099)

8
0

1.27 (0.0500)

0.41 (0.0160)

 45

Revision History

Location Page

08/02—Data Sheet changed from REV. 0 to REV. A.

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

–8–

PRINTED IN U.S.A.

REV. A