Datasheet ADP3415KRM-REEL7, ADP3415KRM-REEL Datasheet (Analog Devices)

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Preliminary Technical Data

PRELIMINARY TECHNICAL DATA

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

ADP3415

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

Dual MOSFET Driver

with Bootstrapping

FUNCTIONAL BLOCK DIAGRAM

VCC

BST

DRVH

SW

DLY

GND

DRVL

ADP3415

SD

DRVLSD

IN

OVERLAP

PROTECTION

CIRCUIT

UVLO

VCC

FEATURES
All-In-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Programmable Transition Delay
Zero-Crossing Synchronous Drive Control
Synchronous Override Control
Undervoltage Lockout
Shutdown Quiescent Current < 10 mA

APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations

GENERAL DESCRIPTION

The ADP3415 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the noniso­lated synchronous buck power converter topology. The driver
sizes are each optimized for performance in notebook PC regula­tors for CPUs in the 20-amp range. The high-side driver can be
bootstrapped atop the switched node of the buck converter as
needed to drive the upper switch, and is designed to accommo­date the high voltage slew-rate associated with high-performance
high-frequency switching. The ADP3415 has several features: an
overlapping protection circuit (OPC) undervoltage lockout (UVLO)
that holds the switches off until the driver is assured of having
sufficient voltage for proper operation, a programmable transition
delay, and a synchronous drive disable pin. The quiescent
current, when the device is disabled, is less than 100 mA.

The ADP3415 is available in a 10-lead MSOP package.

BST

DRVH

SW

SD

IN

DRVLSD

DLY

GND

DRVL

ADP3415

V

DC-IN

V

OUT

5V

FROM SYSTEM

ENABLE CONTROL

FROM DUTY RATIO

MODULATOR

FROM SYSTEM

STATE LOGIC

VCC

Figure 1. Typical Application Circuit

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PRELIMINARY TECHNICAL DATA

–2–

ADP3415–SPECIFICATIONS

1

(TA = 0ⴗC to 100ⴗC, VCC = 5 V, V

BST

= 4 V to 26 V, SD = 5 V, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY (VCC)

Supply Voltage Range 4.15 5.0 6.0 V
Quiescent Current I

CCQ

Shutdown Mode V

SD

= 0.8 V 30 65 µA

Operating Mode V

SD

= 5 V, No Switching 1.2 2 mA

UNDERVOLTAGE LOCKOUT(

UVLO)

UVLO Threshold

V

CCUVLO

3.9 4.15 4.5 V

UVLO Hysteresis V

CCHUVLO

0.05 V

SYNCHRONOUS RECTIFIER
SHUTDOWN (DRVLSD)

Input Voltage High

2

V

IH

2.0 V

Input Voltage Low

2

V

IL

0.8 V

Propagation Delay

2, 3

tpdl

DRVLSD

VCC = 4.6 V, 23 50 ns

(See Figure 3) tpdh

DRVLSD

C

LOAD(DRVL)

= 3 nF 17 30 ns

SHUTDOWN (SD)

Input Voltage High

2

V

IH

2.0 V

Input Voltage Low

2

V

IL

0.8 V

INPUT (IN)

Input Voltage High

2

V

IH

2.0 V

Input Voltage Low

2

V

IL

0.8 V

THERMAL SHUTDOWN(THSD)

THSD Threshold T

SD

165 °C

THSD Hysteresis T

HSD

10 °C

HIGH-SIDE DRIVER (DRVH)

Output Resistance, DRVH–BST V

BST

– VSW = 4.6 V 1.5 3.5 Ω

Output Resistance, DRVH–SW V

BST

– VSW = 4.6 V .85 2 Ω

DRVH Transition Times

3

tr

DRVH

,V

BST

– VSW = 4.6 V, C

LOAD

= 3 nF 20 30 ns

(See Figure 4) tf

DRVH

25 35 ns

DRVH Propagation Delay

3, 4

tpdh

DRVH,

V

BST

– VSW = 4.6 V,

V

DLY

= 0 V 10 22 40 ns

(See Figure 4) tpdl

DRVH

40 50 ns

LOW-SIDE DRIVER (DRVL)

Output Resistance, DRVL–VCC VCC = 4.6 V 1.6 3

Ω

Output Resistance, DRVL–GND VCC = 4.6 V 1 3

Ω

DRVL Transition Times

3

tr

DRVL

,V

CC

= 4.6 V, C

LOAD

= 3 nF 27 40 ns

(See Figure 4) tf

DRVL

24 30 ns

DRVL Propagation Delay

3, 4, 6

tpdh

DRVL,

VCC = 4.6 V 5 33 38 ns

(See Figure 4) tpdl

DRVL

14 25 ns

SW Transition Timeout

6

t

SWTO

100 300 ns

Zero-Crossing Threshold V

ZC

1V

DRVH TURN-ON DELAY TIMER t

DLY

Programmable Delay

7

0 ≤ R

DLY

≤ 100 kΩ 0 100 µs

100 kΩ ≤ R

DLY

including open 100 200 µs

Delay Slope7 ⌬t

DLY/RDLY

0 ≤ R

DLY

≤ 100 kΩ 0 1 1.2 ks/kΩ

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Logic inputs meet typical CMOS I/O conditions for source current larger than 100 µA.

3

Guaranteed by characterization.

4

For propagation delays, “tpdh” refers to the specified signal going high, “tpdl” refers to it going low.

5

Propagation delay measured until DRVL begins its transition.

6

The turn-on of DRVL is initiated after IN goes low by either VSW crossing a ~1 V threshold or by expiration of t

SWTO

.

7

This delay represents a programmable extension to the propagation delay of DRVH assertion (t

PDH

DRVH). The additional delay is a linear function of the range

0 ≤ R

DLY

≤ 100 kΩ delay resistor tied from DLY to GND if its value is the specified resistance.

8

The DLY pin may be grounded for no additional delay.

Specifications subject to change without notice.

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PRELIMINARY TECHNICAL DATA

–3–

ADP3415

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 IN TTL-Level Input Signal. Has primary control of the drive outputs.
2 SD Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced low

and the supply current (I

CCQ)

) is minimized as specified.

3 DRVLSD Drive-Low Shutdown. When DRVLSD is low, DRVL is kept low. When DRVLSD is high, DRVL is

enabled and controlled by IN and by the adaptive OPC function.

4 DLY High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-off

of the lower FET to turn-on of the upper FET.

5 VCC Input Supply. This pin should be bypassed to GND with ~10 µF ceramic capacitor.

6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.

7 GND Ground. Should be directly connected to the ground plane, close to the source of the lower FET.

8 SW This pin should be connected to the buck switching node, close to the upper FET’s source. It is the

floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for the
OPC function.

9 DRVH Buck Drive. Output drive for the upper (buck) FET.

10 BST Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holds

this bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be a
MLC type and should have substantially greater capacitance (e.g., ~20⫻) than the input capacitance of
the upper FET.

ORDERING GUIDE

Temperature Package Package
Model Range Description Option

ADP3415KRM-Reel 0°C to 100°C

Mini_SO Package

RM-10

MSOP-10)

ADP3415KRM-Reel7 0°C to 100°C

Mini_SO Package

RM-10

(MSOP-10)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V

SD, IN, DRVLSD to GND . . . . . . . . . . . . . –0.3 V to +7.3 V

Operating Ambient Temperature Range . . . . . . 0°C to 100°C

Operating Junction Temperature Range . . . . . . 0°C to 125°C

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

PIN CONFIGURATION

10-Lead Mini_SO Package (MSOP)

(RM-10)

TOP VIEW

(Not to Scale)

10

9

8

7

6

1

2

3

4

5

IN

SD

DRVLSD

DLY

BST

DRVH

SW

GND

ADP3415

VCC

DRVL

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PRELIMINARY TECHNICAL DATA

ADP3415

–4–

VCC

BST

DRVH

SW

IN

DLY

GND

DRVL

ADP3415

V

DC-IN

5V

VCC

SD

R

DLY

C

BST

DRVLSD

VCC

D1

UVLO

EN

TIME OUT

DELAY

TURN ON

DELAY

BIAS

TSD

UVLO

TSD

THERMAL

SHUTDOWN

TSD

DRVL

10%

VCC

SQ

R

VCC

SQ

R

SQ

R

UVLO

4.15V

DRVH

Figure 2. Functional Block Diagram

IN

DRVL

D

RVLSD

0.8V

2.0V

tpdl

DRVLSD

tpdh

DRVLSD

Figure 3.

DRVLSD

Propagation Delay

IN

DRVL

DRVH-SW

tpdh

DRVH

tpdl

DRVH

tr

DRVH

tpdl

DRVL

tf

DRVL

tf

DRVH

tpdh

DRVL

tr

DRVL

V

TH

V

TH

SW

t

SWTO

1V

Figure 4. Driver Switching Timing Diagram (Timing is referenced to the 90% and 10% points unless otherwise noted.)

REV. PrA

PRELIMINARY TECHNICAL DATA

ADP3415

–5–

Typical Performance Characteristics–

DRVH

DRVL

IN

VCC = 5V
C

LOAD

= 3nF

V

SW

= 0V

TIME – ns

20ns/DIV

2V/DIV

TPC 1. DRVH Fall and DRVL Rise Times

DRVL

DRVH

IN

VCC = 5V
C

LOAD

= 3nF

R

DLY

= 0V

TIME – ns

20ns/DIV

2V/DIV

TPC 2. DRVL Fall and DRVH Rise Times

INPUT VOLTAGE – V

PEAK CURRENT – ␮A

80

30

05

1234

70

50

0

10

VCC = 5V
T

A

= 25ⴗC

C

LOAD

= 3nF

100

90

60

40

20

TPC 3. Input Voltage vs. Input Current

JUNCTION TEMPERATURE – ⴗC

TIME – ns

35

27

0 12525 50 75 100

31

29

33

21

25

23

VCC = 5V

C

LOAD

= 3nF

RISE

FA LL

37

TPC 4. DRVL Rise and Fall Times vs. Temperature

JUNCTION TEMPERATURE – ⴗC

TIME – ns

0 12525 50

16

30

18

V

CC

= 5V

C

LOAD

= 3nF

RISE TIME

FALL TIME

75 100

28

26

24

22

20

TPC 5. DRVH Rise and Fall Time vs. Temperature

LOAD CAPACITANCE – nF

TIME – ns

40

1103579

60

50

70

10

30

20

VCC = 5V

DRVH

DRVL

2468

T

A

= 25ⴗC

TPC 6. DRVH and DRVL Rise Time vs. Load Capacitance

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PRELIMINARY TECHNICAL DATA

ADP3415

–6–

JUNCTION TEMPERATURE – ⴗC

TIME – ns

52

42

22

0 12525 50 75 100

32

27

37

47

7

17

12

VCC = 5V

C

LOAD

= 3nF

2

t

pdl

DRVH

t

pdl

DRVL

TPC 7. DRVH and DRVL Propagation
Delay vs. Temperature

LOAD CAPACITANCE – uF

TIME – ns

52

42

22

1103568

32

27

37

47

7

17

12

VCC = 5V
T

A

= 25ⴗC

24 79

DRVH

DRVL

TPC 8. DRVH and DRVL Fall Time vs. Load Capacitance

JUNCTION TEMPERATURE – ⴗC

TIME – ns

182

142

62

0 125

25 50 75 100

102

82

122

162

2

42

22

VCC = 5V
f

IN

= 200kHz

OPEN DELAY PIN

SHORTED TO GROUND

C

LOAD

= 3nF

TPC 9. t

PDH

DRVH vs. Temperature

IN FREQUENCY – kHz

SUPPLY CURRENT – mA

45

35

15

200 1200

400 600 800 1000

25

20

30

40

0

10

5

VCC = 5V
T

A

= 25ⴗC

C

LOAD

= 3nF

TPC 10. Current vs. Frequency

JUNCTION TEMPERATURE – ⴗC

SUPPLY CURRENT – mA

10.5

9.5

7.5

0 125

25 50 75 100

8.5

8.0

9.0

10.0

6.0

7.0

6.5

VCC = 5V

f

IN

= 250kHz

C

LOAD

= 3nF

TPC 11. Current vs. Temperature

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PRELIMINARY TECHNICAL DATA

ADP3415

–7–

THEORY OF OPERATION

The ADP3415 is a dual MOSFET driver optimized for driving
two N-channel FETs in a synchronous buck converter topology.
A single duty ratio modulation signal is all that is required to
command the proper drive signal for the high-side and the low­side FETs.

A more detailed description of the ADP3415 and its features
follows. Refer to the functional block diagram (Figure 3).

Drive State Input

The drive state input, IN, should be connected to the duty ratio
modulation signal of a switch-mode controller. IN can be driven
by 2.5 V–5.0 V logic. The FETs will be driven so that the SW
node follows the polarity of IN.

Low-Side Driver

The supply rails for the low-side driver, DRVL, are VCC and
GND. In its conventional application it drives the gate of the
synchronous rectifier FET.

When the driver is enabled, the driver’s output is 180° out of
phase with the duty ratio input aside from OPC, propagation,
and transition delays. When the driver is shut down or the entire
ADP3415 is in shutdown or in under-voltage lockout, the low­side gate is held low.

High-Side Driver

The supply rail for the high-side driver, DRVH, is between the
BST and SW pins, and is created by an external bootstrap sup­ply circuit. In its conventional application it drives the gate of
the (top) main buck converter FET.

The bootstrap circuit comprises a Schottky diode, D1, and
bootstrap capacitor, C

BST

. When the ADP3415 is starting up,
the SW pin is at ground, so the bootstrap capacitor will charge
up to VCC through D1. As the supply voltage ramps up and
exceeds the UVLO threshold, the driver is enabled. When the
input pin, IN, goes high, the high-side driver will begin to turn
the high-side FET (Q1) ON by transferring charge from C

BST

to the gate of the FET. As Q1 turns ON, the SW pin will rise
up to V

DC-IN

, forcing the BST pin to V

DC-IN

+ V

C(BST)

, which
is enough gate to source voltage to hold Q1 ON. To complete
the cycle, when IN goes low, Q1 is switched OFF as DRVH
discharges the gate to the voltage at the SW pin. When the low­side FET, Q2, turns ON, the SW pin is held at ground. This
allows the bootstrap capacitor to charge up to VCC again.

The high-side driver’s output is in phase with the duty ratio
input. When the driver is in under-voltage lockout, the high­side gate is held low.

Overlap Protection Circuit

The Overlap Protection Circuit (OPC) prevents both of the
main power switches, Q1 and Q2, from being ON at the same
time. This prevents excessive shoot-through currents from flowing
through both power switches and minimizes the associated losses
that can occur during their ON-OFF transitions. The Overlap
Protection Circuit accomplishes this by adaptively controlling
the delay from Q1’s turn OFF to Q2’s turn ON, and by pro­gramming the delay from Q2’s turn OFF to Q1’s turn ON.

To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at
the SW pin. When IN goes low, Q1 will begin to turn OFF

(after a propagation delay) but before Q2 can turn ON, the
overlap protection circuit waits for the voltage at the SW pin to
fall from V

DC-IN

to 1 V. Once the voltage on the SW pin has
fallen to 1 V, Q2 will begin to turn ON. By waiting for the volt­age on the SW pin to reach 1 V, the overlap protection circuit
ensures that Q1 is OFF before Q2 turns on, regardless of varia­tions in temperature, supply voltage, gate charge, and drive
current. There is, however, a timeout circuit that will override
the waiting period for the SW pin to reach 1 V. After the time­out period has expired, DRVL will be asserted regardless of the
SW voltage.

To prevent the overlap of the gate drives during Q2’s turn
OFF and Q1’s turn ON, the overlap circuit provides a pro­grammable delay that is set by a resistor on the DLY pin.
When IN goes high, Q2 will begin to turn OFF (after a
propagation delay), but before Q1 can turn ON the overlap
protection circuit waits for the voltage at DRVL to drop to
around 10% of VCC. Once the voltage at DRVL has reached
the 10% point, the overlap protection circuit initiates a
delay timer that is programmed by the external resistor
R

DLY

. The delay resistor adds an additional specified delay.
The delay allows time for current to commutate from the
body diode of Q2 to an external Schottky diode, which
allows turnoff losses to be reduced. Although not as fool­proof as the adaptive delay, the programmable delay adds a
safety margin to account for variations in size, gate charge,
and internal delay of the external power MOSFETs.

Low-Side Driver Shutdown

The low-side driver shutdown (DRVLSD) allows a control
signal to shut down the synchronous rectifier. This signal should
be modulated by system state logic to achieve maximum battery
life under light load conditions and maximum efficiency under
heavy load conditions. Under heavy load conditions, DRVLSD
should be high so that the synchronous switch is modulated for
maximum efficiency. Under light load conditions, DRVLSD
should be low to prevent needless switching losses due to charge
shuttling caused by polarity reversal of the inductor current
when the average current is low.

When the DRVLSD input is low, the low-side driver stays low.
When the DRVLSD input is high, the low-side driver is enabled
and controlled by the driver signals as previously described.

Shutdown

For optimal system power management, when the output voltage is
not needed, the ADP3415 can be shut down to conserve power.

When the SD pin is high, the ADP3415 is enabled for normal
operation. Pulling the SD pin low forces the DRVH and DRVL
outputs low, turning the buck converter OFF, and reducing the
VCC supply current to less than 40 µA.

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit holds both FET
driver outputs low during VCC supply ramp-up. The UVLO
logic becomes active and in control of the driver outputs at a
supply voltage of no greater than 1.5 V. The UVLO circuit waits
until the VCC supply has reached a voltage high enough to bias
logic level FETs fully ON, around 4.1 V, before releasing con­trol of the drivers to the control pins.

REV. PrA

PRELIMINARY TECHNICAL DATA

–8–

ADP3415

Thermal Shutdown

The thermal shutdown circuit protects the ADP3415 against
damage due to excessive power dissipation. Under extreme
conditions, high ambient temperature and high power dissipa­tion, the die temperature may rise up to the thermal shutdown
threshold of 165°C. If the die temperature exceeds 165°C, the
thermal shutdown circuit will turn the output drivers OFF. The
drivers remain disabled until the junction temperature has
decreased by 10°C, at which point the drivers are again enabled.

APPLICATION INFORMATION
Supply Capacitor Selection

For the supply input (VCC) of the ADP3415, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 10 µF, MLC capacitor.
Keep the ceramic capacitor as close as possible to the ADP3415.
Multilayer ceramic (MLC) capacitors provide the best combina­tion of low ESR and small size, and can be obtained from the
following vendors:

Murata GRM235Y5V106Z16 www.murata.com

Taiyo-Yuden EMK325F106ZF www.t-yuden.com

Tokin C23Y5V1C106ZP www.tokin.com

Bootstrap Circuit

The bootstrap circuit requires a charge storage capacitor, C

BST

,
and a Schottky diode, D1, as shown in Figure 2. Selecting these
components can be done after the high-side FET has been chosen.

The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. The capaci­tance is determined using the following equation:

C

Q

V

BST

GATE

BST

=

∆

(1)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

10-Lead Mini_SOIC Package (MSOP)

(RM-10)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

0.022 (0.56)

0.021 (0.53)

6ⴗ
0ⴗ

10

6

51

0.0197 (0.50) BSC

0.124 (3.15)

0.112 (2.84)

0.124 (3.15)

0.112 (2.84)

0.199 (5.05)

0.187 (4.75)

PIN 1

0.122 (3.10)

0.110 (2.79)

0.006 (0.15)

0.002 (0.05)

0.016 (0.41)

0.006 (0.15)

0.038 (0.97)

0.030 (0.76)

SEATING
PLANE

0.043 (1.09)

0.037 (0.94)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

where Q

GATE

is the total gate charge of the high-side FET, and

∆V

BST

is the voltage droop allowed on the high-side FET drive.
For example, the IRFR8503 has a total gate charge of about
15 nC. For an allowed droop of 150 mV, the required bootstrap
capacitance is 100 nF. Use an MLC capacitor.

A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high-side FET. The bootstrap diode must also be able to
withstand the maximum battery voltage plus 5 V. The average
forward current can be estimated by:

IQf

F AVG GATE MAX()

≈×

(2)

where f

MAX

is the maximum switching frequency of the controller.

Delay Resistor Selection

The delay resistor, R

DLY

, is used to add an additional delay
when the low-side FET drive turns off and when the high-side
drive starts to turn on. The delay resistor programs a specified
additional delay besides the 20 ns of fixed delay.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed
circuit boards:

1. Trace out the high current paths and use short, wide traces

to make these connections.

2. The VCC bypass capacitor should be located as close as

possible to VCC and GND pins.