Datasheet ADP3408ARU-2.5 Datasheet (Analog Devices)

Page 1

GSM Power Management System

ADP3408

FEATURES Handles all GSM Baseband Power Management Six LDOs Optimized for Specific GSM Subsystems Li-Ion and NiMH Battery Charge Function Optimized for the AD20msp430 Baseband Chipset

APPLICATIONS GSM/DCS/PCS/CDMA Handsets

GENERAL DESCRIPTION

The ADP3408 is a multifunction power system chip optimized for GSM handsets, especially those based on the Analog Devices AD20msp430 system solution. It contains six LDOs, one to power each of the critical GSM sub-blocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end-of-charge signal when a Li-Ion battery is being charged.

The ADP3408 is specified over the temperature range of –20°C to +85°C and is available in narrow body TSSOP-28 pin package.

PWRONKEY

ROWX

PWRONIN

TCXOEN

SIMEN

RESCAP

CHRDET

EOC

CHGEN

GATEIN

BATSNS

ISENSE

GATEDR

CHRIN

FUNCTIONAL BLOCK DIAGRAM

VBAT VBAT2 VRTCIN

SIM

LDO

DIGITAL

CORE LDO

ANALOG

LDO

POWER-UP

SEQUENCING

AND

PROTECTION

LOGIC

BATTERY

CHARGE

CONTROLLER

ADP3408

TCXO

LDO

MEMORY

LDO

RTC LDO

REF

BUFFER

BATTERY

CHARGE

DIVIDER

VSIM

VCORE

VAN

VTCXO

VMEM

VRTC

REFOUT

RESET

MVBAT

DGND

AGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

Page 2

ADP3408–SPECIFICATIONS

CVMEM = 2.2 ␮F, VTCXO = 0.22 ␮F, CVRTC = 0.1 ␮F, CVBAT = 10 ␮F, minimum loads applied on all outputs, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit

SHUTDOWN SUPPLY CURRENT ICC

VBAT ≤ 2.5 V VBAT = VBAT2 = 2.3 V 7 20 µA (Deep Discharged Lockout Active)

2.5 V < VBAT ≤ 3.2 V VBAT = VBAT2 = 3.0 V 30 55 µA (UVLO Active) VBAT > 3.2 V VBAT = VBAT2 = 4.0 V 45 80 µA

OPERATING GROUND CURRENT IGND VBAT = 3.6 V

VSIM, VCORE, VMEM, VRTC On Minimum Loads 225 300 µA All LDOs On Minimum Loads 345 450 µA

UVLO ON THRESHOLD VBAT 3.2 3.3 V

UVLO HYSTERESIS VBAT 200 mV

DEEP DISCHARGED LOCKOUT ON VBAT 2.4 2.75 V

THRESHOLD

DEEP DISCHARGED LOCKOUT VBAT 100 mV

HYSTERESIS

INPUT HIGH VOLTAGE V

(PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN)

INPUT LOW VOLTAGE V

(PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN)

INPUT HIGH BIAS CURRENT I

(PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN)

INPUT LOW BIAS CURRENT I

(PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN)

PWRONKEY INPUT HIGH VOLTAGE V

PWRONKEY INPUT LOW VOLTAGE V

PWRONKEY INPUT PULL-UP 70 100 130 kΩ

RESISTANCE TO VBAT

THERMAL SHUTDOWN THRESHOLD

THERMAL SHUTDOWN HYSTERESIS 45 ºC

ROWX CHARACTERISTICS

ROWX Output Low Voltage V

ROWX Output High Leakage I Current V(ROWX) = 5 V 1 µA

SIM CARD LDO (VSIM)

Output Voltage VSIM Line, Load, Temp 2.80 2.85 2.92 V Line Regulation ∆VSIM Min Load 2 mV Load Regulation ∆VSIM 50 µA ≤ I

Output Capacitor Required for Stability C Dropout Voltage V

DIGITAL CORE LDO (VCORE)

Output Voltage

ADP3408ARU-2.5 VCORE Line, Load, Temp 2.40 2.45 2.50 V

ADP3408ARU-1.8 VCORE Line, Load, Temp 1.75 1.80 1.85 V Line Regulation ∆VCORE Min Load 2 mV Load Regulation ∆VCORE 50 µA ≤ I

Output Capacitor Required for Stability C

(–20ⴗC ≤ TA ≤ +85ⴗC, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN =

Maximum Loads 1.0 3.0 % of max

2.0 V

0.4 V

1.0 µA

–1.0 µA

0.7 × VBAT V

0.3 × VBAT V

160 ºC

PWRONKEY = Low IOL = 200 µA 0.4 V PWRONKEY = High

≤ 20 mA, 1 mV

BAT

LOAD

= 3.6 V

2.2 µF VO = V I

LOAD

BAT

= 3.6 V

– 100 mV,

INITIAL

= 20 mA 35 100 mV

≤ 100 mA, 7 mV

LOAD

2.2 µF

load current

–2–

REV. 0

Page 3

ADP3408

Parameter Symbol Condition Min Typ Max Unit

RTC LDO REAL-TIME CLOCK LDO/ COIN CELL CHARGER (VRTC)

Maximum Output Voltage

ADP3408ARU-2.5 VRTC 1 µA ≤ I

ADP3408ARU-1.8 VRTC 1 µA ≤ I Off Reverse Input Current I Output Capacitor Required for Stability C

BAT

ANALOG LDO (VAN)

Output Voltage VAN Line, Load, Temp 2.40 2.45 2.50 V Line Regulation ∆VAN Min Load 2 mV Load Regulation ∆VAN 50 µA ≤ I

V Output Capacitor Required for Stability C Ripple Rejection ∆VBAT/ f = 217 Hz 65 dB

Output Noise Voltage V

∆VAN

NOISE

BAT

f = 10 Hz to 100 kHz 80 µV rms

LOAD

BAT

TCXO LDO (VTCXO)

Output Voltage VTCXO Line, Load, Temp 2.66 2.715 2.77 V Line Regulation Load Regulation

Output Capacitor Required for Stability C Dropout Voltage V

∆

VTCXO Min Load 2 mV

∆

VTCXO 50 µA ≤ I

BAT

VO = V

LOAD

Ripple Rejection ∆VBAT/ f = 217 Hz 65 dB

Output Noise Voltage V

∆VTCXO V

NOISE

BAT

f = 10 Hz to 100 kHz 80 µV rms

LOAD

BAT

MEMORY LDO (VMEM)

Output Voltage VMEM Line, Load, Temp 2.744 2.80 2.856 V Line Regulation ∆VMEM

Min Load Load Regulation ∆VMEM 50 µA < I

V Output Capacitor Required for Stability C

BAT

Dropout Voltage 80 180 mV

REFOUT

Output Voltage VREFOUT Line, Load, Temp 1.19 1.210 1.23 V Line Regulation Load Regulation

Ripple Rejection

Maximum Capacitive Load C Output Noise Voltage V

∆

VREFOUT Min Load 0.2 mV

∆

VREFOUT 0

∆

VBAT/ f = 217 Hz 65 75 dB

∆

VREFOUT V

NOISE

µA

BAT

f = 10 Hz to 100 kHz, 40 µV rms

BAT

RESET GENERATOR (RESET)

Output High Voltage V Output Low Voltage V Output Current IOL/I

Delay Time per Unit Capacitance T Applied to RESCAP Pin

IOH = 500 µAV

IOL = –500 µA 0.25 V

VOH = V

BATTERY VOLTAGE DIVIDER

Divider Ratio BATSNS/MVBAT TCXOEN = High 2.32 2.35 2.37 kΩ Divider Impedance at MVBAT Z Divider Leakage Current TCXOEN = Low 1 µA

Divider Resistance TCXOEN = High 215 300 385 kΩ

≤ 10 µA 2.39 2.45 2.51 V

LOAD

≤ 10 µA 1.80 1.95 2.1 V

LOAD

= 2.15 V, TA = 25°C 0.5 µA

0.1 µF

≤ 130 mA, 8 mV

LOAD

= 3.6 V

2.2 µF

= 3.6 V

= 130 mA

= 3.6 V

≤ 20 mA, 1 mV

LOAD

= 3.6 V

0.22 µF

– 100 mV 160 310 mV

INITIAL

= 20 mA

= 3.6 V

= 20 mA,

= 3.6 V

2mV

= 3.6 V

< 60 mA, 3 mV

LOAD

2.2 µF

< I

< 50

LOAD

µA

0.5 mV

= 3.6 V

= 3.6 V, I

LOAD

= 50 µA

100 pF

= 3.6 V

– 0.25 V

MEM

= 0.25 V, 1 mA

– 0.25 V

MEM

0.6 1.2 2.4 ms/nF

59.5 85 110 kΩ

REV. 0

–3–

Page 4

ADP3408

Parameter Symbol Condition Min Typ Max Unit

BATTERY CHARGER

Charger Output Voltage BATSNS 4.35 V ≤ CHRIN ≤ 10 V

CHGEN = Low, No Load

Load Regulation ∆BATSNS CHRIN = 5 V 15 mV

0 ≤ CHRIN – ISENSE < Current Limit Threshold

CHGEN = Low CHRDET On Threshold CHRIN – BATSNS 30 90 150 mV CHRDET Off Threshold CHRIN – BATSNS 15 45 100 mV CHRDET Off Delay

CHRIN < VBAT 6 ms/nF CHRIN Supply Current CHRIN = 5 V 0.6 mA

BATTERY CHARGER

Current Limit Threshold CHRIN – ISENSE High Current Limit CHRIN = 5 V dc 142 160 190 mV (UVLO Not Active) VBAT = 3.6 V

CHGEN = Low Low Current Limit VBAT = 2 V 20 35 mV (UVLO Active) CHGEN = Low

CHRIN = 5 V ISENSE Bias Current 200 µA

4.150 4.200 4.250 V

End-of-Charge Signal Threshold CHRIN – ISENSE CHRIN = 5 V 14 35 mV

VBAT > 4.0 V

CHGEN = Low

EOC Reset Threshold VBAT CHGEN = Low 3.82 3.96 4.10 V

GATEDR Transition Time t

, t

CHRIN = 5 V 0.1 1 µs

VBAT > 3.6 V

CHGEN = High, CL = 2 nF

GATEDR High Voltage V

CHRIN = 5 V 4.5 V

VBAT = 3.6 V

CHGEN = High,

GATEIN = High

IOH = –1 mA GATEDR Low Voltage V

CHRIN = 5 V 0.5 V

VBAT = 3.6 V

CHGEN = High

GATEIN = Low

= 1 mA

Output High Voltage V

(EOC, CHRDET)

Output Low Voltage V

(EOC, CHRDET)

IOH = –250 µA 2.4 V

IOL = +250 µA 0.25 V

Battery Overvoltage BATSNS CHRIN = 7.5 V 5.30 5.50 5.70 V

Protection Threshold CHGEN = High

(GATEDR → High) GATEIN = Low Battery Overvoltage BATSNS CHRIN = 7.5 V 200 mV Protection Hysteresis CHGEN = High

GATEIN = Low

NOTES

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

This feature is intended to protect against catastophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC could cause permanent damage to the device.

No isolation diode present between charger input and battery.

Delay set by external capacitor on the RESCAP pin.

Specifications subject to change without notice.

–4–

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ADP3408

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Voltage on any pin with respect to

any GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V

Voltage on any pin may not exceed VBAT, with the following

exceptions: CHRIN, GATEDR, ISENSE

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Operating Ambient Temperature Range . . . . . –20°C to +85°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C

, Thermal Impedance (TSSOP-28)

4-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W

1-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W

Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device

to be permanently damaged.

ORDERING GUIDE

Core LDO Output Temperature Package

Model Voltage Range Option*

ADP3408ARU-2.5 2.5 V –20°C to +85°C RU-28 ADP3408ARU-1.8 1.8 V –20°C to +85°C RU-28

*RU = Thin Shrink Small Outline

PIN CONFIGURATION

PWRONIN

PWRONKEY

ROWX

SIMEN

VRTCIN

VRTC

BATSNS

MVBAT

CHRDET

CHRIN

GATEIN

GATEDR

DGND

ISENSE

ADP3408

TOP VIEW

(Not to Scale)

TCXOEN

AGND

REFOUT

VTCXO

VAN

VBAT

VCORE

VMEM

VBAT2

VSIM

RESET

RESCAP

CHGEN

EOC

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 PWRONIN Power On/Off Signal from

Microprocessor 2 PWRONKEY Power-On/-Off Key 3 ROWX Power Key Interface Output 4 SIMEN SIM LDO Enable 5 VRTCIN RTC LDO Input Voltage 6 VRTC Real-Time Clock Supply/

Coin Cell Battery Charger 7 BATSNS Battery Voltage Sense Input 8 MVBAT Divided Battery Voltage Output 9 CHRDET Charge Detect Output 10 CHRIN Charger Input Voltage 11 GATEIN Microprocessor Gate Input

Signal 12 GATEDR Gate Drive Output 13 DGND Digital Ground 14 ISENSE Charge Current Sense Input 15 EOC End of Charge Signal 16 CHGEN Charger Enable for GATEIN,

NiMH Pulse Charging 17 RESCAP Reset Delay Time 18 RESET Main Reset 19 VSIM SIM LDO Output 20 VBAT2 Battery Input Voltage 2 21 VMEM Memory LDO Output 22 VCORE Digital Core LDO Output 23 VBAT Battery Input Voltage 24 VAN Analog LDO Output 25 VTCXO TCXO LDO Output 26 REFOUT Output Reference 27 AGND Analog Ground 28 TCXOEN TCXO LDO Enable and

MVBAT Enable

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3408 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

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ADP3408

Table I. LDO Control Logic

DDLO

UVLO*

CHRDET

PWRONKEY

PWRONIN

TCXOEN

SIMEN

VSIM

VCORE

VAN and REFOUT

VTCXO

VMEM

VRTC

PHONE STATUS

State #1 Battery Deep Discharged L XXXXL XOFFOFFOFFOFFOFFOFFOFF

State #2 Phone Off H L X X X L X OFF OFF OFF OFF OFF ON OFF

State #3 Phone Off, Turn-On Allowed H H L H L L X OFF OFF OFF OFF OFF ON OFF

State #4 Charger Applied H H H X X L L OFF ON ON ON ON ON OFF

State #5 Phone Turned On by User Key H H X L X L L OFF ON ON ON ON ON OFF

State #6 Phone Turned On by BB H H L H H L L OFF ON OFF OFF ON ON OFF

State #7 Enable SIM Card H H L H H L H ON ON OFF OFF ON ON OFF

State #8 Phone and TCXO LDO Kept On by BB H H L HHHHONONONONONONON

MVBAT

*UVLO is active only when phone is turned off. UVLO is ignored once the phone is turned on.

–6–

REV. 0

Page 7

Typical Performance Characteristics–

ADP3408

450

ALL LDO, MVBAT, REFOUT, ON_MIN_LOAD (SIMEN = H,

400

TCXOEN = H)

350

300

– ␮A

250

GND

200

150

100

3.0 3.5 4.0 4.5 5.0 5.5

VSIM, VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = H, TCXOEN = L)

VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = L, TCXOEN = L)

VBAT – V

TPC 1. Ground Current vs. Battery Voltage

180

160

VTCXO

140

120

100

VSIM

DROPOUT VOLTAGE – mA

0 20406080

LOAD CURRENT – mA

VMEM

10000

+85ⴗC

1000

– ␮A

VRTC

100

+25ⴗC

0 0.5 1.0 1.5 2.0 2.5

–20ⴗC

VRTC – V

TPC 2. RTC I/V Characteristic

3.2

VBAT

3.0

VTCXO

10mV/DIV

VMEM

10mV/DIV

TIME – 100␮s/DIV

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

REVERSE LEAKAGE CURRENT – ␮A

25 30 35 40 45 50 55 60 65 70 75 80 85

RTC REVERSE LEAKAGE

(VBAT = FLOAT)

RTC REVERSE LEAKAGE (VBAT = 2.3V)

TEMPERATURE – ⴗC

TPC 3. VRTC Reverse Leakage Current vs. Temperature

3.2

VBAT

3.0

VTCXO

10mV/DIV

VMEM

10mV/DIV

TIME – 100␮s/DIV

TPC 4. Dropout Voltage vs. Load Current

3.2

VBAT

3.0

VCORE

VAN

VSIM

10mV/DIV

TIME – 100␮s/DIV

TPC 7. Line Transient Response, Minimum Loads

TPC 5. Line Transient Response, Minimum Loads

3.2

VBAT

3.0

VTCXO

10mV/DIV

VMEM

10mV/DIV

TIME – 100␮s/DIV

TPC 8. Line Transient Response, Maximum Loads

TPC 6. Line Transient Response, Maximum Loads

20mA

LOAD

VTCXO

10mV/DIV

TIME – 200␮s/DIV

3mA

TPC 9. VTCXO Load Step

REV. 0

–7–

Page 8

ADP3408

LOAD

20mA

3mA

LOAD

60mA

5mA

LOAD

100mA

10mA

VSIM

5mV/DIV

TIME – 200␮s/DIV

TPC 10. VSIM Load Step

130mA

LOAD

VAN

10mV/DIV

TIME – 200␮s/DIV

10mA

TPC 13. VAN Load Step

VMEM

10mV/DIV

TIME – 200␮s/DIV

TPC 11. VMEM Load Step

PWRONIN (2V/DIV)

VAN (100mV/DIV)

VSIM (100mV/DIV)

VCORE (100mV/DIV)

TIME – 400␮s/DIV

TPC 14. Turn On Transient by PWRONIN, Minimum Load (Part 1)

VCORE

10mV/DIV

TIME – 200␮s/DIV

TPC 12. VCORE Load Step

PWRONIN (2V/DIV)

REFOUT

(100mV/DIV)

VMEM (100mV/DIV)

VTCXO (100mV/DIV)

TIME – 100␮s/DIV

TPC 15. Turn On Transient by PWRONIN, Minimum Load (Part 2)

PWRONIN (2V/DIV)

VAN (100mV/DIV)

VSIM (100mV/DIV)

VCORE (100mV/DIV)

TIME – 20␮s/DIV

TPC 16. Turn On Transient by PWRONIN, Maximum Load (Part 1)

PWRONIN (2V/DIV)

REFOUT

(100mV/DIV)

VMEM (100mV/DIV)

VTCXO (100mV/DIV)

TIME – 20␮s/DIV

TPC 17. Turn On Transient by PWRONIN, Maximum Load (Part 2)

VAN

MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS

RIPPLE REJECTION – dB

4 100k10 100 1k 10k

FREQUENCY – Hz

VTCXO

VCORE

REFOUT

TPC 18. Ripple Rejection vs. Frequency

–8–

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Page 9

ADP3408

TEMPERATURE – ⴗC

4.25

4.24

4.23

4.22

4.21

4.20

4.19

4.18

4.17

4.16

4.15 40–20 0 20 60 80 100 120–40

CHARGER V

OUT

– V

REFOUT

RIPPLE REJECTION – dB

2.5 3.32.6 2.7 2.8 2.9 3.0 3.1 3.2

VCORE VAN

VTCXO

VBAT – V

VSIM

VMEM

FREQUENCY =

217Hz MAX LOADS

TPC 19. Ripple Rejection vs. Battery Voltage

4.24 VIN = 5.0V

= 250m⍀

SENSE

4.23

4.22

4.21

OUTPUT VOLTAGE – V

600

FULL LOAD

500

400

300

200

100

VOLTAGE SPECTRAL NOISE DENSITY – nV/ Hz

VAN

TCXO

REF

10 100k100 1k 10k

FREQUENCY – Hz

MLCC CAPS

TPC 20. Output Noise Density

4.24 R

= 250m⍀

SENSE

4.23

= 500mA

LOAD

4.22

= 10mA

LOAD

OUTPUT VOLTAGE – V

4.21

TPC 21. Charger V ture, V

= 5.0 V, I

LOAD

vs. Tempera-

OUT

= 10 mA

4.20 0 200 400 600 800

TPC 22. Charger V (VIN = 5.0 V)

REV. 0

LOAD

– mA

OUT

vs. I

LOAD

4.20 5678910

TPC 23. Charger V

INPUT VOLTAGE – V

OUT

vs. V

–9–

Page 10

ADP3408

100k⍀

VBAT2VRTCINVBAT

SIM LDO

VBAT

UVLO

DEEP

DISCHARGED

VREF

OUT

DGND

VSIM

PWRONKEY

ROWX

PWRONIN

SIMEN

TCXOEN

RESCAP

CHRDET

EOC

CHGEN

GATEIN

BATSNS

ISENSE

GATEDR

CHRIN

CHARGER

DETECT

CONTROLLER

␮PROCESSOR

LI-ION BATTERY CHARGE

AND

CHARGE

INTERFACE

OVER- TEMP SHUTDOWN

RESET

GENERATOR

DIGITAL CORE LDO

VBAT

VREF

ANALOG LDO

VBAT

VREF

VBAT

VREF

MEMORY LDO

VBAT

VREF

VBAT

VREF

DGND

AGND

TCXO LDO

AGND

DGND

RTC LDO

DGND

OUT

VCORE

VA N

RESET

VTCXO

VMEM

VRTC

MVBAT

AGND

ADP3408

1.21V

Figure 1. Functional Block Diagram

EOC

CHGEN

Q1 SI3441DY

0.2⍀C110nF

GATEIN

BATSNS

GATEDR

ISENSE

CHRIN (10V MAX)

CHRDET

ADP3408

BATTERY

CHARGE

CONTROLLER

Figure 2. Battery Charger Typical Application

–10–

EN REF

–

BUFFER

REFOUT

AGND

DGND

REV. 0

Page 11

ADP3408

TCXOEN

AGND

REFOUT

VTCXO

VAN

VBAT

VCORE

VMEM

VBAT2

VSIM

RESET

RESCAP

CHGEN

EOC

PWRON

PWRONKEY

KEYPADROW

GPIO

VRTC

AUXADC

GPIO

CHARGER IN

GPIO

CAPACITOR

TYPE BACKUP

COIN CELL

0.33⍀

SI3441DY

LI OR NIMH

BATTERY

0.1␮F

C2, 10nF

PWRONIN

PWRONKEY

ROWX

SIMEN

VRTCIN

ADP3408

VRTC

BATSNS

MVBAT

CHRDET

CHRIN

GATEIN

GATEDR

DGND

ISENSE

Figure 3. Typical Application Circuit

THEORY OF OPERATION

The ADP3408 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3408.

The ADP3408 contains several blocks:

• Six Low Dropout Regulators (SIM, Core, Analog, Crystal Oscillator, Memory, Real-Time Clock)

• Reset Generator

• Buffered Precision Reference

• Lithium Ion Charge Controller and Processor Interface

• Power-On/-Off Logic

• Undervoltage Lockout

• Deep Discharge Lockout

These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3408 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a GSM environment while maintaining a cost competitive solution.

Figure 3 shows the external circuitry associated with the ADP3408. Only a minimal number of support components are required.

Input Voltage

The input voltage range of the ADP3408 is 3 V to 5.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The thermal impedance of the ADP3408 is 68°C/W for four-layer boards. The end-of-charge voltage for high capacity NiMH cells can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125°C maximum allowable junction temperature. Figure 4 shows the maximum power dissipation as a function of ambient temperature.

CLKON

10⍀

C3, 10␮F

0.1␮F

2.2␮F

2.2␮FC90.22␮F

2.2␮F

C10

0.1␮F

REF

VTCXO

VAN

VCORE

VMEM

VSIM

RESET

GPIO

However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.25 V, where the ADP3408 can deliver the maximum power (0.56W) up to 85°C ambient temperature.

1.2

1.0

0.8

0.6

0.4

POWER DISSIPATION – W

0.2

0.0 –20 1000

20 40 60 80

AMBIENT TEMPERATURE – ⴗC

Figure 4. Power Dissipation vs. Temperature

Low Dropout Regulators (LDOs)

The ADP3408 high-performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 µF tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, SIM, and analog LDOs. A 0.22 µF capacitor is recommended for the TCXO LDO.

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ADP3408

NON-CHARGING

MODE

CHGEN = HIGH

CHARGING MODE GATEIN = PULSED

CHARGER OFF GATEIN = HIGH

CHRIN > BATSNS

VBAT > UVLO

LOW CURRENT

CHARGE MODE

SENSE

NIMH

VBAT > 5.5V

YES

NIMH

VBAT < 5.5V

YES

CHARGER

DETECTER

YES

= 20mV

YES

NIMH

BATTERY

TYPE

LI+

CHGEN = LOW

HIGH CURRENT CHARGE MODE

= 160mV

SENSE

VBAT > 4.2V

YES

CONSTANT

VOLTAGE MODE

< I END

CHARGE

OF CHARGE

YES

EOC = HIGH

TERMINATE CHARGE

CHREN = HIGH GATEIN = HIGH

Figure 5. Battery Charger Flow Chart

Digital Core LDO (VCORE)

The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on at all times.

Memory LDO (VMEM)

The memory LDO supplies the peripheral subsystems of the baseband processor including GPIO, display, and SIM interfaces as well as memory. The LDO has also been optimized for low quiescent current and will power up at the same time as the core LDO.

Analog LDO (VAN)

This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the

ripple coming from the RF power amplifier. VAN is rated to 130 mA load, which is sufficient to supply the complete analog section of the baseband converter such as the AD652l.

TCXO LDO (VTCXO)

The TCXO LDO is intended as a supply for a temperaturecompensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 5 mA of output current and is turned on along with the analog LDO when TCXOEN is asserted.

RTC LDO (VRTC)

The RTC LDO charges up a capacitor-type backup coin cell to run the real-time clock module. It has been designed to charge electric double layer capacitors such as the PAS621 from Kanebo. The PAS621 has a small physical size (6.8 mm diameter) and a nominal capacity of 0.3 F, giving many hours of backup time.

The ADP3408 supplies current both for charging the coin cell and for the RTC module when the digital supply is off. The nominal charging voltage is 2.45 V, which ensures long cell life while obtaining in excess of 90% of the nominal capacity. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module.

SIM LDO (VSIM)

The SIM LDO generates the voltage needed for 3 V SIMs. It is rated for 20 mA of supply current and can be controlled completely independently of the other LDOs.

Reference Output (REFOUT)

The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% over temperature. The reference can be used with the baseband converter, if the converter’s own reference is not accurate. This will significantly reduce calibration time needed for the baseband converter during production. Note that the reference in the AD6521 has an initial accuracy of 10%, but can be calibrated to within 1%.

Power ON/OFF

The ADP3408 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3408 in three different ways:

• Pulling the PWRONKEY Low

• Pulling PWRONIN High

• CHRIN exceeds CHRDET Threshold

Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn all the LDOs on, except the SIM LDO, as long as the PWRONKEY is held low. When the VCORE LDO comes into regulation the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3408 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/ OFF control.

Pulling the PWRONIN pin high is how the alarm in the Real-Time Clock module will turn the handset on. Asserting PWRONIN will turn the core and memory LDOs on, starting up the baseband processor.

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ADP3408

Applying an external charger can also turn the handset on. This will turn on all the LDOs, except the SIM LDO, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs.

Deep Discharge Lockout (DDLO)

The DDLO block in the ADP3408 has two functions:

• To shut off the VRTC LDO in the event that the main battery discharges to below the RTC LDO’s output voltage. This will force the real-time clock to run off the backup coin cell or double layer capacitor.

• To shut down the handset in the event that the software fails to turn off the phone when the battery drops below 2.9 V to

3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the cells.

Undervoltage Lockout (UVLO)

The UVLO function in the ADP3408 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than

3.2 V, such as inserting a fresh battery, the UVLO comparator

trips, and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below

3.0 V. Note that the DDLO has enabled the RTC LDO under

this condition.

Once the system is started, and the core and memory LDOs are up and running, the UVLO function is disabled. The ADP3408 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor and usually shuts off the phone at around 3.0 V.

If the handset is off, and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3408 into UVLO shutdown mode. In this mode the ADP3408 draws very low quiescent current, typically 30 µA. The RTC LDO is still running until the DDLO disables it. In this mode the ADP3408 draws 5 µA of quiescent current. NiMH batteries can reverse polarity if the three-cell battery voltage drops below 3.0 V which will degrade the batteries’ performance. Lithium ion batteries will lose their capacity if repeatedly overdischarged, so minimizing the quiescent currents helps prevent battery damage.

RESET

The ADP3408 contains a reset circuit that is active at both power-up and power-down. The RESET pin is held low at initial power-up. An internal power good signal is generated by the core LDO when its output is up, which starts the reset delay timer. The delay is set by an external capacitor on RESCAP:

=×12.

ms nF

(1)

RESET RESCAP

At power-off, RESET will be kept low to prevent any baseband processor starts.

Over-Temperature Protection

The maximum die temperature for the ADP3408 is 125°C. If the die temperature exceeds 160°C, the ADP3408 will disable all the LDOs except the RTC LDO. The LDOs will not be

This ensures that the handset will always power-off before the ADP3408 exceeds its absolute maximum thermal ratings.

Battery Charging

The ADP3408 battery charger can be used with Lithium Ion (Li+) and Nickel Metal Hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software.

The charger block works in three different modes:

• Low Current (Trickle) Charging

• Lithium Ion Charging

• Nickel Metal Hydride Charging

Charge Detection

The ADP3408 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 90 mV, the CHRDET output will go high. If the adapter is then removed and the voltage at the CHRIN pin drops to only 45 mV above the BATSNS pin, CHRDET goes low.

Trickle Charging

When the battery voltage is below the UVLO threshold, the charge current is set to the Low Current Limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by:

CHR TRICKLE

()

SENSE

(2)

Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold.

Once the UVLO threshold has been exceeded the charger will switch to the high current limit, the LDOs will start up, and the baseband processor will start to run. The processor must then poll the battery to determine which chemistry is present and set the charger to the proper mode.

Lithium Ion Charging

For lithium ion charging, the CHGEN input must be low. This allows the ADP3408 to continue charging the battery at the full current. The full charge current can be calculated by using:

CHR FULL

()

160

SENSE

(3)

If the voltage at BATSNS is below the charger’s output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 14 mV, an Endof-Charge signal is generated and the EOC output goes high. See Figure 6.

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ADP3408

ICHG

VBAT

EOC

TIME

Figure 6. End of Charge

The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN and CHGEN pins high.

NiMH Charging

For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the processor can charge a NiMH battery. Note that when charging NiMH cells, a current-limited adapter is required.

During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached, at which time the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected.

Battery Voltage Monitoring

The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider can be connected to BATSNS when both the digital and analog baseband sections are powered up. To enable MVBAT both PWRONIN and TCXOEN must be high.

The ratio of the voltage divider is selected so that the 2.4 V maximum input of the AD6521’s auxiliary ADC will correspond with the maximum battery voltage of 5.5 V. The divider will be disconnected from the battery when the baseband sections are powered down.

APPLICATION INFORMATION Input Capacitor Selection

For the input (VBAT, VBAT2, and VRTCIN) of the ADP3408, a local bypass capacitor is recommended. Use a 10 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel.

Separate inputs for the SIM LDO and the RTC LDO are supplied for additional bypassing or filtering. The SIM LDO has VBAT2 as its input and the RTC LDO has VRTCIN.

LDO Capacitor Selection

The performance of any LDO is a function of the output capacitor. The core, memory, SIM, and analog LDOs require a 2.2 µF capacitor and the TCXO LDO requires a 0.22 µF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application.

All the LDOs are stable with a wide range of capacitor types and ESR (anyCAP

technology). The ADP3408 is stable with extremely low ESR capacitors (ESR ~ 0), such as Multilayer Ceramic Capacitors (MLCC), but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, capacitor is recommended.

The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 µF ceramic capacitor is recommended for stability and best performance.

RESET Capacitor Selection

RESET is held low at power-up. An internal power-good signal starts the reset delay when the core LDO is up. The delay is set by an external capacitor on RESCAP:

=×12.

ms nF

(4)

RESET RESCAP

A 100 nF capacitor will produce a 120 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VCORE is off to minimize power consumption. When VCORE is on, RESET is capable of driving 500 µA.

Setting the Charge Current

The ADP3408 is capable of charging both Lithium Ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For Lithium Ion batteries, the charge current is programmed by selecting the sense resistor, R1.

The Lithium Ion charge current is calculated using:

CHR

Where V

SENSE

is the high current limit threshold voltage. Or if

SENSE

160

(5)

the charge current is known, R1 can be found.

SENSE

CHR CHR

160

(6)

Similarly the trickle charge current and the end of charge current can be calculated:

TRICKLE EOC

== =

SENSE

(7)

Example: Assume an 800mA-H capacity Lithium Ion battery and an 1C charge rate. R1 = 200 mΩ, I

= 100 mA.

EOC

= 100 mA, and

TRICKLE

anyCAP is a registered trademark of Analog Devices Inc.

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ADP3408

Appropriate sense resistors are available from the following vendors:

Vishay Dale IRC Panasonic

Charger FET Selection

The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and the charge current. The selected PMOS must satisfy the physical, electrical and thermal design requirements.

To ensure proper operation, the minimum V

the ADP3408

can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following:

VV V V

=−−

GS ADAPTER MIN GATEDR SENSE

()

(8)

where:

ADAPTER(MIN)

gate drive “low” voltage, 0.5 V, and V

is the minimum adapter voltage, V

is the maximum

SENSE

GATEDR

is the

high current limit threshold voltage.

The difference between the adapter voltage (V final battery voltage (V

) must exceed the voltage drop due to

BAT

ADPTER

) and the

the blocking diode, the sense resistor, and the ON resistance of the FET at maximum charge current, where:

VV V V V

=−−−

DS ADAPTER MIN DIODE SENSE BAT

The R

of the FET can then be calculated.

DS(ON)

DS ON

()

CHR MAX

()

(9)

(10)

The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using:

P V V V UVLO I

=−−−

()

DISS ADAPTER MAX DIODE SENSE CHR

()

(11)

It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design.

For example:

ADAPTER(MIN)

ADAPTER(MAX)

DIODE

SENSE

GATEDR

= 5 V – 0.5 V – 160 V = 4.34 V

= 5.0 V

= 6.5 V

= 0.5 V at 800 mA

= 160 mV

= 0.5 V

Therefore, choose a low threshold voltage FET.

VV V V V

DS ADAPT MIN DIODE SENSE BAT

VV VV mV

– . – . – .

5 0 5 0 160 4 2 140

P V V V UVLO I

PVVV A

===

DS ON

()

CHR MAX

()

DISS ADAPT MAX DIODE SENSE CHR

. – . – . – .. .

65 05 0160 32 08 211ΩWW

()

DISS

–––

()

140

800

–––

175

×=

Appropriate PMOS FETs are available from the following vendors:

Siliconix IR Fairchild

Charger Diode Selection

The diode, D1, shown in Figure 2, is used to prevent the battery from discharging through the PMOS’ body diode into the charger’s internal bias circuits. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed circuit boards:

1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3408. Locate the input capacitor as close to the pins as possible.

2. VAN and VTCXO capacitors should be returned to AGND.

3. VCORE, VMEM and VSIM capacitors should be returned to DGND.

4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return.

5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement.

6. Kelvin-connect the charger’s sense resistor by running separate traces to the CHRIN and ISENSE pins. Make sure that the traces are terminated as close to the resistor’s body as possible.

7. Use the best industry practice for thermal considerations during the layout of the ADP3408 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance.

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ADP3408

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Thin Shrink Small Outline (TSSOP)

(RU-28)

0.386 (9.80)

0.378 (9.60)

28 15

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.0256 (0.65) BSC

0.0118 (0.30)

0.0075 (0.19)

0.177 (4.50)

0.169 (4.30)

141

0.0433 (1.10) MAX

0.0079 (0.20)

0.0035 (0.090)

0.256 (6.50)

0.246 (6.25)

8ⴗ 0ⴗ

C02623–1–9/01(0)

0.028 (0.70)

0.020 (0.50)

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PRINTED IN U.S.A.

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