Datasheet ADP3401 Datasheet (Analog Devices)

a

DIGITAL

LDO

VCC

VRTC

VTCXO

PWRONKEY

ROWX

PWRONIN

RESET

ANALOGON

POWER-UP

SEQUENCING

AND

PROTECTION

LOGIC

ADP3401

VBAT

REFOUT

AGND

VCCA

RESCAP

CHRON

SIMBAT

CAP+

CAP2

SIMPROG

SIMON

SIMGND

RESETIN

CLKIN

DATAIO

CHARGE

PUMP

LOGIC LEVEL

TRANSLATION

BUFFER

REF

+

I/O

RSTCLK

VSIM

RTC LDO

XTAL OSC

LDO

ANALOG

LDO

DGND

GSM Power Management System

ADP3401

FEATURES
Handles all GSM Baseband Power Management

Functions
Four LDOs Optimized for Specific GSM Subsystems
Charges Li-Mn Coin Cell for Real-Time Clock
Charge Pump and Logic Level Translators for 3 V and 5 V

GSM SIM Modules
Thermally Enhanced 6.1 mm 28-Lead TSSOP Package

APPLICATIONS
GSM/DCS/PCS Handsets
TeleMatic Systems
ICO/Iridium Terminals

GENERAL DESCRIPTION

The ADP3401 is a multifunction power management system IC
optimized for GSM cell phones. The wide input voltage range of

3.0 V to 7.0 V makes the ADP3401 ideal for both single cell Li-Ion
and three cell NiMH designs. The current consumption of the
ADP3401 has been optimized for maximum battery life, featuring
a ground current of only 150 µA when the phone is in standby
(digital LDO, and SIM card supply active). An undervoltage lock­out (UVLO) prevents the startup when there is not enough energy
in the battery. All four integrated LDOs are optimized to power
one of the critical sub-blocks of the phone. Their novel anyCAP™
architecture requires only very small output capacitors for stability,
and the LDOs are insensitive to the capacitors’ equivalent series
resistance (ESR). This makes them stable with any capacitor,
including ceramic (MLCC) types for space-restricted applications.

A step-up converter is implemented to supply both the SIM
module and the level translation circuitry to adapt logic signals
for 3 V and 5 V SIM modules. Sophisticated controls are avail­able for power-up during battery charging, keypad interface, and
charging of an auxiliary backup battery for the real-time clock.
These allow an easy interface between ADP3401, GSM proces­sor, charger, and keypad. The 28-lead TSSOP package has been
thermally enhanced to maximize power dissipation capability.
Furthermore, a reset circuit and a thermal shutdown function
have been implemented to support reliable system design.

FUNCTIONAL BLOCK DIAGRAM

anyCAP is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADP3401–SPECIFICATIONS

(–20°C ≤ TA ≤ +85°C, VBAT = 3 V to 7 V, C

C

= C

VCC

= 2.2 ␮F, C

VCCA

= 0.1 ␮F, C

VRTC

VBAT

= 0.22 ␮F, C

VTCXO

= C

SIMBAT

= C

= 10 ␮F,

VSIM

= 0.1 ␮F, min. loads applied

VCAP

on all outputs, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

1

Parameter Symbol Conditions Min Typ Max Unit

SHUTDOWN SUPPLY CURRENT I

BAT

VBAT = Low (UVLO Low) VBAT = 2.7 V 3 20 µA
VBAT = High (UVLO High) VBAT

OPERATING GROUND CURRENT I

GND

VCC and VRTC On Minimum Loads, VBAT
VCC, VRTC and VSIM On Minimum Loads, VBAT
All LDOs and VSIM On Minimum Loads, VBAT

= 3.6 V, VRTC On 12 30 µA

= 3.6 V 100 140 µA
= 3.6 V 150 240 µA
= 3.6 V 260 400 µA

All LDOs and VSIM On Maximum Loads, VBAT = 3.6 V 15 mA

UVLO CHARACTERISTICS

UVLO On Threshold VBAT

UVLO

3.0 3.3 V

UVLO Hysteresis 100 mV

INPUT CHARACTERISTICS

Input High Voltage V

IH

PWRONIN and ANALOGON 2 V
PWRONKEY 0.7 ⫻ VBAT V
Input Low Voltage V

IL

PWRONIN and ANALOGON 0.4 V
PWRONKEY 0.3 ⫻ VBAT V

PWRONKEY INPUT PULL-UP

RESISTANCE TO VBAT 15 20 25 kΩ

CHRON CHARACTERISTICS

CHRON Threshold V
CHRON Hysteresis Resistance R
CHRON Input Bias Current I

T
IN

B

2.38 < CHRON < V
CHRON > V

T

T

2.38 2.48 2.58 V
108 125 138 kΩ

0.5 µA

ROWX CHARACTERISTICS

ROWX Output Low Voltage V

ROWX Output High Leakage I

OL

IH

PWRONKEY = Low 0.4 V

= 200 µA

I

OL

PWRONKEY = High 1 µA

Current V(ROWX) = 5 V

SHUTDOWN

Thermal Shutdown Threshold

2

Junction Temperature 160 ºC

Thermal Shutdown Hysteresis Junction Temperature 35 ºC

DIGITAL LDO (VCC)

Output Voltage VCC Line, Load, Temp 2.710 2.765 2.820 V
Line Regulation DVCC 3 V < VBAT < 7 V, Min Load 2 mV
Load Regulation DVCC 50 µA < I

Output Capacitor

3

Dropout Voltage V

C

O
DO

VBAT = 3.6 V

VO = V
I

= 100 mA

LOAD

< 100 mA, 15 mV

LOAD

2.2 µF

– 100 mV 215 mV

INITIAL

ANALOG LDO (VCCA)

Output Voltage VCCA Line, Load, Temp 2.710 2.765 2.820 V
Line Regulation DVCCA 3 V < VBAT < 7 V, Min Load 2 mV
Load Regulation DVCCA 200 µA < I

Output Capacitor

3

Dropout Voltage V

C

O
DO

VBAT = 3.6 V

VO = V

INITIAL

= 130 mA

I

LOAD

< 130 mA, 15 mV

LOAD

2.2 µF

– 100 mV 215 mV

Ripple Rejection DVBAT/ f = 217 Hz (t = 4.6 ms) 65 70 dB

DVCCA VBAT = 3.6 V

Output Noise Voltage V

NOISE

f = 10 Hz to 100 kHz 75 µV rms
I

= 130 mA, VBAT = 3.6 V

LOAD

–2– REV. 0

ADP3401

Parameter Symbol Conditions Min Typ Max Unit

CRYSTAL OSCILLATOR LDO (VTCXO)

Output Voltage VTCXO Line, Load, Temp 2.710 2.765 2.820 V
Line Regulation ∆VTCXO 3 V < VBAT < 7 V, Min Load 2 mV
Load Regulation ∆VTCXO 100 µA < I

Output Capacitor

3

Dropout Voltage V

C

O
DO

VBAT = 3.6V

VO = V

INITIAL

= 5 mA

I

LOAD

Ripple Rejection ∆VBAT/ f = 217 Hz (t = 4.6 ms) 65 72 dB

∆VTCXO VBAT = 3.6 V

Output Noise Voltage V

NOISE

f = 10 Hz to 100 kHz 80 µV rms
I

= 5 mA, VBAT = 3.6 V

LOAD

VOLTAGE REFERENCE (REFOUT)

Output Voltage V
Line Regulation ∆V

REFOUT

REFOUT

Line, Load, Temp 1.192 1.210 1.228 V
3 V < VBAT < 7 V, Min Load 2 mV

< 5 mA, 1 mV

LOAD

0.22 µF

– 100 mV 150 mV

Load Regulation ∆V

REFOUT

0 µA < I

< 50 µA, 0.5 mV

LOAD

VBAT = 3.6 V

Ripple Rejection ∆VBAT/ f = 217 Hz (t = 4.6 ms), 65 75 dB

VBAT = 3.6 V

100 pF

f = 10 Hz to 100 kHz 40 µV rms

Maximum Capacitive Load C
Output Noise Voltage V

∆V

O
NOISE

REFOUT

VBAT = 3.6 V

REAL-TIME CLOCK LDO/
BATTERY CHARGER (VRTC)

Maximum Output Voltage VRTC I
Current Limit I
Off Reverse Leakage

Current

Dropout Voltage V

MAX

I

L

DO

≤ 10 µA 2.810 2.850 2.890 V

LOAD

3.050 V < VBAT < 7 V 175 µA

2.0 V < VBAT < UVLO 1 µA
VO = V
I

LOAD

= 10 µA

– 10 mV 170 mV

INITIAL

SIM CHARGE PUMP (VSIM)

Output Voltage for 5 V SIM Modules VSIM 0 mA ≤ I

≤ 10 mA 4.70 5.00 5.30 V

LOAD

SIMPROG = High

Output Voltage for 3 V SIM Modules VSIM 0 mA ≤ I

≤ 6 mA 2.82 3.00 3.18 V

LOAD

SIMPROG = Low

GSM/SIM LOGIC TRANSLATION
(GSM INTERFACE)

Input High Voltage (SIMPROG, SIMON, V

IH

VCC – 0.6 V
RESETIN, CLKIN)
Input Low Voltage (SIMPROG, SIMON, V

IL

0.6 V
RESETIN, CLKIN)
DATAIO V

DATAIO Pull-Up Resistance to VCC R

IL

, V

V

IH

OH

I

IL

V

OL
IN

VOL(I/O) = 0.4 V, 0.230 V

(I/O) = 1 mA

I

OL

(I/O) = 0.4 V, 0.335 V

V

OL

(I/O ) = 0 mA

I

OL

IIH, I

= ±10 µA VCC

OH

– 0.4 V
VIL = 0 V –0.9 mA
VIL (I/O) = 0.4 V 0.420 V

16 20 24 kΩ

–3–REV. 0

ADP3401

Parameter Symbol Conditions Min Typ Max Unit

SIM INTERFACE

VSIM = 5 V
RST V
RST V
CLK V
CLK V
I/O V
I/O V
I/O I
I/O V

OL
OH
OL
OH
IL

, V

IH

OH

IL

OL

VSIM = 3 V
RST V
RST V
CLK V
CLK V
I/O V
I/O V
I/O I
I/O V

I/O Pull-Up Resistance to VSIM R
Max Frequency (CLK) f
Prop Delay (CLK) t
Output Rise/Fall Times (CLK) t
Output Rise/Fall Times (I/O, RST) t

OL
OH
OL
OH
IL
IH

IL

OL

IN
MAX
D

, t

R

, t

R

, V

F

F

OH

Duty Cycle (CLK) D D CLKIN = 50% 47 53 %

RESET GENERATOR (RESET)

Output High Voltage V
Output Low Voltage V
Delay Time Per Unit Capacitance t

OH

OL
D

Applied to RESCAP Pin

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods .

2

This feature is intended to protect against catastophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC
could cause permenant damage to the device.

3

Required for stability.

Specifications subject to change without notice.

I = +200 µA 0.6 V
I = –20 µA VSIM

– 0.7 V

I = +200 µA 0.5 V
I = –20 µA 0.7 ⫻ VSIM V

0.4 V

IIH, I

= ±20 µA VSIM – 0.4 V

OH

VIL = 0 V –0.9 mA
IOL = +1 mA 0.4 V
DATAIO ≤ 0.23 V

I = +200 µA 0.2 ⫻ VSIM V
I = –20 µA 0.8 ⫻ VSIM V
I = +20 µA 0.2 ⫻ VSIM V
I = –20 µA 0.7 ⫻ VSIM V

0.4 V

IIH, I

= ±20 µA VSIM – 0.4 V

OH

VIL= 0 V –0.9 mA
IOL = 1 mA 0.4 V
DATAIO ≤ 0.23 V

81012kΩ

CL = 30 pF 5 MHz

30 50 ns
CL = 30 pF 9 18 ns
C

= 30 pF 1 µs

L

f = 5 MHz

I

= –15 µA VCC – 0.3 V

OH

I

= –15 µA 0.3 V

OL

1.0 ms/nF

–4– REV. 0

ADP3401

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin with Respect

to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V

Voltage on Any Pin May Not Exceed VBAT,

with the Following Exceptions: VRTC, VSIM,
CAP+, PWRONIN, I/O, CLK, RST

°

Storage Temperature Range . . . . . . . . . . . . –65

Operating Temperature Range . . . . . . . . . . . –20

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125

, Thermal Impedance (TSSOP-28) . . 2-Layer Board 90°C/W

θ

JA

, Thermal Impedance (TSSOP-28) . . 4-Layer Board 60°C/W

θ

JA

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300

*This is a stress rating only, operation beyond these limits can cause the device to

be permanently damaged.

C to +150°C

°

C to +85°C

°

°

C

C

PIN CONFIGURATION

VBAT

VCC
PWRONKEY
ANALOGON

PWRONIN

ROWX

CHRON

VRTC

CAP2
SIMBAT
DATAIO

RESETIN

CLKIN

SIMGND

1
2
3
4
5
6
7

ADP3401

8

9
10
11
12
13
14

28

AGND

27

VCCA

26

REFOUT

25

RESET

24

VTCXO

23

DGND

22

RESCAP

21

CAP+
VSIM

20
19

CLK

18

SIMON

17

SIMPROG

16

RST

15

I/O

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADP3401ARU –20°C to +85°C 28-Lead TSSOP RU-28A

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 VBAT Battery Input Voltage
2 VCC Digital Low Dropout Regulator
3 PWRONKEY Power On/Off Key
4 ANALOGON VTCXO Enable
5 PWRONIN Power On/Off Signal from

Microprocessor
6 ROWX Microprocessor Keyboard Output
7 CHRON Charger On/Off Input
8 VRTC Real-Time Clock Supply/Coin

Cell Battery Charger
9 CAP– Negative Side of Boost Capacitor
10 SIMBAT Battery Input for the SIM

Charge Pump
11 DATAIO Non-Level-Shifted Bidirectional

Data I/O
12 RESETIN Non-Level-Shifted SIM Reset
13 CLKIN Non-Level-Shifted Clock
14 SIMGND Charge Pump Ground
15 I/O Level-Shifted Bidirectional SIM

Data Input/Output
16 RST Level-Shifted SIM Reset
17 SIMPROG VSIM Programming:

Low = 3 V, High = 5 V
18 SIMON VSIM Enable
19 CLK Level-Shifted SIM Clock
20 VSIM SIM Supply
21 CAP+ Positive Side of Boost Capacitor
22 RESCAP Reset Delay Timing Cap
23 DGND Digital Ground
24 VTCXO Crystal Oscillator Low Dropout

Regulator
25 RESET Main Reset
26 REFOUT Reference Output
27 VCCA Analog Low Dropout Regulator
28 AGND Analog Ground

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. 0

ADP3401

Table I. LDO Control Logic

INPUTS OUTPUTS

UVLO CHRON PWRONKEY PWRONIN ANALOGON VRTC VCC VCCA REFOUT VTCXO
L X X X X Off Off Off Off Off

H H XXX OnOnOnOnOn
HX L X X On On On On On
H L H L X On Off Off Off Off
HL H H L On On Off Off Off
HL H H H On On On On On

X = Don't care
Bold denotes the active control signal.

Table II. VSIM Control Logic

INPUTS OUTPUTS

VCC RESET SIMON SIMPROG VSIM

Off L X X Off
On L X X Off
On H L X Off
On H H L 3 V
On H H H 5 V

X = Don't care

PWRONKEY

ROWX

PWRONIN

RESCAP

CHRON

ANALOGON

SIMBAT

CAP+

CAP2

SIMPROG

SIMON

SIMGND

RESETIN

CLKIN

DATAIO

ADP3401

CHARGER

ON

THRESHOLD

CHARGE

3V/5V
EN

20kV

EN

PUMP

LOGIC

LEVEL

TRANSLATION

UVLO

UVLO

RESET

GENERATOR

VBAT

OVER
TEMP

ADJ

POWER GOOD

+

1.210V

DIGITAL LDO
VBAT
VREF

EN

GND PG

RTC LDO

VBAT
EN GND

XTAL OSC LDO

VBAT
VREF

EN GND

ANALOG LDO
VBAT
VREF

EN

GND

EN
REF

BUFFER

OUT

OUT

OUT

OUT

VCC

2.765V

DGND

VRTC

2.85V

RESET

VTCXO

2.765V

VCCA

2.765V

REFOUT

AGND

VSIMRSTCLKI/O

Figure 1. Functional Block Diagram

–6– REV. 0

350

+258C

2208C

VRTC – V

300

0

0

30.5

I

RTC

– mA

1.0 1.5 2.0 2.5

150

100

50

250

200

+858C

VOLTAGE

TIME – 100ms/DIV

VBAT 100 mV/DIV

3.2

3.0

MLCC CAPS

VCC 10 mV/DIV

VCCA 10 mV/DIV

VTCXO 10 mV/DIV

VOLTAGE

TIME – 100ms/DIV

3.2

3.0

MLCC CAPS

VBAT (100 mV/DIV)

VCC (10 mV/DIV)

VCCA (10 mV/DIV)

VTCXO (10 mV/DIV)

PWRONIN, SIMON, AND ANALOGON

PWRONIN AND SIMON

PWRONIN

374

56

VBAT – V

– mA

GND

I

300

250

200

150

100

50

Figure 2. Ground Current vs. Battery Voltage

140

120

ADP3401

Figure 5. RTC I/V Characteristic

100

80

60

40

DROPOUT VOLTAGE – mV

20

0

0

VCC

VCCA

LOAD CURRENT – mA

Figure 3. VCC, VCCA Dropout Voltage vs. Load Current

70

60

50

40

30

20

DROPOUT VOLTAGE – mV

10

0

0

12345

LOAD CURRENT – mA

Figure 4. VTCXO Dropout Voltage vs. Load Current

14020 40 60 80 100 120

Figure 6. Line Transient Response, Maximum Loads

Figure 7. Line Transient Response, Minimum Loads

–7–REV. 0

ADP3401

I

LOAD

I = 200mA

MLCC CAPS

I = 100mA

PWRONIN AND ANALOGON (2V/DIV)

VCC

VOLTAGE – 20mV/DIV

Figure 8. VCC Load Step

I

VCCA

VOLTAGE – 20mV/DIV

TIME – 200ms/DIV

LOAD

I = 50mA

MLCC CAPS

I = 130mA

VCCA (100mV/DIV)

VOLTAGE

REFOUT (100mV/DIV)

VCC (100mV/DIV)

VTCXO (100mV/DIV)

TIME – 50ms/DIV

Figure 11. Turn-On Transients, Maximum Loads

80

70

VCCA

60

MLCC OUTPUT CAPS

50

VBAT = 3.2V, FULL LOADS

40

30

RIPPLE REJECTION – dB

20

10

REFOUT

VTCXO

VCC

TIME – 100ms/DIV

Figure 9. VCCA Load Step

PWRONIN AND ANALOGON (2V/DIV)

VCCA (100mV/DIV)

VOLTAGE

VTCXO (100mV/DIV)

VCC (100mV/DIV)

TIME – 50ms/DIV

Figure 10. Turn-On Transients, Minimum Loads

0

4 100k10

100 1k 10k

FREQUENCY – Hz

Figure 12. Ripple Rejection vs. Frequency

80

REFOUT

70

60

50

40

30

RIPPLE REJECTION – dB

20

10

0

2.5

VCCA

VTCXO

2.7 2.8 2.9 3.0 3.1 3.2

VCC

VBAT – V

FREQUENCY = 217Hz
MAX LOADS

3.32.6

Figure 13. Ripple Rejection vs. Battery Voltage

–8– REV. 0

ADP3401

ANALOG GND

DIGITAL AND
SIM GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

2.2mF

100nF

28

27

26

25

23

22

21

20

19

18

17

16

15

ADP3401

100V

10mF

R1

CHARGER INPUT

R2

BACKUP COIN CELL

10mF

SIM PIN OF

GSM PROCESSOR

2.2mF

10mF

24

0.22mF

100nF

10mF

CLK TO SIMCARD

RST TO SIMCARD

I/O TO SIM CARD

100nF

1 Li-ION OR

3 NiMH

CELLS

GSM

PROCESSOR

GSM

PROCESSOR

VBAT

VCC

PWRONKEY

ANALOGON

PWRONIN

ROWX

CHRON

VRTC

CAP–

SIMBAT

DATAIO

RESETIN

CLKIN

SIMGND

AGND

VCCA

REFOUT

VTCXO

DGND

RESCAP

CAP+

VSIM

CLK

SIMON

SIMPROG

RST

I/O

RESET

600

500

400

300

200

100

VOLTAGE SPECTRAL NOISE DENSITY – nV/ Hz

0

VCCA

TCXO

REF

10 100k100

1k 10k

FREQUENCY – Hz

FULL LOAD
MLCC CAPS

Figure 14. Output Noise Density

THEORY OF OPERATION

The ADP3401 is a power management chip optimized for use with
the AD20msp425 GSM baseband chipsets in handset applications.
Figure 1 shows a functional block diagram of the ADP3401.

The ADP3401 contains several blocks:

• Four Low Dropout Regulators (Digital, Analog, Crystal
Oscillator, Real-Time Clock)

• Reset Generator

• Buffered Precision Reference

• SIM Interface Logic Level Translation (3 V/5 V)

• SIM Voltage Supply

• Power-On/-Off Logic

• Undervoltage Lockout

These functions have traditionally been done as either a discrete
implementation or a custom ASIC design. ADP3401 combines
the benefits of both worlds by providing an integrated standard
product solution where every block is optimized to operate in a
GSM environment while maintaining a cost-competitive solution.

Figure 15 shows the external circuitry associated with the
ADP3401. Only a few support components, mainly decoupling
capacitors, are required.

Input Voltage

The input voltage range for ADP3401 is 3 V to 7 V and optimized
for a single Li-Ion cell or three NiMH/NiCd cells. The ADP3401
uses Analog Devices’ patented package thermal enhancement
technology, which allows 15% improvement in power handling
capability over standard plastic packages. The thermal impedance

) of the ADP3401 is 60°C/W. The charging voltage for a high

(θ

JA

capacity NiMH cell can be as high as 5.5 V. Power dissipation
should be calculated at maximum ambient temperatures and

°

battery voltage in order not to exceed the 125

C maximum allow­able junction temperature. Figure 16 shows the maximum total
LDO output current as a function of ambient temperature and
battery voltage.

However, high battery voltages normally occur only when the
battery is being charged and the handset is not in conversation
mode. In this mode there is a relatively light load on the LDOs.
A fully charged Li-Ion battery is 4.25 V, where the LDOs deliver
the maximum 240 mA up to the max 85

°

C ambient temperature.

Figure 15. Typical Application Circuit

–9–REV. 0

ADP3401

ADP3401

ENHANCED
GSM PROCESSOR
(AD20msp425)

VRTC

PWRON

PWRONIN

COIN

CELL

VRTC

RTC

MODULE

300

4-LAYER BOARD

u

= 608C/W

JA

250

200

150

100

TOTAL LDO CURRENT – mA

50

0

220

0

AMBIENT TEMPERATURE – 8C

20 40 60 80

VBAT = 5V

VBAT = 5.5V

VBAT = 6V

VBAT = 7V

Figure 16. Total LDO Load Current vs. Temperature and VBAT

Low Dropout Regulators (LDOs)

The ADP3401 high-performance LDOs are optimized for
their given functions by balancing quiescent current, dropout
voltage, line/load regulation, ripple rejection, and output
noise. 2.2 µF tantalum or MLCC ceramic capacitors are
recommended for use with the digital and analog LDOs, and

0.22 µF for the TCXO LDO.

Digital LDO (VCC)

The digital LDO (VCC) supplies all the digital circuitry in the
handset (baseband processor, baseband converter, external
memory, display, etc). The LDO has been optimized for very
low quiescent current (30 µA maximum) at light loads as this
LDO is on at all times. This is due to both the structure of GSM
and a new clocking scheme used in the AD20msp425. Figure 17
shows how the digital current varies as a function of time.

POWER

~50mA

~200mA

MICROPROCESSOR

START

~2ms

0.5s TO 2s

MICROPROCESSOR
STOP

Figure 17. Digital Power as a Function of Time

Analog LDO (VCCA)

This LDO has the same features as the digital LDO. It has further­more been optimized for good low frequency ripple rejection for use
with analog sections in order to reject the ripple coming from the RF
power amplifier. VCCA is rated to 130 mA load which is sufficient
to supply the complete analog section of a baseband converter such
as the AD6421/AD6425, including a 32 Ω earpiece. The analog
LDO and the TCXO LDO can be controlled by ANALOGON.

TCXO LDO (VTCXO)

The TCXO LDO is intended as a supply for the temperature­compensated crystal oscillator, which needs its own ultralow noise
supply. The output current is rated to 5 mA for the TCXO LDO.

TIME

RTC LDO (VRTC)

The RTC LDO charges a rechargable coin cell to run the real­time clock module. It has been targeted to charge Manganese
Lithium batteries such as the ML series (ML621/ML1220)
from Sanyo. The ML621 has a small physical size (6.8 mm
diameter) and a nominal capacity of 2.5 mAh, which yields
about 250 hours of backup time.

Figure 18 shows the use of VRTC with the Enhanced GSM
Processor which is a part of the AD20msp425 chipset.

85

Figure 18. Connecting VRTC and POWERONIN to the
AD20msp425 Chipset

The ADP3401 supplies current both for charging the coin cell and
for the RTC module when the digital supply is off. The nominal
charging voltage of 2.85 V ensures charging down to a main
battery voltage of 3.0 V. The inherent current limit of VRTC
ensures long cell life while the precise output voltage regulation
charges the cell to more than 90% of its capacity. In addition, it
features a very low quiescent current (10 µA) since this LDO is
running all the time, even when the handset is switched off. It also
has reverse current protection with low leakage which is needed
when the main battery is removed and the coin cell supplies the
RTC module.

The RTC module has a built-in alarm which, when it expires,
will pull POWERONIN high, allowing an alarm function even if
the handset is switched off.

Reference Output (REFOUT)

The reference output is a low-noise, high-precision reference
with a guaranteed accuracy of 1.5% over temperature. The
reference can be fed to the baseband converter, such as the
AD6425, improving the absolute accuracy of the converters
from 5% to 1.5%. This significantly reduces calibration time
needed for the baseband converter during production.

SIM Interface

The SIM interface generates the needed SIM voltage—either 3 V
or 5 V, dependent on SIM type, and also performs the needed
logic level translation. Quiescent current is low, as the SIM card
will be powered all the time. Note that DATAIO and I/O have
integrated pull-up resistors as shown in Figure 19. See Table II for
the control logic of the charge pump output, VSIM.

–10– REV. 0

ADP3401

ADP3401

RESETIN

CLKIN

DATAIO

VCC

VCC

VCC

LEVEL

SHIFT

LEVEL

SHIFT

VSIM

RST

VSIM

CLK

VSIM

I/O

Figure 19. Schematic for Level Translators

Power-On/-Off

ADP3401 handles all issues regarding power-on/-off of the hand­set. It is possible to turn on the ADP3401 in three different ways:

• Pulling PWRONKEY low

• Pulling PWRONIN high

• CHRON exceeds threshold

Pulling PWRONKEY key low is the normal way of turning on the
handset. This will turn on all the LDOs as long as PWRONKEY is
held low. The microprocessor then starts and pulls PWRONIN
high after which PWRONKEY can be released. PWRONIN going
high will also turn on the handset. This is the case when the alarm
in the RTC module expires.

An external charger can also turn on the phone. The turn-on
threshold and hysteresis can be programmed via external resistors
to allow full flexibility with any external charger and battery chem­istry. These resistors are referred to as R1 and R2 in Figure 15.

Undervoltage Lockout (ULVO)

The UVLO function in the ADP3401 prevents startup when the
initial voltage of the main battery is below the 3.0 V threshold.
If the battery is this low with no load, there will be little or no
capacity left. When the battery is greater than 3.0 V, as with the
insertion of a fresh battery, the UVLO comparator trips, the
RTC LDO is enabled, and the threshold is reduced to 2.9 V.
This allows the handset to start normally until the battery volt­age decays to 2.9 V open circuit. Once the 3.0 V threshold is
exceeded, the RTC LDO is enabled. If, however, the backup
coin cell is not connected, or is damaged or discharged below

1.5 V, the RTC LDO will not start on its own. In this situation,
the RTC LDO will be started by enabling the VCC LDO.

Once the system is started, i.e., the phone is turned on and the
VCC LDO is up and running, the UVLO function is entirely
disabled. The ADP3401 is then allowed to run down to very low
battery voltages, typically around 2 V. The battery voltage is
normally monitored by the microprocessor and usually shuts the
phone off at around 3.0 V.

If the phone is off, i.e., the VCC LDO is off, and the battery
voltage drops below 2.9 V, the UVLO circuit disables startup
and the RTC LDO. This is implemented with very low quies­cent current, typically 3 µA, to protect the main battery against
any damage. NiMH batteries can reverse polarity if the 3-cell
battery voltage drops below 3.0 V and a current of more than
about 40 µA continues to flow. Lithium ion batteries will lose
their capacity, although the built-in safety circuits normally
present in these cells will most likely prevent any damage.

RESET

ADP3401 contains reset circuitry that is active both at power-up
and at power-down. RESET is held low at power-up. An inter­nal power-good signal starts the reset delay. The delay is set by
an external capacitor on RESCAP:

=×10.

ms

nF

C

t

RESET RESCAP

A 100 nF capacitor will produce a 100 ms reset time. At power-off,
RESET will be kept low to prevent any spurious microprocessor
starts. The current capability of RESET is low (a few hundred nA)
when VCC is off, to minimize power consumption. Therefore,
RESET should only be used to drive a single CMOS input. When
VCC is on, RESET will drive about 15 µA.

Overtemperature Protection

The maximum die temperature for ADP3401 is 125°C. If the die

°

temperature exceeds 160

C, the ADP3401 will disable all the
LDOs except the RTC LDO, which has very limited current capa­bilities. The LDOs will not be re-enabled before the die tempera-

°

ture is below 125

C, regardless of the state of PWRONKEY,
PWRONIN, and CHRON. This ensures that the handset will
always power-off before the ADP3401 exceeds its absolute maxi­mum thermal ratings.

APPLICATIONS INFORMATION
Input Capacitor Selection

For the input voltage, VBAT, of the ADP3401, a local bypass
capacitor is recommended. Use a 5 µF to 10 µF, low ESR capaci-
tor. Multilayer ceramic chip capacitors provide the best combina­tion of low ESR and small size, but may not be cost-effective. A
lower cost alternative may be to use a 5 µF to 10 µF tantalum
capacitor with a small (1 µF to 2 µF) ceramic in parallel.

LDO Capacitor Selection

The performance of any LDO is a function of the output capaci­tor. The digital and analog LDOs require a 2.2 µF capacitor and
the TCXO LDO requires a 0.22 µF capacitor. Larger values
may be used, but the overshoot at startup will increase slightly.
If a larger output capacitor is desired, be sure to check that the
overshoot and settling time are acceptable for the application.

All the LDOs are stable with a wide range of capacitor types and
ESR due to Analog Devices’ anyCAP technology. The ADP3401
is stable with extremely low ESR capacitors (ESR ~ 0), such as
multilayer ceramic capacitors, but care should be taken in their
selection. Note that the capacitance of some capacitor types shows
wide variations over temperature or with dc voltage. A good quality
dielectric, X7R or better, is recommended.

The RTC LDO has a rechargeable coin cell or an electric double­layer capacitor as a load, but an additional 0.1 µF ceramic capaci-
tor is recommended for stability and best performance.

Charge Pump Capacitor Selection

For the input (SIMBAT) and output (VSIM) of the SIM charge
pump, use 10 µF low ESR capacitors. The use of low ESR capaci-
tors improves the noise and efficiency of the SIM charge pump.
Multilayer ceramic chip capacitors provide the best combination of
low ESR and small size but may not be cost-effective. A lower cost
alternative may be to use a 10 µF tantalum capacitor with a small
(1 µF to 2 µF) ceramic capacitor in parallel.

–11–REV. 0

ADP3401

For the lowest ripple and best efficiency, use a 0.1 µF, ceramic
capacitor for the charge pump flying capacitor (CAP+ and CAP–).
A good quality dielectric, such as X7R is recommended.

Setting the Charger Turn-On Threshold

The ADP3401 can be turned on when the charger input exceeds
a programmable threshold voltage. The charger’s threshold and
hysteresis are set by selecting the values for R1 and R2 shown in
Figure 15.

The turn-on threshold for the charger is calculated using:





RR

+

2

V

=



CHR








HYS

RR

×

2

HYS

×

Where VT is the CHRON threshold voltage and R





RV

+

×

11






T





is the

HYS

CHRON hysteresis resistance.
The hysteresis is determined using:

V

V

HYS

T

=×1

R

R

HYS

Combining the above equations and solving for R1 and R2 gives
the following formulas:

R

HYS

R

1 =×

R

2

=



V

CHR



V



T

V

V

RR

−

HYS

T

1

×

HYS



11

×−

RR

HYS




Example: R1 = 10 kΩ and R2 = 30.2 kΩ gives a charger thresh­old (not counting the drop in the power Schottky diode) of

3.5 V ± 160 mV with a 200 mV ± 30 mV hysteresis.

Charger Diode Selection

The diode shown in Figure 15 is used to prevent the battery from
discharging into the charger turn-on setting resistors, R1 and R2.
A Schottky diode is recommended to minimize the voltage differ­ence from the charger to the battery and the power dissipation.
Choose a diode with a current rating high enough to handle both
the battery charging current and the current the ADP3401 will
draw if powered up during charging. The battery charging current
is dependent on the battery chemistry and the charger circuit.
The ADP3401 current will be dependent on the loading.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed
circuit boards:

1. Split the battery connection to the VBAT and SIMBAT
pins of the ADP3401. Use separate traces for each connection
and locate the input capacitors as close to the pins as possible.

2. SIM input and output capacitors should be returned to the
SIMGND and kept as close as possible to the ADP3401 to
minimize noise. Traces to the SIM charge pump capacitor
should be kept as short as possible to minimize noise.

3. VCCA and VTCXO capacitors should be returned to AGND.

4. VCC and VRTC capacitors should be returned to DGND.

5. Split the ground connections. Use separate traces or planes
for the analog, digital, and power grounds, and tie them
together at a single point, preferably close to the battery return.

C3768–8–1/00 (rev. 0)

28

PIN 1

0.0374 (0.95)

0.0335 (0.85)

0.006 (0.15)

0.002 (0.05)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Thin Shrink Small Outline (TSSOP)

(RU-28A)

0.386 (9.80)

0.378 (9.60)

15

0.244 (6.20)

0.236 (6.00)

0.325 (8.25)

0.313 (7.95)

141

0.0433 (1.10)
MAX

88

0.0256
(0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

SEATING

PLANE

0.0078 (0.200)

0.0035 (0.090)

08

PRINTED IN U.S.A.

0.030 (0.75)

0.020 (0.50)

–12–

REV. 0