Page 1
Ultralow, IQ, anyCAP
®
a
FEATURES
Accuracy Over Line and Load: ⴞ4.0% @ 25ⴗC,
ⴞ5% Over Temperature
Ultralow Dropout Voltage: 300 mV (Typ) @ 300 mA
Requires Only C
anyCAP = Stable with any Type of Capacitor
(including MLCC)
Current and Thermal Limiting
Low Shutdown Current: < 2 A
1.7 V ⱕ V
IN
2.8 V ⱕ VCC ⱕ 6 V
= 1.2 V ⴞ5%
V
OUT
–40ⴗC to +100ⴗC Ambient Temperature Range
Ultrasmall Thermally Enhanced 8-Lead MSOP Package
APPLICATIONS
Notebook PCs
Desktop PCs
GENERAL DESCRIPTION
The ADP3342 is a unique member of the ADP330x family of
precision low dropout anyCAP voltage regulators. The ADP3342
operates with an input voltage range of 1.7 V to 6 V and delivers
a continuous load current up to 300 mA. In order to support the
ability to regulate from such a low input voltage, the power rail
to the IC, VCC, has been split off from the main power rail, VIN,
from which the output is powered.
The ADP3342 stands out from the conventional LDOs with the
lowest thermal resistance of any MSOP-8 package and an enhanced
process that enables it to offer performance advantages beyond
its competition. Its patented design requires only a 1.0 µF output
capacitor for stability. This device is insensitive to output capacitor
Equivalent Series Resistance (ESR), and is stable with any good
quality capacitor, including ceramic (MLCC) types for spacerestricted applications. The dropout voltage of the ADP3342 is
only 190 mV (typical) at 300 mA. This device also includes a
safety current limit, thermal overload protection and a shutdown
control pin.
= 1.0 F for Stability
O
ⱕ 6 V
VCC
PWRGD
SD
Low Dropout Regulator
FUNCTIONAL BLOCK DIAGRAM
IN
THERMAL
PROTECTION
ADP3342
V
IN
1.8V
1F
OFF
+
ON
Figure 1. Typical Application Circuit
Q1
DRIVER
GND
3.3V
VCC
ADP3342
IN
OUT
IN
OUT
PWRGD
SD
GND
CC
ADP3342
OUT
g
m
BANDGAP +
REF –
V
OUT
1.2V
+
1F
anyCAP is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Page 2
ADP3342–SPECIFICATIONS
(VCC = 3.0 V, VIN = 1.8 V, CIN = C
+100ⴗC, unless otherwise noted.)
= 1 F, TA = 0ⴗC to 100ⴗC and TA = –40ⴗC to
OUT
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT
Voltage Accuracy V
OUT
Line Regulation VCC = 2.8 V to 6 V, V
Load Regulation I
Dropout Voltage V
DROP
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V –4.0 +4.0 %
= 0.1 mA to 300 mA
I
L
T
= 25°C
A
VCC = 2.8 V to 6 V, V
= 0.1 mA to 300 mA,
I
L
T
= –40°C to +100°C
A
= 25°C
T
A
= 0.1 mA to 300 mA 0.12 mV/mA
L
T
= 25°C
A
V
= 98% of V
OUT
= 1.7 V to 6 V –5.0 +5.0 %
IN
= 1.7 V to 6 V 0.04 mV/V
IN
OUTNOM
IL = 300 mA 190 450 mV
I
= 200 mA 125 mV
L
= 100 mA 70 mV
I
Current Limiting I
Output Noise V
LIM
NOISE
L
VCC = 3 V, VIN = 1.8 V 450 mA
f = 10 Hz–100 kHz, CL = 1 µF60µV rms
IL = 300 mA
OPERATING CURRENTS
Ground Current in Regulation I
GND
VCC Current in Regulation IVCC I
Ground Current in Shutdown I
GNDSD
IL = 300 mA, TA = –40°C to +100°C 3.0 8.5 mA
I
= 300 mA, TA = 0°C to 100°C 3.0 6.0 mA
L
I
= 300 mA, TA = 25°C 3.0 4.0 mA
L
= 200 mA 2.0 mA
I
L
I
= 0.1 mA 100 175 µA
L
= 300 mA 100 170 µA
L
SD = 0 V, VCC = 6 V, VIN = 1.8 V 0.01 2 µA
SHUTDOWN
Threshold Voltage V
THSD
ON VCC – 0.9 V
OFF 0.6 V
SD Input Current I
Output Current In Shutdown I
SD
OSD
0 ≤ SD ≤ 6 V 1.4 7 µA
TA = 25°C VCC = 6 V, VIN = 6 V 0.01 1 µA
TA = 100°C VCC = 6 V, VIN = 6 V 0.01 2 µA
PWRGD
Power Good Output Voltage I
PWRGDL
V
PWRGDL
V
PWRGDH
Power Good On Time Delay TD1
TD2
Power Good Off Time Delay TD3
V
= 1.2 V, VCC = 3.0 V 0.85 1.5 mA
PWRGD
2
I
= 300 µA 0.4 V
PWRGD
2
I
= 300 µA VCC – 0.4 V
3
4
5
PWRGD
IL = 3 mA to 300 mA, 5 300 µs
= 1 µF to 10 µF
C
OUT
IL = 3 mA to 300 mA, 50 300 µs
C
= 1 µF to 10 µF
OUT
IL = 3 mA to 300 mA, 0.05 1 µs
C
= 1 µF to 10 µF
OUT
THERMAL PROTECTION
Shutdown Temperature TH
NOTES
1
Ambient temperature of 100°C corresponds to a junction temperature of 125°C under typical full load test conditions.
2
V
, V
PWRGDL
3
TD1: Delay time from V
4
TD2: Delay time from SD high to PWRGD high. Guaranteed by design.
5
TD3: Delay time between SD low to PWRGD low. Guaranteed by design.
Specifications subject to change without notice.
,: Powergood output voltages. Guaranteed by design and characterization.
PWRGDH
crossing 1 V to PWRGD high. Guaranteed by design.
OUT
PROTIL
= 100 mA 165 °C
–2–
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Page 3
ADP3342
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
VCC
OUT
OUT
GND
IN
ADP3342
SD
PWRGD
IN
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +13 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +13 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . –40°C to +100°C
Operating Junction Temperature Range . . . –40°C to +125°C
(2-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157°C/W
JA
(4-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121°C/W
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
JC
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device
to be permanently damaged.
ORDERING GUIDE
Model Output Voltage* Package Option Marking Code Temperature Range
ADP3342JRM-REEL7 1.2 V RM-8 (MSOP-8) LJA 0°C to 100°C
ADP3342ARM-REEL7 1.2 V RM-8 (MSOP-8) LJB –40°C to +100°C
*Contact the factory for other output voltage options.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
Pin No. Mnemonic Function
1, 2 OUT Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be
connected together for proper operation.
3 VCC Supply Voltage
4 GND Ground Pin
5 PWRGD Power Good. Used to indicate output is in regulation.
6 SD Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shut down
is not used, this pin should be connected to the input pin.
7, 8 IN Regulator Input. All pins must be connected together for proper operation.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3342 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
Page 4
ADP3342
–Typical Performance Characteristics
1.25
V
= 1.2V
OUT
1.24
1.23
1.22
1.21
1.20
OUTPUT VOLTAGE – V
1.19
1.18
1.17
= 3V
V
CC
I
= 0mA
L
IL = 100mA
= 200mA
I
L
IL = 300mA
1.7 2.7 3.7 4.7 5.7
INPUT VOLTAGE – V
TPC 1. Line Regulation Output Voltage
vs. Supply Voltage
3.5
VIN = 1.8V
V
= 3.0V
3.0
CC
2.5
2.0
1.5
1.0
GROUND CURRENT – mA
0.5
0
50 100 150 200 250 300
0
OUTPUT LOAD – mA
TPC 4. Ground Current vs. Load Current
1.23
1.22
1.21
1.20
1.19
OUTPUT VOLTAGE – V
1.18
1.17
0 50 100 150 200 250 300
OUTPUT LOAD – mA
V
V
= 1.8V
IN
CC
= 3.0V
TPC 2. Output Voltage vs. Load Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
OUTPUT CHANNEL – %
–0.1
–0.2
–0.3
–0.4
–50 –25 150
0 25 50 75 100 125
JUNCTION TEMPERATURE – ⴗC
0
200mA
300mA
TPC 5. Output Voltage Variation
vs. Junction Temperature
120
110
100
90
80
70
GROUND CURRENT – A
60
50
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
1.2
IL = 0A
INPUT VOLTAGE – V
V
= 1.2V
OUT
= 3V
V
CC
TPC 3. Ground Current vs. Supply
Voltage
GROUND CURRENT – mA
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
–40
–200 20406080100
IL = 300mA
IL = 200mA
IL = 100mA
IL = 0mA
JUNCTION TEMPERATURE – ⴗC
VCC = 3.0V
V
= 1.8V
IN
TPC 6. Ground Current vs. Junction
Temperature
0.25
0.20
0.15
0.10
0.05
INPUT-OUTPUT VOLTAGE – V
0
50 100 200 250150 300
0
OUTPUT LOAD – mA
TPC 7. Dropout Voltage vs. Output
Current
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
GROUND CURRENT @ 300mA LOAD – mA
1.0
–25 –105 2035506580 0
–40
MAX
TYP
TEMPERATURE – ⴗC
MIN
VCC = 3.0V
V
= 1.8V
IN
95
TPC 8. Ground Current @ 300 mA
Load vs. Ambient Temperature
–4–
6
5
4
3
2
1
0
–1
INPUT/OUTPUT VOLTAGE – V
–2
0 1000
200 400 600 800
TIME – s
V
OUT
SD = V
RL = 4⍀
= 1.2V
IN
TPC 9. Power-Up/Power-Down
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Page 5
ADP3342
VCC = 3V
C
= 1F
– V
1.32
OUT
1.22
1.12
3.00
– VV
1.80
IN
V
0 200
40 80 120 160
TIME – s
L
R
= 4⍀
L
TPC 10. Line Transient Response
1.3
1.2
1.1
400
200
mA VOLTS
5
0 1600 2000
400 1200800
TIME – s
VCC = 3V
V
IN
C
L
= 1.8V
= 10F
– V
1.32
OUT
1.22
1.12
3.00
– VV
1.80
IN
V
TPC 11. Line Transient Response
0
1.2
1.0
0.5
A VOLTS
VCC = 3V
C
= 10F
L
= 4⍀
R
L
40 80 120 160
0 200
0
0
0 1000
200 400 600 800
TIME – s
VIN = 1.8V
TIME – s
1.3
1.2
1.1
400
200
mA VOLTS
5
0 1600 2000
400 1200800
TIME – s
VCC = 3V
V
= 1.8V
IN
C
= 1F
L
TPC 12. Load Transient Response
2.0
1.0
OUTPUT – VPWRGD – V
0
3.0
0
1.8
0
SD – V
–200 1800
200 600 1000 1400
TIME – s
VCC = 3V
R
= 4⍀
L
V
= 1.8V
IN
0
TPC 13. Load Transient Response
2.0
1.0
0
OUTPUT – VPWRGD – V
3.0
0
1.8
0
SD – V
100
0 500
200 300 400
TIME – s
VCC = 3V
V
= 1.8V
IN
R
= 4⍀
L
TPC 16. Turn On Delay
TPC 14. Short Circuit Current
2.0
1.0
0
OUTPUT – VPWRGD – V
3.0
0
1.8
0
SD – V
6101418
2
TIME – s
TPC 17. Turn Off Delay
VCC = 3V
V
= 1.8V
IN
R
= 4⍀
L
TPC 15. Power-On/Power-Off
Response from Shutdown
2.0
1.0
OUTPUT – V
0
3.0
– V
0
CC
V
200 600 1000 1400
TIME – s
VIN = 1.8V
SD = 3.0V
R
TPC 18. Power-On/Power-Off
Response from V
CC
= 4⍀
L
1800
REV. 0
–5–
Page 6
ADP3342
1.2
OUTPUT – VPWRGD – V
0
3.0
0
1.8
– V
0
IN
V
0 1000
200 400 600 800
VIN = 1.8V
SD = 3.0V
R
TIME – s
= 4⍀
L
TPC 19. Power On/Power Off
Response from V
100
10
1
0.1
DENSITY – V/ Hz
0.01
VOLTAGE NOISE SPECTRAL
CL = 10F
IN
V
OUT
= 1mA
I
L
CL = 1F
= 1.2V
–20
V
= 1.2V
OUT
–30
–40
–50
–60
–70
RIPPLE REJECTION – dB
–80
–90
10 100 1k 10k 100k 1M 10M
CL = 1F
= 50A
I
L
CL = 1F
I
L
CL = 10F
= 300mA
I
L
= 300mA
FREQUENCY – Hz
CL = 10F
= 50A
I
L
TPC 20. Power Supply Ripple
Rejection
1.25
1.23
1.21
1.19
OUTPUT VOLTAGE – V
1.17
0mA
50mA
100mA
200mA
300mA
70
60
50
40
30
RMS NOISE – V
20
10
0
10 20 30 40 50
0
300mA
0mA
CL – F
TPC 21. RMS Noise vs. C
(10 Hz–100 Hz)
650
600
– mA
CL
I
550
L
0.001
100 1k 10k 100k 1M
10
FREQUENCY – Hz
TPC 22. Output Noise Density
3.6
– VmA
3.0
CC
V
400
200
0
5253545
15
TIME – ms
VIN = 1.8V
= 3V
SD
TPC 25. Current Limiting from V
CC
1.15
35 55 75 95 115 135 155 175
AMBIENT TEMPERATURE – ⴗC
TPC 23. Thermal Protection
500
1.5 1.7 1.8 2.0
1.6
VIN – V
1.9
TPC 24. Current Limit vs. V
IN
–6–
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Page 7
ADP3342
THEORY OF OPERATION
The new anyCAP LDO ADP3342 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
APPLICATION INFORMATION
PC Application—VCCVID
The ADP3342 has been optimized for PC applications that
require a 1.2 V output for powering the voltage identification
rail, VCCVID. The rail from which the output draws current,
the IN pin, is separated from the rail that powers the IC, the
VCC pin. This allows a higher efficiency design when, as
INPUT
Q1
NONINVERTING
WIDEBAND
DRIVER
ADP3342
VCC
COMPENSATION
CAPACITOR
OUTPUT
ATTENUATION
(V
BANDGAP /VOUT
PTAT
V
OS
g
m
R3
PTAT
CURRENT
R4
R1
)
C
D1
(a)
LOAD
R
LOAD
R2
recommended for the IMVP-3 application, the VCC pin is
connected to a 3.3 V supply to power the IC adequately, and
the IN pin is connected to a 1.8 V supply. The efficiency is
nearly 60% in this case.
Capacitor Selection
As with any voltage regulator, output transient response is a
function of the output capacitance. The ADP3342 is stable with
a wide range of capacitor values, types and ESR (anyCAP).
A capacitor as low as 1 µF is all that is needed for stability; larger
GND
Figure 2. Control Loop Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage”
that is repeatable and very well controlled. The temperature
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility
on the trade-off of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1 and a second divider consisting
of R3 and R4, the values can be chosen to produce a temperature
stable output. This unique arrangement specifically corrects for
the loading of the divider so that the error resulting from base
current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve reduced
sensitivity to the value, type and ESR of the load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limitations
make designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
With the ADP3342 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the output.
Additional advantages of the pole splitting scheme include superior
line noise rejection and very high regulator gain which leads to
excellent line and load regulation.
Additional features of the circuit include current limit and thermal
capacitors can be used if high output current surges are anticipated.
The ADP3342 is stable with extremely low ESR capacitors (ESR ≈ 0),
such as multilayer ceramic capacitors (MLCC) or OSCON.
Note that the effective capacitance of some capacitor types may
fall below the minimum at cold temperature. Ensure that the
capacitor provides more than 1 µF at minimum temperature.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance.
the circuit's sensitivity to PC board layout. If a larger value output
capacitor is used, then a larger value input capacitor is also
recommended.
Power Good Monitoring Function
The PWRGD pin does not monitor the output voltage directly,
but rather detects whether the internal PNP pass transistor is being
modulated by the regulation loop. This means of detecting PWRGD,
rather than using a voltage threshold detection, provides an inherent
and desirable delay in asserting the PWRGD signal. During
startup or overload, the regulation loop is not in control, so the
PWRGD pin is low.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output ON. Pulling SD down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced.
Paddle-Under-Lead Package
The ADP3342 uses a patented paddle-under-lead package design
to ensure the best thermal performance in an MSOP-8 footprint.
This new package uses an electrically isolated die attach that
allows all pins to contribute to heat conduction. This technique
reduces the thermal resistance to 110°C/W on a 4-layer board as
compared to >160°C/W for a standard MSOP-8 leadframe.
Thermal Overload Protection
The ADP3342 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output current
is reduced until the die temperature has dropped to a safe
The output current is restored when the die temperature is reduced.
shutdown and noise reduction.
Connecting a 1 µF capacitor from IN to ground reduces
level.
REV. 0
–7–
Page 8
ADP3342
Current and thermal limit protections are intended to protect the
device against accidental overload conditions. For normal operation,
Assuming I
V
OUT
device power dissipation should be limited by operating conditions
so that junction
Calculating Junction Temperature
Device power dissipation is calculated as follows:
temperatures will not exceed 150°C.
The proprietary package used in the ADP3342 has a thermal
resistance of 110°C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction tem-
PVV I VI
Where I
and V
=+( – )()
D IN OUT LOAD IN GND
and I
LOAD
are input and output voltages respectively.
OUT
are load current and ground current, V
GND
perature rise above ambient temperature will be approximately
equal to:
IN
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Micro SOIC (MSOP)
(RM-8)
0.122 (3.10)
0.114 (2.90)
0.122 (3.10)
0.114 (2.90)
85
0.199 (5.05)
0.187 (4.75)
1
4
= 300 mA, I
LOAD
= 4 mA, VIN = 1.8 V and
GND
= 1.2 V, device power dissipation is:
PD=− + =(. .) (.)18 12 300 18 4 187 mA mA mW
∆TWCWC
=×°=°0 187 110 20 6..
AJ
C02712–.8–1/02(0)
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.006 (0.15)
0.002 (0.05)
SEATING
CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
PLANE
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
0.120 (3.05)
0.112 (2.84)
33ⴗ
27ⴗ
0.028 (0.71)
0.016 (0.41)
PRINTED IN U.S.A.
–8–
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