Page 1
High Accuracy Ultralow IQ, 500 mA
THERMAL
PROTECTION
CC
IN
ADP3336
OUT
GND
Q1
BANDGAP
REF
DRIVER
g
m
FB
SD
a
anyCAP
®
Adjustable Low Dropout Regulator
FEATURES
High Accuracy Over Line and Load: ⴞ0.9% @ 25ⴗC,
ⴞ1.8% Over Temperature
Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA
Requires Only C
= 1.0 F for Stability
O
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1.0 A
2.6 V to 12 V Supply Range
1.5 V to 10 V Output Range
–40ⴗC to +85ⴗC Ambient Temperature Range
Ultrasmall Thermally-Enhanced 8-Lead MSOP Package
APPLICATIONS
PCMCIA Card
Cellular Phones
Camcorders, Cameras
Networking Systems, DSL/Cable Modems
Cable Set-Top Box
MP3/CD Players
DSP Supply
GENERAL DESCRIPTION
The ADP3336 is a member of the ADP333x family of precision
low dropout anyCAP voltage regulators. The ADP3336 operates
with an input voltage range of 2.6 V to 12 V and delivers a
continuous load current up to 500 mA. The ADP3336 stands
out from conventional LDOs with the lowest thermal resistance
of any MSOP-8 package and an enhanced process that enables
it to offer performance advantages beyond its competition.
Its patented design requires only a 1.0 µF output capacitor for
stability. This device is insensitive to output capacitor Equivalent Series Resistance (ESR), and is stable with any good
quality capacitor, including ceramic (MLCC) types for spacerestricted applications. The ADP3336 achieves exceptional
accuracy of ±0.9% at room temperature and ±1.8% over temperature, line, and load. The dropout voltage of the ADP3336 is
only 200 mV (typical) at 500 mA. This device also includes a
safety current limit, thermal overload protection and a shutdown
feature. In shutdown mode, the ground current is reduced to
less than 1 µA. The ADP3336 has ultralow quiescent current
80 µA (typical) in light load situations.
ADP3336
FUNCTIONAL BLOCK DIAGRAM
ADP3336
OUT
OUT
IN
V
IN
C
IN
1F
OFF
IN
SD
ON
Figure 1. Typical Application Circuit
GND
OUT
R1
FB
R2
C
1F
V
OUT
OUT
anyCAP is a registered trademark of Analog Devices Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
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1, 2
ADP3336–SPECIFICATIONS
(VIN = 6.0 V, CIN = C
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT
Voltage Accuracy
Line Regulation
Load Regulation I
Dropout Voltage V
3, 4
3
V
OUT
DROP
VIN = V
I
T
V
I
T
V
I
T
VIN = V
I
T
T
V
OUT(NOM)
= 0.1 mA to 500 mA
L
= 25°C
J
= V
IN
OUT(NOM)
= 0.1 mA to 500 mA
L
= –40°C to +125°C
J
= V
IN
OUT(NOM)
= 0.1 mA to 500 mA
L
= 150°C
J
OUT(NOM)
= 0.1 mA
L
= 25°C
A
= 0.1 mA to 500 mA 0.04 mV/mA
L
= 25°C
A
= 98% of V
OUT
+ 0.4 V to 12 V –0.9 +0.9 %
+ 0.4 V to 12 V –1.8 +1.8 %
+ 0.4 V to 12 V –2.3 +2.3 %
+ 0.4 V to 12 V 0.04 mV/V
OUT(NOM)
IL = 500 mA 200 400 mV
I
= 300 mA 140 235 mV
L
I
= 50 mA 60 130 mV
L
= 0.1 mA 10 mV
I
Peak Load Current I
Output Noise V
LDPK
NOISE
L
VIN = V
OUT(NOM)
+ 1 V 800 mA
f = 10 Hz–100 kHz, CL = 10 µF27µV rms
= 500 mA, CNR = 10 nF, V
I
L
f = 10 Hz–100 kHz, C
IL = 500 mA, CNR = 0 nF, V
GROUND CURRENT
In Regulation I
In Dropout I
In Shutdown I
5
GND
GND
GNDSD
IL = 500 mA 4.5 10 mA
I
= 300 mA 2.6 6 mA
L
I
= 50 mA 0.5 1.5 mA
L
= 0.1 mA 80 110 µA
I
L
VIN = V
I
= 0.1 mA
L
OUT(NOM)
– 100 mV 120 400 µA
SD = 0 V, VIN = 12 V 0.01 1 µA
SHUTDOWN
Threshold Voltage V
THSD
ON 2.0 V
OFF 0.4 V
SD Input Current I
Output Current In Shutdown I
SD
OSD
0 ≤ SD ≤ 12 V 1.2 5 µA
TA = 25°C, VIN = 12 V 0.01 1 µA
TA = 85°C, VIN = 12 V 0.01 1 µA
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2
Application stable with no load.
3
VIN = 2.6 V to 12 V for models with V
4
Over the V
5
Ground current includes current through external resistors.
Specifications subject to change without notice.
range of 1.5 V to 10 V.
OUT
OUT(NOM)
≤ 2.2 V.
= 1.0 F, TJ = –40ⴗC to +125ⴗC unless otherwise noted.)
OUT
= 2.5
OUT
= 10 µF45µV rms
L
OUT
= 2.5
–2–
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ADP3336
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40°C to +85°C
Operating Junction Temperature Range . . . –40°C to +150°C
2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153°C/W
θ
JA
4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W
θ
JA
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Output Package Package Branding
Model Voltage Description Option Information
ADP3336 ADJ mini_SO RM-8 LHA
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1, 2, 3 OUT Output of the Regulator. Bypass to
ground with a 1.0 µF or larger capacitor.
All pins must be connected together for
proper operation.
4 GND Ground Pin.
5 FB Feedback Input. Connect to an external
resistor divider which sets the output
voltage. Can also be used for further
reduction of output noise (see text for
detail).
Capacitor required if C
> 3.3 µF.
OUT
6 SD Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
7, 8 IN Regulator Input. All pins must be con-
nected together for proper operation.
PIN CONFIGURATION
OUT
OUT
OUT
GND
1
2
ADP3336
TOP VIEW
3
(Not to Scale)
4
8
IN
7
IN
6
SD
5
FB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3336 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADP3336
–Typical Performance Characteristics
2.202
IL = 0
2.201
2.200
2.199
150mA
2.198
2.197
300mA
2.196
OUTPUT VOLTAGE – Volts
2.195
2.194
24 12
500mA
6810
INPUT VOLTAGE – Volts
V
OUT
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
5.0
VIN = 6V
= 2.2V
V
OUT
4.0
3.0
2.0
GROUND CURRENT – mA
1.0
0
0
100 500200 300 400
OUTPUT LOAD – mA
TPC 4. Ground Current vs. Load
Current
= 2.2V
2.201
2.200
2.199
2.198
2.197
2.196
2.195
OUTPUT VOLTAGE – Volts
2.194
2.193
0 100 500
200 300 400
OUTPUT LOAD – mA
V
= 2.2V
OUT
V
= 6V
IN
TPC 2. Output Voltage vs. Load
Current
0.5
0.4
0.3
0.2
0.1
0
OUTPUT CHANGE – %
500mA
–0.1
0
–0.2
–40 105
–15 5 25
JUNCTION TEMPERATURE – ⴗC
45
300mA
65 85
0
500mA
125
TPC 5. Output Voltage Variation %
vs. Junction Temperature
140
120
100
80
60
40
GROUND CURRENT – A
20
0
IL = 100A
IL = 0
0
24 68 10
INPUT VOLTAGE – Volts
V
= 2.2V
OUT
12
TPC 3. Ground Current vs. Supply
Voltage
8
IL = 500mA
6
5
300mA
4
3
100mA
2
GROUND CURRENT – mA
50mA
1
0
0
–155 254565857125
–40 105
JUNCTION TEMPERATURE – ⴗC
VIN = 6V
= 2.2V
V
OUT
TPC 6. Ground Current vs. Junction
Temperature
250
V
= 2.2V
OUT
200
150
100
DROPOUT VOLTAGE – mV
50
0
0
100 500
200 300 400
OUTPUT LOAD – mA
TPC 7. Dropout Voltage vs.
Output Current
V
3.0
2.5
2.0
1.5
1.0
0.5
INPUT/OUTPUT VOLTAGE – Volts
0
1234
TIME – Sec
OUT
SD = V
RL = 4.4⍀
TPC 8. Power-Up/Power-Down
–4–
= 2.2V
IN
3
C
= 1F
OUT
2
– Volts
1
– Volts V
V
OUT
0
4
2
IN
0
C
OUT
400 600 800
200
TIME – s
= 10F
TPC 9. Power-Up Response
V
= 2.2V
OUT
SD = V
IN
RL = 4.4⍀
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ADP3336
2.210
2.200
– Volts
2.190
OUT
– Volts V
IN
V
2.189
2.179
3.500
3.000
40 80 140 180
TIME –
V
OUT
R
= 4.4⍀
L
C
= 1F
L
s
TPC 10. Line Transient Response
2.3
2.2
2.1
400
V
mA Volts
200
0
= 2.2V
OUT
V
= 6V
IN
C
= 10F
L
200 400 600 800
TIME – s
= 2.2V
2.210
2.200
– Volts
2.190
– Volts V
V
OUT
2.189
2.179
3.500
3.000
IN
40 80 140 180
TIME – s
V
OUT
R
L
C
L
= 2.2V
= 4.4⍀
= 10F
TPC 11. Line Transient Response
2.2
0
FULL SHORT
VIN = 4V
TIME – s
A Volts
3
2
1
0
800m⍀
SHORT
200 400 600 800
2.3
2.2
2.1
400
200
mA Volts
0
VIN = 6V
= 2.2V
V
OUT
= 1F
C
L
200 400 600 800
TIME –
s
TPC 12. Load Transient Response
1F
VIN = 6V
V
= 2.2V
OUT
R
= 4.4⍀
L
10F
V
V
3
1F
2
OUT
1
0
2
SD
0
10F
200 400 600 800
TIME – s
TPC 13 Load Transient Response
–20
V
= 2.2V
OUT
–30
–40
CL = 1F
–50
I
–60
–70
RIPPLE REJECTION – dB
–80
–90
10 100 1k 10k 100k 1M 10M
= 50A
L
CL = 1F
= 500mA
I
L
FREQUENCY – Hz
CL = 10F
= 500mA
I
L
CL = 10F
= 50A
I
L
TPC 16. Power Supply Ripple
Rejection
TPC 14. Short Circuit Current
160
140
120
100
80
60
RMS NOISE – V
40
20
0
05010 20 30 40
IL = 500mA WITHOUT
NOISE REDUCTION
IL = 0mA WITH NOISE REDUCTION
C
L
V
OUT
CNR = 10nF
IL = 500mA WITH
NOISE REDUCTION
IL = 0mA WITHOUT
NOISE REDUCTION
– F
TPC 17. RMS Noise vs. C
(10 Hz–100 kHz)
= 2.0V
L
TPC 15. Turn On–Turn Off Response
100
10
CL = 10F
C
NR
1
0.1
DENSITY – V/ Hz
0.01
VOLTAGE NOISE SPECTRAL
0.001
10 100 1M1k 10k 100k
CL = 10F
C
= 10nF
NR
CL = 1F
= 10nF
C
NR
FREQUENCY – Hz
= 0
V
OUT
= 1mA
I
L
CL = 1F
= 0
C
NR
= 2.2V
TPC 18. Output Noise Density
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ADP3336
THEORY OF OPERATION
The new anyCAP LDO ADP3336 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
Q1
NONINVERTING
WIDEBAND
DRIVER
ADP3336
COMPENSATION
CAPACITOR
PTAT
V
g
m
(V
OS
R4
GND
ATTENUATION
BANDGAP/VOUT
R3
PTAT
CURRENT
OUTPUT
R1
)
D1
FB
C
LOAD
(a)
R
LOAD
R2
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input, “offset voltage”
that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
With the ADP3336 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive ±1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and thermal shutdown.
APPLICATION INFORMATION
Capacitor Selection
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3336 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 1 µF is all that is
needed for stability; larger capacitors can be used if high output
current surges are anticipated. The ADP3336 is stable with
extremely low ESR capacitors (ESR ≈ 0), such as multilayer
ceramic capacitors (MLCC) or OSCON. Note that the effective
capacitance of some capacitor types may fall below the minimum at cold temperature. Ensure that the capacitor provides
more than 1 µF at minimum temperature.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit's sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capacitor is also recommended.
Noise Reduction
A noise reduction capacitor (CNR) can be placed between
the output and the feedback pin to further reduce the noise by
6 dB–10 dB (TPC 18). Low leakage capacitors in 100 pF–500 pF
range provide the best performance. Since the feedback pin (FB)
is internally connected to a high impedance node, any connection
to this node should be carefully done to avoid noise pickup from
external sources. The pad connected to this pin should be as
small as possible and long PC board traces are not recommended.
When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown.
It is important to note that as C
will be delayed. With C
NR
increases, the turn-on time
NR
values greater than 1 nF, this delay
may be on the order of several milliseconds.
ADP3336
IN
V
IN
C
1F
IN
OFF
ON
IN
SD
GND
OUT
OUT
OUT
FB
V
OUT
C
C
NR
OUT
R1
1F
R2
Figure 3. Typical Application Circuit
–6–
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Page 7
Output Voltage
The ADP3336 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be
divided by R1 and R2, and then fed back to the FB pin.
In order to have the lowest possible sensitivity of the output
voltage to temperature variations, it is important that the parallel resistance of R1 and R2 is always 50 kΩ.
RR
12
×
RR
12
+
k
50
=Ω
Also, for the best accuracy over temperature the feedback voltage should be set for 1.178 V:
VV
=×
FB OUT
where V
is the desired output voltage and VFB is the “virtual
OUT
bandgap” voltage. Note that V
RR
does not actually appear at the
FB
2
R
12
+
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2 gives
the following formulas:
V
OUT
V
FB
k
50
Ω
V
FB
1
–
V
OUT
V
OUT
Rk
150
=Ω×
R
2
=
Table I. Feedback Resistor Selection
R1 (1% Resistor) R2 (1% Resistor)
1.5 V 63.4 kΩ 232 kΩ
1.8 V 76.8 kΩ 147 kΩ
2.2 V 93.1 kΩ 107 kΩ
2.7 V 115 kΩ 88.7 kΩ
3.3 V 140 kΩ 78.7 kΩ
5 V 210 kΩ 64.9 kΩ
10 V 422 kΩ 56.2 kΩ
Paddle-Under-Lead Package
The ADP3336 uses a proprietary paddle-under-lead package
design to ensure the best thermal performance in an MSOP-8
footprint. This new package uses an electrically isolated die
attach that allows all pins to contribute to heat conduction.
This technique reduces the thermal resistance to 110°C/W on a
4-layer board as compared to >160°C/W for a standard MSOP-8
leadframe. Figure 4 shows the standard physical construction
of the MSOP-8 and the paddle-under-lead leadframe.
ADP3336
DIE
Figure 4. Thermally Enhanced Paddle-Under-Lead Package
Thermal Overload Protection
The ADP3336 is protected against damage from excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a
safe level. The output current is restored when the die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
P
= (VIN – V
D
Where I
and V
Assuming I
V
OUT
and I
LOAD
are input and output voltages respectively.
OUT
LOAD
are load current and ground current, V
GND
= 400 mA, I
= 3.3 V, device power dissipation is:
P
= (5 – 3.3) 400 mA + 5.0(4 mA) = 700 mW
D
The proprietary package used in the ADP3336 has a thermal
resistance of 110°C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately
equal to:
∆TWCC
=×°=°0 700 110 77 0..
AJ
To limit the maximum junction temperature to 150°C, maximum allowable ambient temperature will be:
T
= 150°C – 77.0°C = 73.0°C
AMAX
Printed Circuit Board Layout Consideration
All surface mount packages rely on the traces of the PC board to
conduct heat away from the package.
) I
OUT
GND
+ (VIN) I
LOAD
= 4 mA, VIN = 5.0 V and
GND
IN
REV. 0
–7–
Page 8
ADP3336
In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be
attached to these fused pins.
The proprietary paddle-under-lead frame design of the ADP3336
uniformly minimizes the value of the dominant portion of the
thermal resistance. It ensures that heat is conducted away by all
pins of the package. This yields a very low 110°C/W thermal
resistance for an MSOP-8 package, without any special board
layout requirements, relying only on the normal traces connected
to the leads. This yields a 33% improvement in heat dissipation
capability as compared to a standard MSOP-8 package. The
thermal resistance can be decreased by, approximately, an additional 10% by attaching a few square cm of copper area to the
IN pin of the ADP3336 package.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead mini_SO
(RM-8)
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3336’s pins since it will increase
the junction-to-ambient thermal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output ON. Pulling SD down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced to much less
than 1 µA.
C02174–2.5–10/00 (rev. 0)
0.122 (3.10)
0.114 (2.90)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.122 (3.10)
0.114 (2.90)
85
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
0.008 (0.20)
0.199 (5.05)
0.187 (4.75)
41
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
0.120 (3.05)
0.112 (2.84)
33ⴗ
27ⴗ
0.028 (0.71)
0.016 (0.41)
PRINTED IN U.S.A.
–8–
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