Datasheet ADP3333ARM-5, ADP3333ARM-3.3, ADP3333ARM-3.15, ADP3333ARM-3, ADP3333ARM-2.77 Datasheet (Analog Devices)

a

THERMAL

PROTECTION

CC

IN

ADP3333

OUT

GND

Q1

BANDGAP

REF

DRIVER

g

m

SD

R1

R2

High Accuracy Ultralow IQ, 300 mA,

®

anyCAP

Low Dropout Regulator

ADP3333

FEATURES
High Accuracy Over Line and Load: 0.8% @ 25C,

1.8% Over Temperature
Ultralow Dropout Voltage: 230 mV (Max) @ 300 mA
Requires Only C

= 1.0 F for Stability

O

anyCAP = Stable with Any Type of Capacitor

(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1 A

2.6 V to 12 V Supply Range
–40C to +85C Ambient Temperature Range
Ultrasmall 8-Lead MSOP Package

APPLICATIONS
Cellular Phones
PCMCIA Cards
Personal Digital Assistants (PDAs)
DSP/ASIC Supplies

GENERAL DESCRIPTION

ADP3333 is a member of the ADP333x family of precision low
dropout anyCAP voltage regulators. Pin-compatible with the
MAX8860, the ADP3333 operates with a wider input voltage
range of 2.6 V to 12 V and delivers a load current up to 300 mA.
ADP3333 stands out from other conventional LDOs with a
novel architecture and an enhanced process that enables it to
offer performance advantages over its competition. Its patented
design requires only a 1.0 µF output capacitor for stability. This
device is insensitive to output capacitor Equivalent Series Resis­tance (ESR), and is stable with any good quality capacitor,
including ceramic (MLCC) types for space-restricted applica­tions. ADP3333 achieves exceptional accuracy of ±0.8% at
room temperature and ±1.8% over temperature, line and load
variations. The dropout voltage of ADP3333 is only 140 mV
(typical) at 300 mA. This device also includes a safety current
limit, thermal overload protection and a shutdown feature. In
shutdown mode, the ground current is reduced to less than
1 µA. The ADP3333 has ultralow quiescent current, 70 µA (typ)
in light load situations.

FUNCTIONAL BLOCK DIAGRAM

ADP3333

V

IN

C

IN

1F

IN

SD

OFF

ON

NC

OUT

GND

NC = NO CONNECT

Figure 1. Typical Application Circuit

C
1F

OUT

V

OUT

anyCAP is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

1

ADP3333–SPECIFICA TIONS

(VIN = 6.0 V, CIN = C

Parameter Symbol Condition Min Typ Max Unit

OUTPUT

Voltage Accuracy

Line Regulation
Load Regulation I
Dropout Voltage V

2

2

V

OUT

DROP

VIN = V
I
T
V
I
VIN = V
T

T
V

OUTNOM

= 0.1 mA to 300 mA

L

= 25°C

J

= V

IN

OUTNOM

= 0.1 mA to 300 mA

L

OUTNOM

= 25°C

J

= 0.1 mA to 300 mA 0.04 mV/mA

L

= 25°C

J

= 98% of V

OUT

IL = 300 mA 140 230 mV
I

= 200 mA 105 185 mV

L

= 0.1 mA 30 mV

I

L

Peak Load Current I
Output Noise V

LDPK

NOISE

VIN = V

OUTNOM

f = 10 Hz–100 kHz, CL = 10 µF45µV rms
IL = 300 mA

GROUND CURRENT

In Regulation I

In Dropout I

In Shutdown I

GND

GND

GNDSD

IL = 300 mA 2.0 5.5 mA
I

= 300 mA, TJ = 25°C 2.0 4.3 mA

L

= 300 mA, TJ = 85°C 1.5 3.3 mA

I

L

I

= 200 mA 1.4 mA

L

I

= 10 mA 200 275 µA

L

= 0.1 mA 70 100 µA

I

L

VIN = V
I
V
I

OUTNOM

= 0.1 mA,

L

= V

IN

OUTNOM

= 0.1 mA, TJ = 0°C to 125°C

L

SD = 0 V, VIN = 12 V 0.01 1 µA

SHUTDOWN

Threshold Voltage V

THSD

ON 2.0 V
OFF 0.4 V

SD Input Current I

SD

0 ≤ SD ≤ 12 V 0.85 7 µA
0 ≤ SD ≤ 5 V 0.8 4.5 µA

Output Current In Shutdown I

OSD

TJ = 25°C VIN = 12 V 0.01 1 µA
TJ = 125°C VIN = 12 V 0.01 1 µA

NOTES

1

Application stable with no load.

2

VIN = 2.6 V for models with V

Specifications subject to change without notice.

OUTNOM

≤ 2.3 V.

= 1.0 F, TJ = –40C to +125C, unless otherwise noted)

OUT

0.3 V to 12 V 0.8 0.8 %

0.3 V to 12 V –1.8 +1.8 %

0.3 V to 12 V 0.04 mV/V

OUTNOM

+ 1 V 600 mA

– 100 mV 70 190 µA
– 100 mV 70 160 µA

–2–

REV. 0

ADP3333

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V

Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V

Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited

Operating Ambient Temperature Range . . . . –40°C to +85°C

Operating Junction Temperature Range . . . –40°C to +125°C

␪

(4-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

JA

(2-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W

␪

JA

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Output Package Branding

Model Voltage Option Information

ADP3333ARM-1.5 1.5 V RM-8 LKA

(MSOP-8)

ADP3333ARM-1.8 1.8 V RM-8 LKB

(MSOP-8)

ADP3333ARM-2.5 2.5 V RM-8 LKC

(MSOP-8)

ADP3333ARM-2.77 2.77 V RM-8 LKD

(MSOP-8)

ADP3333ARM-3 3 V RM-8 LKE

(MSOP-8)

ADP3333ARM-3.15 3.15 V RM-8 LKF

(MSOP-8)

ADP3333ARM-3.3 3.3 V RM-8 LKG

(MSOP-8)

ADP3333ARM-5 5 V RM-8 LKH

(MSOP-8)

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 OUT Output of the Regulator. Bypass to ground

with a 1.0 µF or larger capacitor.

2 IN Input pin. Bypass to ground with a 1.0 µF

or larger capacitor.
3 GND Ground Pin
4–6, 8 NC No Connect
7 SD Active Low Shutdown Pin. Connect to

ground to disable the regulator output.

When shutdown is not used, his pin should

be connected to the input pin

PIN CONFIGURATION

1

OUT

2

IN

ADP3333

TOP VIEW

3

GND

(Not to Scale)

4

NC*

NC = NO CONNECT

*CAN BE CONNECTED
TO ANY OTHER PIN.

8

NC

7

SD

6

NC

5

NC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3333 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADP3333

–Typical Performance Characteristics

2.502

2.500

2.498

2.496

2.494

2.492

OUTPUT VOLTAGE – V

2.490

2.488

0mA

100mA

200mA

300mA

34 12

6810

INPUT VOLTAGE – V

V

OUT

TPC 1. Line Regulation Output
Voltage vs. Supply Voltage

2.5

2.0

1.5

1.0

GROUND CURRENT – mA

0.5

0

0 300

50 100 150 200 250

OUTPUT LOAD – mA

VIN = 6V

TPC 4. Ground Current vs.
Load Current

= 2.5V

11975

OUTPUT VOLTAGE – V

2.502

2.500

2.498

2.496

2.494

2.492

2.490

2.488
50 200

0 100

OUTPUT LOAD – mA

150 300250

VIN = 6V
V

= 2.5V

OUT

TPC 2. Output Voltage vs. Load
Current

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

OUTPUT CHANGE – %

–0.1
–0.2
–0.3

0

–0.4

–25 0 25 50 75 100

–50

JUNCTION TEMPERATURE – C

0

200mA

300mA

125

TPC 5. Output Voltage Variation % vs.
Junction Temperature

A



GROUND CURRENT –

140

120

100

80

60

40

20

0

IL = 100A

IL = 0

0

24 6810

INPUT VOLTAGE – Volts

V

= 2.5V

OUT

TPC 3. Ground Current vs. Supply
Voltage

3.5

3.0

2.5

2.0

1.5

1.0

GROUND CURRENT – mA

0.5

0

–50 –25 0 25 50 75 100 125

IL = 300mA

IL = 200mA

IL = 0mA

JUNCTION TEMPERATURE – C

VIN = 6V

IL = 100mA

TPC 6. Ground Current vs.
Junction Temperature

12

0.16

0.14

0.12

0.10

0.08

0.06

0.04

INPUT/OUTPUT VOLTAGE – mV

0.02

0

0 50 250

100 150 200

OUTPUT LOAD – mA

TPC 7. Dropout Voltage vs.
Output Current

300

3.0

2.5

2.0

1.5

1.0

0.5

0

INPUT/OUTPUT VOLTAGE – V

1234

TIME – Sec

TPC 8. Power-Up/Power-Down

–4–

V

= 2.5V

OUT

SD = V

IN

RL = 8.3

C

= 1F

OUT

3

– V

2

OUT

V

1
0
4

– V

IN

2

V

0

200 400 600 800

C

= 10F

OUT

TIME – s

TPC 9. Power-Up Response

V

= 2.5V

OUT

SD = V

RL = 8.3

REV. 0

IN

ADP3333

V

= 2.5V

OUT

R

L

C

L

= 8.3
= 1F

– V

– V V
V

OUT

IN

2.52

2.51

2.50

2.49

3.50

3.00

40 80 140 180

TIME – s

TPC 10. Line Transient Response

VIN = 4V

2.7

V

= 2.5V

OUT

C

= 10F

L

2.6

2.5

2.4

300

mA Volts

10

200 400 600 800

TIME – s

TPC 13. Load Transient Response

V

= 2.5V

OUT

R

L

C

L

= 8.3
= 10F

– V

– V V
V

OUT

IN

2.52

2.51

2.50

2.49

3.50

3.00

40 80 140 180

TIME – s

TPC 11. Line Transient Response

2.5
0
3
2

A Volts

1
0

VIN = 6V

200 400 600 800

TIME – s

VIN = 6V

TPC 14. Short Circuit Current

2.7

2.6

2.5

2.4

300

mA Volts

10

200 400 600 800

TIME – s

VIN = 4V
V

= 2.5V

OUT

C

= 1F

L

TPC 12. Load Transient Response

1F

3

1F

10F

VIN = 6V

= 2.5V

V

OUT

= 8.3

R

L

V

V

OUT

SD

2
1
0

2
0

10F

200 400 600 800

TIME – s

TPC 15. Turn ON-Turn OFF
Response

–20

V

= 2.2V

OUT

–30

–40

CL = 1F

–50

I

–60

–70

RIPPLE REJECTION – dB

–80

–90

10 100 1k 10k 100k 1M 10M

= 50A

L

CL = 1F

= 500mA

I

L

FREQUENCY – Hz

CL = 10F

= 500mA

I

L

CL = 10F

= 50A

I

L

TPC 16. Power Supply Ripple
Rejection

120

100

V

80



60

0mA

0 10

300mA

20 30 40 50

CL – F

40

RMS NOISE –

20

0

TPC 17. RMS Noise vs. C
(10 Hz–100 kHz)

100

10

1

0.1

DENSITY – V/ Hz

0.01

VOLTAGE NOISE SPECTRAL

0.001
10 100 1M1k 10k 100k

L

TPC 18. Output Noise Density

CL = 10F

FREQUENCY – Hz

V

OUT

= 1mA

I

L

CL = 1F

= 2.5V

REV. 0

–5–

ADP3333

THEORY OF OPERATION

The new anyCAP LDO ADP3333 uses a single control loop for
regulation and reference functions see (Figure 2). The output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 which is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.

INPUT

Q1

NONINVERTING

WIDEBAND

DRIVER

COMPENSATION
CAPACITOR

ADP3333

ATTENUATION

(V

BANDGAP /VOUT

R3

PTAT

V

OS

g

m

R4

GND

PTAT
CURRENT

OUTPUT

)

R1

C

D1

FB

LOAD

(a)

R

LOAD

R2

Figure 2. Functional Block Diagram

A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it pro­duces a large, temperature-proportional input “offset voltage” that
is repeatable and very well controlled. The temperature propor­tional offset voltage is combined with the complementary diode
voltage to form a “virtual bandgap” voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately, this
patented design makes it possible to control the loop with only one
amplifier. This technique also improves the noise characteristics
of the amplifier by providing more flexibility on the trade-off of
noise sources that leads to a low noise design.

The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load­ing of the divider so that the error resulting from base current
loading in conventional circuits is avoided.

The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve
reduced sensitivity to the value, type and ESR of the load
capacitance.

Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover,
the ESR value, required to keep conventional LDOs stable, changes
depending on load and temperature. These ESR limitations make

designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.

With the ADP3333 anyCAP LDO, this is no longer true. It can be
used with virtually any good quality capacitor, with no constraint
on the minimum ESR. This innovative design allows the circuit to
be stable with just a small 1 µF capacitor on the output. Additional
advantages of the pole splitting scheme include superior line noise
rejection and very high regulator gain which leads to excellent line
and load regulation. An impressive ±1.8% accuracy is guaranteed
over line, load and temperature.

Additional features of the circuit include current limit and ther­mal shutdown.

APPLICATION INFORMATION
Capacitor Selection

Output Capacitor

The stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types and ESR (anyCAP). A capacitor as
low as 1.0 µF is all that is needed for stability; larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors
(ESR » 0), such as Multilayer Ceramic Capacitors (MLCC) or
OSCON. Note that the effective capacitance of some capacitor
types fall below the minimum over temperature or with dc voltage.
Ensure that the capacitor provides at least 1.0 µF of capacitance
over temperature and dc bias.

Input Bypass Capacitor

An input bypass capacitor is not strictly required but it is recom­mended in any application involving long input wires or high
source impedance. Connecting a 1.0 µF capacitor from the inpu t
to ground reduces the circuit's sensitivity to PC board layout and
input transients. If a larger output capacitor is necessary then a
larger value input capacitor is also recommended.

Output Current Limit

The ADP3333 is short circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 1 A. See TPC 14.

Thermal Overload Protection

The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current will be reduced until the die tempera­ture has dropped to a safe level.

Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device's power dissipation should be externally
limited so that the junction temperature will not exceed 125°C.

–6–

REV. 0

ADP3333

Calculating Junction Temperature

Device power dissipation is calculated as follows:

PVV I VI

=−

()

D IN OUT LOAD IN GND

Where I
and V

and I

LOAD

are the input and output voltages respectively.

OUT

are load current and ground current, V

GND

Assuming the worst-case operating conditions are I
300 mA, I

= 2.6 mA, VIN = 4.0 V and V

GND

+

()

= 3.0 V, the

OUT

LOAD

IN

=

device power dissipation is:

P V V mA V mA mW

=−

()

D

+

()

=40 30 300 42 20 308.. ..

The package used on the ADP3333 has a thermal resistance of
158°C/W for 4-layer boards. The junction temperature rise
above ambient will be approximately equal to:

TWCWC

=×°=°0 308 158 48 7./.

AJ

So, to limit the junction temperature to 125°C, the maximum
allowable ambient temperature is:

TCCC

Shutdown Mode

MAXA()

..=°− °= °125 48 7 76 3

Applying a high signal to the shutdown pin, or connecting it to
the input pin, will turn the output ON. Pulling the shutdown
pin to 0.3 V or below, or connecting it to ground, will turn the
output OFF. In shutdown mode, the quiescent current is reduced
to less than 1 µA.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed
circuit boards:

1. Keep the output capacitor as close to the output and ground
pins as possible.

2. Keep the input capacitor as close to the input and ground
pins as possible.

3. PC board traces with larger cross sectional areas will remove
more heat from the ADP3333. For optimum heat transfer,
specify thick copper and use wide traces.

4. Connect the NC pins (Pins 5, 6, and 8) to ground for better
thermal performance.

5. The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.

6. Use additional copper layers or planes to reduce the thermal
resistance. Again, connecting the other layers to the ground and
NC pins of the ADP3333 is best, but not necessary. When
connecting the ground pad to other layers use multiple vias.

REV. 0

–7–

ADP3333

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Mini/micro SOIC Package [Mini_SO]

(RM-8)

0.122 (3.10)

0.114 (2.90)

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)
SEATING

PLANE

85

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

0.199 (5.05)

0.187 (4.75)

41

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

33



27



C02615–1.5–7/01(0)

0.028 (0.71)

0.016 (0.41)

–8–

PRINTED IN U.S.A.

REV. 0